JP2796311B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a reduction in power consumption of a semiconductor device, and more particularly to a memory operated by a voltage of a battery.

[Prior art]

As described in Japanese Patent Publication No. 61-61479, a conventional DRAM circuit includes a memory array (memory cell matrix) including a plurality of memory cells for storing signals, an X decoder for selecting one of the plurality of memory cells, and a Y decoder. It comprises a decoder, a sense amplifier for amplifying a signal read from the memory cell, and the like. The memory cell matrix is composed of data lines, word lines provided to cross the data lines, and memory cells provided at the intersections. The memory cell is composed of one MOS-FET and one capacitor. The drain terminal of the MOS-FET is connected to the data line, the source terminal is connected to one end of the capacitor, and the gate terminal is connected to the word line. Further, a controlled voltage is applied to the other end (here, referred to as a plate) of the capacitor. Reading and writing of the signal of the memory cell in these circuits are performed as follows. A certain word line voltage is set to a high potential, and a signal (hereinafter, referred to as a memory cell signal) stored in a memory cell is read out to a data line. The read signal is amplified by a sense amplifier, and a pair of data lines is set to a high potential and a low potential. At this time, the voltage of the data line is stored in the selected memory cell. Thereby, the same signal is written into the memory cell again. Thereafter, the potential of the selected word line is slightly lowered from the high potential. The amount of decrease in this potential is caused by the transfer gate (MOS-FET) of the memory cell in which the high potential is written.
It is about FF. Thereafter, the potential of the plate terminal is changed from a low potential to a high potential. As a result, among the memory cell signals, those having a high potential further increase the potential. On the other hand, a low-potential one does not change because its potential is held by the sense amplifier. As a result, the amount of signals stored in the memory cells is increased, and high S / N is achieved. However, the memory circuit has not been considered in terms of reducing power consumption.

[Problems to be solved by the invention]

2. Description of the Related Art In recent years, memory applications have been widened, and memory devices have been used in portable devices such as laptop computers. A memory for such an application also needs to operate on a battery, and thus requires a low power supply voltage and low power consumption of the memory. Some microcomputers use a power supply voltage of 5 V or less. When building a system with these LSIs, the conventional memory has a power supply voltage of 5 V,
Microcomputers and the like required pull-up resistors and the like. This reduces system packaging density and increases manufacturing costs. This problem is solved if there is a memory that operates at 5V or less (for example, 1V to 3V). Therefore, it is necessary to lower the power supply voltage of the memory. On the other hand, high integration of memories is still advancing, and along with that, the number of data lines to be charged / discharged at one time increases, which tends to increase power consumption. The increase in power consumption is due to DRAM
Of the information retention characteristics of the device, and an increase in noise inside and outside the chip, which causes a malfunction of the memory. Therefore,
It is necessary to reduce the power consumption of the memory. An object of the present invention is to significantly reduce the power consumption of a memory and to operate the memory at a low voltage such as a battery voltage.

[Means for Solving the Problems]

Still another object is to provide a memory capable of coping with at least two kinds of external power supply voltages with one basic chip. The purpose is to reduce the voltage amplitude of the signal used in the chip by using an on-chip voltage limiter. This can be achieved by reducing the voltage amplitude to the minimum size at which the sense amplifier operates. The voltage limiter can be switched between use and non-use by bonding or master slicing.
Products that can handle multiple external power supply voltages can be made from one basic chip.

[Action]

Power consumption can be reduced by reducing the voltage amplitude of a signal in a chip using a voltage limiter. In addition, since the charge stored in the memory cell is secured by writing from the plate of the memory cell and the voltage amplitude of the data line having a large parasitic capacitance is reduced, lower power supply voltage and lower power consumption can be achieved.

【Example】

Hereinafter, an embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a low power consumption memory chip and a power supply for operating the memory chip. Here, the power source is a battery. In FIG. 1, reference numeral 1 denotes a memory chip. MA denotes a memory array, which includes memory cells MC, data lines D and / D, word lines W, plate lines P, sense amplifiers SA, and the like. CC is a peripheral circuit,
It comprises an input / output interface circuit and a drive signal generation circuit for a memory array. This peripheral circuit includes a voltage limiter circuit. JP-A-58-70482 as a voltage limiter circuit
There is something as shown in the issue. RV is a reference voltage generation circuit,
Make several kinds of voltage between power supply voltage and 0V. This voltage is transmitted to a voltage limiter, amplified by current, and becomes a voltage used in the chip. A reference voltage generating circuit is also disclosed in Japanese Patent Application Laid-Open No. 58-70482. PAD1 and PAD2 are bonding pads, and here only power supply (Vcc, Vss) are shown. BW1 and BW2 indicate bonding wires, and L1 and L2 indicate outlines of package pins. B is a battery. The peripheral circuit uses the voltage created by the voltage limiter and the voltage input from outside the chip. Power consumption is reduced by lowering the voltage amplitude of the pulse signal using a voltage limiter. As described above, the memory array has a very large data line charge / discharge current. The voltage amplitude of the data line is large in order to secure the charge stored in the memory cell. The charge actually input to the memory cell is about 1/10 or less of the charge on the data line. That is, most of the charge is not used, but is consumed as useless charge / discharge current.
If the charge stored in the memory cell can be increased regardless of the voltage amplitude of the data line, the voltage amplitude of the data line can be reduced. Therefore, in the present embodiment, the voltage amplitude of the data line is reduced by increasing the accumulated charge irrespective of the voltage amplitude of the data line, thereby achieving low power consumption. As a method of increasing the accumulated charge, there is a method of increasing the capacitance of the capacitor of the memory cell. In addition, there is a method of increasing a stored charge by writing a memory cell signal from a plate terminal to a memory cell selected by a word line. As a result, the power consumption can be reduced while sufficiently securing the charge stored in the memory cell. As described above, according to this embodiment, the power consumption of the DRAM can be significantly reduced. As a result, the information holding characteristics can be improved and noise can be reduced. Therefore, malfunction of the DRAM can be eliminated. In addition, the DRAM can be operated with a battery, and the application to portable devices can be expanded. Here, the power source is a battery, but a voltage generated from a commercial power line may be used. Another embodiment of the present invention will be described with reference to FIG. This embodiment shows a method of reducing the data line voltage amplitude by using writing of a memory cell signal from a plate. FIG. 2A shows a memory chip, in which a case where 5 V is externally applied as a power supply voltage is shown.
The MOS-FET shown here is a P-channel MOS-FET (PMOS) with an arrow, and an N-channel MOS-FET (NMOS) without an arrow. MOS-FET threshold voltage is | 0.5
| Assume V. In FIG. 2A, reference numeral 1 denotes a memory chip. MA is a memory array and includes a plurality of data lines D ₀ , / D ₀ to
D _n , / D _n , a plurality of word lines W ₀ , W ₁ , plate wiring P ₀ , memory cell MC ₀ , sense amplifiers SA _{0 to} SA _n , data line precharge transistors Tp _{0 to} Tp ₃ , switch transistor Ty
Consisting of _{0 ~Ty 3.} Although only one plate wiring is shown here, it is provided in units of several to several tens of word lines.
Drive selectively. XD selects one of a plurality of word lines by an X decoder. YD selects one of a plurality of data line pairs by a Y decoder. Y ₀ to Y _n conveys the output signal of the Y decoder output signal line of the Y decoder. PD is a plate drive circuit for selectively driving a plurality of plate wirings. 2 is a data line precharge voltage generation circuit. In this circuit, a data line precharge voltage is generated using the reference voltage generated by the reference voltage generation circuit. This circuit is shown in FIG. 8 of JP-A-58-70482 and FIG. 12 of JP-A-62-121990. CD is a sense amplifier drive signal generation circuit, which drives the sense amplifier via sense amplifier drive signal lines CSP and CSN. IO is a data input / output line for transmitting a write signal to a memory cell and a read signal from a memory cell. DOB is an output amplifier that amplifies the signal read from the memory cell to generate an output signal Do. DiB is a data input buffer that receives an input signal Di from outside the chip and creates a signal to be written to a memory cell. The PC generates a signal for controlling the memory array, the X decoder, the Y decoder, the sense amplifier drive signal generation circuit and the like by a timing pulse generation circuit. Reference numeral 3 denotes a reference voltage generating circuit which generates several kinds of reference voltages used inside the chip from a power supply voltage of 5 V applied from outside the chip. here
We make 3 kinds of reference voltage of 4V, 3V, 2V. This circuit is shown in FIGS. 10 to 18 of Japanese Patent Application Laid-Open No. 58-70482. 4 and 5 are bonding pads, here for power supply (V
(cc, Vss) only. The reading operation of the circuit shown in FIG. 2A will be described with reference to the operation waveforms shown in FIG. Here it will be mainly described the reading operation of the memory cell MC _0. While the data line precharge signal / Φp is 5V, the data line is precharged to the data line precharge voltage Vdp (= 4V). At this time, the sense amplifier drive signal lines CSP, CS
N is also 4V. Therefore, the sense amplifier is off. After / Φp becomes 0V, one of the plurality of word lines is selected by the X decoder XD. Here is the 7V word line W ₀ is selected. As a result, a memory cell signal appears on each data line. When a high level signal to the memory cell MC ₀ (1) is accumulated data lines D ₀
Potential slightly increases from 4V. Next, the sense amplifier drive signal generation circuit CD sets CSP to 5V and CSN to 3V. Thereby operating the sense amplifier SA ₀ -SA _n, it amplifies the memory cell signal. At this time, D ₀ has a high level of 5V and / D ₀ has a low level of 3V. Thereafter, the potential of the plate P ₀ by a plate driving circuit PD is changed to 2V from 5V. The potential of the storage node N ₀ and the data lines at this time the selected memory cell is changed by capacitive coupling, but the potential of each node is restored to the original potential because it is held by the sense amplifier. Next, Y decoder
A pair is selected from a plurality of data lines by YD. Here, it is assumed that D ₀ and / D ₀ are selected. Thus the output signal Y ₀ is 5V next Y decoder, the memory cell signal is taken into the data input and output lines IO. The extracted memory cell signal is amplified by the output amplifier DOB and becomes an output signal Do. In the write operation, on the contrary, the data input buffer DiB
Input signals received by the, when the Y ₀ becomes 5V, the data input and output lines are written into the memory cell via the data line. After the input of the memory cell signal, the output is performed as described above, the potential of the word line W ₀ is 5V. Here the storage node N ₀ of the memory cell MC ₀ is 5V, the data lines D ₀ has a 5V transistor T ₀ is turned off. Then plate P ₀
Changes from 2V to 5V. This allows the memory cell MC
Storage node N ₀ of ₀ is boosted to approximately 8V from 5V. Then word lines W ₀ to 0V, the memory cell MC ₀ 8V is accumulated. After that, / Φp becomes 5V and the data line is precharged to 4V. CSP and CSN become 4V. However when a low level signal (0) is accumulated in the memory cell MC _0,
D ₀ when the sense amplifier is to be working is 3V, / D ₀ is 5V. Thus transistor T ₀ of the memory cell even if the word line is a 5V remains on. After this, the plate P ₀ goes from 2V
When changes to 5V, the potential of the storage node of the memory cell MC ₀ 3
A little to rise from V, but the potential of N ₀ returns to 3V because it is held by the sense amplifier. Next, the word line W ₀ is set to 0V
Next, the memory cell MC ₀ 3V is accumulated. In this embodiment, the plate potential of the non-selected memory cell is also changed. Thereby, the potential of the storage node of the unselected memory cell also changes. To illustrate this situation the potential change of the node N ₁ as an example. When a high level signal to N ₁ (1) is to have been accumulated during the standby memory, N ₁ has a 8V. Thereafter, when the plate is changed and 5V-2V-5V, N ₁ is 8V
It changes to -5V-8V. At this time, W ₁ is 0V, / D ₀ is 5V or 3V
In the transistor T ₁ of the memory cell is turned off, especially no problem. When the low level signal to N ₁ (0) is assumed to have been accumulated during the standby memory, N ₁ has a 3V. When the plate thereafter is changed as 5V-2V-5V, N ₁ is changed 3V-0V-3V. In this case W ₁ is 0V, / D ₀ is 5V or 3V, the transistor T ₁ of the memory cell is turned off, especially no problem.
By raising the low-level potential of the memory cell as in this embodiment, erroneous selection of an unselected memory cell due to a change in the potential of the plate can be prevented. As described above, according to the present embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, by reducing the voltage amplitude of a data line having a large parasitic capacitance and a large charge / discharge current and increasing the voltage amplitude of a plate having a small parasitic capacitance, power consumption can be reduced while securing a memory cell signal. Also, it is more efficient to increase the voltage amplitude of the plate as compared with the data line voltage amplitude. In this embodiment, the data line voltage amplitude is 1 V, and the charge / discharge current can be reduced to 1/5 as compared with the conventional 5 V amplitude. Data line voltage amplitude constitutes sense amplifier
Although it can be reduced to near the threshold voltage of the MOS-FET, considering operation stability, | Vtn | + | Vtp | <ΔVd (Vtn: threshold voltage of NMOS, Vtp: threshold voltage of PMOS, ΔVd: data line Voltage amplitude). The power consumption by driving the plate is as follows: Assuming an array of 256 word lines x 1024 data line pairs, the capacity of the data line that is charged and discharged at one time is 20.
In this embodiment, the potential at the time of precharging of the data line is set between the high potential and the low potential of the data line voltage amplitude. This can further reduce power consumption. The capacitor of the memory cell is usually made using a thin oxide film. Therefore, in this embodiment, the potential of the plate is set to a potential between the two types of accumulation potentials of the memory cells during standby of the memory. As a result, the electric field applied to the capacitor of the memory cell is reduced, and the reliability is improved. Further, in this embodiment, the memory cell signal is higher on the high level side than on the low level side. Therefore, the information retention characteristic and the α-ray soft error characteristic are improved. Another embodiment of the present invention will be described with reference to FIG. This embodiment also shows a method of reducing the data line voltage amplitude by using writing of a memory cell signal from a plate. This embodiment shows a case where the power supply voltage (Vcc) applied from outside the chip is 1.5V. The circuit configuration is the same as that of the embodiment shown in FIG. 2, but the operating voltage is different. Therefore, the outputs of the reference voltage generating circuit 3 are 1.2V, 0.9V, 0.6V. The same symbols as those in FIG. 2 indicate the same circuits. Assume that the threshold voltage of the MOS-FET is | 0.15 | V. The reading operation of the circuit shown in FIG. 3A will be described with reference to the operation waveforms shown in FIG. Again it will be mainly described the read-out operation of the memory cell MC _0. While the data line precharge signal / Φp is 1.5 V, the data line is precharged to the data line precharge voltage Vdp (= 1.2 V). At this time, the sense amplifier drive signal line CS
P and CSN are also 1.2V. Therefore, the sense amplifier is off. After / Φp becomes 0V, one of the plurality of word lines is selected by the X decoder XD. Here is the 2V word line W ₀ is selected. As a result, a memory cell signal appears on each data line. Memory cell MC ₀
High-level signal (1) the potential of the data line D ₀ When have been accumulated is increased slightly from 1.2V to. Next, CSP is 1.5 V and CSN is 0.9 by the sense amplifier drive signal generation circuit CD.
V. This sense amplifier SA ₀ ~SA _n is operated,
Amplify the memory cell signal. At this time, D ₀ is 1.
5V, / D ₀ is a low level of 0.9V. Thereafter, the potential of the plate P ₀ by a plate driving circuit PD is changed to 0.6V from 1.5V. The potential of the storage node N ₀ and the data lines at this time the selected memory cell is changed by capacitive coupling, but the potential of each node is restored to the original potential because it is held by the sense amplifier. Next, a pair of the plurality of data lines is selected by the Y decoder YD. Here, it is assumed that D ₀ and / D ₀ are selected.
Thus the output signal Y ₀ is 1.5V next Y decoder, the memory cell signal is taken into the data input and output lines IO. The extracted memory cell signal is amplified by the output amplifier DOB and becomes an output signal Do. In the write operation, the input signal taken by the data input buffer DiB the contrary is, when Y ₀ becomes 1.5V, the data input and output line, is written into the memory cell via the data line. Above manner, the input of the memory cell signals, after output is performed, the potential of the word line W ₀ is 1.5V. Here the storage node N ₀ of the memory cell MC ₀ is 1.5V, the data lines D ₀ is in the 1.5V transistor T ₀ is turned off. Then the potential of the plate P ₀ is changed to 1.5V from 0.6V. Thus storage node N ₀ of the memory cell MC ₀ is boosted to approximately 2.4V from 1.5V. Then word lines W ₀ to 0V, the memory cell MC ₀ 2.4V is accumulated. Thereafter, / Φp becomes 1.5V and the data line is precharged to 1.2V. Also, CSP and CSN become 1.2V. However when a low level signal (0) is accumulated in the memory cell MC _0, D ₀ when the sense amplifier is operated is 0.9
V, / D ₀ becomes 1.5V. Thus transistor T ₀ of the memory cell even if the word line is a 1.5V remains on.
Thereafter, when the plate P ₀ is changed to 1.5V from 0.6V, although the potential of the storage node of the memory cell MC ₀ slightly raised from 0.9V, the potential of the N ₀ to 0.9V because it is held by the sense amplifier Back. Then word lines W ₀ to 0V, the memory cell MC ₀ 0.0 V is stored. By the way, also in this embodiment, the plate potential of the non-selected memory cell is changed. Thereby, the potential of the storage node of the unselected memory cell changes. To illustrate this situation the potential change of the node N ₁ as an example. When a high level signal to N ₁ (1) is to have been accumulated during the standby memory, N ₁ has a 2.4V. After this, when the plate changes to 1.5V-0.6V-1.5V,
N ₁ changes from 2.4V-1.5V-2.4V. At this time, W ₁ is 0V, / D ₀ is 1.
In 5V or 0.9V, transistor T ₁ of the memory cell is turned off, especially no problem. Low-level signal to the N ₁ (0)
There standby of assuming that have been accumulated memory, N ₁ has a 0.9V. When the plate after which changes 1.5V-0.6V-1.5V, N ₁ changes the 0.9V-0V-0.9V. At this time, W ₁ is 0V, / D ₀
In 1.5V or 0.9V, transistor T ₁ of the memory cell is turned off, especially no problem. By raising the low-level potential of the memory cell signal as in this embodiment, erroneous selection of an unselected memory cell due to a change in the potential of the plate can be prevented. As described above, also in this embodiment, the voltage amplitude of the data line and the write voltage to the memory cell can be determined independently. Therefore, by reducing the voltage amplitude of a data line having a large parasitic capacitance and a large charge / discharge current and increasing the voltage amplitude of a plate having a small parasitic capacitance, power consumption can be reduced while securing a memory cell signal. Also, it is more efficient to increase the voltage amplitude of the plate as compared with the data line voltage amplitude. The data line voltage amplitude can be reduced to near the threshold voltage of the MOS-FET that constitutes the sense amplifier. However, considering operation stability, | Vtn | + | Vtp | <ΔVd (Vtn: NMOS
(Vtp: PMOS threshold voltage, ΔVd: data line voltage amplitude). Also in this embodiment, the potential at the time of precharging the data line is set between the high potential and the low potential of the data line voltage amplitude. This can further reduce power consumption. In addition, the potential of the plate is set to a potential between two kinds of storage potentials of the memory cell during standby of the memory. As a result, the electric field applied to the capacitor of the memory cell is reduced, and the reliability is improved. Further, the memory cell signal is higher on the high level side than on the low level side. Therefore, the information retention characteristic and the α-ray soft error characteristic are improved. According to this embodiment, the power supply voltage is 1.5V and the low power consumption DRAM is used.
Can be realized. Therefore, it is possible to realize a DRAM that operates on a battery during both standby and operation of the memory. Also, DRAM 1.
Operating at 5V makes it easy to switch between normal power and batteries. Therefore, the use of the DRAM can be expanded. Another embodiment of the present invention will be described with reference to FIG. This embodiment also shows a method of reducing the voltage amplitude of the data line by using the writing of the memory cell signal from the plate. This embodiment is different from the embodiment shown in FIG. 3 in that a plate wiring is provided for each word line. Other circuit configurations and operations are the same as those of the embodiment shown in FIG. Since the plate wiring is provided for each word line, the potential of the storage node of the memory cell connected to the unselected word line does not change even if the potential of the plate changes. That is, even if the voltage amplitude of the plate is made larger than the potential difference between the low-level potential of the memory cell signal and 0 V, an unselected memory cell does not enter the selected state. Therefore, the writing voltage from the plate can be made higher than in the embodiment shown in FIG. 3, and the storage voltage of the memory cell can be made higher than the power supply voltage. As described above, according to the present embodiment, the storage voltage of the memory cell can be further increased, and the information retention characteristic and the α-ray soft error characteristic can be improved.
Therefore, the power supply voltage can be easily reduced, which is effective for operating the memory at a low voltage. In the operation waveform of FIG. 4B, the lower potential of the data line is set higher than 0 V.
0 V and the high-level potential may be 0.6 V. However, in this case, it is necessary to lower the intermediate level of the word line voltage accordingly. FIGS. 5 to 9 show specific examples of the control circuit of the memory array unit used in the embodiment shown in FIGS. Although the case where the power supply voltage is 5V is shown here, the present invention can be applied to a case where the power supply voltage is 1.5V if the voltage relationship is changed. FIG. 5 shows a specific example of the X decoder. XD in FIG.
Reference numeral 1 denotes a decoder unit which receives an address signal and selects one word line, and W denotes a word line. A voltage VCH of 7 V is applied to the node 54. The signal Φx is a word line drive signal. The operation of the circuit shown in FIG. 5A will be described with reference to the operation waveforms shown in FIG. When the memory is idle, the decoder
The output node 52 of XD1 is at 0V. At this time,
[Phi ₁ is a 5V, the node 55 is 7V. Therefore, transistor _T51 is off, _T52 is on, and word line W is at 0V. After the signal / [Phi ₁ becomes to 0V, and the output node 52 of the decoder XD1 are address signals to the memory input 5
Let's say it's V. This causes node 55 to go to 0V and T ₅₁
Is on and _T52 is off. As a result, the signal Φx appears on the word line. At this time, Φx is 7V and the word line is
It becomes 7V. Thereafter, Φx drops to 5V, and the word line also goes to 5V. Output node 52 to 0V decoders XD1, then the signal / [Phi ₁ becomes 5V, the node 55 is 7V, the word line W becomes 0V. FIG. 6 is an example of a circuit for generating the word line drive signal Φx used in the circuit of FIG. The operation of this circuit will be described with reference to operation waveforms shown in FIG. Signal [Phi ₂ the transistor T ₆₂ when the 0V is turned on, T ₆₁ are turned off, the output node 62
It becomes 5V. Then [Phi ₂ the transistor T ₆₁ becomes a 5V is on, T ₆₂ is turned off, the node 62 by the capacitor C ₆₁
Boosted to 7V. If it then Φ ₂ returns to 0V node 62 is 5V
Becomes This produces a Φx signal. FIG. 7 is an example of a circuit for generating a 7V voltage VCH used in FIG. The pulse signal Φ ₃ is supplied to the capacitor C ₇₁ and the transistor T
_71, made by rectifying at T _72. The voltage is transistor _T73 ,
T _74, determined by the threshold voltage of T _75. FIG. 8 shows a specific example of the sense amplifier drive signal generation circuit. In FIG. 3A, CSP and CSN are sense amplifier drive signal lines. A ₈₁ is a differential amplifier, and Vr ₁ is a reference voltage (3 V) created by a reference voltage generating circuit. Vdp is a data line precharge voltage (4 V). This voltage is generated with reference to the reference voltage as described above. The operation of this circuit will be described with reference to operation waveforms shown in FIG. When the memory is idle, a signal /
Φp is 5V, Φsap is 5V, Φsan is 0V, CSP, CSN is 4V
Has been precharged. After Φp becomes 0V, the word line is selected, and a memory cell signal appears on the data line, Φsap becomes 0V and Φsan becomes 5V. CSP Thus transistors T _81, T ₈₂ is turned on is 5V, CSN becomes 3V. After that, Φsap becomes 5V, Φsan becomes 0V, / Φp becomes 5V, CSP, C
SN is precharged to 4V. FIG. 9 shows a specific example of the plate drive circuit. Fig In A ₉₁ is Sa働amplifier, Vr ₂ is the reference voltage made by the reference voltage generating circuit (2V), a 93 output node. The operation of this circuit will be described with reference to operation waveforms shown in FIG. During signal [Phi ₄ is 0V, the transistor T ₉₁ is turned on, T ₉₂ is output turned off has a 5V. When [Phi ₄ becomes 5V, T ₉₁ is turned off, T ₉₂ is output turned on becomes 2V. Then, Φ ₄
Becomes 0V and the output becomes 5V. FIG. 10 shows an embodiment of a memory chip in which a DRAM operating at 1.5 V can be used with a 3.3 V power supply. FIG. 10 (a) shows a case where a chip is mounted on a package.
By performing bonding selectively, for 1.5V power supply,
Shows a chip that can be switched for 3.3V power. In the figure, 101 is a memory chip. Reference numeral 103 denotes a memory array, and reference numeral 102 denotes a peripheral circuit including an input / output interface circuit and a timing pulse generation circuit for controlling the memory array. As the input / output interface circuit, for example, there is a circuit described on pages 997 to 999 of a data book of a 4-bit single-chip microcomputer of NEC Corporation. L is a voltage limiter that drops a voltage input from the outside to 1.5 V (Vcl) for internal use. 104 to 106
Is a bonding pad, 105 and 106 are for power supply, and 104 is for controlling a voltage limiter. Now, when using this chip with a power supply voltage of 1.5V, do as follows. Connect the bonding pad 106 to the power pin of the package. Here, it is assumed that the voltage limiter is turned off when the node 107 is at a low level, the output terminal becomes high impedance when the node 107 is at a high level, and is turned on when the node 107 is at a high level. Therefore, in this case the bonding pad
104 is connected to nowhere and kept open. In addition, the bonding pad 105 is also in an open state. As a result, a voltage of 1.5 V is applied to the memory array and peripheral circuits. When using with a power supply voltage of 3.3 V, do as follows. Connect the bonding pad 105 to the power pin of the package. Bonding pad 104 is also connected to the power supply pin, causing node 107 to go high. As a result, the voltage limiter is turned on. The bonding pad 106 is in an open state.
As a result, a voltage of 1.5 V dropped by the voltage limiter is applied to the memory array and peripheral circuits. As described above, according to the present embodiment, the circuit in the chip always operates at a constant voltage except for the input / output interface circuit, so that the speed and the power consumption can be made substantially constant. Therefore, the memory chip is easy to use for the user. Further, two types of products can be manufactured from one chip, and the manufacturing cost can be reduced. Since the products are separated by bonding, it is easy to adjust the number of products. In this embodiment, the ON / OFF of the voltage limiter is switched by bonding, but a fuse provided on a chip may be used. Alternatively, an input signal to a plurality of chips may be used, input to a logic gate provided in the chip, and control may be performed using the result. Note that, although a memory chip has been described as an example here, the circuits denoted by 102 and 103 may be a combination of a memory circuit and a logic circuit, or may be only a logic circuit. FIG. 10 (b) shows an embodiment in which the above power supply switching is performed in the Al master slice. In FIG. 10 (b), the Al master slice portion is indicated by switches SW1 and SW2. When using this chip with a power supply voltage of 1.5 V, the switches SW1 and SW
Connect both to the b side. As a result, a voltage is directly applied to the memory array and peripheral circuits from the bonding pads of the power supply. In addition, the voltage limiter turns off the input node 107 and turns off. When using the power supply voltage 3.3V,
Connect both SW1 and SW2 to a side. As a result, the input limiter 107 goes high and the voltage limiter is turned on.
Therefore, a voltage dropped to 1.5 V is applied to the memory array and peripheral circuits by the voltage limiter. According to this embodiment also, since the circuits in the chip are operated at a constant voltage, the speed and the power consumption can be made substantially constant, and the chip is easy to use for the user. Further, two types of products can be manufactured from one chip, and the manufacturing cost can be reduced. Since the product is divided by the Al master slice, the number of bonding pads can be reduced, and the chip area can be reduced. FIG. 10 (c) shows an embodiment of a memory chip which can be used even when the power supply voltage continuously changes from 1.5V to 3.3V. In this embodiment, the characteristics of the voltage limiter are as shown in FIG. That is, even if the power supply voltage Vcc changes from 1.5V to 3.3V, the output is kept constant at 1.0V. Further, the memory array and peripheral circuits are operated at 1V. In this embodiment, the memory array and peripheral circuits are operated at a voltage of 1 V dropped by the voltage limiter between the power supply voltages of 1.5 V to 3.3 V. Therefore, the memory chip can be operated regardless of the magnitude of the power supply voltage between 1.5 V and 3.3 V. Since the chip always operates at 1V, the speed and power consumption can be kept almost constant. Therefore, the memory chip is easy to use for the user. Further, since there is no need to turn on and off the voltage limiter, the chip configuration is simplified. Here, 1.5V corresponds to one battery, and 3.3V corresponds to two batteries connected in series, so that a device using one battery or a device using two memory chips can be operated.

【The invention's effect】

According to the present invention, the power consumption of the DRAM can be significantly reduced.
In particular, since the voltage amplitude of the data line during the operation of the sense amplifier can be significantly reduced, the data line charge / discharge current can be reduced. Further, the memory cell signal can be increased by writing the memory cell signal from the plate. Therefore,
The information retention characteristics of the DRAM and the α-ray soft error characteristics can be improved. Therefore, lower power supply voltage and lower power consumption of the DRAM can be achieved, and the DRAM can be operated with a battery.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIGS. 2 (a) and 2 (b) are circuit diagrams and operation waveforms of one embodiment of the present invention, and FIGS. 4 (a) and 4 (b) are circuit diagrams and operation waveforms of an embodiment of the present invention, and FIGS. 5 (a) and 5 (b) to 9 are diagrams. (A) and (b) are specific examples of a control circuit of a memory array unit used in the embodiment shown in FIGS. 1 to 4, and FIGS. 10 (a) to (d) are circuits of an embodiment of the present invention. FIG. Description of symbols MA: memory array, XD: X decoder, YD: Y decoder, PD: plate drive circuit, CD: sense amplifier drive signal generation circuit, 2: data line precharge voltage generation circuit, DOB …… Output amplifier, DiB …… Data input buffer, PC …… Timing pulse generator, 3 …… Reference voltage generator, P ₀ … Plate wiring, D ₀ / D ₀ , D _n , / D _n …… Data Line, W ₀ , W ₁ … word line, SA ₀ , SAn… sense amplifier, CSP, CSN… sense amplifier drive signal line.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-3161 (JP, A) JP-A-63-76007 (JP, A) JP-A-61-163655 (JP, A) (58) Investigation Field (Int.Cl. ⁶ , DB name) G11C 11/407

Claims (3)

(57) [Claims] 1. A plurality of dynamic memory cells provided at predetermined intersections between a plurality of complementary data lines and word lines, and output to corresponding complementary data lines provided for each of the plurality of complementary data lines. A memory array having a sense amplifier for amplifying a signal of the dynamic type, wherein each of the plurality of dynamic memory cells includes a transistor and a capacitor having one end connected to the transistor. The other ends of the capacitors of the plurality of dynamic memory cells are commonly connected to a plate electrode, and after the sense amplifier amplifies the voltage between the corresponding complementary data lines to a first voltage amplitude, the plate electrode is connected to the first electrode. The voltage is changed to a second voltage amplitude larger than the voltage amplitude, and the semiconductor device receives an external power supply voltage, A voltage limiter circuit that outputs an internal power supply voltage having a smaller absolute value voltage than the external power supply voltage, wherein the first voltage amplitude and the second voltage amplitude are smaller than the external power supply voltage by the voltage limiter circuit. A semiconductor device characterized by being limited to: 2. The semiconductor device according to claim 1, wherein the semiconductor device operates by supplying a first external power supply voltage to the voltage limiter and supplying the internal power supply voltage output from the voltage limiter to the memory array. A second operation mode in which a second external power supply voltage having a power supply voltage lower than the first external power supply voltage is directly supplied to the memory array to operate; the first operation mode and the second operation mode include: 2. The semiconductor device according to claim 1, wherein said semiconductor device is selectively switched by a bonding pad provided on said semiconductor device or by a master slice. 3. The semiconductor device according to claim 2, wherein said internal power supply voltage and said second power supply voltage are substantially equal.