JP2639147B2 - Layout verification device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout verification device for LSI design and printed circuit board design, and more particularly to a crosstalk verification device.

[Conventional technology]

For verification of crosstalk in integrated circuits and circuit printed circuit boards, designers have traditionally laid out low-output impedance transistors that are easily affected by crosstalk and high-output impedance nodes that are easily affected by crosstalk. The pattern is analyzed while visually tracking the output wiring, and the combination of signal lines where crosstalk is likely to occur and the location of occurrence are estimated.

[Problems to be solved by the invention]

In the above-described conventional verification, a combination of signal lines in which crosstalk is likely to occur manually and a place where the crosstalk easily occurs in the LSI and the circuit printed board are presumed, so that the burden on the designer is extremely large.

In addition, the problem was often overlooked due to manual estimation.

It is anticipated that verification of crosstalk will become more and more difficult due to future large-scale LSI and fine patterning.

The present invention has been made in view of such a point,
The purpose is to automatically estimate a combination and a place where signals are likely to cause crosstalk from the layout pattern data, and to display the location of the combination to easily verify the crosstalk. Is to get

[Means for solving the problem]

In order to achieve such an object, the present invention provides a transistor size extracting means for extracting a transistor size of all transistors by referring to a design rule file from layout pattern data to be verified, and a transistor of a transistor which is likely to be affected by crosstalk. A transistor which sets a size, compares the transistor size extracted by the transistor size extracting means with the reference size set by the reference size setting means, and sets a transistor which is liable to be affected by crosstalk outside the reference size. And a logic simulation is performed by inputting a simulation waveform through first comparison and extraction means for extracting the output wiring and a waveform input means for inputting the simulation waveform, and executes circuit connection information. A high impedance node extracting means for extracting the a high impedance node Ri,
Cross-reference extraction means for extracting a node on the layout pattern corresponding to the high impedance node from the layout pattern data, and a capacity calculation rule for calculating the capacitance of the node on the high impedance layout pattern extracted by the cross reference extraction means And a capacitance standard value for setting a capacitance standard value necessary for extracting only nodes that are easily affected by crosstalk based on the capacitance value obtained by the capacitance calculation unit. A second comparing step of comparing the capacity value calculated by the setting means and the capacity calculating means with the capacity standard value set by the capacity standard value setting means, and extracting only nodes having a capacity value smaller than the capacity standard value; Extracting means, and each of the extracted means by the first comparing and extracting means and the second comparing and extracting means. Calculating means for calculating any of the area where the lines overlap and the part to be parallel wiring, the wiring length, and the capacitance, and the standard value setting means for setting the standard value of the area to be compared, the wiring length or the capacitance, Error output means for comparing the value of the area, wire length or capacitance calculated by the calculation means with the standard value set by the standard value setting means and outputting information such as coordinates to a file as an error if the value is out of specification; And error display means for visually displaying an error location.

[Action]

In the present invention, a logic simulation input waveform and a capacitance standard value are set in order to set a reference size for extracting a transistor which is easily affected by crosstalk and to extract a high impedance node which is easily affected by crosstalk. For the case where the output wiring that is more susceptible to crosstalk and the high-impedance wiring that is more susceptible to crosstalk overlap each other and are parallel wiring, the area of the overlapping portion where crosstalk can occur, The standard value of the wiring length of the parallel wiring part or the capacitance between wirings is set.

On the other hand, the output wiring of the transistor which is likely to be affected by the crosstalk is automatically extracted from the layout pattern data, a logic simulation is executed from the circuit connection information to extract a high impedance node, and a cross reference with the layout pattern is obtained. , Nodes that are susceptible to crosstalk are extracted, and locations where crosstalk occurs with respect to portions where wires that are susceptible to crosstalk and wires that are susceptible to crosstalk overlap and where portions are parallel wires Any of the area, the wiring length, and the capacitance is calculated in order to estimate the error, a portion where the calculated value is equal to or larger than the set value is erroneously displayed, and the erroneous portion is visually displayed on the layout pattern. As a result, the crosstalk can be easily verified.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a layout verification apparatus according to the present invention, and FIG. 2 is a flowchart for explaining the operation of the apparatus shown in FIG.

FIG. 3 is a plan view of a transistor in a layout pattern, FIG. 4 is a graph showing an example of a transistor size distribution of transistors included in the layout pattern, and FIG. 5 is a node N1 having a high impedance.
6 (a) and 6 (c) and FIGS. 6 (b) and 6 (d) are circuit diagrams showing the output wiring of a transistor which is liable to be affected by crosstalk, the portion where the wiring having high impedance overlaps, and FIG. 7 is a plan view and a sectional view showing an example of a portion to be a wiring, and FIG. 7 is a plan view showing an example of error output.

In FIG. 1, a transistor as shown in FIG. 3 is recognized from the verified layout pattern data of file 1 using the design rule of file 2, and the transistor size (gate length L, gate width W) of the transistor is recognized. Is extracted.

In FIG. 4, if the transistor sizes of all the transistors in the layout pattern are distributed as shown in FIG. 4, a transistor having a low output impedance that is liable to be affected by crosstalk, that is, a transistor having a large transistor size W / L, It is included in a portion (area SA) larger than the value A in FIG.

Therefore, in FIG. 1, a reference size A is necessary to extract a transistor which is likely to be affected by crosstalk, a reference size file 5 exists, and a reference size setting means 4 for setting the reference size A is provided. is there. Further, there is a first comparison / extraction unit 6 for extracting a transistor which is likely to be affected by crosstalk exceeding A by referring to the reference size A set by the reference size setting unit 4 and extracting an output wiring thereof.

Further, based on the circuit connection information a of the file 7, the simulation waveform b is input from the file 9 by the waveform input means 8 for inputting the simulation waveform, and the logic simulation is executed, and the high impedance as shown in FIG. There is a high-impedance extracting means 10 for extracting a node (wiring) N1 to be (Z), and a node on a layout pattern corresponding to the node extracted by the high-impedance extracting means 10 is extracted from the layout pattern data by using the design rule of file 2. And a capacity calculating means 13 for calculating the capacity of the node on the layout pattern extracted by the cross-reference extracting means 11 based on the capacity calculating rule of the file 12. . Then, regarding the node extracted by the cross reference extraction unit 11,
Based on the calculated value obtained by the capacity calculating means 13, a capacity standard value B of the file 15 for extracting only nodes that are susceptible to crosstalk is required. There is a setting means 14, a capacity standard value setting means
With reference to the capacity standard value B set by 14, only those whose values calculated by the capacity calculation means 13 are smaller than the capacity standard value B are extracted, and the second comparison and extraction means 16 for extracting the node is extracted.
There is.

Further, an output wiring of a transistor which is likely to be affected by the crosstalk extracted by the first comparison and extraction means 6;
As shown in FIG. 6, the nodes that are susceptible to the crosstalk extracted by the second comparison and extraction means 16 determine the location where the crosstalk occurs with respect to the overlapping part or the parallel wiring part. There is a calculating means 18 for calculating any of the area, the wiring length, and the capacitance for estimation. Here, regarding the area and the wiring length, the area of the part where the wirings overlap each other and the wiring length of the part which becomes the parallel wiring are obtained, and the wiring interval, the wiring film, Information such as thickness is obtained and converted into one of the area and the wiring length. If a plurality of overlapping portions or parallel wiring portions exist in two wirings, the data is converted into one of them and totalized. Further, regarding the capacitance, after obtaining the area of the overlapping portion and the wiring length of the parallel wiring portion, the capacitance value is obtained by referring to the design rule of the file 2 and the calculation rule of the file 17. At this time, the capacitance value C0 is generally represented by C0 = εS / d (ε: dielectric constant, S: facing area, d: facing distance). For an overlapping part, the facing area S is the area of the overlapping part, Since the facing distance d corresponds to the thickness of the insulating film, the dielectric constant ε and the insulating film thickness are obtained by referring to the design rule of the file 2. As for the part to be the parallel wiring, the facing area S corresponds to the product of the parallel wiring length and the wiring thickness, and the facing distance d corresponds to the distance between the wirings. Get to see. If there are a plurality of overlapping portions and a plurality of portions serving as parallel wirings, the respective calculated capacitance values are summed.

Furthermore, the standard value of the area to be compared, the standard value of the wiring length,
Calculation means 18 calculates one of the standard values C of the area standard value, the wiring length standard value and the capacitance standard value set by the standard value setting means 19 for setting any standard value C of the capacitance standard value in the file 20. The error output means 21 outputs information such as the coordinates of the error location to a file 22 by comparing with any of the determined area, wiring length and capacitance, and if the value exceeds the standard value, the error output means 21 is provided. As shown in (1), there is an error display means 23 for visually displaying on a layout pattern.

In FIG. 3, GL denotes a gate wiring, DF denotes a drain diffusion region, and SF denotes a source diffusion region. In FIG. 5, T1 and T5 are clock input terminals, T2 to T4 are signal input terminals, T6 is an output terminal, T7 and T8 are power terminals, and GND is a ground. Further, FIG. 6A shows an overlapping portion LW of the wirings LA and LB, and FIG. 6B shows VI B-VI of FIG. 6A.
FIG. 6 (c) is a sectional view taken along the line VID-VID of FIG. 6 (c), and FIG. 6 (c) shows a parallel portion LP of the wirings LA and LB. 50 is an insulating film, 41 and 51 are substrates, L1 is an insulating film thickness, L2 is a wiring length of the parallel portion LP, L3 is a distance between wirings, and L4 is a wiring film thickness. 7 (a) and 7 (b) show an overlapping portion and a parallel portion of the wirings LA and LB.

Next, the operation of the apparatus shown in FIG. 1 will be described with reference to the flowchart shown in FIG.

In advance, the reference size A, the capacitance standard value B for extracting nodes susceptible to crosstalk, the area standard value, the wiring length standard value or the capacitance standard value C are set, and a simulation waveform is input. (Step 24).

Then, the transistor size is automatically extracted from the layout pattern data of file 1 by referring to the design rule of design rule file 2 (step 2).
5), file 5 where this value was set in step 24
The reference size A is compared with the reference size A by the first comparison and extraction means 6, and output wirings exceeding A are extracted (step 26). At the same time, a logic simulation is performed using the circuit connection information a and the simulation waveform b input in step 24, and a node that becomes high impedance (Z) is extracted by the means 10 (step 27). Further, with respect to the node having the above-described high impedance (Z), a node on the layout pattern corresponding to the node is extracted from the layout pattern data of the file 1 (step 28), and the capacity of the node is calculated by the means 13 (step 28). Step 29). Further, the capacity standard value B set in step 24 and the capacity value calculated in step 29 are compared by the second comparison and extraction means 16 to extract nodes smaller than B (step 30).

After that, the area, wiring length, or capacitance of a portion where the respective wirings extracted in Steps 26 and 30 overlap and a portion which becomes a parallel wiring are calculated (Step 3).
1) A value outside the standard values (area C, standard length C, standard value C of the capacitance) set in step 24 is output to the error file 22 as an error (step 32).

Next, referring to the error file 22, the error portion is displayed in a visible manner by superimposing the error portion on the layout pattern to be verified (step 33), thereby facilitating finding the crosstalk error portion.

〔The invention's effect〕

As described above, the present invention extracts the transistor sizes of all the transistors by referring to the design rule file from the layout pattern data to be verified, sets the transistor sizes of the transistors that are likely to be affected by crosstalk, and sets the extracted transistors. Compares the size with the set reference size, extracts transistors that are likely to be affected by crosstalk outside the reference size, extracts their output wiring, inputs simulation waveforms, executes logic simulation, and executes circuit connection information. A node having a higher impedance is extracted, a node on the layout pattern corresponding to the node having a higher impedance is extracted from the layout pattern data, and a capacity of the extracted node on the layout pattern having the higher impedance is stored. Calculated based on the calculation rule, set the capacity standard value necessary to extract only nodes susceptible to crosstalk based on the calculated capacity value, and set the calculated capacity value Compare with the capacitance standard value, extract only nodes with a capacitance value less than the capacitance standard value, and calculate the area and wiring of the part where the respective wirings extracted based on the reference size and the capacitance standard value overlap and the part that becomes parallel wiring Calculate either the length or the capacitance, set the area to be compared, the wiring length or the standard value of the capacitance,
The area, wiring length or capacitance value calculated by the calculating means is compared with the set standard value, and information such as coordinates is output to a file as a nonstandard error as an error, and the error location is displayed in a visible manner. By doing so, it is possible to automatically estimate the location of the occurrence of crosstalk, which has the effect of reducing the crosstalk verification load.

Also, there is an effect that even a designer with little experience can easily verify crosstalk.

Furthermore, there is no need for design revision for crosstalk, which is effective in shortening the design period and reducing development costs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a layout verification apparatus according to the present invention, FIG. 2 is a flowchart for explaining the operation of the apparatus shown in FIG. 1, FIG. 3 is a plan view of a transistor in a layout pattern, FIG. 4 is a graph showing an example of a transistor size distribution of transistors included in the layout pattern, FIG. 5 is a circuit diagram showing an example of a circuit having a node having high impedance, and FIGS. 6 (a), (c) and (c). FIGS. 7B and 7D are plan views and cross-sectional views showing examples of the output wiring of a transistor which is liable to be affected by crosstalk, a portion where high impedance wiring overlaps, and a portion which becomes parallel wiring, and FIG. It is a top view which shows an example. 1 ... layout pattern data file, 2 ... design rule file, 3 ... transistor size extraction means, 4 ... transistor reference size setting means,
5 ... Transistor reference size file, 6 ...
... first comparison and extraction means, 7 ... circuit connection information file,
8: simulation waveform input means, 9: simulation input waveform file, 10: high impedance node extraction means, 11: cross reference extraction means,
12 ... capacity calculation rule file, 13 ... capacity calculation means,
14: Capacity standard value setting means, 15: Capacity standard value file, 16: Second comparison and extraction means, 17: Calculation rule file, 18: Calculation means, 19: Standard value setting means, 20: …
Standard value file, 21 ... Error output means, 22 ... Error file, 23 ... Error display means.

Claims (1)

(57) [Claims] 1. A transistor size extracting means for extracting transistor sizes of all transistors by referring to a design rule file from layout pattern data to be verified, and a transistor reference size setting for setting a transistor size of a transistor which is easily affected by crosstalk. Means, comparing the transistor size extracted by the transistor size extraction means with the reference size set by the reference size setting means, extracting a transistor which is likely to be affected by crosstalk outside the reference size, and outputting the extracted transistor. A simulation waveform is input by a first comparison and extraction unit for extracting wiring and a waveform input unit for inputting a simulation waveform, and a logic simulation is executed. High-impedance node extracting means for extracting a high-impedance node; cross-reference extracting means for extracting a node on a layout pattern corresponding to the high-impedance node from layout pattern data; Capacitance calculation means for calculating the capacitance of the node on the layout pattern that becomes high impedance based on the capacitance calculation rule, and only nodes that are easily affected by crosstalk based on the capacitance value obtained by the capacitance calculation means Capacity standard value setting means for setting a capacity standard value required for extraction, and a capacity value calculated by the capacity calculating means, and comparing the capacity standard value set by the capacity standard value setting means, Second comparison for extracting only nodes having a capacitance value less than the capacitance specification value Calculation means for calculating any one of an area, a wiring length, and a capacitance of a portion where the respective wirings extracted by the first comparison and extraction means and the second comparison and extraction means overlap and become a parallel wiring. A standard value setting means for setting a standard value of an area, a wiring length or a capacitance to be compared; a value of the area, wiring length or capacitance calculated by the calculating means and a standard set by the standard value setting means A layout verification apparatus comprising: an error output unit that outputs information such as coordinates to a file by comparing a value with a value that is out of specification as an error; and an error display unit that displays an error location in a visible manner.