JP2637734B2 - Output circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, particularly to an output circuit of a logic integrated circuit.

[Conventional technology]

Generally, an output circuit of a logic integrated circuit is required to be driven by sending its output signal to another logic integrated circuit.

Logic integrated circuits receiving output signals have different current values required for driving depending on their characteristics. Therefore, when the driving current of the output circuit is small and the driven logic integrated circuit requires a large current, it is driven. When the logic integrated circuit to be driven is not driven, and conversely, when the drive current of the output circuit is large and the driven logic integrated circuit requires a small current, the current flows excessively and wastes power consumption and the like.

Therefore, the conventional output circuit is individually designed by the logic integrated circuit.

[Problems to be solved by the invention]

Since the output circuits of the above-described conventional logic integrated circuits are individually designed by the logic integrated circuits, the use of the output circuits is fixed, and the number of products increases. That is, there is no versatility.

An object of the present invention is to provide an output circuit of a logic integrated circuit which is versatile with respect to an output load and does not waste output current.

[Means for solving the problem]

An output circuit of a logic integrated circuit according to the present invention includes a buffer for inputting a signal inside the logic integrated circuit, directly connecting an output to an output load, and driving the output load, and an input side and an output side of the buffer, respectively. A first EXOR gate circuit for detecting the difference between the input side signal and the output side signal as a change in the output signal due to the output load, and the buffer input side connected to two input circuits directly and via a delay circuit. At least one logic circuit comprising: a plurality of EXOR gate circuits; a latch circuit using the output side of the EXOR gate circuit as a latch control signal and the output side of the first EXOR gate circuit as a data signal; At least one three-state buffer connected to the buffer in parallel with the buffer using the output side of the logic circuit as an enable signal and varying output driving capability. And a plurality of logic circuits each having a different delay time of the delay circuit.

〔Example〕

The details of the present invention will be described below with reference to the accompanying drawings with reference to the embodiments.

FIG. 1 is a circuit diagram of an embodiment of an output circuit according to the present invention.
The figure is a timing chart showing the operation of FIG. In FIG. 1, a buffer 1 receives a signal A inside a logic integrated circuit 14 as an input, is connected to an output load via an output terminal 4, and
The input of the EXOR gate circuit 5 is connected to the input side and the output side of the buffer 1, respectively. The inputs of the EXOR gate circuits 7 and 9 are connected to the input side of the buffer 1 and the input side of the buffer 1, respectively.
6 and 8, connected to the other inputs, the latch control signals of the latch circuits 10 and 11 are connected to the outputs of EXOR7 and 9, respectively, and the data signal is connected to the output of the first EXOR gate circuit 5. The outputs of the latch circuits 10 and 11 are connected to the enable signals of the three-state buffers 2 and 3, respectively, and the buffer 1 and the three-state buffers 2 and 3 are connected in parallel.

Next, the operation of the output circuit of this embodiment will be described. As shown in FIG. 1, the signal A in the logic integrated circuit 14 drives the output load via the buffer 1 and the output terminal 4. The delay time of buffer 1 generated at this time is expressed by EX as shown in FIG.
The signal is detected by the OR gate circuit 5 and used as the signal C on the output side of the EXOR gate circuit 5. Here, as the delay time td ₁ buffer 1 is large, the width of the high level of the output side of the signal C of the EXOR gate circuit 5 increases. Also, as shown in FIG.
EXOR gate circuit having delay times td ₆ and td ₈ using delay circuits 6 and 8 when the level of signal A on the input side of buffer 1 changes
Signals D and E on the output side of 7, 9 are generated, and first, the output value of the EXOR gate circuit 5 is set to a through state in the latch circuits 10 and 11. Subsequently, an EXOR gate circuit having delay times td ₆ and td ₈
The latch circuits 10 and 11 latch the output value of the EXOR gate circuit 5 according to the falling timing of the signals D and E on the output side of 7, 9.

When the high level is latched in the latch circuits 10 and 11, that is, when the delay of the output signal due to the output load is large, the three-state buffers 2 and 3 maintain the enabled state, the output driving capability is increased, and the To give a large current. When the low level is latched in the latch circuits 10 and 11, that is, when the delay of the output signal due to the output load is small, the three-state buffers 2,
3 is in a disabled state, the output driving capability is reduced, and a small current is externally applied. As a result, the output drivability until the next signal level change on the input side of the buffer 1 is set.

In the above description, as an example, two sets of a three-state buffer for varying the driving capability and a logic circuit for generating the enable signal are used. However, the present invention is not limited to this, and at least one three-state buffer is used. The use of a state buffer and a logic circuit that generates its enable signal enables a logic integrated circuit that has a different output drive capability setting range depending on the number of three-state buffers, is versatile with respect to output load, and has no waste in output current. Is obtained, and the object of the present invention can be achieved.

〔The invention's effect〕

As is apparent from the above description, the present invention has a versatility with respect to an output load by having a circuit for detecting a change in an output signal due to an output load, and a circuit for varying output drive capability, and An output circuit of a logic integrated circuit without waste of current can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of FIG. 1 ... buffer, 2,3 ... three-state buffer, 4
... output terminals, 5, 7, 9 ... EXOR gate circuits, 6, 8 ... delay circuits, 10, 11 ... latch circuits, 12, 13 ... logic circuits.

Claims (2)

(57) [Claims] 1. A buffer for inputting a signal inside a logic integrated circuit and directly connecting an output to a load and driving an output load thereof, and an input side and an output side of the buffer with the input side and the output side of the buffer as inputs. A first EXOR gate circuit for detecting a difference between side signals as a change in an output signal due to an output load, and one EXOR gate circuit in which the input side of the buffer is connected to two input circuits directly and via a delay circuit And at least one logic circuit comprising: a latch circuit which uses the output side of the EXOR gate circuit as a latch control signal and the output side of the first EXOR gate circuit as a data signal; And at least one three-state buffer connected to the buffer in parallel with the buffer as an enable signal and varying output driving capability. Output circuit. 2. The output circuit according to claim 1, comprising a plurality of said logic circuits, wherein said delay circuits have different delay times.