JP2602731B2 - A device that tracks certain data to update a secondary database - Google Patents

Description

The present invention relates to an apparatus for updating a secondary database of a redundant processor in a process control system, and more particularly, to an apparatus for updating a secondary database of a redundant processor in a process control system.
An apparatus for tracking changes in predetermined data of a primary database in preparation for a subsequent update of a secondary database.

[Problems to be solved by conventional technology and invention]

As described and claimed in U.S. Patent No. 4,133,027 issued to JA Hogan on January 2, 1979 and U.S. Patent No. 4,141,066 issued to Y. Keiles on February 20, 1979. A process control system having a backup process controller includes a backup controller having a dedicated random access memory (RAM) and a dedicated read only memory (ROM). The backup controller is essentially idle and can therefore perform some background task, but in general,
It does not perform tasks directly related to the process control function. If a failure is detected in one of the primary process controllers, the data stored in the RAM of the failed controller must be transferred to the RAM of the backup controller so that the operation of the primary controller must be executed. No. Such a system is called a 1: N redundant system.

According to the present invention, in a 1: 1 redundant system, when predetermined information is stored in a primary memory of a primary control device, a device that captures and stores the information is provided. The secondary database of the secondary device (i.e., the secondary or backup control device) is updated periodically with information stored in the device of the present invention, the update being performed by the CPU, i.e., the primary process. It is performed to constrain the processor performance of the controller, i.e., to use a minimum amount of time without penalizing performance. The device of the present invention captures only changed information (and then updates it), so that the primary CPU, ie, the microprocessor, can be used more efficiently and the update process can be performed more frequently and in real time. It becomes possible to do. Thus, when a failure condition occurs, the time required for the secondary controller to take over the function of the failed primary controller is substantially reduced to a minimum.

[Means for solving the problem]

Accordingly, the present invention provides an apparatus for collecting certain information stored in a primary database for subsequent updates of a secondary database. The process control system includes a primary processor connected to a primary memory via a bus. The primary processor transfers the data to be stored to this primary memory. The device of the present invention connected to the bus collects predetermined data in the data being transferred at the same time as the data is transferred to the primary memory. The predetermined data collected by the device is then transferred to the backup controller to update the database of the backup controller. The apparatus includes a storage element for storing the collected data. The logic device controls the operation of the device, including the collection of predetermined data. The control device of the device of the present invention transfers predetermined data stored in the storage element to the backup control device.

In the method of the present invention, the primary control device executes the control function, writes information representing the result of the execution to the database of the primary control device, and simultaneously writes a portion of the information written to the database to the database. The information is written to the storage means for temporarily storing, and the information written to the storage means for temporarily storing is transferred to the backup control device.

Therefore, an object of the present invention is to provide an apparatus for collecting predetermined information.

Another object of the present invention is to provide an apparatus for collecting predetermined information stored in a primary database.

It is yet another object of the present invention to provide an apparatus for collecting certain information stored in a primary database for subsequent updates of a secondary database.

These and other objects of the present invention will become more apparent upon consideration of the following description and accompanying drawings.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same parts, and the drawings form a part of the present invention.

FIG. 1 will be described. FIG. 1 shows a block diagram of a process control system 10 having a plurality of redundant controllers utilizing the apparatus of the present invention, and more specifically, a primary controller 30 and a backup controller. A functional block diagram of the redundant process control device 20 including the secondary control device 40 is shown. In the following description, among the two control devices, 30 is designated as a primary control device and 40 is designated as a secondary control device, but the control devices have bidirectionality.
That is, both the primary and redundant (ie, secondary) controllers can operate completely as primary or secondary controllers. The primary and secondary labels attached here are
It is merely a means of identification and explanation.

Process control system 10 is a plant control network
A data highway 12, including and connected to 11, allows a plurality of process controllers to be attached to the data highway 12. Primary controller 30
Is a primary processor 31, a primary memory 32, and a primary tracking device.
Including 33. The secondary control device 40 includes a secondary processor 41, a secondary memory 42, and a secondary tracking device 43. Primary processor
31 and the secondary processor 41 are connected to the data highway 12, respectively. The primary processor 31 has its primary memory 32
And the primary processor 33, and the secondary processor 41 is connected to its secondary memory 42 and to the secondary tracking device 43.
The process control device 20 includes various input units including an analog input unit (A / I), an analog output unit (A / O), a digital input unit (D / I), and a digital output unit (D / O), and outputs. The inputs and outputs are coupled and their inputs and outputs indicate the current information, i.e. the current status, and various valves, pressure switches, pressure gauges, pressure gauges, used to control the process of the process control system. Connected to a thermocouple, etc. The plant control network 11 was established on August 19, 1986 by RAHenz
and may be of the type described in U.S. Pat. No. 4,607,256 issued to el and assigned to the same assignee as the present application. Although not shown, it is clear that various analog input / output and digital input / output are connected to the primary processor 31 and the secondary processor 41 via suitable interface devices. The tracking devices 33 and 43, which are the devices of the present invention, will be described in more detail below. Before describing the tracking devices 33 and 43, a system utilizing the device of the present invention will be described before the tracking devices 33 and 43 are described to make the function and operation of the tracking device easier to understand.

In the process control device 20, the determination as to which control device 30, 40 should be primary or secondary is made based on the download control personality from the plant control network 11 (that is, command information). At that point, one of the controllers 30, 40 becomes the primary controller,
The other plays the role of the secondary control device, but in FIG. 1, the control devices 30 and 40 of the process control device 20 need to be described by way of example, so that the primary control device 30 and the secondary control device Identified as 40. However, it will be understood that the primary controller could be the controller 40, and similarly, the secondary controller could be the controller 30. After determining the primary / secondary roles of the control devices 30 and 40 in this way, the primary control device 30
It executes control processing algorithms including reading input data from valves, pressure gauges, etc., performing predetermined calculations, and outputting the results. The data is also stored in the primary memory 32. The primary memory 32 includes a tracking memory (or a tracking RA).
There is an area designated as M). The writing to this area, ie, the tracking RAM, is followed by the primary tracking device 33. The primary tracking device 33 stores the predetermined data in its own internal storage device (not shown) in a predetermined format, shown here as a packet, simultaneously with the writing to the tracking RAM. When the primary processor 31 completes its processing function for a predetermined time interval, the primary tracking device 33
By transmitting a control signal to the secondary tracking device 43, the transfer of the data stored in the primary tracking device 33 to the secondary tracking device 43 is started. Some control information, ie, header information, byte counts, data types, etc., are also transferred by the primary processor 31. Therefore, the secondary processor 41 is a secondary tracking device
Retrieving the data stored in 43, generating necessary information from the information packet stored in the secondary tracking device 43,
The secondary memory 42 is updated. Secondary processor 41 receives the packets, performs integrity tests and returns the results of those tests to primary processor 31, retrieves data values, and identifies the data values in information packets in secondary memory 42. The address is calculated for storage at the assigned address. By performing the update of the secondary memory in this manner, the primary CPU (that is, the CPU of the primary processor 31) is
(Not shown)), there is no performance penalty for writing the tracking memory, so the bandwidth of the primary processor 31 is effectively extended. CPU used in processors 31, 41
Is selected from the Motorola 68000 series in a preferred embodiment.

The primary controller 30 and the secondary controller 40 are connected via three media, namely, the data highway 12 and the primary tracking device.
A link 13 between the secondary tracking device 33 and the secondary tracking device 43 and an input / output link (not shown. This link is used to interface with A / I, A / O, D / I and D / O. (This is a path to which the primary processor 31 and the secondary processor 41 are connected). Through these communication paths,
The primary controller 30 can verify that the secondary controller 40 is present and in operation, and that the secondary controller has determined that it (ie, the controller designated as secondary) is in the primary state ( That is, the primary controller can be tested for operation to determine when to take the mode).

FIG. 2 will be described. FIG. 2 shows the allocation of time used by the primary processor 31. In the system according to the preferred embodiment of the present invention, one cycle is defined as a time period of one second and is divided into eight sub-cycles. At each sub-cycle, the processor executes a predetermined algorithm as described above (represented as point processing in FIG. 2). The time required for point processing is less than the time of a subcycle. When the point processing is completed, the primary processor 31 sends the tracking data to the secondary controller 40.
(Represented as DBA data transfer in FIG. 2). As can be readily seen from this time frame diagram, the data stored in the database of secondary controller 40 is one step (ie, one subcycle) later than the data stored in the database of primary controller 30. . (In systems where writes to the primary memory are written to the secondary memory each time, the primary and the secondary maintain the same database. However, errors, ie, failures during transmission of all bytes, Is likely to occur, the secondary will have a subset of bytes, i.e., mismatched data.) In the system of the present invention, as mentioned earlier, the secondary , But one step behind the data in the primary database.

FIG. 3 will be described. FIG. 3 shows the primary memory 32
A partial memory map is shown. This includes scan data including actual values of the input / output unit read from a valve, a pressure gauge, or the like. The portion indicated as the configuration data includes information indicating the selected option, the arrangement state of the points, the type of the algorithm being executed, and the like. The part shown as process data to be backed up contains the result of the algorithm. Also included is information to indicate various functions in progress, such as various timers being set, various alarms being set. The area of memory designated as DBA data is the area of primary memory 32 (ie, RAM) allocated as "tracking memory".
Writing to this area of the primary memory 32 is performed by the primary tracking device 33.
(Also referred to herein as tracking, following or capturing). On the other hand, the data collected by the tracking device 33 takes the form of a predefined packet, which will be described further below.

FIG. 4 will be described. FIG. 4 shows the format of a packet generated by the primary tracking unit 33 in the preferred embodiment of the present invention. The upper data strobe value and the lower data strobe value indicate the value of the least significant address bit, and the four most significant address bits can be secured by the layout of the tracking memory. A tracking memory packet is constructed for each write (byte or word) to the tracking memory, but only while memory tracking is required. One of the key features of the primary tracking device 33 is that there is no performance penalty when writing to the tracking memory. The method of transferring changes to the primary database from the primary controller 30 to the secondary controller 40 utilizing the apparatus of the present invention is described in further detail in the above-referenced related applications.

FIG. 5 will be described. FIG. 5 shows the primary control device.
Thirty block diagrams are shown, and a block diagram of the preferred embodiment of the primary tracking device 33 is shown. The primary processor 31 is connected to a primary memory 32 via a primary controller bus 301, also referred to herein as a local bus. The primary tracking device 33 is also connected to the local bus 301. First RAM32
The data terminal D of 0 is connected to the data line of the local bus 301. The data terminal D of the second RAM 330 is connected to a multiplexer (MU
X) 310, the first input terminal of the MUX 310 is connected to the data line of the local bus 301, and the second input terminal of the MUX 310 is connected to the address line of the local bus 301.
A counter 351 for sequentially counting addresses of the first RAM 320 and the second RAM 330 is connected to a first input terminal of the MUX 352, and a second input terminal of the MUX 352 is connected to an address line of the local bus 301. Token bus controller (TBC) 3 that controls communication between the primary tracking device 33 and the secondary tracking device 43
53 is connected to the local bus 301. An interface device 354 connected to the TBC 353 is also connected to the link 13 and forms an interface between the TBCs. TBC353 of the preferred embodiment of the present invention is Motorola MC68824Token-P
assing Bus Controller.

The tracking data packet is stored in the RAMs 320 and 330 of the primary tracking device 33. The three word packets are not stored sequentially, but in a column format. The primary tracking device 33
Packets are stored based on a counter 351 of the primary tracking device which increments by one each time a packet is stored. This counter 351 can be read by the primary processor 31 to determine the amount of data to be transferred. During transfer of data stored in RAM320,330, TBC353
(Ie TBC of primary and secondary trackers)
Passes the data so that the data is stored in RAM (not shown) of the secondary tracking device. As described above, the structure of the secondary tracking device 43 is the same as the structure of the primary tracking device. The control logic 355 is connected to the local bus 301 and includes a logic 357 for generating control signals SEL1, SEL2, CONT1, etc. Depending on the function to be performed, they either track (collect or capture) the data being written to the primary memory 32 by the primary processor, or the data from the RAM 320, 330 First, depending on whether
Or the second input terminal is selected. Local bus 30
A CPU 356 connected to 1 is also included in the control logic 355 and coordinates control of the tracking device with the primary processor 31.

FIG. 6 will be described. FIG. 6 shows a detailed block diagram of the structure of the storage elements RAMs 320 and 330 of the preferred embodiment of the present invention. MUX310 is MUX1 311 and MUX2 3
12 and MUX3 313. The first RAM320 is RA
The second RAM 330 is composed of MD1 321 and RAMD2 322.
It is composed of MA1 331, RAMA2 332, and RAMA3 333. Each RAM 321,322,331,332,333 of the preferred embodiment has 32
KX8 bit RAM. Thus, RAMD1 321 and RAMD2
Reference numeral 322 stores a 16-bit data value (shown in FIG. 4). RAMA1 331 and RAMA2 332 store 16-bit address values, and RAMA3 333 stores the third word of the packet, namely,
The three address bits and the upper / lower strobe bits are stored. A predefined area of primary memory 32 (in the preferred embodiment, storage locations 170000 to 19FFFF, H
X) stores the data to be captured. Primary processor 3
When 1 is writing to this area of memory, the primary tracker 33 also captures its data and address and
RAMD1 321, RAMD2 322,
RAMA1 331, RAMA2 332 and RAMA3 333 store in the first words respectively. This memory is called "wide memory". Only 37 bits are used, 16 bits of data and 19 bits of address, and two control strobes (strobe UDS and LDS) are used to indicate whether a word or byte has been modified in primary memory. )is required. The wide memory is addressed by the 15-bit address counter 351 during this time. The value of the counter 351 is incremented by one for each wide writing. As described above, wide writing is sequentially performed on the wide memory 37 bits at a time. The counter is initialized to zero by the CPU 356 forming part of the control logic 355. Also
The CPU 356 can read the value of the counter 351. When data collection is complete (ie, at the end of the point processing time slot), the primary processor 31
It notifies that the transfer to the secondary control device 40, that is, the secondary tracking device 43, should be started. The transfer is performed by the TBC 353. TBC empties RAM in the form of 16-bit wide words ("narrow read"). Use the address space (1COOOO to 1EFFFF) when addressing RAM in a narrow format. Since this space occupies an odd width of RAM, three banks of 16-bit wide address space are required. However, one of those banks (1EOOOO
To 1EFFFF) have significant data only in the lower byte. The secondary tracker's TBC receives the data and its RAM
"Narrow writing" is performed. When all data has been transferred, counter 351 is reset and the next sub-cycle begins. During the next sub-cycle, the control logic of the secondary tracker begins to empty its RAM contents and duplicates the data contents stored in primary memory 32 by storing the data in secondary memory 42. .

A preferred embodiment of the present invention, not shown,
As a method for protecting memory access, a parity check is used. It will be apparent to those skilled in the art that other forms of memory protection may be utilized without departing from the scope of the invention.
That is not described here.

While the above is considered to be a preferred embodiment of the invention, it will be apparent that many modifications and variations can be made without departing from the essential spirit of the invention.
It is therefore intended that the following claims cover all such modifications and variations as fall within the true scope of the invention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a process control system having a redundant controller, FIG. 2 is a diagram showing a time allocation defining one cycle of the controller, and FIG. 3 is a preferred embodiment of the present invention. FIG. 4 shows a partial memory map of the primary memory of the example controller, FIG. 4 shows a packet format of data captured in a preferred embodiment of the present invention, and FIG. 5 shows a preferred implementation of the primary tracking device. A block diagram of the primary controller, with particular emphasis on the example, FIG.
FIG. 2 is a block diagram showing a storage element according to a preferred embodiment of the present invention. 10 Process control system, 20 Process control device, 30 Primary control device, 31 Primary processor, 32
… Primary memory, 33… primary tracking device, 40… secondary control device, 41… primary processor, 42… secondary memory, 43…
Secondary tracking device, 301: primary control device bus, 310: multiplexer, 320: first RAM, 330: second RAM, 35
1… Counter, 352… Token bus controller, 354…
... Interface device, 355 ... Control logic, 356 ... CP
U.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-177666 (JP, A) JP-A-56-153460 (JP, A) JP-A-61-118848 (JP, A) JP-A-63-118 231652 (JP, A) JP-A-51-60422 (JP, A)

Claims (2)

(57) [Claims] 1. A process controller connected to a primary memory via a bus and having a primary controller for transferring data to be stored in the primary memory, wherein the process controller transfers the data to the primary memory simultaneously with the transfer of the data to the primary memory. A tracking device for tracking predetermined data of the transferred data, the database of the backup control device needing to be updated; a) storage means for storing the collected predetermined data; and b) storage thereof. Control logic means connected to the control means for controlling the operation of the tracking device including the collection of the predetermined data; and c) a predetermined logic means connected to the storage means and the control logic means and stored in the storage means. A tracking unit for tracking data for updating a database of the backup control device, comprising: control means for transferring data to the backup control device. 2. A process control device having a primary control device and a backup control device, each having its own processor and its own memory, and transferred from the processor of the primary control device to the primary memory via a bus. Of predetermined data is tracked simultaneously and continuously to update the memory of the backup controller,
A tracking device connected to the bus, comprising: a) storage means for storing the predetermined data; and b) control logic connected to the storage means for controlling writing of the predetermined data to the storage means. And c) control means connected to the storage means and the control logic means for transferring predetermined data stored in the storage means for storage in a backup memory of a backup control device. A tracking device that tracks data that updates a database of a backup control device connected to the bus.