JP2690044B2 - Power supply - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a power supply device that converts AC power into DC power and switches the DC power to supply power to a load.

[Prior Art] FIG. 20 shows a conventional power supply device (Japanese Patent Application No. 64465 of 1991).
No.) circuit diagram. Hereinafter, the circuit configuration will be described. This circuit uses power MO as a switching element.
It is equipped with transistors Q ₁ and Q ₂ that are SFETs. The source of transistor Q ₁ is connected to the drain of transistor Q ₂ . Transistors Q ₁ and Q ₂ have diodes D ₁ and
D ₂ are respectively connected in anti-parallel. This diode D ₁ , D ₂
Can be replaced by a reverse diode that is parasitic between the drain and source of the power MOSFET. The cathode of diode D ₃ is connected to the drain of transistor Q ₁
The anode of D ₃ is connected to the cathode of the diode D _4, the anode of the diode D ₄ is connected to the source of the transistor Q _2. The drain of the transistor Q ₁ is, one end of the capacitor C ₂ is connected, the other end of the capacitor C ₂ is connected to one end of the capacitor C _3, the other end of the capacitor C ₃ is connected to the source of the transistor Q ₂ . Transistors Q ₁ and Q ₂
A load circuit Z is connected between a connection point A of B and a connection point B of capacitors C ₂ and C ₃ . The connection point A of the transistors Q ₁ and Q ₂ is connected to one end of the AC power supply V _s . AC power supply V _s
The other end of the diode is connected to the diode D ₃ , through the inductors L ₁ and L ₂ .
It is connected to the connection point of D ₄ . The capacitor C ₁ is connected between the connection point of the inductors L ₁ and L ₂ and one end of the AC power supply V _s . The inductor L ₁ and the capacitor C _{1 form} an AC filter.

The first rectangular wave signal s ₁ is input between the gate and source of the transistor Q _{1 and} the gate of the transistor Q ₂
Between the source, the first rectangular wave signal s ₁ is a high level low level when the second rectangular wave signal s ₂ to the first rectangular wave signal s ₁ is a high level when the low level It has been entered. As a result, the transistors Q ₁ and Q ₂ are alternately turned on / off.

First, when the transistor Q ₁ turns on while the AC power supply V _s is in a positive half cycle, the inductor L ₂ , the diode D ₃ ,
Inductor from AC power supply V _{s in the} path through transistor Q ₁
A current flows through L ₂ , and the current value increases with a slope proportional to the instantaneous value of the input AC voltage V _in . At this time, the transistor Q ₁ also functions as a switching element for the inverter, and a current flows from the capacitor C ₂ to the load circuit Z via the transistor Q ₁ .

Then, when transistor Q ₁ turns off, inductor L ₂ ,
Diode D ₃ , capacitor C ₂ , load circuit Z, AC power supply V _s
The energy of the inductor L ₂ is released through the inductor L ₂ , the diode D ₃ , the capacitors C ₂ and C ₃ , the diode D ₂ , and the AC power supply V _s through the inductor L ₂ and the capacitor L _2.
Charge C ₂ and C ₃ . At this time, the transistor Q ₂ is on, and the capacitor C ₃ to the load circuit Z and the transistor
A current flows through the load circuit Z in the opposite direction to the above through a path passing through Q ₂ .

Thus, in the positive half cycle of the AC power supply V _s , the transistor Q ₁ serves as a switching element for the chopper and a switching element for the inverter, and the transistor Q ₂ functions only as a switching element for the inverter.

Next, when the AC power supply V _s is in the negative half cycle and the transistor Q ₂ is turned on, the AC power supply V _s , the transistor Q ₂ ,
In the path through diode D ₄ and inductor L ₂ ,
A current flows through L ₂ , and the current value increases with a slope proportional to the instantaneous value of the input AC voltage V _in . At this time, the transistor Q ₂ also functions as a switching element for the inverter, and a current flows through the load circuit Z from the capacitor C ₃ through the load circuit Z and the transistor Q ₂ .

Next, when the transistor Q ₂ is turned off, the AC power supply V _s , the load circuit Z, the capacitor C ₃ , the diode D ₄ , the inductor L ₂
The energy of the inductor L ₂ is released through the path passing through the AC power supply V _s , the diode D ₁ , the capacitors C ₂ , C ₃ , the diode D ₄ , and the inductor L ₂ , and the capacitor L
Charge C ₂ and C ₃ . At this time, the transistor Q ₁ is on, and from the capacitor C ₂ via the transistor Q ₁ ,
A current is passed through the load circuit Z in the opposite direction to the above.

As described above, in the half cycle in which the AC power supply V _s is negative, the transistor Q ₂ functions as a switching element for the chopper and a switching element for the inverter, and the transistor Q ₁ functions only as a switching element for the inverter.

Therefore, in the above circuit, the switching element for the inverter also serves as the switching element for the chopper and is configured with a small number of elements, which has the advantages of low power loss and a simple circuit configuration. Also,
In the above circuit, since the transistors Q ₁ and Q ₂ alternately act as switching elements for the chopper and the inverter every half cycle of the AC power supply V _s , the stress per switching element is reduced. Since there is an advantage and the power loss of the switching elements (transistors Q ₁ and Q ₂ ) is balanced, for example, the heat radiation structure may be the same. In addition, switching elements (transistors
Since Q ₁ and Q ₂ ) operate as switching elements for choppers and inverters, it is not necessary to separately provide a chopper drive circuit, and the drive circuit configuration is simplified. The input current distortion can be reduced by inserting an AC filter composed of the inductor L ₁ and the capacitor C ₁ between the AC power supply V _s and the inductor L ₂ to make the input current I _in continuous. The input current I _in to the input voltage V
_Since a sine wave with the same phase as in can be created, the input power factor is almost 1.

In the above circuit, the load circuit Z is, for example,
A circuit as shown in FIGS. 21 (a) to 21 (c) is used. The circuit shown in FIG. 9A is a resistive load R, which is composed of, for example, an incandescent lamp. The circuit shown in FIG. 1B is a discharge lamp lighting circuit. For example, an inductor L ₃ for current limiting and resonance is connected in series to _a power supply side terminal of _a hot cathode discharge lamp la such as a fluorescent lamp, and a non-power supply is used. A capacitor C ₄ for resonance and preheating current conduction is connected in parallel between the side terminals. With preheating current flows through the filaments through a capacitor C ₄ during start of the discharge lamp l _a, a high voltage is generated across the discharge lamp l _a a series resonance of the inductor L ₃ and capacitor C _4, a discharge lamp l _a Is lit up. In the circuit shown in FIG. (C), and further connected in parallel a capacitor C ₅ for resonance to the power supply side terminal of the discharge lamp l _a,
Resonance is strengthened.

[Problems to be Solved by the Invention] In the above-described conventional example, when the load circuit Z is in an unloaded state, for example, when the resistive load R shown in FIG. ), when the disconnection discharge lamp l _a is disengaged or filaments shown in (c), the power in the load circuit Z is not consumed. This unloaded transistor
If Q ₁ and Q ₂ continue to operate, the AC power supply V _s means that the chopper circuit is operating.
Power is supplied from V _s . Since this electric power is not consumed in the load circuit Z, all the electric power is stored in the capacitors C ₂ and C ₃ .
Therefore, the charging voltage V _DC of the capacitor C _2, C ₃ rises indefinitely, a capacitor C _2, C ₃ in a pressure-over is destroyed. Further, the circuit elements such as the transistors Q ₁ and Q ₂ and the diodes D _{1 to} D ₄ may be destroyed due to the breakdown voltage being exceeded. Furthermore, a high voltage is generated before the device is destroyed, which is not preferable in terms of safety.

In order to avoid the element breakdown in the no-load state as described above and to prevent the generation of high voltage from a safety point of view, turn off the transistors Q ₁ and Q ₂ completely when detecting no-load. I'm fine. However, in this case, the load circuit Z becomes in the rest state, and the resistive load R is reconnected in the circuit shown in FIG. 21 (a), or the circuit shown in FIG.
For example, when re-attached by replacing the discharge lamp l _a in the circuit (c), the detection becomes difficult. Therefore, even if the load is remounted from the no-load state and the load circuit R recovers to the state in which power can be consumed, it is difficult to supply power to the load again. In this case, in order to restart the load, it is necessary to open and close the AC power supply V _s , which is the main power supply, once.

The present invention has been made in view of such a point,
The purpose is to prevent the rise of the capacitor voltage when there is no load in the power supply device that also serves as a switching element in the chopper circuit and the inverter circuit, and to prevent the load from re-installing from the no-load state. It is to make it easy to restart.

[Means for Solving the Problems] FIG. 1 is a circuit diagram showing the basic configuration of the present invention. In the circuit of the figure, the AC power source V _s
Of the power source polarity of No. 2, the no-load detection means 2 detects the no-load state of the load Z, and the detection output SGN, NL of each detection means 1, 2.
Are supplied to the switch driving means 3, and the driving signals S ₁ and S ₂ for the transistors Q ₁ and Q ₂ are generated by the switch driving means 3. The other circuit configuration is the same as the conventional example shown in FIG.

In this circuit, the power source polarity of the AC power source V _s and the switching element controlling the input chopper have a one-to-one correspondence. That is, the number of switching elements whose inputs can be controlled is one for each power supply polarity of the AC power supply V _s .
When the power source polarity of the AC power source V _s is positive (V _in > 0), the transistor Q ₁ can control the input,
Q ₂ has no control over the input. On the contrary, when the power supply polarity of the AC power supply V _s is negative (V _in <0), the transistor Q ₂ can control the input, but the transistor Q ₁ can control the input. Therefore, the switch driving means 3 stops the input controllable switching element and operates the input controlless switching element in accordance with the power supply polarity detected by the power supply polarity detecting means 1. Specifically, when the power source polarity of the AC power source V _s is positive (V _in > 0), the operation of the transistor Q ₁ is stopped and the transistor Q ₂
To work. On the contrary, the polarity of the AC power supply V _s is negative (V
_{When in} <0), the transistor Q ₁ is activated and the transistor Q ₂ is deactivated. In this way, by stopping the operation of the input controllable switching element, the power input from the AC power supply V _s is stopped and the capacitor
It is possible to prevent the voltage V _DC of C ₂ and C _{3 from} rising abnormally.
Further, since the switching element that does not control the input is operated, the no-load detection means 2 can easily detect the re-mounting of the load.

[Operation] Hereinafter, the operation of the circuit shown in FIG. 1 will be described more specifically. The detection output SGN of the power source polarity detecting means 1 is at "High" level when V _in > 0, and at "Low" level when V _in <0. Further, the detection output NL of the no-load detecting means 2 is, for example, "High" level in the no-load state, and is "Low" level otherwise. The switch driving means 3 is composed of, for example, a logic circuit as shown in FIG. In the figure, s ₁ is a rectangular-wave oscillation signal for driving the transistor Q ₁ , and s ₂ is a rectangular-wave oscillation signal for driving the transistor Q ₂ , and these are oscillators built in the switch driving means 3. Created by.

Detection output NL is "Low" level of the no-load detector 2, that is, when not in no-load state, the output of the OR gate G _3, G ₄ are both "High" level, the detection output SGN power polarity detection means 1 AND gates G ₅ and G ₆ are both enabled to pass signals, the oscillation signal s ₁ is supplied as the drive signal S ₁ of the transistor Q ₁ , and the drive signal of the transistor Q ₂ is supplied.
The oscillation signal s ₂ is supplied as S ₂ . Next, when the detection output NL of the no-load detecting means 2 is at the “High” level, that is, in the no-load state, the outputs of the OR gates G ₃ and G ₄ are AND gates.
G _1, the same as the output of G _2. At this time, AND gates G ₁ , G
_Since the "High" level detection output NL of the no-load detection means 2 is supplied to _one input of ₂ , the outputs of the AND gates G ₁ and G ₂ depend on the detection output SGN of the power supply polarity detection means 1. Decided. Detection output SGN is "High" level of the power supply polarity detection means 1, that is, when the power supply polarity is V _in> 0, the output of the AND gate G ₂ becomes a "High" level, the oscillation as a drive signal S ₂ of the transistor Q ₂ The signal s ₂ is provided. But AN
Since the output of D gate G ₁ is at "Low" level, AND gate
First input of G ₅ is always "Low" level, the transistor Q ₁
The drive signal S _{1 of} is always at "Low" level. This allows
The input controllable transistor Q ₁ stops operating, and the input controllable transistor Q ₂ operates. Then, the detection output SGN is "Low" level of the power supply polarity detection means 1, the words when the power supply polarity is V _in <0, the output of the AND gate G ₁ is becomes a "High" level, the drive signal of the transistor Q ₁ S _The oscillation signal s ₁ is supplied as ₁ . However, since the output of the AND gate G ₂ is at “Low” level, one input of the AND gate G ₆ is always at “Low” level, and the drive signal of the transistor Q ₂ is
S ₂ is always at “Low” level. As a result, the input controllable transistor Q ₂ stops operating and the input controllable transistor Q ₁ operates.

FIG. 3 is an operation waveform diagram of the above circuit. As shown in the figure, when the detection output NL of the no-load detection means 2 is at "Low" level, the drive signals S ₁ and S ₂ are output regardless of the detection output SGN of the power supply polarity detection means 1. When the detection output NL of the no-load detection means 2 becomes "High" level after time t ₀ , the detection output SGN of the power supply polarity detection means 1 becomes "Hig.
h "when the level is stopped driving signals S _1," Low "when the level is stopped driving signal S _2. Therefore, the time t ₀ after the load circuit Z is a no-load state, input controllable switching The element stops operating and the switching element whose input cannot be controlled operates.For convenience of illustration, the periods of the drive signals S ₁ and S ₂ are expressed as long in FIG. It goes without saying that the period is sufficiently shorter than that shown.

FIG. 4 shows the locations where the power polarity detection means 1 detects the power polarity. To detect the power supply polarity, for example, (a) the current of the AC power supply V _s , (b) the voltage of the AC power supply V _s , (c) the chopper current, and (d) the voltage of the inductor L ₂ for the chopper (for example, Detected by the secondary winding),
(E), (e ') diode D ₃ , D ₄ current, (f),
(F ') diode D _3, the voltage of the _{D 4, (g), (} g') transistors Q _1, Q ₂ of current, (h), (h ' ) transistors Q _1, Q ₂ of the voltage, (i) , (I ′) load loop current (non-load side) and the like may be detected. However,
(A), (c), (e), (e '), (g),
Since (g '), (i), and (i') detect current, they cannot be detected in the no-load state where no current flows, and can be detected only in the loaded state. Further, (d) is for detecting a voltage, but since no voltage is generated in the secondary winding unless a current flows through the inductor L ₂ , (d) can be detected only in a loaded state. On the contrary, (h) and (h ') cannot be detected in the loaded state. This is because in the loaded state, the voltage of the switching element becomes a rectangular wave synchronized with the drive signals S ₁ and S ₂ , and has nothing to do with the power supply polarity. However, if there is no load and no current flows,
The voltage of the switching element varies depending on the polarity of the power supply. Therefore, it is necessary to use (b), (e), or (e ') as the polarity detection location, or to detect the polarity at different locations in the loaded state and the unloaded state.

5 (a) and 5 (b) show the detection points of the no-load state by the no-load detection means 2. In order to detect the no-load state, for example, (j), (j ') transistors Q ₁ ,
Q ₂ of current, (k), (k ' ) voltages of the transistors _{Q 1, Q 2, (l} ) the load loop current (load side), (m),
(M ') load loop current (non-load side) is detected by the (n) current of the electrolytic capacitor, (o) the voltage of the electrolytic capacitor, (p) a load circuit Z of the inductor L ₃ of the voltage (e.g., the secondary winding ), (Q) The voltage at one end of the load may be detected. These can detect not only the no-load state but also the reloading of the load. This is because, in the present invention, one of the switching elements continues to operate, and when the load is reattached, a current flows through the loop including the operating switching element, the load and the electrolytic capacitor, and the voltage changes accordingly. Therefore, the reloading of the load can be detected.

In addition to the above, the non-loaded state can be detected by detecting the temperature of the load, the temperature of the switching element, or the like with a thermal sensor or the like. Further, when the load is the discharge lamp l _a can detect a no-load condition in the presence or absence of light by an optical sensor.

[First Embodiment] FIG. 6 is a circuit diagram of a first embodiment of the present invention. In this embodiment, the power source polarity is detected by the voltage of the diode D ₄ . Moreover, the no-load state is detected by detecting the load loop current by the current transformer CT connected in series with the load circuit. When the discharge lamp l _a is disengaged as shown by the broken line in FIG. 6, the points A and B are open, and no matter how the transistors Q ₁ and Q ₂ are controlled,
Power cannot be consumed between points A and B. In this state, when the power supply polarity is V _in > 0, the transistor Q ₁ is stopped and the transistor Q ₂ is operated. When V _in <0, the transistor Q ₁ is operated and the transistor Q ₂ is stopped. Since the input chopper is not controlled and the power supply from the AC power supply V _s is stopped, it is possible to prevent the voltage of the capacitors C ₂ and C _{3 from} rising abnormally. Besides, when the discharge lamp l _a is reseated, as a power supply capacitor C ₂ or C _3, the point A via the transistor Q ₁ or Q ₂ in operation, current flows between the B. Therefore, when the load is reattached, a voltage is generated between the points X and Y on the secondary side of the current transformer CT, which makes it possible to detect reattachment of the load.
In return the drive signal Q _1, Q ₂ the operation of the loaded conditions, it is possible restart of the load. However, the present invention does not limit the method of shifting from the detection of the reloading of the load to the restart operation. Also, in the normal operating condition that is not in the no-load state, the voltage is always generated between the points X and Y on the secondary side of the current transformer CT, but in the no-load state, the voltage between the points X and Y is zero. Therefore, the unloaded state can be detected by this.

FIG. 7 (a) is a circuit diagram of the no-load detecting means 2 used in this embodiment. When the load is attached, an AC voltage is generated between the points X and Y on the secondary side of the current transformer CT. It rectifies by the diode bridge DB and charges the capacitor C ₆ . The voltage of capacitor C ₆ is
When the reference voltage obtained by R ₃ and R ₄ is compared with the comparator CP ₂ and the voltage of the capacitor C ₆ becomes higher,
The output NL of the comparator CP ₂ becomes “Low” level. When the no-load condition is reached, the capacitor C ₆ is discharged, and when the voltage of the capacitor C ₆ becomes lower than the reference voltage obtained by the voltage dividing resistors R ₃ and R ₄ , the output NL of the comparator CP ₂ becomes “H”.
igh becomes "level. It should be noted that, in the unloaded state, in order to speed up the discharge of the capacitor C _6, to the discharge resistor to the capacitor C ₆ may be connected in parallel, may be set smaller the capacitance of the capacitor C ₆ .

FIG. 7B is a power source polarity detecting means 1 used in this embodiment.
FIG. Power source polarity of AC power supply V _s is positive (V _in ＞
In the case of 0), since a reverse high voltage is applied to the diode D ₄ , this is divided by the resistors R ₁ and R ₂ , and the capacitor C ₇ is charged by the voltage at the voltage dividing point J. Capacitor
The voltage of C ₇ is compared with the reference voltage obtained by the voltage dividing resistors R ₅ and R ₆ by the comparator CP ₁ , and when the voltage of the capacitor C ₇ becomes higher, the output SGN of the comparator CP ₁ becomes “Hi
gh "level. Also, the power supply polarity of the AC power supply V _s is negative (V
_{When in} <0), a low forward voltage is applied to the diode D ₄ , so that the capacitor C ₇ is discharged, and the voltage of the capacitor C ₇ is higher than the reference voltage obtained by the voltage dividing resistors R ₅ and R _6. When it becomes low, the output SGN of the comparator CP ₁ becomes “Low” level. In addition, in FIGS. 7A and 7B, V
_CC is a power supply voltage for the control circuit, and is composed of a DC low voltage.

By applying the detection outputs NL and SGN obtained by the above circuits to the logic circuit shown in FIG. 2, the drive signals S ₁ and S ₂ shown in FIG. 3 can be obtained.

[Second Embodiment] FIG. 8 is a circuit diagram of a second embodiment of the present invention. In the present embodiment, the power source polarity is detected by the input voltage V _in from the AC power source V _s . Further, it detects the current of the transistor Q ₁ in the current transformer CT, the transistor Q ₂
The no-load state is detected by detecting the current of the resistor R ₀ . When the discharge lamp l _a is disconnected as shown by the broken line in FIG. 8, the inductor L ₃ and the capacitor C are placed between points A and B.
It is in the state of being connected via ₅ , and a resonance current flows in this series resonance circuit. However, most of the current is reactive current, and power is only slightly consumed by the resistance component of the circuit element or circuit pattern. Therefore, when also the discharge lamp l _a is disengaged in this circuit, the load circuit is unloaded condition.

In this embodiment, when no load condition is detected,
When the power supply polarity is V _in > 0, the transistor Q ₁ is stopped and the transistor Q ₂ is operated. When V _in <0, the transistor Q ₁ is operated and the transistor Q ₂ is stopped.
Immediately after reversing the polarity of the power supply, current flows through the load circuit for a certain period of time, after which no current flows. The relationship between the input voltage V _in of the AC power supply V _s , the current i _L of the inductor L ₃ and the voltage V _C5 of the capacitor C ₅ is as shown in FIG. First, V _in
If only transistor Q ₂ operates when> 0, no current will flow from the input, but capacitor C ₃ to capacitor
Current flows through C ₅ , inductor L ₃ , and transistor Q ₂ . When the voltage V _C5 of the capacitor C ₅ is equal to the voltage of the capacitor C ₃ (-V _C3), then no current flows. Next, when the power source polarity is reversed and only the transistor Q ₁ is operated when V _in <0, a current flows from the capacitor C ₂ through the transistor Q ₁ , the inductor L ₃ , and the capacitor C ₅ . When the voltage V _C5 of the capacitor C ₅ is equal to the voltage V _C2 of the capacitor C _2, then no current flows.

As described above, in the circuit configuration of the present embodiment, the presence of the capacitor C ₅ causes a current to flow for a fixed period each time the power source polarity is inverted, so that it is not possible to detect reattachment of the load only by the presence / absence of current in the switching element. . Therefore, in this case, after reversing the polarity of the power source, it is necessary to stop the detection operation for a certain period of time during which the current flows, or detect the average value of the current flowing through the switching element.

FIG. 9 (a) shows the power source polarity detecting means 1 used in this embodiment.
FIG. In this circuit, the input voltage V _in from the AC power supply V _s is stepped down by the step-down transformer Tf, and the diode D ₅
Rectified by the resistor R ₇ to generate a voltage V _R corresponding to the polarity of the power supply, and this voltage V _R is compared with the reference voltage obtained by the voltage dividing resistors R ₅ and R ₆ by the comparator CP ₁ to detect the power supply polarity. You are getting the output SGN. When V _in > 0, the voltage of resistor R ₇
Since V _R becomes higher, if this voltage V _R becomes higher than the reference voltage obtained by the voltage dividing resistors R ₅ and R ₆ , the comparator CP ₁
Output SGN becomes "High" level. Further, when V _in <0, the voltage V _R of the resistor R ₇ becomes zero, so the output SGN of the comparator CP ₁ becomes “Low” level. Note that the voltage dividing resistance
If R _5, R ₆ set reference voltage is low so made obtainable by, the output SGN of the comparator CP ₁ can be prevented imbalance period becomes a "High" level and the period "Low" level, too low If set, resistance R ₇ when V _in <0
A noise voltage is generated across both ends of the comparator CP ₁
Since the output SGN of is at "High" level, it should be set to a voltage high enough to prevent malfunction.

FIG. 9 (b) is a circuit diagram of the no-load detecting means 2 used in this embodiment. When a current is flowing through the transistor Q ₁ (or the diode D ₁ ), an AC voltage is generated between the point X on the secondary side of the current transformer CT and the ground point G. This is rectified by the diode D ₇ and the capacitor C ₈ is charged. The voltage of the capacitor C ₈ is compared with the reference voltage obtained by the voltage dividing resistors R ₉ and R ₁₀ by the comparator CP ₃ ,
When the voltage on capacitor C ₈ is higher, comparator CP
The output of ₃ becomes "High" level. Also, the transistor Q ₁
When the current stops flowing (and the diode D ₁ ), the capacitor C ₈ is discharged by the resistor R _11, and when the voltage of the capacitor C ₈ becomes lower than the reference voltage obtained by the voltage dividing resistors R ₉ and R ₁₀ , the comparator CP The output of ₃ becomes "Low" level. When a current is flowing in the transistor Q ₂ (or the diode D ₂ ), an AC voltage is generated between the one end K of the current detection resistor R ₀ and the ground point G. This is rectified by the diode D ₆ and the capacitor C ₆ is charged. The voltage of the capacitor C ₆ is compared with the reference voltage obtained by the voltage dividing resistors R ₃ and R ₄ by the comparator CP ₂ , and when the voltage of the capacitor C ₆ becomes higher, the output of the comparator CP ₂ becomes “Hig
When the current stops flowing in the transistor Q ₂ (and the diode D ₂ ), the capacitor C ₆ becomes the resistance R ₈
The voltage of capacitor C ₆ is discharged by the voltage dividing resistors R ₃ and R ₄
When it becomes lower than the reference voltage obtained by, the output of the comparator CP ₂ becomes “Low” level. This comparator C
By inputting the outputs of P ₂ and CP ₃ to NAND gate G ₁₁ ,
The no-load detection output NL is obtained from the NAND gate G ₁₁ . That is, when not in the no-load state, the comparators CP ₂ and CP ₃
Since both outputs are at "High" level, NAND gate G ₁₁
The output of the NAND gate G ₁₁ is "Hig" because the outputs of the comparators CP ₂ and CP ₃ do not become "High" level at the same time in the no load state.
h "level.

Further, in the present embodiment, as a method for detecting the load reattachment, there is a method in which only one switching element is operated. For example, only the transistor Q ₂ is turned on / off when V _in > 0, and the transistor Q ₁ is always turned off regardless of the power supply polarity. In this way, the voltage V _C5 of the capacitor C ₅ is always the voltage of the capacitor C ₃ (-V _C3)
The current flows only when the polarity of the power supply is first reversed immediately after the load is not applied, and thereafter the current does not flow until the load is reattached. Input voltage V _{in at} this time,
The relationship between the current i _L of the inductor L ₃ and the voltage V _C5 of the capacitor C ₅ is as shown in FIG. In this method, if the detection is not performed for the first fixed period, the reattachment of the load can be detected only by the presence / absence of the current in the switching element, and the detection point can be compared to the case where both switching elements are operated. Since it suffices to be provided in one place, the configuration of the control circuit becomes simple. In this method, it is impossible to detect the re-mounting of the load in the period of V _in <0, but at least the AC power source V _s
There is no problem because it can be detected after half a cycle of. Here, the example in which only the transistor Q ₂ is operated has been described, but only the transistor Q ₁ may be operated. Also,
This method can also be applied to the circuit of the first embodiment.

[Third Embodiment] FIG. 12 is a circuit diagram of a third embodiment of the present invention. In this embodiment, the inverter circuit is a modified half bridge circuit. That is, a load circuit of the type shown in FIG. 21 (b) is connected in parallel to both ends of one switching element (transistor Q ₂ and diode D ₂ ) via a coupling capacitor C ₃ . Where the coupling capacitor C ₃
Has a sufficiently larger capacity than the capacitor C ₄ for conducting resonance and preheating current, and does not affect the resonance action of the series resonant circuit including the inductor L ₃ and the capacitor C ₄ . The coupling capacitor C _{3 functions} as a power source when the transistor Q ₂ is turned on while cutting the direct current component of the load current, and has a smaller capacity than the smoothing capacitor C ₂ .

Also in this embodiment, when V _in > 0, the transistor Q
Only ₂ is operated, when V _in <0, only transistor Q ₁ is operated, and when the load is reattached, the current flowing through the load is detected to detect reattachment of the load. be able to. Also, since the capacitance of the capacitor C ₃ is small, if the charge on the capacitor C ₃ disappears due to spontaneous discharge, no current will flow when the load is reattached even if the transistor Q ₂ is operated, and detection will be impossible. ₁
It suffices to operate only one.

FIG. 13 (a) is a power source polarity detecting means 1 used in this embodiment.
FIG. In this embodiment, the voltage at the point J obtained by dividing the voltage across the diode D ₄ by the resistors R ₁ and R _{2 is}
The power supply polarity detection output SGN is obtained by detection with the same circuit as in FIG. Further, FIG. 13 (b) is a circuit diagram of the no-load detecting means 2 used in this embodiment. In this embodiment,
No-load detection is performed by detecting the voltage at the point K obtained across the current detection resistor R ₀ connected in series with the transistor Q ₂ (and diode D ₂ ) using the same circuit as in FIG. 9 (b). Got output NL.

[Fourth Embodiment] FIG. 14 is a circuit diagram of a fourth embodiment of the present invention. In the present embodiment, in the third embodiment described above, the power supply side terminal of the discharge lamp l _a in which the capacitor C ₅ for resonance connected in parallel. Therefore, as shown by the broken line, current flows between points A and B even if the discharge lamp l _a is disengaged, but most of the current is reactive current, so power consumption is small, and there is virtually no load. Becomes In this case, as a driving method of the switching element for detecting the reloading of the load, it is preferable to operate only the transistor Q ₁ when V _in <0. The reason is that when transistor Q ₂ is activated, capacitor C ₃ and
This is because the charge of C ₅ is completely discharged, and even if the transistor Q ₂ is subsequently operated, the remounting of the load cannot be detected. In addition, when the polarity of the power source is inverted and the transistor Q ₁ operates, the capacitors C ₃ and C ₅ are recharged. Therefore, the average value of the current is detected as in the second embodiment, or a certain period after the polarity is inverted. It is necessary to devise such as not to detect. On the other hand, when only the transistor Q ₁ is operated, the capacitors C ₃ and C ₅ are charged so that V _C3 + V _C5 = V _C2, and no current flows until the load is attached.
The mounting of the load can be detected by the presence / absence of current in the switching element.

[Fifth Embodiment] FIG. 15 is a circuit diagram of a fifth embodiment of the present invention. In this embodiment, the input voltage V from the AC power source V _s to the point M, is obtained between the N
_in by detecting the power polarity. Also, the capacitors C ₂ , C ₃
The voltage across both terminals is divided by resistors R ₁₂ and R ₁₃ , and the no-load condition and re-loading of the load are detected by the voltage obtained between points P and G. In other words, when there is no load, the power consumption of the load becomes zero, so all the input power of the chopper is a capacitor.
It is stored as electric charge of C ₂ and C ₃ , and its voltage rises. Therefore, when a rise in the voltage of the capacitors C ₂ and C ₃ is detected, it is determined that there is no load, and the control state shifts to no load. Then, when the load is reloaded, capacitor C ₂ or C ₃
Since a current flows from the battery to the load through the switching element in the on operation, the voltage of the capacitors C ₂ and C ₃ drops. Therefore, by detecting the voltage drop between points P and G,
Reloading of the load can be detected. In addition, in the present embodiment, the configuration of the load circuit Z is not particularly limited, but for example, circuits as shown in FIGS. 21 (a) to 21 (c) can be used.

FIG. 16 is an operation waveform diagram of this embodiment. In this embodiment, in the no-load state, the switching element is not turned on and off during the operation period of the switching element, but is kept on throughout the operation period. As described above, if the ON signal is continuously supplied during the half cycle of the AC power supply V _s , there is an advantage that less power is required to drive the switching element than when the ON / OFF signal is supplied. . In particular, for elements such as power MOSFETs that require charging / discharging of gate charge for on / off operation of switching elements, the advantage is large, and maintaining on operation is more effective than repeating on / off operation. The power consumption for use is significantly reduced. In this control method, in the unloaded state, the driving signals S ₁ the apparent transistor Q ₁ is becomes inverted signal of the power polarity detection signal SGN, the driving signal S ₂ on the apparent transistor Q ₂ is the power polarity detection signal It has the same signal as SGN. The drive signals S ₁ and S ₂ satisfying such conditions can be generated by the logic circuit shown in FIG. 17, for example.

Note that when the unloaded state, the control method of this embodiment continue to be turned on for half a period of the AC power source V _s the switching element during operation is also applicable for the Examples 1-4 above.

[Sixth Embodiment] FIG. 18 is a circuit diagram of a sixth embodiment of the present invention. In the present invention, a full bridge circuit is used as the inverter circuit. That is, in the half bridge circuit shown in FIG. 1, the transistor Q ₃ is used instead of the capacitor C ₂ .
Transistor Q ₄ is connected instead of capacitor C ₃ , transistor Q ₃ is turned on / off at the same time as transistor Q ₂ , and transistor Q ₄ is turned on at the same time as transistor Q _1.
It is something to turn off. A smoothing capacitor C ₂ is connected in parallel to both ends of the series circuit of the transistors Q ₃ and Q ₄ .

FIG. 19 is an operation waveform diagram of this embodiment. As shown in the figure, the driving signal S ₃ of the transistor Q ₃ are the same as the drive signal S ₂ of the transistor Q _2, the driving signal S ₄ of the transistor Q ₄
Is the same as the drive signal S ₁ of the transistor Q ₁ . When the no-load detection output NL becomes "High" level, that is, no-load state, when V _in > 0, the transistors Q ₂ and Q ₃ simultaneously turn on / off, and the transistors Q ₁ and Q ₄ stop operating. ing. As a result, since the input chopper does not work, it is possible to prevent the voltage of the capacitor C _{2 from} rising abnormally. When the load is reattached, a current flows from the capacitor C ₂ through the path of the transistor Q ₃ , the load circuit, and the transistor Q ₂ , so that the reattachment of the load can be easily detected. When V _in <0, the transistors Q ₁ and Q ₄ are simultaneously turned on and off, and the transistors Q ₂ and Q ₃ are stopped. This will prevent the input chopper from working. When the load is reattached, a current flows from the capacitor C ₂ through the path of the transistor Q ₁ , the load circuit, and the transistor Q ₄ , so that the reattachment of the load can be easily detected.

[Effect of the Invention] According to the present invention, as described above, the on / off operation of the first and second switching elements connected in series with the direct current power source obtained from the alternating current power source through the chopper circuit as an input. In the power supply device in which electric power is supplied to the load circuit by means of which the first or second switching element is alternately used as the switching element of the chopper circuit depending on the power source polarity of the AC power supply, the unloaded state of the load circuit is When it is detected, the operation of the switching element that is also used as the switching element of the chopper circuit is stopped according to the polarity of the power supply. It has the effect of preventing abnormal voltage rise, improving safety, and preventing the destruction of circuit elements. Also, at least one power supply polarity Since the switching element on the side that is not also used as the switching element of the chopper circuit is operated, when the load is reattached, current can flow to the load via the operating switching element, and the reattachment of the load Has an effect that can be easily detected.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing the basic configuration of the present invention, FIG. 2 is a circuit diagram of a switch driving means used in the same as above, FIG. 3 is an operation waveform diagram of the above, and FIG. 5A and 5B are circuit diagrams for explaining a no-load state detection point in the present invention, and FIG. 6 is a circuit diagram of the first embodiment of the present invention. FIG. 7 (a) is a circuit diagram of the no-load detecting means used in the same as above, FIG. 7 (b) is a circuit diagram of the power supply polarity detecting means used in the same as above, and FIG.
FIG. 9 is a circuit diagram of a second embodiment of the present invention, FIG. 9 (a) is a circuit diagram of power supply polarity detecting means used in the same as above, and FIG. 9 (b) is a circuit diagram of no-load detecting means used in the same as above. 10 and 11 are operation waveform diagrams of the same as above, FIG. 12 is a circuit diagram of a third embodiment of the present invention, and FIG. 13 (a) is a circuit diagram of power source polarity detecting means used in the same as above, FIG. b) is a circuit diagram of the no-load detecting means used in the above, FIG. 14 is a circuit diagram of a fourth embodiment of the present invention, FIG. 15 is a circuit diagram of a fifth embodiment of the present invention, and FIG. 16 is the same as above. FIG. 17 is an operation waveform diagram, FIG. 17 is a circuit diagram of a switch driving means used in the same as above, FIG. 18 is a circuit diagram of a sixth embodiment of the present invention, FIG. 19 is an operation waveform diagram of the same as above, and FIG. Circuit diagrams, FIGS. 21 (a), 21 (b), and 21 (c) are circuit diagrams of a load circuit used in the above. 1 is a power source polarity detecting means, 2 is a no-load detecting means, 3 is a switch driving means, V _s is an AC power source, L ₂ is an inductor, C ₂ and C ₃
Is a capacitor, Q ₁ and Q ₂ are transistors, and Z is a load circuit.

Claims (1)

(57) [Claims] 1. An AC voltage of an AC power supply is chopped at high frequency by a switching element and applied to an inductor,
A chopper circuit for charging a capacitor with the energy stored in the inductor to obtain a DC power supply, and a load circuit by ON / OFF operation of first and second switching elements connected in series with the DC voltage of the DC power supply as an input And an inverter circuit for supplying electric power to the first switching element, the first switching element is also used as a switching element of the chopper circuit when one of the power source polarities of the AC power source, and the second switching element of the other power source polarity of the AC power source. In a power supply device that is also used as a switching element of a chopper circuit, a power supply polarity detection unit that detects the power supply polarity of an AC power supply, a no-load detection unit that detects the no-load state of the load circuit, and a load by the no-load detection unit. When the no-load condition of the circuit is detected, based on the detection output of the power supply polarity detection means, the chopper Switch operation means for stopping the operation of the switching element that is also used as the switching element of the path and operating the switching element that is not also used as the switching element of the chopper circuit with at least one of the power supply polarities. Power supply.