JP2664440B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JP2664440B2 JP2664440B2 JP63286046A JP28604688A JP2664440B2 JP 2664440 B2 JP2664440 B2 JP 2664440B2 JP 63286046 A JP63286046 A JP 63286046A JP 28604688 A JP28604688 A JP 28604688A JP 2664440 B2 JP2664440 B2 JP 2664440B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- substrates
- insulating metal
- metal substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
Landscapes
- Combinations Of Printed Boards (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は、混成集積回路に関し、特に二枚の絶縁金属
基板からなる混成集積回路に関する。The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit comprising two insulating metal substrates.
（ロ）従来の技術 従来二枚の混成集積回路基板からなる混成集積回路は
第５図に示す如く、第１及び第２の混成集積回路基板
（21）（22）と、第１及び第２の混成集積回路基板（2
1）（22）上に設けられた回路素子（23）（24）と、第
１及び第２の混成集積回路基板（21）（22）の一側辺か
ら導出された外部リード（25）と、第１及び第２の混成
集積回路基板（21）（22）を離間支持する枠体（26）と
から構成される。(B) Conventional technology Conventionally, as shown in FIG. 5, a hybrid integrated circuit comprising two hybrid integrated circuit boards is composed of first and second hybrid integrated circuit boards (21) and (22) and first and second hybrid integrated circuit boards. Hybrid integrated circuit board (2
1) A circuit element (23) (24) provided on (22) and an external lead (25) derived from one side of the first and second hybrid integrated circuit boards (21) (22). And a frame (26) for supporting the first and second hybrid integrated circuit boards (21) and (22) apart from each other.
第１及び第２の混成集積回路基板（21）（22）は表面
を絶縁処理したアルミニウム基板が用いられる。第１の
混成集積回路基板（21）には発熱の少ない回路素子（2
3）が設けられ、第２の混成集積回路基板（22）には発
熱の伴う回路素子（24）が設けられる。第１及び第２の
混成集積回路基板（21）（22）の一側辺からは外部回路
との接続を行うために外部リード（25）が水平に導出さ
れる。第１及び第２の混成集積回路基板（21）（22）は
金属から成るリード線（27）によって接続される。第１
及び第２の混成集積回路基板（21）（22）を枠体（26）
を介して固着した際、枠体（26）の側壁と第１及び第２
の混成集積回路基板（21）（22）との両端部とで形成さ
れた空間にエポキシ樹脂等の絶縁樹脂（28）を充填して
一体化するものである。As the first and second hybrid integrated circuit boards (21) and (22), aluminum substrates whose surfaces are insulated are used. The first hybrid integrated circuit board (21) has circuit elements (2
3) is provided, and the second hybrid integrated circuit board (22) is provided with a circuit element (24) which generates heat. External leads (25) are led out horizontally from one side of the first and second hybrid integrated circuit boards (21) and (22) for connection with an external circuit. The first and second hybrid integrated circuit boards (21) and (22) are connected by a lead wire (27) made of metal. First
And a second hybrid integrated circuit board (21) (22) with a frame (26).
When the first and second side walls of the frame (26) are fixed through the
The space formed between the hybrid integrated circuit boards (21) and (22) and both ends is filled with an insulating resin (28) such as an epoxy resin and integrated.
上述の様な混成集積回路は実公昭55−8316号公報に記
載されている。Such a hybrid integrated circuit is described in Japanese Utility Model Publication No. 55-8316.
この様な二枚の混成集積回路基板から成る混成集積回
路の夫々の基板は互いに導通されている。Each substrate of such a hybrid integrated circuit comprising two hybrid integrated circuit boards is electrically connected to each other.
導通の方法として例えば、第６図に示す如く、金属性
のリードフレーム（30）によって行うもの、あるいは第
７図に示す如く、絶縁フィルム（31）上に導体を形成し
て二枚の基板（32）（33）を連結して行うものが代表的
である。As a method of conduction, for example, as shown in FIG. 6, a method using a metallic lead frame (30), or as shown in FIG. 7, a conductor is formed on an insulating film (31) and two substrates ( 32) (33) is typically performed.
（ハ）発明が解決しようとする課題 第６図で示した導通構造では金属性リードフレームを
半田付で固着接続するため、半田接合部の半田のバラツ
キにより信頼性が低下し一定の信頼性レベルを確保する
ことが困難であった。(C) Problems to be Solved by the Invention In the conduction structure shown in FIG. 6, since the metallic lead frame is fixedly connected by soldering, the reliability is reduced due to the variation in the solder at the solder joint, and a certain level of reliability is obtained. Was difficult to secure.
また、リードフレームを樹脂層で封止するための領域
が必要となり基板実装面積が制約される問題があった。In addition, a region for sealing the lead frame with the resin layer is required, and there is a problem that the board mounting area is restricted.
更に第６図及び第７図で示した導通構造ではリードフ
レーム及び絶縁フィルムの折曲げ部分がアンテナとなり
外部ノイズを吸収し、内部回路に悪影響を及す問題があ
った。Further, in the conduction structure shown in FIGS. 6 and 7, there is a problem that the bent portion of the lead frame and the insulating film becomes an antenna, absorbs external noise, and adversely affects the internal circuit.
（ニ）課題を解決するための手段 本発明は上述した課題に鑑みて為されたものであり、
二枚の絶縁金属基板上に複数の半導体素子が固着され、
前記半導体素子が対向する様に前記二枚の絶縁金属板が
ケース材により離間固着された混成集積回路において、
前記二枚の絶縁金属基板の少なくとも一側辺周端部間に
前記二枚の絶縁金属基板を同電位とするための導電性シ
ートを配置して解決する。(D) Means for Solving the Problems The present invention has been made in view of the problems described above,
A plurality of semiconductor elements are fixed on two insulating metal substrates,
In a hybrid integrated circuit in which the two insulating metal plates are separated and fixed by a case material so that the semiconductor elements face each other,
The problem is solved by disposing a conductive sheet for making the two insulating metal substrates have the same potential between at least one peripheral edge of the two insulating metal substrates.
（ホ）作用 この様に本発明に依れば、二枚の絶縁金属基板の少な
くとも一側辺周端面部間に導電性シートを配置すること
により、二枚の絶縁金属基板を同電位とすると同時に半
田付レスで二枚の基板上に形成された所望の回路を接続
することがでる。(E) Function According to the present invention, by arranging a conductive sheet between at least one peripheral edge of two insulating metal substrates, the two insulating metal substrates are set to the same potential. At the same time, desired circuits formed on the two substrates can be connected without soldering.
（ヘ）実施例 以下に第１図に示した実施例に基づいて本発明の混成
集積回路を詳細に説明する。(F) Embodiment Hereinafter, the hybrid integrated circuit of the present invention will be described in detail with reference to the embodiment shown in FIG.
本発明の混成集積回路は第１図に示す如く、二枚の絶
縁金属基板（１）（２）と、二枚の絶縁金属基板（１）
（２）を離間固着するケース材（３）と、二枚の絶縁金
属基板（１）（２）間に配置される導電性シート（４）
とから構成される。As shown in FIG. 1, the hybrid integrated circuit of the present invention has two insulating metal substrates (1) and (2) and two insulating metal substrates (1).
A case material (3) for fixing the (2) apart and a conductive sheet (4) disposed between the two insulating metal substrates (1) and (2).
It is composed of
二枚の絶縁金属基板（１）（２）としてはアルミニウ
ム基板、ケイ素鋼板、鉄基板、及びホーロー基板等を使
用することができ、本実施例ではアルミニウム基板を用
いるものとする。そのアルミニウム基板の表面には周知
の陽極酸化技術によって酸化アルミニウム膜が形成され
絶縁処理が施されている。この二枚の基板（１）（２）
上には接着性を有する絶縁樹脂層を介して銅箔が貼着さ
れており、その銅箔が所定のパターンにエッチングされ
所望形状の導電路（５）（６）が形成される。As the two insulating metal substrates (1) and (2), an aluminum substrate, a silicon steel plate, an iron substrate, an enamel substrate, or the like can be used. In this embodiment, an aluminum substrate is used. An aluminum oxide film is formed on the surface of the aluminum substrate by a well-known anodic oxidation technique, and is subjected to insulation treatment. These two substrates (1) (2)
A copper foil is stuck on the upper side via an insulating resin layer having an adhesive property, and the copper foil is etched into a predetermined pattern to form conductive paths (5) and (6) having desired shapes.
その導電路（５）（６）は第２図に示す如く、夫々の
基板（１）（２）の略全面に形成され、夫々の基板
（１）（２）の一側辺周端部にはシールド用の導電路
（５′）（６′）が基板（１）（２）の終端辺と平行し
てライン状に形成されている。（尚第２図では１つの図
面で二枚の基板（１）（２）を説明している）。As shown in FIG. 2, the conductive paths (5) and (6) are formed on substantially the entire surface of each of the substrates (1) and (2), and are formed on the peripheral edge of one side of each of the substrates (1) and (2). In the figure, conductive paths (5 ') and (6') for shielding are formed in a line in parallel with the terminal sides of the substrates (1) and (2). (Note that FIG. 2 illustrates two substrates (1) and (2) in one drawing).
シールド用の導電路（５′）（６′）の近傍の所定位
置には基板の金属部分を露出させるためのザグリ部
（７）（７）が形成されている。ザグリ部（７）（７）
はドリル及びエンドミル等によって削り取られて形成さ
れる。このザグリ部（７）（７）はあとでシールド効果
をもたらすためにシールド用の導電路（５′）（６′）
とワイヤ線（８）（８）で電気的に接続が行われてい
る。Counterbored portions (7) and (7) for exposing the metal portion of the substrate are formed at predetermined positions near the conductive paths (5 ') and (6') for shielding. Counterbore part (7) (7)
Is formed by shaving with a drill and an end mill. The counterbore portions (7) and (7) are used to provide a shielding effect later.
And the wires (8) and (8) are electrically connected.
シールド用の導電路（５′）（６′）の内側近傍には
二枚の基板（１）（２）上に形成された夫々の回路を接
続するための複数の接続用パッド（５″）（６″）が所
定のピッチで形成されている。A plurality of connection pads (5 ″) for connecting respective circuits formed on the two substrates (1) and (2) are provided near the inside of the conductive paths (5 ′) and (6 ′) for shielding. (6 ″) are formed at a predetermined pitch.
夫々の導電路（５）（６）上にはトランジスタ、IC、
LSI等の複数の半導体素子（９）（10）が固着され、近
傍の導電路（５）（６）とワイヤ線でボンディング接続
がなされている。このときザグリ部（７）（７）と基板
（１）（２）との接続も同時に行われる。導電路（５）
（６）上には半導体素子（９）（10）以外にチップコン
デンサー、チップ抵抗等の複数の電子部品（11）（12）
も固着されている。更にシールド用の導電路（５′）
（６′）の反対側には外部回路と接続するための複数の
外部リード（13）（14）が固着されている。On each conductive path (5) (6), a transistor, IC,
A plurality of semiconductor elements (9) and (10) such as LSIs are fixed, and are bonded to nearby conductive paths (5) and (6) by wire lines. At this time, the connection between the counterbore portions (7) and (7) and the substrates (1) and (2) is performed simultaneously. Conductive path (5)
(6) On top of the semiconductor elements (9) and (10), a plurality of electronic components such as chip capacitors and chip resistors (11) and (12)
Is also fixed. Further conductive path for shielding (5 ')
A plurality of external leads (13) (14) for connecting to an external circuit are fixed to the opposite side of (6 ').
夫々の基板（１）（２）はケース材（３）によって夫
々の半導体素子（９）（10）が対向する様に離間固着さ
れる。このとき夫々の基板（１）（２）終端部間に帯状
の導電性シート（４）が配置され、夫々のシールド用の
導電路（５′）（６′）及び接続用パッド（５″）
（６″）が導電性シート（４）によって圧接接続され
る。The respective substrates (1) and (2) are separated and fixed by the case material (3) such that the respective semiconductor elements (9) and (10) face each other. At this time, a strip-shaped conductive sheet (4) is disposed between the terminal portions of the substrates (1) and (2), and the conductive paths (5 ') and (6') for shielding and the connection pads (5 ") are provided.
(6 ″) is press-connected by the conductive sheet (4).
導電性シート（４）はゴム又は合成樹脂から成る絶縁
シートで第３図に示す如く、帯状に形成されその厚さ方
向に線状導体（15）が複数本埋め込まれており、帯状の
導電性シート（４）の両面からは複数の線状導体（15）
が突出されている。斯る導電性斯（４）は特開昭62−22
9714号公報、特開昭59−58709号公報に記載されてい
る。As shown in FIG. 3, the conductive sheet (4) is an insulating sheet made of rubber or synthetic resin and is formed in a band shape, and a plurality of linear conductors (15) are buried in the thickness direction thereof. Multiple linear conductors (15) from both sides of the sheet (4)
Is protruding. Such conductive resin (4) is disclosed in JP-A-62-22
9714 and JP-A-59-58709.
導電性シート（４）は枠状に形成されたケース材
（３）とあらかじめ一体化されている。即ち、第１図に
示す如く、ケース材（３）の支持体（16）によって保持
されることになる。このとき、導電性シート（４）の両
先端部はケース材（３）の段差部（17）より若干突出す
る様にしておく。The conductive sheet (4) is integrated beforehand with the frame-shaped case material (3). That is, as shown in FIG. 1, it is held by the support (16) of the case material (3). At this time, both end portions of the conductive sheet (4) are slightly projected from the step portion (17) of the case material (3).
斯る二枚の基板（１）（２）上に固着された半導体素
子（９）（10）が対向する様に二枚の基板（１）（２）
で帯状の導電性シート（４）が一体化されたケース材
（３）を挟持する様に配置して接着シート等の接着剤で
ケース材（３）と二枚の基板（１）（２）とを一体化す
る。この結果導電性シート（４）は二枚の基板（１）
（２）で挟持され、夫々の基板（１）（２）の終端部に
形成されたシールド用の導電路（５′）（６′）及び接
続用パッド（５″）（６″）が導電性シート（４）によ
り圧接接続され、半田付レスで二枚の基板（１）（２）
上に形成された所望の回路を接続することができると共
に夫々の基板（１）（２）を同電位にすることができ
る。導電性シート（４）には多数の線状導体（15）が配
置されているためにシールド用の導電路（５′）
（６′）と接続されるシート（４）の線状導体（15）で
シールドが行える。The two substrates (1) and (2) such that the semiconductor elements (9) and (10) fixed on the two substrates (1) and (2) face each other.
The case material (3) in which the strip-shaped conductive sheet (4) is integrated is disposed so as to sandwich the case material (3) and the case material (3) and the two substrates (1) and (2) with an adhesive such as an adhesive sheet. And are integrated. As a result, the conductive sheet (4) has two substrates (1).
(2), the conductive paths (5 ') (6') and the connection pads (5 ") (6") for the shield formed at the end of each of the substrates (1) and (2) are conductive. Two substrates (1) and (2) that are pressure-welded and connected by a non-woven sheet (4) without soldering
A desired circuit formed above can be connected, and the respective substrates (1) and (2) can be set to the same potential. Since a large number of linear conductors (15) are arranged on the conductive sheet (4), the conductive path (5 ') for shielding is used.
Shielding can be performed by the linear conductor (15) of the sheet (4) connected to (6 ').
第４図は他の実施例を示す平面図であり、導電性シー
ト（４）を基板（１）（２）の三側辺に配置したもので
ある。この構造に依ればシールド用のケースを必要とせ
ずに完全シールドが行える。このときの導電性シート
（４）の形状は帯状のものを夫々の側辺に配置するかあ
るいはコ字状のものをあらかじめ形成しておけばよい。FIG. 4 is a plan view showing another embodiment, in which conductive sheets (4) are arranged on three sides of substrates (1) and (2). According to this structure, complete shielding can be performed without requiring a shielding case. At this time, the shape of the conductive sheet (4) may be such that a strip is disposed on each side or a U-shape is formed in advance.
（ト）発明の効果 以上に詳述した如く、本発明に依れば、二枚の絶縁金
属基板の終端部間に二枚の絶縁金属基板を同電位とする
ための導電性シートを配置することにより、シールド専
用の金属ケースを用いることがなく導電性シートのみで
シールドを行うことができる利点を有する。(G) Effects of the Invention As described in detail above, according to the present invention, a conductive sheet for equalizing the potential of two insulating metal substrates is disposed between the terminal portions of the two insulating metal substrates. Thus, there is an advantage that the shield can be performed only with the conductive sheet without using the metal case dedicated to the shield.
また、導電性シートによって二枚の基板上に形成され
た回路を同時に接続することができる。Further, circuits formed on two substrates can be simultaneously connected by the conductive sheet.
更に導電性シートは二枚の基板で挟持されるために半
田付レスで接続が行え信頼性が向上する利点を有する。Furthermore, since the conductive sheet is sandwiched between the two substrates, there is an advantage that connection can be performed without soldering and reliability is improved.
第１図は本発明の実施例を示す断面図、第２図は本実施
例の基板を示す平面図、第３図は本実施例で用いる導電
性シートを示す斜視図、第４図は他の実施例を示す平面
図、第５図、第６図及び第７図は従来例を示す断面図で
ある。 （１）（２）……絶縁金属基板、（３）……ケース材、
（４）……導電性シート、（５）（５′）（６）
（６′）……導電路。FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a plan view showing a substrate of this embodiment, FIG. 3 is a perspective view showing a conductive sheet used in this embodiment, and FIG. FIGS. 5, 5, 6 and 7 are cross-sectional views showing a conventional example. (1) (2) ... insulated metal substrate, (3) ... case material,
(4) ... conductive sheet, (5) (5 ') (6)
(6 ') ... conductive path.
Claims (8)
が固着され、前記半導体素子が対向する様に前記二枚の
絶縁金属板がケース材により離間固着された混成集積回
路において、 前記二枚の絶縁金属基板間の少なくとも一側辺周端部間
に前記二枚の絶縁金属基板を同電位とするための導電性
シートが配置されていることを特徴とする混成集積回
路。1. A hybrid integrated circuit comprising: a plurality of semiconductor elements fixed on two insulating metal substrates; and the two insulating metal plates fixedly separated by a case material so that the semiconductor elements face each other. A hybrid integrated circuit, wherein a conductive sheet for setting the two insulating metal substrates to the same potential is disposed between at least one peripheral edge between the two insulating metal substrates.
導体が突出され、前記二枚の絶縁金属基板で挟持されて
いることを特徴とする請求項１記載の混成集積回路。2. The hybrid integrated circuit according to claim 1, wherein a number of linear conductors protrude from both sides of said conductive sheet and are sandwiched between said two insulating metal substrates.
板を同電位とすると同時に前記夫々の基板上に形成され
た導電路を接続することを特徴とする請求項１記載の混
成集積回路。3. The hybrid integrated circuit according to claim 1, wherein the conductive sheet connects the conductive paths formed on each of the two insulating metal substrates at the same time as making the two insulating metal substrates have the same potential. .
絶縁金属基板の少なくとも一側辺周端部にはライン状の
導電路が形成され、前記ライン状の導電路近傍に形成さ
れた前記基板の金属部分を露出するためのザグリ部と前
記ライン状の導電路とが接続されていることを特徴とす
る請求項１記載の混成集積回路。4. A line-shaped conductive path is formed on at least one peripheral edge of the two insulating metal substrates on which the conductive sheet is disposed, and is formed near the line-shaped conductive path. The hybrid integrated circuit according to claim 1, wherein a counterbore portion for exposing a metal portion of the substrate and the linear conductive path are connected.
二枚の基板を接続するための複数の接続用パッドが形成
されていることを特徴とする請求項１記載の混成集積回
路。5. The hybrid integrated circuit according to claim 1, wherein a plurality of connection pads for connecting the two substrates are formed near the inside of the linear conductive path.
ことを特徴とする請求項１記載の混成集積回路。6. The hybrid integrated circuit according to claim 1, wherein said conductive sheet is formed in a strip shape.
板の三側辺周端部間に配置されていることを特徴とする
請求項１記載の混成集積回路。7. The hybrid integrated circuit according to claim 1, wherein said conductive sheet is disposed between peripheral edges of three sides of said two insulating metal substrates.
アルミニウム基板であることを特徴とする請求項１記載
の混成集積回路。8. A hybrid integrated circuit according to claim 1, wherein said two insulating metal substrates are insulated aluminum substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63286046A JP2664440B2 (en) | 1988-11-11 | 1988-11-11 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63286046A JP2664440B2 (en) | 1988-11-11 | 1988-11-11 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02130952A JPH02130952A (en) | 1990-05-18 |
| JP2664440B2 true JP2664440B2 (en) | 1997-10-15 |
Family
ID=17699269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63286046A Expired - Fee Related JP2664440B2 (en) | 1988-11-11 | 1988-11-11 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2664440B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2721093B2 (en) * | 1992-07-21 | 1998-03-04 | 三菱電機株式会社 | Semiconductor device |
-
1988
- 1988-11-11 JP JP63286046A patent/JP2664440B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02130952A (en) | 1990-05-18 |
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| LAPS | Cancellation because of no payment of annual fees |