JP2662821B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, in particular, two bits for writing and reading corresponding to each memory cell represented by a serial access memory. And a word line and two word lines for writing and reading.

[Prior Art] In a semiconductor memory device, data writing to a memory cell,
In some cases, data reading from a memory cell is performed via a different path. A typical example of such a semiconductor storage device is a serial access memory.

In a serial access memory, data input serially one bit at a time is written into a memory cell array in address order, and data is serially read out one bit at a time from the memory cell array in address order.

FIG. 5 is a schematic block diagram showing the entire configuration of a conventional serial access memory.

Referring to FIG. 5, a serial access memory includes a memory block 100 in which memory cells are arranged in a matrix.
And a sense amplifier 102 for amplifying data read from the memory block 100, and a read data buffer 104 for leading the data amplified by the sense amplifier 102 to an output terminal 106. Further, the serial access memory has a write data buffer 110 for buffering data input from a data input terminal 108 and providing the data to the memory block 100, and writes memory cells in the memory block 100 in address order when writing data. A write address pointer 112 for enabling the state and a memory block 100 for reading data.
And a read address pointer 114 for setting the memory cells in the memory in a data readable state in the order of addresses.

At the time of data writing, input data D _{0 to} D _n (n is a natural number) is applied to write data buffer 110 via data input terminal 108. Write data buffer 110 receives a write clock signal W externally input to write clock terminal 116.
According to CK, input data D _{0 to} D from the data input terminal 108
_n is output to the memory block 100 for each row. at the same time,
The write address pointer 112 operates in accordance with the write clock signal WCK so that each of the input data output from the write data buffer 110 is written into the memory cells in the memory block 100 in address order. The memory cells are set in a writable state in address order. As a result, the input data is written into the memory cells in the memory block 100 bit by bit in the order of addresses.

At the time of data reading, read address pointer 114
In accordance with a read clock signal RCK externally applied to read clock terminal 118, memory cells in memory block 100 are selected in address order to enable reading, and sense amplifier 102 is activated. As a result, after the data is output from the memory cells in the memory block 100 in the order of addresses, the data is amplified to a predetermined level by the sense amplifier 102. Next, the read data buffer 104 derives each of the data Q _{O to} Q _n amplified by the sense amplifier 102 to the data output terminal 106 at a constant cycle according to the read clock signal RCK. In this way, the data stored in the memory block 100 is taken out to the data output terminal 106 one row at a time in the order of addresses.

Next, a specific configuration of the memory block 100 will be described. FIG. 6 is a partial circuit diagram showing the internal configuration of the memory block 100.

Referring to FIG. 6, in memory block 100, memory cell 1 is provided between write bit line 3 and read bit line 4 to form a memory cell column. At the same time, memory cells adjacent in the row direction are connected to the same write word line 5 and read word line 6 to form a memory cell row.

Between each read bit line 4 and a power supply line 19 to which a voltage Vcc of a logic level "H" is supplied from a power supply (not shown), an N-channel MOS and a transistor 7 connect the read bit line 4 to "H". It is connected as a precharge transistor for precharging to the level potential.

Precharge transistor 7 receives power supply voltage Vcc at its gate and drain. Therefore, precharge transistor 7 is always on, and when data is not read from memory cell 1, power supply voltage Vcc
Read bit line 4 is precharged to a voltage lower than the threshold voltage.

An inverter for inverting the potential of the read bit line is provided between the read bit line 4 and the read address pointer 114.
13 and two N-channel MOS transistors 8a and 8b are connected.

The transistor 8a is provided between the input terminal of the inverter 13 and the sense amplifier 102, and the transistor 8b
Is provided between the output terminal of the inverter 13 and the sense amplifier 102. The gates of the transistors 8a and 8b are commonly connected and connected to the address pointer 114. The address pointer 114 corresponds to each of the read bit lines 4,
Output terminals A _0, A _1, ... have A _n, the gates of transistors 8a and 8b provided in correspondence to each of the read bit lines 4 are respectively connected to the output terminal A ₀ to A _n You. Address pointer 114, from the output terminal A ₀ to A _n in accordance with the signal RCK to read clock, and outputs a sequentially "H" level voltage, the corresponding transistors 8a and 8b into the ON state. Transistors 8a and 8b are read bit line access transistors that transmit the potential of corresponding read bit line 4 and its inverted potential to sense amplifier 102 only when in the ON state.

The sense amplifier 102 differentially amplifies two voltages input via the transistors 8a and 8b,
The voltage of read bit line 4 provided corresponding to transistors 8a and 8b is amplified to a predetermined level corresponding to the logic level and applied to read data buffer 104.

The write bit line 3 is connected to the write data buffer 110 in FIG. 5 to sequentially transmit input data to the memory cells 1 one row at a time. It is connected to a write address pointer 112 and applies a potential for simultaneously writing data to one row of memory cells as a write word line selection signal.
Specifically, the write address pointer 112 has the same number (m) of output terminals B _{0 to} B _m as the write word lines 5. Each write word line 5 of the m lines, via the N-channel MOS transistor 90 which are diode-connected, are connected to these output terminals B ₀ .about.B _m. Write address pointer 112
Outputs the data write operation to, any one of the m output terminals B ₀ .about.B _m, the "H" level potential as the write word line selection signal. As a result, only one potential of the m write word lines 5 rises to the “H” level. The read word lines 6 are sequentially driven one by one by the address pointer 114. That is, a memory cell from which data is to be read (hereinafter, referred to as a selected memory cell)
Address pointer 11 only to read word line 6 corresponding to
From 4, a potential for setting the memory cell 1 in a data readable state is supplied as a read word line selection signal.

FIG. 7 is a circuit diagram showing the internal configuration of the memory cell 1.

Referring to FIG. 7, memory cell 1 includes a write word line 5
And an N-channel MOS transistor 16 having a gate connected to the read word line 6, an N-channel MOS transistor 15 and a memory capacitor 17. The transistors 15 and 16 are provided in series between the read bit line 4 and the ground 18, and the transistor 14 is provided between the write bit line 3 and the gate of the transistor 15. The memory capacitor 17 is provided between a connection point between the gate of the transistor 15 and the transistor 14 and the ground 18. Read bit line 4 is connected to power supply line 19 via precharge transistor 7. Next, the operation of this memory cell during data writing and data reading will be described.

Data writing to memory cell 1 is performed as follows.

The potential of write word line 5 is set to “H” level by a write word line selection signal, and a voltage of “H” level or “L” level is applied to write bit line 3 as input data. When the write word line 5 goes to "H" level, the transistor 14 is turned on. As a result, the memory capacitor 17 is charged or discharged according to the potential level of the write bit line 3 which is input data. Writing to cell 1 is performed. That is, when the input data is at “H” level, the memory capacitor 17 is charged, and the gate potential of the transistor 15 becomes “H” level. Conversely, when the input data is at “L” level, the memory capacitor 17 is discharged. As a result, the gate potential of the transistor 15 becomes “L” level. When the writing is completed, the write word line 5 goes to the “L” level, and the transistor 14 is turned off.
State. However, the gate potential of transistor 15 is
The memory capacitor 17 keeps the written level for a certain period of time (typically several hundred milliseconds). Thus, the input data is stored in the memory cell 1.

Data reading from memory cell 1 is performed as follows.

The potential of the read word line 6 is set to "H" level by the read word line selection signal, and the transistor 16 is turned on.
As a result, the read bit line 4 is set to a potential corresponding to the conduction state of the transistor 15. That is, the memory cell 1
When “L” is written in the transistor 15, the transistor 15 is in the OFF state.
A high voltage is supplied to the read bit line 4 from the power supply line 19, and the level of the read bit line 4 becomes "H". Conversely, when "H" is written in the memory cell 1, the transistor 15
Is in the ON state. Therefore, in this case, the power line
Transistors 15 and 19 connected in series between 19 and ground;
16 and the precharge transistor 7 are all turned on to generate a current (through current) flowing between the power supply line 19 and the ground 18. Therefore, the read bit line 4
The power supply voltage is divided by the ratio of the sum of the ON resistances of the transistors 15 and 16 and the ON resistance of the transistor 7, and supplied. However, the transistors 15 and 16 are set to have a higher driving capability than the precharge transistor 7, so that
The resistance sum is sufficiently smaller than the ON resistance of the transistor 7. Therefore, the potential of the read bit line 4 is set to the low potential of the ground 18.
It is lowered by 0V and becomes “L” level. in this way,
At the time of data reading, data stored in memory cell 1 is inverted and read out on read bit line 4.

The amplification (level sensing) of the data read to the read bit line 4 is performed by the sense amplifier 102 in FIG. Next, the necessity of the sense amplifier 102 and the operation principle thereof will be described.

The potential of the read bit line 4 is expressed as follows when the storage data of the memory cell 1 is "H" and when it is "L".

When the data stored in the memory cell 1 is “H”: When the data stored in the memory cell 1 is “L”: Vcc−V _TH ... In the above equation, V _TH represents the threshold voltage of the precharge transistor 7. As can be seen from the above equation, when the storage data of the memory cell 1 is "L", the read bit line 4
Is not lowered between 0 V, the difference between this potential and the potential read to read bit line 4 when the data stored in memory cell 1 is "H", that is, the logical amplitude is
The difference Vcc between the power supply potential Vcc and the ground potential 0 V is not so large but small. Therefore, if the potential of the read bit line 4 is simply inverted to obtain read data, it is difficult to determine whether the read data corresponds to the logical value “0” or “1”. Therefore, a sense amplifier 102 that is a high-sensitivity amplifier is required. The sense amplifier 102 is a differential amplifier to which the potential of the read bit line 4 and the differential signal obtained by inverting the potential of the read bit line 4 by the inverter 13 are input.

In the following description, transistors 15 and 16 shown in FIG. 7 are referred to as a storage transistor and a read transistor, respectively.

FIG. 9 is a circuit diagram showing the internal configuration of the sense amplifier 102.

Referring to FIG. 9, sense amplifier 102 is connected to power supply line 1
It includes a series connection circuit of a P-channel MOS transistor TR2 and an N-channel MOS transistor TR3 and a series connection circuit of a P-channel MOS transistor TR1 and an N-channel MOS transistor TR4 provided in parallel between 9 and the ground 18. The gate of the transistor TR3 and the gate of the transistor TR4 are connected to the read bit line 4 and the output terminal of the inverter 13 in FIG. 5, respectively. Transistor TR1
And the gate of TR2 are connected to transistors TR2 and TR3, respectively.
And the connection point of transistors TR1 and TR4. The potential O at the connection point between transistors TR2 and TR3 and the potential at the connection point between transistors TR1 and TR4 are supplied to read data buffer 104 in FIG. 5 as the output of this sense amplifier. At the time of data reading, the gates of transistors TR3 and TR4 are supplied with the potentials of the complementary logic levels represented by the above formulas from read bit line 4 and inverter 13, respectively. When the gate potential of the transistor TR3 is higher than that of the transistor TR4, the transistor TR3 is turned on, and the source potential of the transistor TR2 is lowered by the potential 0V of the ground 18. In response, transistor TR1 turns O
In the N state, the potential at the connection point between the transistors TR1 and TR4 is raised by the power supply potential Vcc. The potential at the connection point of the transistors TR1 and TR4
Transistors TR2 and TR3 to work to FF state
Is reliably reduced to the ground potential 0V. Therefore, finally, the transistors TR2 and TR3
The potential at the connection point is 0 V at the ground 18, and the potential at the connection point between the transistors TR1 and TR4 is the power supply potential Vcc. Similarly, when the gate potential of the transistor TR4 is lower than that of the transistor TR4, the transistor TR4 is turned on.
State, the transistors TR2 and T2
The potential at the connection point of R3 becomes the power supply potential Vcc, and the transistor T
The potential at the connection point between R1 and TR4 becomes the ground potential 0V.

As described above, by this sense amplifier, the “L” level potential represented by the above equation is further reduced to 0 V, and the “H” level potential represented by the above equation is further raised to the power supply potential Vcc. It appears at the connection point between transistors TR2 and TR3 and the connection point between transistors TR1 and TR4. In this manner, the potentials at the two output terminals of the sense amplifier complementarily change in accordance with the difference between the gate potentials of the transistors TR3 and TR4 to change the power supply potential Vcc and the ground potential 0V to the logic levels "H" and "H". L ". Therefore, in FIG. 6, the potential level read from memory cell 1 to corresponding read bit line 4 is amplified by sense amplifier 102 and derived to read data buffer 104.

The read data buffer 104 transfers the read data amplified by the sense amplifier 102 to the aforementioned read clock signal RCK.
Is a circuit having a latch function for taking in and outputting at a predetermined timing according to the following.

Referring to FIG. 5 again, at the time of data reading, stored data is inverted and read out from all the memory cells connected to read word line 6 which has attained the "H" level to corresponding read bit line 4. However, since only read bit line access transistors 8a and 8b provided corresponding to read bit line 4 connected to the selected memory cell are turned on, sense amplifier 102 stores data of the selected memory cell. Only a potential corresponding to data is applied.

Figure 8 is a case where the data read operation of the serial access memory shown in FIG. 6, the read bit lines 4 provided corresponding to one A ₀ output terminal of the address pointer 114 is selected It is a timing chart figure shown as an example.

Referring to FIGS. 6 to 8, at the time of data reading,
The output terminals A _{0 to} A ₀ of the address pointer 114 are synchronized with the rising of the read clock signal RCK (FIG. 8A) having a fixed period.
_{From "n} ", "H" for one cycle period of the read clock signal RCK sequentially
A level signal is output. Accordingly, the output from the terminal A _0, as shown in FIG. 8 (b), for example k-1 th read clock signal RCK (k = 2,3, ...) "H" level voltage to the cycle period of Is output. Read bit line in the period signal of the output terminal A ₀ from the "H" level is output, the read word line 6 to be given "H" level potential as a read word line selection signal, corresponding to the output terminals A ₀ 4 is read out from the memory cell connected to. That is,
If the storage data of this memory cell is "H", the output terminal
As the read bit line 4 corresponding to A ₀ are shown in Figure No. 8 (c), it decreases from the precharge potential (Vcc-V _TH), to a potential (> 0V) obtained by the equation. Thereafter, when data is read from another memory cell connected to read bit line 4 and having the stored data of "L", the potential of read bit line 4 is changed as shown in FIG. 8 (d). To
From the potential obtained by the above equation, the precharge potential (Vc
c−V _TH ). The potential of the read bit line 4 is amplified by the sense amplifier 102 using its inverted potential, and then applied to the read data buffer 104.
On the other hand, read data buffer 104 has read clock signal RCK
The output of the sense amplifier 102 is taken in synchronism with the rising edge of. Accordingly, as shown in FIG. 8 (e), the read bit line 4 in the period the output is at "H" level of the output terminal A ₀ of the address pointer 114 is the potential to take the final, the read clock signal RCK It is output to the data output terminal 106 during the next (k-th) one cycle period. As described above, in the conventional serial access memory, the read clock signal RCK 1
During the period, the potential read on the read bit line 4 connected to the selected memory cell is level-sensed, and all other read bit lines 4 are precharged to Vcc- _VTH .

Next, the tenth configuration of the read address pointer 114 will be described.
This will be briefly described with reference to the drawings.

FIG. 10 is a circuit diagram showing the internal configuration of the address pointer 114.

Referring to FIG. 10, the address pointer includes n + 1 D flip-flops F0 to Fn and two-input AND gates G0 to Gn. D flip-flop is a clock terminal
In synchronization with the rising (or falling) of the clock signal applied to CK, the voltage applied to the data terminal D is taken in and held as data, and output from the output terminal Q. Therefore, a change in the voltage applied to the data terminal D appears on the outputs of the flip-flops F0 to Fn with a delay of one cycle of the read clock signal RCK.

Each of the flip-flops F0 to Fn receives the above-described read clock signal RCK at the clock terminal CK, and receives the output of the preceding flip-flop at the data terminal D. Therefore, a potential change at the data terminal D of the flip-flop F0 is sequentially transmitted to the output terminals Q of the flip-flops F1 to Fn with a delay of one cycle of the read clock signal RCK.

AND gates G0-Gn are provided corresponding to flip-flops F0-Fn, respectively, and receive the output of the corresponding flip-flop and read clock signal RCK as inputs. Each output of the AND gate G0~Gn is derived to the output terminal A ₀ to A _n of the address pointer 114 in Figure 5. Therefore, A
Each of the ND gates G0 to Gn outputs an "H" level signal voltage only during a period in which the voltage appearing at the corresponding output terminal Q and the read clock signal RCK are both at "H" level.
However, the potential change at the output terminal Q of each of the flip-flops F0 to Fn appears at the output terminal Q of the next-stage flip-flop with a delay of one cycle of the read clock signal RCK.
For this reason, the signal voltage that sets the outputs of the AND gates G0 to Gn to the “H” level is transmitted to the output terminals Q of the flip-flops F0 to Fn with a delay of one cycle of the read clock signal RCK.
The outputs of the AND gates G0 to Gn sequentially become "H" level for a certain period. As a result, in FIG.
Are sequentially turned on for a certain period of time.

[Problem to be Solved by the Invention] As described above, in a semiconductor memory device represented by a conventional serial access memory and having two bit lines of a read bit line and a write bit line for each memory cell column,
The precharge transistor for precharging the bit line is always ON. For this reason, a through current at the time of data reading becomes large, and the following problem occurs.

That is, in the serial access memory shown in FIG. 5, all the gates and drains of the transistors 7 are connected to the power supply line 19, and all the read bit lines 4 are always electrically connected to the power supply line 19. It is in. Therefore, among the memory cells 1 connected to the read word line 6 selected at the time of data reading, the storage data is "H".
The period during which reading is being performed from the power supply line 19 to the ground 18 through the read word line 6
Is at “H” level, a through current flows. For example,
In the worst case, that is, when “H” is written in all the memory cells 1, the read word line 6 corresponding to the selected memory cell is selected during the period in which any of the memory cells is selected. 7 from the power supply line 19 to the ground 18 through the precharge transistor 7, the read bit line 4, the storage transistor 15, and the read transistor 16 in FIG. A through current flows. In other words, in such a case,
Through current always flows through all read bit lines during the data read period.

If the shoot-through current is large, the ground potential becomes the original level (= 0
V), or the power supply potential is lower than the original level Vcc, so that the ground potential or the power supply potential fluctuates. It has already been found that such a change in the potential level serving as a memory operation reference is one of the causes of shortening the discharge time of the memory capacitor 17 in the memory cell 1, that is, the data retention time of the memory cell. And should be avoided as much as possible. Also, if the current flowing in the memory during operation is large, the power consumption of the memory increases, and the heat generation of the memory chip on which the memory is mounted increases, or the power supply load of the entire system on which the memory is mounted increases. Problems arise. Therefore,
It is desirable that the through current as described above is as small as possible.

Further, when the storage data of the selected memory cell is “H”, the precharge transistor 7 is always in the ON state when reading data from the memory cell,
The corresponding read bit line 4 is pulled down to the low potential 0 V of the ground 18 by the storage transistor 15 and the read transistor 16 (see FIG. 7) in the selected memory cell, while the pre-connected to the read bit line 4 A high voltage is supplied from the power supply line 19 by the charge transistor 7. Therefore, it takes time for the read bit line 4 to go to the “L” level. In order to correctly derive the storage data of the selected memory cell to the sense amplifier 102 in FIG. 5, the potential level of the read bit line 4 corresponding to the selected memory cell must be set according to the storage data of the selected memory cell. And the level to be taken (shown in the above formula and). Therefore, a signal amplified by the sense amplifier 102 after the level of the read bit line 4 has reached the original level needs to be led to the buffer 106 as read data. Therefore, as described above, it takes time for the read bit line 4 to reach the "L" level potential, which makes it difficult to quickly read data from the memory cell whose stored data is "H". Means that.

In particular, since the number of memory cells connected to one word line is increasing with the recent increase in the capacity of the memory cells, a through current at the time of data reading is increased and the above-described problem caused by the increase Is no longer negligible.

In order to reduce the through current, a method of reducing the driving capability (size) of the precharge transistor 7 in FIG. 7 and increasing the ON resistance value of the precharge transistor 7 is considered. However, if the size of the precharge transistor is small, the following problem occurs.

For example, after data is read from a certain memory cell and the potential level of corresponding read bit line 4 attains "L", another memory connected to read bit line 4 and having storage data of "L" is connected. When data is read from a cell, in order to read data at high speed, it is necessary that read bit line 4 be brought to "H" level early during data read. However, if the size of the precharge transistor 7 is small, the current flowing from the power supply line 19 to the read bit line 4 via the precharge transistor 7 decreases, and the potential level of the read bit line 4 becomes "H" depending on the power supply voltage. The time it takes to ascend is longer. That is, the time required for the precharge transistor 7 to completely precharge the read bit line 4 to the “H” level (until the potential of the read bit line 4 becomes Vcc− _VTH in FIG. 8D). ) Becomes longer, data cannot be immediately read from a memory cell whose storage data is “H”, which is connected to the read bit line 4 once at “L” level.

An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor memory device capable of performing high-speed operation with lower power consumption than conventional ones.

Means for Solving the Problems In order to achieve the above object, a semiconductor memory device according to the present invention is arranged in a plurality of rows and a plurality of columns, each of which has a write node and a write node. A plurality of memory cells having different read nodes, each connected to a read node of a plurality of memory cells provided corresponding to any one of the plurality of columns and arranged in the corresponding column; And a plurality of read bit lines, each of which is provided corresponding to any one of the plurality of read bit lines and outputs an output based on a potential appearing on the corresponding read bit line when selected. And a plurality of switch means, each of which is provided corresponding to any one of the plurality of read bit lines, and when selected, any one of the plurality of read bit lines corresponding to one of the plurality of read bit lines is precharged. And a plurality of output nodes corresponding to the plurality of switch means and the plurality of precharge means, each output node having an address connected to the corresponding switch means and precharge means. A pointer means for simultaneously selecting a switch means and a precharge means provided corresponding to any one of the plurality of read bit lines of the plurality of switch means and the plurality of precharge means; A switching unit provided corresponding to the read bit line; and a selection unit for setting the precharge unit to a non-selection state.

[Operation] Since the semiconductor memory device according to the present invention is configured as described above, all of the read bit lines are precharged by the corresponding precharge means only during a period when the read bit lines are selected by the selection means. That is, the period in which any of the read bit lines is electrically connected to the corresponding precharge means is also limited to the time period in which the selection means selects one read bit line. Therefore, when data is read, the total amount of current flowing through the read bit line when the read bit line is precharged by the precharge means is increased during the period in which any of the read bit lines is selected by the selection means. This is significantly reduced as compared with the case where all are precharged by the corresponding precharge means.

Embodiment FIG. 1 is a partial schematic block diagram of a serial access memory according to an embodiment of the present invention. FIG. 1 shows the configuration of the memory block 100 of the serial access memory, the memory block 100, the address pointer 114, the sense amplifier 1
The connection relationship between 02 and the read data buffer 104 is mainly shown. The overall configuration of this serial access memory is the same as that of the conventional serial access memory shown in FIG. FIG. 2 also shows the internal configuration of the memory cell 1 and the connection relationship between the memory cell 1 and the write word line 5, the read word line 6, and the write bit line 3 and the read bit line 4 in the memory block 100. As shown in FIG.

FIG. 2 is a circuit diagram showing a connection relationship between an internal configuration of an arbitrary memory cell 1 and a corresponding precharge transistor 7 in the present embodiment.

Referring to FIG. 1, in this serial access memory, unlike the conventional one, the gate of precharge transistor 7 is connected to a corresponding read bit line access transistor.
8a and 8b together with the gate of, are respectively connected to the output terminal A ₀ to A _n of the address pointer 114. Address pointer 11
4 has the configuration shown in FIG. 10 and operates in the same manner as in the prior art. The read word line 6 selected at the time of data reading
Is set to "H" level only for one cycle of read clock signal RCK in synchronization with the rise of read clock signal RCK, as in the prior art.

FIG. 3 is a timing chart showing the operation of the address pointer 114 and the read data buffer 104.

Referring to FIG. 3, read clock signal RCK (3
(A) rises at a constant cycle. Address pointer 114 sequentially from the output terminal A ₀ to A _n, in synchronization with the rising edge of the read clock signal RCK, the "H" level voltage,
It is output for one cycle of the read clock signal RCK. That is, as representatively shown in FIG. 3 (b) and (c), from the time t ₁ ~t output terminal A ₀ during the period ₂ the "H" level voltage is outputted, the next 1 During the period (time t ₂ to
The t period _3), the voltage of the "H" level from the output terminal A ₁ is output. Therefore, the precharge transistor 7
Is different from the conventional one, together with the corresponding read bit line access transistors 8a and 8b, together with the address pointer 11
From the corresponding output terminals of the four output terminals A ₀ ~A _n "H"
It is turned ON only while the voltage of the level is being output. That is, all of the read bit lines 4 are each, shifted by one cycle of the read clock signal RCK, is precharged to a potential of Vcc-V _TH in the one period.

Therefore, during a period in which data is read from an arbitrary memory cell 1 whose stored data is “H”, only the read bit line 4 connected to this memory cell is connected via the corresponding precharge transistor 7. A through current flows, and no through current flows through the other read bit lines 4.

Even when the through current is maximized, that is, even when the storage data of all the memory cells is “H”, the through current is always set to all the read bit lines 4 until the data read from all the memory cells is completed. Each time a read bit line is selected by the address pointer 114, the selected read bit line 1
Only flows into books.

Thus, in this serial access memory, at the time of reading data,
The time during which the through current flows through the selected read bit line is one cycle of the read clock signal RCK, and the number of the read bit lines through which the through current flows is 1 / (n + 1) as compared with the conventional case. The total amount of through current is greatly reduced as compared with the conventional case. As a result, the power consumption of the serial access memory is smaller than that of the conventional serial access memory.

Further, by switching the precharge transistor 7 to the OFF state, the precharge transistor 7
, The potential of the read bit line 4 connected immediately to the ground potential immediately drops to 0V.

FIG. 4 is a timing chart showing a potential change of the read bit line 4 at the time of reading data in the serial access memory. The fourth figure, when the output terminal read bit line 4 connected to A ₀ of the address pointer 114 in FIG. 1 are representatively shown.

Referring to Figure 4, for example, it is assumed that the output terminal is connected to a read bit line 4 corresponding to A _0, the data read is performed from the memory cell is storing data "H". In this case, when the voltage of the output terminal A ₀ (FIG. 4 (b)) is in synchronization with the rise of the read clock signal RCK (FIG. 4 (a)) rises to "H" level, the read bit lines 4 As shown in FIG. 4 (c), "H"
The potential gradually decreases from the level potential Vcc- _VTH, and becomes the "L" level potential (> 0 V) determined by the above equation. And
The period precharge transistor 7 is ON state corresponding to the read bit line 4 (the voltage at the output terminal A ₀ is "H"
During the level, the potential of the read bit line 4 is maintained at the above-mentioned value. However, when the precharge transistor 7 is turned off, the power supply line 19 for supplying the power supply potential Vcc in the selected memory cell.
And the current path between the read bit line 4 and the read bit line 4 is interrupted (see FIG. 2). As a result, the read bit line 4 is turned ON.
With the storage transistor 15 and the read transistor 16 in the state, the potential is rapidly lowered to the potential 0 V of the ground 18 (see FIG. 2).

As described above, in this embodiment, the potential of the read bit line 4 rapidly changes to the original potential level corresponding to the “L” level in response to the fall of the potential level of the corresponding output terminal of the address pointer 114. (= 0 V), and as a result, the time required for the potential of the read bit line 4 to become “L” is shorter than in the conventional case.

As described above, in the present embodiment, the current flowing from the power supply to the ground via the precharge transistor 7 and the memory cell 1 at the time of data reading is small, so that the size of the precharge transistor 7 can be made larger than before. . If the size of the precharge transistor 7, that is, the driving capability is large, the read bit line 4 connected thereto is precharged to the "H" level voltage and the read bit line 4 is read out by reading data from the memory cell. The time required to reach the “H” level potential is reduced. As a result, the time for reading data from a memory cell whose stored data is “L” can be reduced.

By increasing the size of the precharge transistor 7,
For example, "L" in level potential, the read bit line 4 corresponding to the output terminals A _0, it is assumed that the data read is performed from the storage data is "L" memory cell. In this case, in response to the rise of the potential of the output terminal A _0, the potential of the read bit line 4, as shown in FIG. 4 (d), according to the size of the corresponding precharge transistors 7 "H" level potential Vcc at speed
-V Increase to _TH . However, since the size of the precharge transistor 7 is large, this speed is faster than that of the conventional one (shown by a broken line in the figure) as shown by the solid line in FIG. 4 (d).

Thus, according to this serial access memory,
The time required to set the read bit line 4 to either the “L” level potential or the “H” level potential is reduced.

The configuration and operation of the sense amplifier 102 are the same as those of the sense amplifier (the ninth
FIG. 1), and differentially amplifies the voltage of the read bit line 4 and its inverted voltage, which are input via the read bit line access transistors 8a and 8b in the ON state, respectively, and reads the read data in FIG. Buffer 104
Give to. The read data buffer 104 performs the same operation as the conventional one. That is, the read data buffer 10
4 captures the output signal of the sense amplifier 102 in response to the rise of the read clock signal RCK as shown in FIG. 3D, and holds and outputs the signal until the next rise of the read clock signal RCK. Therefore, data output terminal 10
In 6, the final potential level sensed by the sense amplifier 102 is sequentially output as read data within each one cycle of the read clock signal RCK.

Therefore, the cycle of the read clock signal RCK is set in consideration of the time required for the potential of the selected read bit line 4 to change to a predetermined potential corresponding to the data stored in the selected memory cell. However, in this serial access memory, the read bit line 4 reaches the predetermined potential faster than before. Therefore, it is possible to set a period during which the read bit line 4 is precharged and level sensed, that is, a period of the read clock signal RCK to be shorter than before. Such shortening of the cycle of the read clock signal RCK means shortening of the data read time in the serial access memory. Therefore, according to this serial access memory, it is possible to shorten the data read time as compared with the conventional case.

In the above embodiment, the case where the memory cell 1 is constituted by three transistors and one memory capacitor has been described. However, the configuration of the memory cell is not limited to this, and is used for data writing and data reading. It is sufficient if the ports have independent ports.

Further, in the above embodiment, the case where the access of the present invention is applied to a serial access memory in which addresses are performed in the order of addresses has been described. However, the present invention can be applied to other memories such as a RAM (random access memory).

[Effects of the Invention] As described above, according to the present invention, the precharge means
Since activation is performed only during a period in which the corresponding read bit line is selected, a through current flowing through the read bit line due to precharge at the time of data reading is significantly reduced as compared with the related art. As a result, the power consumption during data reading is reduced, and the time required for the potential of the read bit line to go to either the "L" level or the "H" level is shortened. It is possible to obtain a semiconductor memory device that performs the operation.

[Brief description of the drawings]

FIG. 1 is a partial circuit diagram of a serial access memory according to one embodiment of the present invention, FIG. 2 is a circuit diagram showing an internal configuration of a memory cell in the serial access memory shown in FIG.
FIG. 3 is a timing chart showing the operation of the serial access memory shown in FIG. 1 at the time of data reading, and FIG. 4 is a diagram showing the potential change of the read bit line at the time of data reading in the serial access memory shown in FIG. FIG. 5 is a schematic block diagram showing the overall configuration of the embodiment and the conventional serial access memory, FIG. 6 is a partial circuit diagram of the conventional serial access memory, and FIG. 7 is FIG. FIG. 8 is a circuit diagram showing an internal configuration of a memory cell in a serial access memory, FIG. 8 is a timing chart showing an operation at the time of data reading of the serial access memory shown in FIG. 6, and FIG. FIG. 10 is a circuit diagram showing a specific configuration of a sense amplifier used for a memory. Beauty is a circuit diagram showing a specific configuration of the read address pointer for use in a conventional serial access memory. In the figure, 1 is a memory cell, 3 is a write bit line, 4
Is a read bit line, 5 is a write word line, 6 is a read word line, 7 is a precharge transistor, 8a and
8b is a read bit line access transistor, 13 is an inverter, 14 is a write transistor, 15 is a storage transistor, 16 is a read transistor, 18 is ground, 19 is a power supply line, 100 is a memory block, 102 is a sense amplifier, 104
Is a read data buffer, 106 is a data output terminal, 108
Is a data input terminal, 110 is a write data buffer, 112 is a write address pointer, 114 is a read address pointer, 116 is a write clock terminal, and 118 is a read clock terminal. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-43894 (JP, A) JP-A-62-99976 (JP, A) JP-A-3-27207 (JP, A) JP-A-1- 98186 (JP, A) JP-A-59-217288 (JP, A)

Claims (6)

(57) [Claims] A plurality of memory cells arranged in a plurality of rows and a plurality of columns each having a write node and a read node different from the write node; A plurality of read bit lines provided corresponding to the columns and connected to the read nodes of the plurality of memory cells provided in the corresponding example, and any one bit of the plurality of read bit lines; A plurality of switch means provided corresponding to the lines and outputting an output based on the potential appearing on the corresponding read bit line when selected; and each one of the plurality of read bit lines A plurality of precharge means for precharging any one of the plurality of read bit lines corresponding to the selected read bit lines; And a plurality of output nodes corresponding to the plurality of precharge means, each output node having a corresponding switch means and an address pointer connected to the precharge means, the plurality of switch means and the plurality of precharge means. Switching means provided in correspondence to any one of the plurality of read bit lines of the plurality of read bit lines and precharge means are simultaneously selected, and switch means provided corresponding to the remaining read bit lines. And a selecting unit for setting the precharge unit to a non-selected state. 2. The semiconductor memory device according to claim 1, wherein each of said switch means has a series body of an inverter element and a transistor element. 3. Each of the precharge means includes a transistor element connected between a power supply potential node and a corresponding read bit line, the conduction / non-conduction state being controlled by the selection means. 3. The semiconductor memory device according to claim 1, wherein: 4. A plurality of memory cells arranged in a plurality of rows and a plurality of columns, each having a write node and a read node different from the write node, wherein a plurality of memory cells are arranged in the plurality of rows and correspond to each other. A plurality of write word lines connected to a plurality of memory cells arranged in a row; a plurality of read lines arranged in the plurality of rows, each connected to a plurality of memory cells arranged in a corresponding row; A plurality of word lines, a plurality of write bit lines arranged in the plurality of columns, each of which is connected to a write node of a plurality of memory cells arranged in a corresponding column; A plurality of read bit lines connected to read nodes of a plurality of memory cells arranged in a corresponding column; a read bit line and a power supply potential node arranged in the plurality of columns, each arranged in a corresponding column Connected between
A plurality of precharge means having MOS transistors, a plurality of switch means having MOS transistors arranged in the plurality of columns, each connected between a read bit line and a data line arranged in a corresponding column, A plurality of output nodes are provided corresponding to the plurality of columns and connected to the gate electrode of the MOS transistor in the switch means and the gate electrode of the MOS transistor in the precharge means, each of which is disposed in the corresponding column. And a selection means for outputting a selection signal for simultaneously turning on the MOS transistors in the plurality of switch means and the MOS transistors in the plurality of precharge means one by one from the plurality of output nodes simultaneously. Storage device. 5. The semiconductor memory device according to claim 4, wherein each of said switch means further includes an inverter element connected in series with a MOS transistor. 6. A first MOS, wherein each of the memory cells has a storage node, further connected between the write node and the storage node, and a gate electrode connected to a write word line. A transistor, a second MOS transistor having one source / drain electrode connected to the read bit line and a gate electrode connected to the read word line;
And a third MOS transistor connected between the other source / drain electrode of the second MOS transistor and a predetermined potential node and having a gate electrode connected to a storage node. Item 6. The semiconductor memory device according to item 4 or 5.