JP2589352B2 - Test method of coach circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a logic circuit, and more particularly, to a method for testing a logic circuit in which a manufacturing defect of a logic circuit is detected by measuring a standby current.

[Conventional technology]

CMOS logic circuits are P-channel MOS and N-channel MOS
Are complementarily connected to each other, so that when the input potential level is at rest, one of the P-channel MOS and the N-channel MOS is always cut off. Accordingly, there is no path through which a current flows from the power supply, and there should be no current. However, in practice, a reverse bias current of all PN junctions including a parasitic existing in the chip of the CMOS logic circuit flows.

As a means for extracting a manufacturing defect of a CMOS logic LSI or the like, an extremely small reverse bias current (standby current) flowing through a PN junction of a CMOS logic circuit in a state where an input potential level is stable is measured. If the measured standby current is significantly different from the standard standby current, a test for determining the measured CMOS logic circuit component as defective is performed.

In order to measure the standby current, it is necessary that the input potential level of the internal cell is stable. For this reason, a dedicated test pattern for stabilizing the input potential of all cells in the circuit using a normal logic operation is created, or a test is performed by extracting an input potential stable state in a logic operation based on an existing test pattern. I'm trying to do it.

[Problems to be solved by the invention]

However, when designing a dedicated test pattern for standby current measurement, it is necessary to use (1) a normal logic operation as a processing procedure for fixing the internal flip-flop to a hold state at the time of testing. The procedure is complicated.

(2) Since a normal logical operation needs to be used as a processing procedure for determining the internal tristate bus to a non-high impedance state at the time of a test, the processing procedure is complicated.

(3) Further, when actually performing the test, it is necessary to simultaneously hold the internal flip-flop in the hold state and the internal tristate bus in the non-high impedance state for the entire circuit.
It is difficult to design the processing procedure and confirm that the state is established.

(4) Further, for many circuit internal states of one logic circuit, the cost of designing and confirming a test pattern for setting the state conditions in the above (1), (2), and (3) is large. There was a problem.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for testing a logic circuit, which measures a standby current by a simple procedure and easily tests the logic circuit.

It is another object of the present invention to provide a test method of a logic circuit in which a standby current is measured using an arbitrary existing test pattern to easily test the logic circuit.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, for a logic circuit to be tested, a flip-flop incorporated in the logic circuit is forcibly held in a test mode during a test mode, and a flip-flop on a tristate bus incorporated in the logic circuit is set. A logic circuit test method is provided in which a source gate group is forcibly disabled except for only a test signal application gate, and a standby circuit is measured to determine a circuit failure and test the logic circuit.

The test method for a logic circuit according to the present invention includes a flip-flop control circuit for forcibly holding a flip-flop incorporated in the logic circuit in a test mode, a source gate on a tristate bus incorporated in the logic circuit, A tri-state bus control circuit for forcibly disabling the group except for only the test signal application gate in the test mode, in the logic circuit under test, and the flip-flop control circuit and the tri-state bus control circuit are individually provided. In the control, a period in which the whole circuit is in a static stable state is provided in a test cycle to which a test pattern signal is applied, and a standby current is measured to determine a circuit failure.

Furthermore, in the test method for a logic circuit according to the present invention, in a test mode for testing the logic circuit, a first step of applying an arbitrary test pattern to the logic circuit to be tested, and the logic circuit is incorporated in the logic circuit. A second step of forcibly putting the flip-flop in the hold state, and a third step of forcibly disabling all the source gate groups on the tristate bus built in the logic circuit except for only the test signal application gate A fourth step of measuring a standby current, a fifth step of canceling a forced disable state of a group of source gates on a tristate bus incorporated in the logic circuit, and a forcing of a flip-flop incorporated in the logic circuit The processing of the sixth step of releasing the temporary hold state is sequentially repeated.

[Action]

According to the above-mentioned means, when a test of a logic circuit is performed, a flip-flop incorporated in the logic circuit is forcibly put into a hold state with respect to the logic circuit to be tested, and a source on a tristate bus incorporated in the logic circuit is held. Circuit failure is determined by forcibly disabling all the gate groups except for the test signal application gate and measuring the standby current.

As a result, the circuit failure of the logic circuit can be easily and reliably determined without performing a test using a complicated test pattern.

Further, in order to test such a logic circuit, a flip-flop control circuit for forcibly holding a flip-flop built in the logic circuit in a test mode and a tri-state bus built in the logic circuit A tri-state bus control circuit for forcibly disabling all the source gate groups in a test mode except for only a test signal application gate; and a tri-state bus control circuit, the flip-flop control circuit and the tri-state bus control circuit. Are individually controlled to provide a period during which the entire circuit is in a static stable state in a test cycle to which a test signal is applied, and a standby current is measured to determine a circuit failure.

As a result, the circuit failure of the logic circuit can be easily and reliably determined without performing a test using a complicated test pattern.

The method of testing a logic circuit performed here includes a first step of applying an arbitrary test pattern to the logic circuit under test and a second step of forcibly putting a flip-flop incorporated in the logic circuit into a hold state. A third step of forcibly disabling all the source gate groups on the tristate bus built in the logic circuit except for the test signal application gate, a fourth step of measuring the standby current, A fifth step of releasing the forced disable state of the group of source gates on the tristate bus incorporated in the circuit, and a sixth step of releasing the forced hold state of the flip-flop incorporated in the logic circuit The processing is performed by sequentially repeating the processing.

Thereby, in the process of the logic circuit test for performing the circuit test of the logic circuit with respect to an arbitrary test pattern, it can be realized in a state for standby current measurement, and a test item for standby current measurement can be added. For this reason,
Needless to test with complex test patterns,
By adding a test item for standby current measurement, a circuit failure of a logic circuit can be easily and reliably determined.

In order to easily perform such a logic circuit test method, for example, at the time of designing a logic circuit, (1) the value of an internal flip-flop is forcibly applied from an external pin in a test mode. A flip-flop control signal suppression circuit for suppressing a control signal such as a clock signal, a set signal, and a reset signal for setting a hold state is embedded in the test mode. All the normal logic tri-state buses for forcibly bringing a non-high impingement state from an external pin are disabled, and a tri-state bus control circuit for enabling a test-only tri-state source is embedded. 3) Separate these flip-flop control signal suppression circuits and tri-state bus control circuits The test mode setting external pins to control, provided in advance. This makes it possible to easily and reliably test the above-described logic circuit.

Furthermore, in order to realize a desired state in the test mode for an arbitrary test pattern, the order of test execution is as follows: (a) setting a test mode of a logic circuit; (b) applying an arbitrary test pattern; ) Test mode setting, (d) Tri-state gate test mode setting, (e) Standby current measurement, (f) Flip-flop test mode release, (g) Tri-state gate test mode release, (h) (b) ) To (g) are repeated. In such a test execution, the test mode control external pins are independently controlled by a flip-flop control system and a tri-state bus system to perform a test.

The flip-flop control signal suppressing circuit provided in the logic circuit operates to suppress the flip-flop control signal in the test mode, regardless of the values of the data input terminal and the control signal terminal of each flip-flop. . Therefore, the internal state of the flip-flop can be forcibly held in the test mode. In the test mode, the tristate bus control circuit operates so as to enable only the test dedicated tristate source and disable other tristate sources. Therefore, the value of the bus line can be forcibly set to a non-high impedance state from an external pin.

The test execution order changes the value of the tri-state bus after the flip-flop is held, and releases the hold of the flip-flop after the recovery of the value of the tri-state bus. Input and stored values do not change before and after the test mode. Thereby, the order of any test pattern is not disturbed.

Since the test mode control external pins can make the flip-flop control system and the tristate bus control system independent, the test execution procedure can be controlled by the pattern application procedure from the test apparatus. When the external pins for the test mode control are shared by the flip-flop control system and the tri-state bus control system, the internal phase control circuit controls the signals for each control system so that they are independent. As in the case where
The test execution procedure can be controlled by a pattern application procedure from the test apparatus.

〔Example〕

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

In all the drawings for describing the embodiments, the same components are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a circuit diagram specifically showing a configuration of a main part at the time of a test of a logic circuit that implements a logic circuit test method according to an embodiment of the present invention in one aspect. Also, FIG.
FIG. 3 is a circuit diagram illustrating a main configuration of the logic circuit of FIG.

Here, as shown in FIG. 2, the logic circuit for testing the standby current measurement includes a combinational logic unit 21, a flip-flop 22, a combinational logic unit 23, tri-state elements 24a and 24b, a combinational logic unit 25, and a flip-flop. It is assumed that the logic circuit 20 has the loops 26 connected in series.

In order to perform a standby current measurement test on such a logic circuit 20, as shown in FIG. It is assumed that a tristate bus control circuit 12 for forcing the elements 24a and 24b into the non-high impingement state and a flip-flop control signal suppressing circuit 13 for forcing the flip-flop 22 into the hold state are provided. When performing a standby current measurement test to test a logic circuit,
By these circuits (11, 12, 13), the flip-flop in the logic circuit is forcibly brought into the hold state, and the tri-state element is forcibly brought into the non-high impedance state except for the tri-state element for applying the test signal.

With reference to FIG. 1, the description of the circuit configuration of the flip-flop control signal suppressing circuit and the tri-state bus control circuit provided in the logic circuit under test will be continued. In FIG. , 17 are flip-flop system control external pins. The flip-flop control signal suppression circuit 11 suppresses the control signal of the flip-flop 22 by the AND gates 11a, 11b, and 11c in the test mode, and passes the control signal in the non-test mode to enable normal logic operation. Circuit. Also,
The tri-state bus control circuit 12 disables the tri-state elements 24a and 24b in the test mode by the OR gates 12a and 12b, enables normal logic operation in the non-test mode, and furthermore, the tri-state element 12c In the test mode, the test data applied to the input pin 15 is set on the bus line 16, and is disabled in the non-test mode. The flip-flop control signal suppression circuit 13 includes AND gates 13a, 13b, 13c
Is a circuit that suppresses the control signal of the flip-flop 25 in the test mode and sets it to the hold state, and passes the control signal in the non-test mode to enable normal logic operation.

FIG. 3 is a diagram showing a time chart of an operation of giving a test pattern to a logic circuit under test. As shown in FIG. 3, each test cycle is repeatedly performed at predetermined intervals. Test pattern signals other than the test external pins change as necessary at timings 31 and 37 of each test cycle. Corresponding to the timing of each test cycle, the signal of the flip-flop system control external pin and the signal of the tristate bus system control external pin change as shown.

The test operation of the test target logic circuit will be described. When a normal test pattern signal is applied at the beginning timing 31 of the test cycle 1, the signal of the flip-flop system control external pin 17 is at the H (High) level at this time, and the flip-flops 22, 26 Control signal terminal C
Signals during normal logic operation reach the (clock) terminal, the S (set) terminal, and the R (reset) terminal. At this time, the external pins 14
Is at the L (Low) level, and a normal logic operation signal has reached the enable terminals of the tri-state elements 24a and 24b. Also, the tri-state element 12c
Is disabled and does not affect the normal logical operation of the bus line 16. After the input stimulus given by the test pattern signal propagates through the circuit and stabilizes, when the signal of the flip-flop system control external pin 17 is set to L level at the timing 32, the control signals for the flip-flops 22 and 26 are suppressed, The flip-flops 22 and 26 hold the flip-flop set value at that time. After the hold state of the flip-flop is determined, when the signal of the external pin 14 for controlling the tri-state bus system is set to the H level at the timing 33, the tri-state elements 24a and 24b are disabled. Also, the tri-state element 12c
Are enabled, and the level given by the signal from the input pin 15 is set to the bus line 16. At a timing 34 after the circuit is sufficiently stabilized with respect to the input stimulus of the tristate bus system control external pin 14, the flip-flop is in the hold state, and the tristate bus is in the L or H state.
The level becomes a stable state, and at this time, the whole circuit is in a static stable state, so that the requirement for measuring the standby current is satisfied. Therefore, the standby current is measured at the timing.
Thereafter, when the signal of the tristate bus system control external pin 14 is set to L level at the timing 35, the bus line 16 is restored to the state before the test mode. Timing 36 after this
When the signal of the flip-flop system control external pin 17 is set to H level, the value of the signal at the input terminal of the flip-flop has already been recovered at the previous timing 35 before the test mode. The flip-flop also returns to the state before the test mode. The same procedure is repeated in test cycle 2 starting from timing 37 by adding a test pattern signal, and the necessary number of test cycles is repeated in the same procedure.

In this example, the test of the standby current measurement is performed for each successive test cycle.
The test of the standby current measurement may be performed only for a specific test cycle.

Next, another embodiment of the present invention will be described. First, another example of the flip-flop control circuit and the tristate bus control circuit used in the test method of the logic circuit will be described.

FIG. 4 is a diagram showing another embodiment of the flip-flop control circuit. In the circuit example of FIG. 1, the flip-flop control circuit is a circuit configured by an independent gate group. However, as shown in FIG. 4, a flip-flop 41 of a basic circuit cell forming a logic circuit is a flip-flop control circuit. Flip-flop AND gates 42a, 42b, 42c of the flip-flop control circuit
A circuit equivalent to 43 and taken into the cell is used. In this case, since a flip-flop cell to which a gate for controlling supply of a control signal to the flip-flop is added is used for forming a logic circuit, a gate of the flip-flop control circuit is not particularly provided. Alternatively, a gate already provided in a peripheral circuit of the flip-flop may be used as a gate of a similar flip-flop control circuit. In the case where a test gate circuit for performing a test is incorporated by a logic circuit system based on a test facilitation design, such a test gate circuit may be used.

5a and 5b show another embodiment of the tristate bus control circuit. In this circuit example, as shown in FIG. 5a, a tri-state element 53 as a tri-state element cell 51 of a basic circuit cell constituting a logic circuit,
Use a control OR gate 52 equivalent to the inside of the cell and use it as a tri-state gate for applying a test signal, as shown in Fig. 5b. This uses a cell 54. The dedicated cell 54 is a cell in which the tri-state element 55 is built. When a logic circuit is configured using these basic circuit cells, a circuit configuration as shown in FIG. 6 is obtained.
The logic circuit of FIG. 6 has the same configuration as that of FIG.
This is a circuit configured using each basic circuit cell shown in FIGS. 4, 5a and 5b. In these basic circuit cells, a control circuit is incorporated at the gate level inside the cell. However, by realizing equivalent circuit operation at the transistor level, a logic circuit configuration in which overhead such as delay or cell area is reduced is realized. It can also be.

FIG. 7 is a phase control circuit showing another embodiment relating to an external pin for test control. In FIG. 7, reference numeral 71 denotes an external pin for test control, 72 denotes a signal terminal to a flip-flop control system, and 73 denotes a signal terminal to a tristate bus control system. 74, 75, and 76 are AND gates having delay values d1, d2, and d3, respectively. Using this phase control circuit, the signal terminal 72 is connected to the flip-flop control external pin 17, and the signal terminal 73 is connected to the tri-state bus control external pin.
By connecting to 14, the number of external signal pins for test control of the logic circuit can be reduced to one.

FIG. 8 is a time chart showing the operation of the phase control circuit relating to the external signal pin for test control shown in FIG. As shown in the time chart of FIG.
4, AND gate 75 and AND gate 76 each have delay value
It has d1, d2 and d3, and external test control pin 71
When the waveform shown in the timing signal 77 is applied as an external control signal, the timing signal 78 is output to the signal terminal 72, and the timing signal 79 is output to the signal terminal 73. The delay values 91, 92, and 93 of the timing signal waveforms output from these terminals are set to correspond to the timings 31, 32, and 33 in the time chart of FIG. d1 to d3, and timing
By appropriately setting 91 and 94, a configuration in which the external pin for test control is one pin can be realized.

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various changes can be made without departing from the scope of the invention.

〔The invention's effect〕

As described above, according to the present invention, as a test of a logic circuit, an internal flip-flop is easily held from an external pin with a small amount of hardware control overhead, and a tristate bus is set to a non-high impedance state. , A standby current measurement can be performed. As a result, there is no need to test a logic circuit by designing a dedicated test pattern for standby current measurement or searching for a test pattern that meets the standby current measurement requirements from existing test patterns, and performing logic circuit tests. Therefore, there is an effect of reducing the cost.

In addition, by performing a logic circuit test in the test execution procedure according to the present invention, an existing test pattern can be used as it is and can be used as a standby current measurement pattern, so that the design cost of the logic circuit test pattern can be reduced. This has the effect of reducing test pattern file resources and the like. Furthermore, by using a pattern such as a DC function test for an existing pattern, it becomes possible to measure the standby current for an extremely large number of circuit internal states, thereby improving the test performance of the test pattern and making it easier and more reliable. Logic circuits can be tested.

[Brief description of the drawings]

FIG. 1 is a circuit diagram specifically showing a main configuration of a logic circuit at the time of testing, which implements a method for testing a logic circuit according to an embodiment of the present invention in one aspect. FIG. FIG. 3 is a circuit diagram showing a configuration of a main part of the logic circuit at the time of non-test, FIG. 3 is a diagram showing a time chart of an operation of applying a test pattern to a logic circuit under test, and FIG. 4 is another embodiment of a flip-flop control circuit; FIGS. 5a and 5b show an example of another embodiment of the tristate bus control circuit, and FIG. 6 shows a main configuration of a logic circuit of another embodiment of the present invention. FIG. 7 is a circuit diagram of a phase control circuit showing another embodiment relating to external pins for test control, and FIG. 8 is a phase control circuit relating to external signal pins for test control shown in FIG. 6 is a time chart showing the operation of the first embodiment. In the figure, 11, 13 ... flip-flop control circuit, 12 ... tri-state bus control circuit, 14 ... external pin for tri-state bus control, 17 ... external pin for flip-flop control,
Reference numeral 20: logic circuit, 21, 23: combinational logic unit, 22, 26: flip-flop, 24a, 24b: tri-state element, 41: flip-flop cell, 51: tri-state element cell, 54: cell dedicated to test signal application.

Claims (3)

(57) [Claims] In a test mode, a flip-flop incorporated in a logic circuit is forcibly held in a test mode, and a source gate group on a tristate bus incorporated in the logic circuit is subjected to a test signal. A test method for a logic circuit, characterized in that a circuit failure is determined by forcibly disabling all except an application gate and measuring a standby current. 2. A flip-flop control circuit for forcibly holding a flip-flop built in a logic circuit in a test mode in a test mode, and a test signal in a test mode in a source gate group on a tri-state bus built in the logic circuit. A tri-state bus control circuit for forcibly disabling all except for the application gate is provided in the logic circuit under test, and the flip-flop control circuit and the tri-state bus control circuit are individually controlled so that the test signal is A test method for a logic circuit, comprising: providing a period in which a whole circuit is in a static stable state in a given test cycle, and measuring a standby current to determine a circuit failure. 3. A first step of applying an arbitrary test pattern to a logic circuit under test, a second step of forcibly putting a flip-flop incorporated in the logic circuit into a hold state, and a step of incorporating the flip-flop in the logic circuit. A third step of forcibly disabling all of the source gates on the tristate bus except for the test signal application gate, a fourth step of measuring a standby current, and a tristate incorporated in the logic circuit. A step of releasing the forced disable state of the source gate group on the bus and a sixth step of releasing the forced hold state of the flip-flop included in the logic circuit are sequentially and repeatedly performed. A method for testing a logic circuit, comprising: