JP2588361B2 - Laser device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laser device that oscillates a laser beam by using energy stored in an energy storage capacitor. In particular, the present invention can quickly adjust the energy level of an energy storage capacitor when changing the energy level. To a laser device.

[0002]

2. Description of the Related Art Laser devices are widely used for medical or industrial purposes, or for display and decoration purposes. In the case of medical or industrial use, adjustment of the energy level of the laser output is important for appropriate treatment or processing of industrial products.

FIG. 4 shows an outline of the configuration of a conventional laser device capable of adjusting the energy level of a laser output. This figure is a block diagram showing a general configuration of a pulse laser device.

In FIG. 4, reference numeral 21 denotes a commercial AC power supply, and 22 denotes a rectifier circuit.
This is for receiving the AC power from No. 1 and rectifying it to obtain DC power, which is a main power source for laser oscillation and is for obtaining large-capacity DC power. An auxiliary DC power supply 23 receives AC power from the commercial AC power supply 21, rectifies the AC power, and obtains DC power at a low voltage level required for system control.

A DC / AC inverter circuit 24 includes a switching element and an inverter transformer having an output voltage of several KV. This DC /
The AC inverter circuit 24 converts the output of the rectifier circuit 22 into a high-frequency high-voltage alternating current. The AC voltage is set higher than the maximum charging voltage (maximum required energy) for the energy storage capacitor 27. This is to shorten the charging time.

Reference numeral 25 denotes a high-voltage rectifier circuit, 26 denotes a charging current suppressing resistor, 27 denotes an energy storage capacitor, 28 denotes a voltage dividing resistor, 29 denotes a discharge resistor, and 30 denotes an inductance. The high voltage rectifier circuit 25 is a DC / AC inverter circuit 2
4 to rectify the high-voltage AC output to DC. The output side of the high-voltage rectifier circuit 25 is connected to an energy storage capacitor 27 via a charging current suppressing resistor 26 so that the energy storage capacitor 27 can be charged.

Reference numeral 31 denotes a switching element, and the charge stored in the energy storage capacitor 27 is supplied to the flash lamp 32 via the inductance 30 and a series circuit of the switching element 31.

[0008] The switching element 31 is controlled by a control circuit 37 to open and close the energy of the flash lamp 32. Numeral 33 denotes a solid-state laser resonance rod, at both ends of which a light-reflecting mirror (not shown) is arranged to face each other, and is arranged in parallel with the flash lamp 32. When the light is incident, the light is caused to resonate within the rod by the reflection effect of the mirror, thereby exciting the laser light.

The charging current suppressing resistor 26 is for suppressing the charging current of the energy storage capacitor 27.
The voltage dividing resistor 28 is connected in parallel with the energy storage capacitor 27, and divides and extracts the charging voltage of the energy storage capacitor 27. The discharge resistor 29 is connected in parallel with the energy storage capacitor 27 and discharges the charge stored in the energy storage capacitor 27. Discharge resistor 29
Is connected in series with an open / close switch (contact point of a discharge relay 38 described later). By closing the open / close switch, the discharge resistor 29 is connected in parallel with the energy storage capacitor 27 to discharge the charge. I can do it.

The inductance 30 forms an LC circuit with the energy storage capacitor 27 and regulates the pulse width to the flash lamp 32 and the load current peak value. The energy storage capacitor 27 serves as a power source for the flash lamp 32,
By receiving a DC voltage from the inverter circuit 24 via the inverter 6, the electric charge is charged, and the charge becomes a DC voltage supply source for the flash lamp 32.

Reference numeral 33 denotes a solid-state laser resonance rod. Opposite ends of the solid-state laser resonance rod are provided with light-reflecting mirrors (not shown), and are disposed in parallel with the flash lamp 32. When the light is incident by the light emission, the light is caused to resonate in the rod by the reflection action of the mirror, thereby exciting the laser light.

Reference numeral 34 denotes an energy level selection circuit. The energy level selection circuit 34 is composed of a group of switches provided corresponding to the energy levels. When any one of these switches is turned on, the inverter circuit 24 starts.

Reference numeral 35 denotes an inverter drive circuit, which has a DC /
A circuit for controlling the driving of the AC inverter circuit 24, which compares the oscillation circuit of the inverter driving pulse with the driving element, the reference voltage group corresponding to the switch group of the energy level selection circuit 34, and the feedback voltage of the voltage dividing resistor 28. And a comparator. Then, the voltage dividing resistor 28
When the feedback voltage exceeds the selected reference voltage, the pulse oscillation is stopped, the operation of the inverter circuit 24 is stopped,
Thereby, the charging of the energy storage capacitor 27 is stopped, and when the terminal voltage of the energy storage capacitor 27 drops, a servo circuit is formed so that the inverter circuit 24 operates again. Thus, the charging voltage to the energy storage capacitor 27 is maintained at the reference voltage value.

Reference numeral 36 denotes a laser irradiation switch for instructing laser irradiation, and 37 denotes the aforementioned control circuit.
When the laser irradiation switch 36 is turned on, a gate trigger pulse for the switching element 31 is generated to turn on the switching element 31 and apply the charging voltage of the energy storage capacitor 27 to the flash lamp 32 and Generating an ignition pulse for the lamp 32,
Is controlled to output a laser beam having an energy corresponding to the charging voltage of the energy storage capacitor 27. At this time, the control circuit 37 is configured to stop the operation of the inverter circuit 4 at the same time. When the irradiation switch 36 is turned off, the energy storage capacitor 27 is charged to the selected energy level again and waits. Further, the control circuit 37 monitors the comparator output of the inverter drive circuit 35, and operates until the reference voltage group corresponding to the switch group of the energy level selection circuit 34 and the feedback voltage of the voltage dividing resistor 29 reach the reference voltage level. Even if the irradiation switch 36 is operated, laser light cannot be oscillated.

Reference numeral 38 denotes a discharge relay whose contact is configured to short-circuit the terminals of the energy storage capacitor 27 so that unnecessary charges can be discharged. When the discharge relay 38 is stopped (when the commercial AC power supply 21 is turned off), the contact 38a is closed and forms a discharge circuit. However, when the commercial AC power supply 21 is turned on, the contact 38a is energized and the contact 38a is turned on. Open to secure the charging circuit of the energy storage capacitor 27 and enable the operation of the device. The discharge relay 38 is also for preventing harm to the residual charge of the energy storage capacitor 27.

In such a configuration, the commercial AC power supply 2
When 1 is turned on to start power supply, the contact of the discharge relay 38 is turned off, and the energy storage capacitor 27 can be charged. In this state, the energy level selection circuit 3
When the switch for selecting the desired energy level of No. 4 is turned on, the inverter drive circuit 35 is activated, and the inverter circuit 24 is operated.

The output of the commercial AC power supply 21 is applied to the inverter circuit 24 via the rectifier circuit 22, and a DC voltage obtained by rectification by the rectifier circuit 22 is supplied to the inverter circuit 24. Therefore, the inverter circuit 2
4 converts this DC voltage into a high-frequency AC voltage and outputs it. The output of the inverter circuit 24 is rectified by the high-voltage rectifier circuit 25 and applied to the energy storage capacitor 27 via the charging current suppression resistor 26, so that the energy storage capacitor 27 has the selected energy level. Such high voltage charges are accumulated.

When charging is completed, laser irradiation is enabled. When the laser irradiation switch 36 is turned on in this state, the control circuit 37 generates a gate trigger pulse for the switching element 31 and generates an ignition pulse for the flash lamp 32. The switching element 31 is turned on by the gate trigger pulse, whereby the energy charged in the energy storage capacitor 27 is applied to the flash lamp 32,
Further, the flash lamp 32 is discharged by the ignition pulse. Then, the light due to this discharge is incident on the solid-state laser resonance rod 33, and is optically resonated in the rod to excite the laser light.

[0019]

As described above, the solid-state laser rod is excited by using the charge of the capacitor as an energy source, laser is oscillated, and the energy level stored in the capacitor can be selected. In the conventional laser oscillation device having the above-described configuration, by selecting the energy level selection circuit 34,
Under the control of the inverter drive circuit 35, a high voltage output is generated from the DC / AC inverter circuit 24. However, when the switch of the energy level selection circuit 34 is operated to selectively switch from a low value to a high value of the energy level, the servo circuit of the energy level selection circuit 34 follows in a short time, but from a high value of the energy level to a low value. A problem arises when choosing a value.

That is, since the terminal voltage of the energy storage capacitor 27 drops only by self-discharge or discharge by the voltage dividing resistor 28, the discharge time is determined by the time constant of the circuit. Since the self-discharge is reduced in order to reduce the voltage fluctuation due to the discharge and increase the stability, and the voltage dividing resistor itself is also a high resistance in order to reduce the consumption here, a high energy level (high When the setting is changed to a low energy level (low voltage) with the battery charged to the charging voltage, the power supply follows the large time constant until the set level is settled. The larger the time, the longer it takes to reach the desired energy level, during which laser oscillation cannot be performed, which is inconvenient in practice.

The object of the present invention is to:
Exciting the laser rod with the capacitor as the energy source,
It is an object of the present invention to provide a laser oscillation device which is capable of selecting an energy level to be stored in the capacitor while performing laser oscillation, so that when the energy level is changed, the laser can be oscillated in a short time.

[0022]

In order to achieve the above object, the present invention is configured as follows. That is, first, the charging circuit is controlled to the set level by the selection setting means for selecting and setting a desired energy level, and the energy storage capacitor is charged to a desired voltage value and supplied to the laser oscillation source. In the laser device provided with, while providing a circuit for discharging the energy storage capacitor, when the setting level by the selection setting means is changed to a level lower than the current setting level, the discharging circuit is operated for a predetermined time, A first function for forcibly discharging and a second function for controlling to shift to charge control after completion of the forcible discharge.
And an energy level selection control means having the above function.

Secondly, there is provided detection means for detecting the energy level of the energy storage capacitor, and selection setting means for selecting and setting a desired energy level, and charging to the level set by the selection setting means. While controlling the circuit and monitoring the detection output by the detection means, a laser device that charges an energy storage capacitor to a desired voltage value, and supplies the charged energy to a laser oscillation source for laser oscillation. A discharging circuit is provided in the capacitor, and the difference between the energy level of the energy storage capacitor and the level set by the selection setting means is detected using the detection output of the detection means, and the charging voltage of the energy storage capacitor is determined by the selection setting means. When the level is higher than the set level, the discharging circuit is operated for a predetermined time, After features are discharged and forced discharge end was constructed to have the energy level selection control means and a function of controlling so as to shift the charging control.

[0024]

In such a configuration, when the laser light is oscillated using the energy stored in the energy storage capacitor, the setting of the energy level is varied by the selection setting means. If it is for a lower level, the discharge circuit is activated to forcibly discharge the energy stored in the energy storage capacitor for a predetermined time before charging.

Further, in the case of the second configuration, the energy level selection control means detects the difference between the energy level of the energy storage capacitor and the level set by the selection setting means using the detection output of the detection means. When the charge voltage is higher than the level set by the selection setting means, the discharge circuit is operated for a predetermined time to perform forcible discharge, and then control is made to shift to charge control.

As described above, since the charging operation is started after the surplus energy is discharged, when the voltage (energy level) of the energy storage capacitor is high when the laser oscillation energy setting level is changed, the operation is forcibly performed. Discharging by operating a discharge circuit, and charging after lowering the charging voltage level of the energy storage capacitor, thereby ending the time-consuming charge voltage drop (energy release) of the energy storage capacitor in a short time. And the energy storage capacitor can be quickly charged to a desired level. Therefore, laser oscillation can be performed in a short time after the level setting operation, and a laser device with good usability can be obtained.

In particular, when the lower energy level is selected from the upper energy level, the surplus energy of the energy storage capacitor is first released and then charged to the required energy level, so that the energy level can be set without delay.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of the present apparatus. The laser device of the present invention is obtained by improving the energy level selection circuit, and the other basic configuration is the same as the configuration of the conventional device described with reference to FIG. Therefore, the same components as those in the conventional example of FIG. 4 are denoted by the same reference numerals, but the details thereof will not be described again here.

In FIG. 1, reference numeral 21 denotes a commercial AC power supply;
Is a rectifier circuit, 23 is an auxiliary DC power supply, 24 is a DC / AC inverter circuit, 25 is a high voltage rectifier circuit, 26 is a charging current suppression resistor, 27 is an energy storage capacitor, 28 is a voltage dividing resistor, and 29 is a discharge resistor. Vessel, 30 is inductance,
31 is a switching element, 32 is a flash lamp,
33 is a solid-state laser resonance rod.

A light reflecting mirror (not shown) is disposed at both ends of the solid-state laser resonance rod 33 so as to face each other, and is disposed in parallel with the flash lamp 32. Accordingly, when the light is incident, the light is caused to resonate in the rod by the reflection action of the mirror, thereby exciting the laser light.

Numeral 34A is an energy level selection circuit.
The energy level selection circuit 34A has a group of switches provided corresponding to the energy levels. When any one of the switches is turned on, the DC / AC inverter circuit 24 starts.

Reference numeral 35A denotes an inverter drive circuit which is DC / AC
This is a circuit for controlling the drive of the inverter circuit 24. The circuit is provided by decoding an inverter drive pulse oscillation circuit and a drive element, and a switch group of the energy level selection circuit 34A by a decoder 2 incorporated in the energy level selection circuit 34A. The comparator includes a comparator that compares a reference voltage group corresponding to the value with a feedback voltage of the voltage dividing resistor 28. Then, when the feedback voltage exceeds the selected reference voltage, the pulse oscillation is stopped, the operation of the inverter circuit 24 is stopped, and the energy storage capacitor 2 is thereby stopped.
7 is stopped, and when the terminal voltage of the energy storage capacitor 27 drops, the inverter circuit 24
The servo circuit is formed so as to operate.

Reference numeral 36 denotes a laser irradiation switch, and 37 denotes the above-described control circuit. When the laser irradiation switch 36 is turned on, a gate trigger pulse for the switching element 31 and the flash lamp 3
2 to generate an ignition pulse, control the flash lamp 32 to emit light, and output a laser. At this time, the control circuit 37 is configured so that the operation of the inverter circuit 24 is stopped at the same time.
When the irradiation switch 36 is turned off, the energy storage capacitor 27 is charged to the selected energy level again and waits. Further, the control circuit 37 includes an inverter driving circuit 35.
The comparator output of A is monitored, and the laser irradiation switch 36 is operated until the reference voltage group corresponding to the switch group of the energy level selection circuit 34A and the feedback voltage of the voltage dividing resistor 28 reach the reference voltage level. Light cannot be oscillated.

Reference numeral 38 denotes a discharge relay whose contact is configured to short-circuit the terminals of the energy storage capacitor 27 so that unnecessary charges can be discharged. The contact is closed when the discharge relay 38 is stopped (when the commercial AC power supply 21 is off), and when the commercial AC power supply 21 is turned on, the contact is opened, the contact is opened, and the device becomes operable. This discharge relay 38 is for preventing harm to the residual charge of the energy storage capacitor 27.

The above is the schematic configuration of the entire laser device. In the present invention, the energy level selection circuit 34
A has a feature, which is configured as shown in FIG. In FIG. 2, 1 is an energy level selection switch,
This corresponds to the energy level selection switch 34A in FIG. 4, and as an example, the switches LS1 to LS7
And the level can be selected for each switch, so that the switches LS1 to LS7
7 levels can be selected by the 7 switches. Then, LS1 is selected as the lowest energy (lowest charging voltage to the energy storage capacitor 27), and LS7 is selected as the highest (highest charging voltage) energy. Seven levels can be selected by the switches LS1 to LS7. The selectable level is LS7 which is the maximum, becomes lower as it is closer to LS1, and the energy level is set to zero when LS1 to LS7 are all off. .

Reference numeral 2 denotes an encoder, which is an 8-bit priority encoder (8-BIT PRIORITY ENCODER) IC
It is configured using elements (semiconductor integrated circuit elements).
The encoder 2 has data input terminals D1 to D7, data output terminals Q0 to Q2, and a GS terminal. In this embodiment, the least significant bit data input terminal D0 of this IC element is not used.

The encoded output of the encoder 2 is a binary code, and the GS terminal is a data input terminal D1.
To "D7" when there is an input to any of D7 to D7. In this embodiment, each of the switches LS1 to LS7 has one end connected to the DC system power supply VDD, and the other end connected to the data input terminals D1 to D7 of the encoder 2 one by one. The data input terminals D1 to D7 of the encoder 2 are grounded via pull-down resistors, respectively. When the corresponding switches LS1 to LS7 are turned off, they are kept at the ground potential and set to the logic level "L". Are maintained at the VDD level and become a logic level "H".

The encoder 2 receives any data from "1" to "7" depending on which of the data input terminals D1 to D7 is at the logic level "H". Outputs appear at the data output terminals Q0 to Q2 in binary data format according to the data. That is, the seven levels are converted to binary data format 3.
Has the function of an encoder that outputs in bit parallel. Further, the encoder 2 is configured to output the output "H" from the GS terminal while the input of any one of the data input terminals D1 to D7 is set to "H".

Reference numeral 3 denotes a decoder, which is composed of a BCD TO DECIMAL DECODER IC element. This BCD decimal decoder IC element has data input terminals A, B, C, D and data output terminals Q0 to Q7.
However, the data input terminal D and the data output terminal Q0 of this IC element are not used. The data input terminals A, B, and C of the decoder 3 are connected to the data output terminals Q0, Q1, and Q2 of the encoder 2 so that a binary data format 3-bit parallel, which is the encoded output of the encoder 2, is converted to a BCD decimal code. To decode.

Reference numeral 4 denotes a latch circuit, which is configured using a dual 4-bit latch (DUAL 4-BIT LATCH) IC element. Of the two circuits, all terminals of one of the circuits are used while the other is used. The terminals D4 and Q4 are not used, and the clock input terminal CK is connected in parallel. The latch circuit 4 acquires input data at the rising edge of the clock pulse and latches the input data at the falling edge.

The latch circuit 4 is provided with one of the dual 4-bit data input terminals D1 to D4 and D1 'to D4'.
D4 to D4 are connected in correspondence with the lower 4 bits of a BCD (binary code decimal; binary coded decimal) code, and D1 'to D4' are connected in correspondence with the upper 3 bits. . Therefore, the latch circuit 4 is capable of latching BCD code data corresponding to up to seven levels output from the decoder 3.

Reference numeral 5 denotes a pulse generating circuit, which is constituted by using an inverter (HEX INVERTER) IC element containing six inverter logic circuits (hereinafter referred to as an inverter), of which an inverter 5a and an inverter 5b are provided.
And a differentiating circuit including a capacitor C1 and a resistor R1 is provided to differentiate the GS terminal output of the encoder 2, generate a waveform, generate a clock pulse (single pulse), and apply it to one input of the NAND gate 8. The clock pulse is delayed and output via a delay unit formed by providing a pulse delay circuit including a capacitor C2 and a resistor R2 between the inverter 5c and the inverter 5d. The delayed clock pulse output from pulse generation circuit 5 is applied to latch circuit 4 and D
The configuration is such that the input to the clock input terminal CK of the latch 6 is given to these.

The D latch 6 is a quad clocked D
A latch (QUAD CLOCKED “D” LATCH) is configured using an IC element, and has a data input terminal D3 and a data output terminal Q
3 is not used. This IC element acquires (acquires) input data at the rising edge of a clock pulse and latches data at the falling edge. Input data of the D latch 6 is output data of the encoder 2.

Reference numeral 7 denotes a comparator, which is a 4-bit magnitude comparator (4-BIT MAGNITUDED COMPARETO).
R) It is configured using IC elements. The comparator 7 has A input terminals A0 to A3 and B input terminals B0 to B3.
And both A input terminals A0 to A3 and B input terminal B
This is for comparing inputs of 0 to B3. The comparator 7 does not use the A input terminals A3 and B input terminal B3. As a comparison result, "A = B" (A input terminal input = B input terminal input), "A>B" (A input terminal input> B Input terminal input), the output of logic level "L" is output as the comparison output.
“A <B” (A input terminal input <B input terminal input)
In this case, it is set so as to generate a logic level "H" output.

As a result, when the input is “A <B” or “A = B”, the output “H” is output from the comparison result output terminal A <B output terminal of the comparator 7 and the input is “ If "A>B","L" is output. This "H" or "L" output is inverted by an inverter 5e to obtain an "L" or "H" output. The A input terminal input of the comparator 7 is latch data of the D latch 6, and the B input terminal input is output data of the encoder 2.

The NAND gate 8 has a two-input positive
A NAND gate, which is obtained by inverting the output of 7 with an inverter 5e as the other input. Reference numeral 9 denotes a timer, which is configured using a timer IC element.
Capacitor C and resistor R which are time constant elements for timing
Are not shown. The timer 9 is used in the monostable operation mode, and is started by giving a negative trigger pulse to the trigger input terminal TR, so that a positive timing
A pulse (a voltage equivalent to the voltage of the system power supply VDD, for example, 5 V) is output, but the output has a logic level "L" (0 V) and a high sink current at rest. The timer 9 outputs the output of the NAND gate 8 to the trigger input terminal TR.
It is as a structure given to.

Reference numeral 38 denotes a discharge relay, which is the discharge relay 38 shown in FIG. 1, and reference numeral 29 denotes a discharge resistor, which is the discharge resistor 29 shown in FIG. The discharge coil of the discharge relay 38 has one end connected to the system power supply VDD and the other end connected to the output side of the timer 9, and operates in response to the output state of the output terminal of the timer 9. The contact of the timer 9 is configured to short-circuit the terminals of the energy storage capacitor 27, and discharges unnecessary charges of the energy storage capacitor 27.

The timer 9 is provided before the discharge relay 38 and supplies an output for energizing the discharge relay 38. Therefore, when the timer 9 is stopped, the output becomes "L". , The discharge relay 38 is energized by the voltage from VDD flowing through the timer 9 and its contact is opened, and when the timer 9 outputs the timing signal (logic level "H"), the output voltage becomes VDD and Since they are equal, the discharge relay 38 is inactive and its contacts are "closed",
The charge of the energy storage capacitor 27 is discharged through the discharge resistor 9. Thus, the characteristic of discharging the charge of the energy storage capacitor 27 can be freely selected according to the resistance value of the discharge resistor 29 and the timing time.

Reference numeral 35A in FIG. 2 denotes an inverter drive circuit, which corresponds to the inverter drive circuit 35A in FIG. When one of the switches LS1 to LS7 in the energy level selection switch 1 is turned on, the inverter drive circuit 35A selects a reference voltage corresponding to the switch, and outputs the reference voltage and the feedback voltage from the voltage dividing resistor 28 in FIG. And set a desired energy in the energy storage capacitor 27.

That is, the energy level selection switch 1
When any of the switches LS1 to LS7 is turned on, the encoder 2 outputs a corresponding 3-bit parallel binary code from the encoder 2, and the decoder 3 decodes this binary data into a BCD decimal code, and this BCD decimal code is latched. The circuit 4 latches the data at the timing of the delayed clock pulse c of the pulse generating circuit 5, and the output data of the latch circuit 4 is made to correspond to preset selection data of various reference voltages that are different in stages.

As described above, the latch circuit 4 has the dual 4-bit data input terminals D1 to D4, D1 'to D4'.
Among them, D1 to D4 are connected to correspond to the lower 4 bits of a BCD (binary code decimal; binary coded decimal) code, respectively, and the upper 3 bits are connected to D1 'to D4'.
Since the bits are connected in correspondence with each other, this latch circuit 4 can latch BCD code data corresponding to up to seven levels output from the decoder 3.

Accordingly, in this case, various reference voltages of seven levels are prepared in the inverter drive circuit 35A in advance, and the inverter drive circuit 35A selects one of the seven levels of reference voltages in accordance with the BCD code data so that it can be used. The circuit 35A is configured.

Next, the operation of the present apparatus having the above configuration will be described. In such a configuration, upon receiving power supply from the commercial AC power supply 21, the rectifier circuit 22 rectifies the AC power and supplies it to the DC / AC inverter circuit 24.

The DC / AC inverter circuit 24 is controlled by an inverter drive circuit 35A. The inverter drive circuit 35A selects a reference voltage corresponding to the setting of the energy level selection switch 1 in the energy level selection circuit 34A, and sets the reference voltage as the reference voltage. A corresponding energy storage capacitor 27 output voltage can be obtained.

As described above, the inverter drive circuit 35A that operates according to the setting of the energy level selection switch 1
Is converted into a DC voltage by a high voltage rectifier circuit 25 and supplied to an energy storage capacitor 27 via a charging current suppressing resistor 26. The storage capacitor 27 is charged with a DC charge of a desired voltage according to the setting of the energy level selection switch 1.

Various cases of changing the charging voltage by changing the setting of the level selection switch 1 will be specifically described. Now, an operation will be described in which a desired voltage is set from the level “0 V”, the capacitor 27 is charged to that voltage, and then the level is further reset.

It is assumed that the switches LS1 to LS7 of the energy level selection switch 1 are off, and in this state, the auxiliary power supply 23 supplies the system power V _DD as a DC power.
Is supplied.

Then, the encoder 2 outputs a binary code "000" corresponding to the setting state of the switches LS1 to LS7 of the energy level selection switch 1 (LS1 to LS7).
(S7 off). This binary code is supplied to the data input terminals D0 to D2 of the D latch 6 and the B input terminals B0 to B2 of the comparator 7, respectively.

At the same time, the D-latch 6 is cleared by a power-on reset pulse from a reset pulse generating circuit (not shown).
Latches the input code "000" to the output by the CK input, and the output is used as the A input of the magnitude comparator 7. Therefore, the input of the comparator 7 is “A =
B ”, the output is“ H ”, the output of the inverter 5e is“ L ”,
The output of the NAND gate IC8 becomes "H" and waits.

Next, for example, when the switch LS5 of the energy level selection switch 1 is turned on, the encoder 2 is turned on.
Becomes "101", the latch circuit 4 captures data at the rising edge of a clock pulse (data acquisition), which will be described later, latches at the falling edge of the clock pulse, and outputs "H" from Q1 '. Then, this latch output is input to the inverter drive circuit 35A, and the inverter drive circuit 35A generates a reference voltage corresponding to this input. The control output from the inverter drive circuit 35A is input to the inverter circuit 24,
Is activated by this, and converts the rectified output from the rectifier circuit 22 into high-voltage AC and outputs it. The high-voltage AC output is rectified by the high-voltage rectifier circuit 25 and applied to the energy storage capacitor 27. The energy storage capacitor 27 is charged with a voltage corresponding to the rectified output.

Then, under the control of the inverter drive circuit 35A, the charging operation is stopped when the battery is charged to a value corresponding to the reference voltage. Thus, by setting the energy by the energy selection switch 1, the energy storage capacitor 27 is charged to the corresponding voltage value.

At the same time, while the output “101” of the encoder 2 is turned on, the D latch 6
And the B input terminal input of the comparator 7 to these. At this time, since “000” is input from the encoder 2 as the A input terminal input of the comparator 7, “A <B”, so that the output of the A <B terminal which is the comparison result output terminal of the comparator 7 is “H”. Becomes

The "H" output from the terminal A <B is applied to the NAND gate 8 via the inverter 5e. However, since the output is inverted to "L" by the inverter 5e, the output of the NAND gate 8 is output. Becomes "H", so that the timer 9 of negative logic is not triggered by receiving the output "H" of the NAND gate 8, so that the timer 9
Since the output is "L", the energizing coil of the discharge relay 38 connected between the output terminal of the timer 9 and the system power supply VDD is energized by the application of the power supply VDD. , The contact of the discharge relay 38 is "open".

At the same time, while any one of the energy selection switches 1 is turned on, the GS terminal of the encoder 2 outputs a signal a of "H". The output of the GS terminal of the encoder 2 is given to a pulse generation circuit 5, and the pulse generation circuit 5 performs a differential-shaping-delay operation via inverters 5a to 5d forming the circuit. (See timing charts a, b, and c in FIG. 3). Among the obtained clock pulses, b is a pulse that does not receive a delay, and c is a pulse that receives a delay.

Of the clock pulses b and c, the delayed pulse c is input to the clock input terminal CK as the clock pulse of the D latch 6, so that the D latch 6 causes the encoder 2 to rise at the rising edge of the clock pulse. Acquisition (acquisition) of output data "101" from
Then, it is latched at the falling edge of the clock pulse and applied to the A input terminal of the comparator 7.

On the other hand, the output data “101” from the encoder 2 is input to the B input terminal of the comparator 7.
The input terminal inputs are both "101". Therefore, "A =
B ", the output d of the A <B output terminal of the comparator 7 remains at the logic level" H ", which is applied to the timer 9 via the inverter 5e. The output is inverted and becomes "L", which is input to the NAND gate 8, so that the output of the NAND gate 8 which takes NAND logic with the clock pulse b is logic "H" and operates with logic "L". Timer 9 is not triggered.

Thereafter, when the switch LS5 of the energy selection switch 1 is turned off, the encoder 2 outputs "000" and the input of the B input terminal of the comparator 7 becomes "00".
0 "and the input data of the A input terminal which receives the output of the D latch 6 is" 101 "since the latch data of the D latch 6 is" 101 ". A <B terminal output becomes “L”.
The A <B terminal output “L” is inverted by the inverter 5 e to become “H” and output to the NAND gate 8. At this time, the GS terminal output of the encoder 2 is set to the switch LS 5 of the energy selection switch 1. Since it is turned to “L” by being turned off, there is no clock pulse b (that is, level “L”).
The output of the NAND gate 8 receiving the two inputs goes "H", so that the timer 9 is not triggered at this point.

Therefore, the output of the timer 9 is still "L". Therefore, the energizing coil of the discharge relay 38 connected between the output terminal of the timer 9 and the system power supply VDD continues to be energized while the power supply VDD is still applied. The contacts remain open. Therefore, the energy storage capacitor 27 is supplied by the high voltage DC supplied through the main circuit including the rectifier circuit 22, the inverter circuit 24, and the high voltage rectifier circuit 25.
Are kept charged.

Next, it is assumed that the switch LS1 of the energy selection switch 1 is turned on. Then, the encoder 2 sets “0”
01 "is output, and the corresponding lower reference voltage is selected in the same manner as described above. However, since the energy storage capacitor 27 has been charged to the voltage at the previous set level by the previous charging, the voltage (energy level) Therefore, the feedback voltage of the voltage dividing resistor 28 in the configuration shown in Fig. 1 is higher than the reference voltage selected this time, and the operation of the inverter circuit 4 is suspended.

On the other hand, the output "001" of the encoder 2 becomes the input of the B input terminal of the comparator 7, and is compared with "101" which is the input of the A input terminal at the time of the previous operation. As a result, since “A> B”, the comparator 7 determines that A> B
The B terminal output is set to “L”. And this "L" A
> B terminal output is inverted by inverter 5e to become "H" and input to NAND gate 8.

At this time, since the switch LS1 of the energy selection switch 1 is on, the output a of the GS terminal of the encoder 2 becomes "H" and the output pulse b of the inverter 5b becomes "H". The output of the NAND gate 8 which takes NAND logic with the output e obtained by inverting the output d of the B terminal by the inverter 5e becomes "L".

The output of the NAND gate 8 is input to a timer 9 to trigger the timer 9. Accordingly, the timer 9 outputs a timing pulse g having a predetermined pulse width of the level “H” (the level of VDD) for a predetermined period and applies it to the energizing coil of the discharge relay 38.
, And the contact 38a of the discharge relay 38 becomes "closed". As a result, the discharge relay 38 is stopped, and the contact is closed. As a result, the discharge circuit formed by the discharge resistor 29 connected in parallel with the energy storage capacitor 27 is closed, whereby the energy storage capacitor 2 is closed.
The charge of 7 is discharged.

After the elapse of the predetermined period, the timer 9 sets the timing pulse g to "L", so that the energizing coil of the discharge relay 38 is energized again, and its contact becomes "open".
Charging of the energy storage capacitor 27 is started again. Here, the above-mentioned timing pulse g is for stopping the energization of the discharge relay 38 and securing the discharge circuit of the energy storage capacitor 27, and therefore, the time width during which most of the charge stored in the energy storage capacitor 27 is discharged. However, since recharging is performed, the residual charge of the energy storage capacitor 27 after discharging must be minimized in order to minimize waste of energy and to reach the target level in a short time. It is better to set the level close to the new set value with the changed amount. Therefore, the above-mentioned timing pulse g is set to a pulse width such that the residual charge amount after discharge becomes an optimum target value in consideration of these points.

In this manner, the discharge relay 38 is deactivated for a predetermined pulse width (the width of the timing pulse g of the timer 9), the contact (normally closed contact) is closed, and the charge of the energy storage capacitor 27 is released. After that, the discharge relay 38 is operated again to open the contact, and the energy storage capacitor 27 is charged again.

The inverter drive circuit 35 A controls the start and stop of the inverter circuit 24, and a high-voltage AC is generated from the started inverter circuit 24. After the conversion, the voltage is supplied to the energy storage capacitor 27, so that the terminal voltage of the energy storage capacitor 27 is charged toward a value corresponding to the selected reference voltage. Then, at the stage when the inverter driving circuit 35 is charged to a value corresponding to the reference voltage,
Under the control of A, the charging operation is stopped. Thus, the energy storage capacitor 27 is charged to a voltage value corresponding to the energy setting made by the energy selection switch 1.

When the energy selection switch 1 is turned on, the comparator 6 receives a single clock pulse c generated from the inverter 5d forming the pulse generation circuit 5.
Is set to "001" in the A input terminal of. Although not shown, the inverter driving circuit 35A is configured to inhibit the operation during the output period of the timing pulse g from the timer 9.

Further, in the energy selection switch 1,
For example, when the switch LS3 having a higher setting level than the current switch LS1 is selected, the output of the encoder 2 becomes “01”.
As a result, the comparator 7 compares "001" as the A input terminal input with "011" as the new B input terminal input, and as a result of the comparison, "A <B". H ", the timer 9 does not start as described above, and therefore, the inverter driving circuit 35A for generating a voltage corresponding to the selected reference voltage.
, The energy storage capacitor 27 is charged by increasing its terminal voltage to a value corresponding to the reference voltage, and then the inverter drive circuit 35A is stopped.

As described above, the energy storage capacitor 27 can be charged to a desired level. And
When charging is completed, laser irradiation becomes possible. When the laser irradiation switch 36 is turned on in this state, the control circuit 3
7 generates a gate trigger pulse for the switching element 31 and an ignition pulse for the flash lamp 32. Gate trigger
The switching element 31 is turned on by the pulse, whereby the energy charged in the energy storage capacitor 27 is applied to the flash lamp 32, and the flash lamp 32 is triggered by the ignition pulse.
Discharges. Then, the light due to this discharge is incident on the solid-state laser resonance rod 33, and is optically resonated in the rod to excite the laser light.

Since the charge of the energy storage capacitor 27 is lost by exciting the laser beam, the energy storage capacitor 27 is charged to the voltage of the set value again by the above operation.

However, after the oscillation of the laser beam ends and the charge stored in the energy storage capacitor 27 is lost, the charging of the energy storage capacitor 27 is still performed up to the value set by the energy level selection switch when the recharging operation is started. If the value set by the energy level selection switch is changed to a lower level at a stage where the energy is not reached, and the above-described operation is performed, the amount of recharge after forcible discharge increases, resulting in waste of energy. And there is a concern that the charging time is wasted. Since the control circuit 37 monitors the voltage of the energy storage capacitor 27 by the voltage dividing resistor 28, if the set value after the change is lower than the voltage of the energy storage capacitor 27, the setting is changed from the upper level to the lower level. However, since the timer 9 can be easily controlled so as not to perform the discharging operation, the charging time is longer than the time required for the setting value changing operation by the energy level selection switch. It is even more convenient to take such measures.

As described above, the selection circuit for selectively setting the desired energy level controls the charging circuit to the set level, charges the energy storage capacitor to a desired voltage value, and supplies the voltage to the laser oscillation source. In an apparatus provided for oscillation, a discharge circuit is provided in an energy storage capacitor, and the discharge circuit is set when the charge voltage (energy level) of the energy storage capacitor is higher than the level set by the selection setting means. An energy level selection circuit is provided for operating for a predetermined time during operation, forcibly discharging and then shifting to charge control, so that the voltage (energy level) of the energy storage capacitor is high when the laser oscillation energy setting level is changed. In this case, discharge is performed by forcibly operating the discharge circuit to charge the energy storage capacitor. Control is performed so that charging is performed after the voltage level has been lowered. This allows a time-consuming drop in the charging voltage level (energy release) of the energy storage capacitor to be completed in a short time, and thus can be completed quickly. The energy storage capacitor can be charged to a desired level. Therefore, laser oscillation can be performed in a short time after the level setting operation, and a laser device with good usability can be obtained.

The present invention is not limited to the above-described embodiment, but can be implemented with appropriate modifications without departing from the scope of the invention. Further, in the above-described embodiment, when the energy storage capacitor 27 is forcibly discharged by the timing pulse g, there may be a case where most of the charge stored in the energy storage capacitor 27 is discharged. In such a case, a loss in recharging is large. To improve this, the reference voltage set to the lowest energy level is compared with the feedback voltage from the voltage dividing resistor 28 using an analog comparator IC. When the latter is larger than the former, the logic level is "H".
, And the timing pulse g output from the timer 9 is ANDed by an AND gate, and the output is used to control the discharge relay 38. At this time, the width of the timing pulse g is large and fixed. By doing so, the charge stored in the energy storage capacitor 27 is discharged only while the feedback voltage is higher than the reference voltage, and the time loss in recharging the capacitor 27 is eliminated.

[0083]

As described above in detail, according to the present invention, when the setting is changed to the low energy level in the setting state of the high energy level, the charging potential can be changed to that energy level without delay. After the level setting operation, it is possible to perform laser oscillation in a short time, so that an easy-to-use laser device can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention, and is a block diagram of a pulse laser device.

FIG. 2 is a diagram for explaining an embodiment of the present invention,
FIG. 2 is a detailed diagram of an energy level selection circuit in FIG. 1.

FIG. 3 is a diagram for explaining an embodiment of the present invention,
3 is a timing chart during operation of the circuit in FIG. 2.

FIG. 4 is a diagram for explaining a conventional example, and is a block diagram of a general pulse laser device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Energy level selection switch 2 ... Encoder 3 ... Decoder 4 ... Latch circuit 5 ... Pulse generation circuit 6 ... D latch 7 ... Comparator 8 ... Nand gate 9 ... Timer 21 ... Commercial AC power supply 22 ... Rectifier circuit 23 ... Auxiliary DC power supply 24 ... DC / AC inverter circuit 25 ... High voltage rectifier circuit 26 ... Charging current suppressing resistor 27 ... Energy storage capacitor 28 ... Voltage dividing resistor 29 ... Discharge resistor 30 ... Inductance 31 ... Switching element 32 ... Flash lamp 33 ... Solid state laser Resonant rods 34, 34A Energy level selection circuit 35, 35A Inverter drive circuit 36 Laser irradiation switch 37 Control circuit 38 Discharge relay 38a Discharge relay contact

Claims (2)

(57) [Claims] 1. A charge setting circuit for selecting and setting a desired energy level controls a charging circuit to a set level, charges an energy storage capacitor to a desired voltage value, and supplies the charged voltage to a laser oscillation source. In the laser device to be provided, a discharge circuit is provided in the energy storage capacitor, and when the setting level set by the selection setting means is changed to a level lower than the current setting level, the discharging circuit is operated for a predetermined time to force the discharge circuit to operate. A laser device comprising: an energy level selection control unit having a first function of discharging and a second function of controlling to shift to charge control after completion of forced discharge. 2. The apparatus according to claim 1, further comprising: detecting means for detecting an energy level of the energy storage capacitor; and selecting and setting means for selecting and setting a desired energy level. The charging circuit is controlled to the level set by the selecting and setting means. In addition, while monitoring the detection output by the detection means, the energy storage capacitor is charged to a desired voltage value, and the charged energy is supplied to a laser oscillation source for laser oscillation. And detecting the difference between the energy level of the energy storage capacitor and the level set by the selection setting means using the detection output of the detection means, and setting the charging voltage of the energy storage capacitor to the level set by the selection setting means. When the voltage is higher, the discharge circuit is operated for a predetermined time to perform a forced discharge. After capacity and forced discharge end, a laser device, characterized in that constructed by providing an energy level selection control means and a function of controlling so as to shift the charging control.