JP2576899B2 - Information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus that retains the same processing when a predetermined interrupt processing occurs.

2. Description of the Related Art Conventionally, there has been known a technique for maintaining compatibility between an existing microprocessor and an object code and maintaining compatibility between different microprocessors as much as possible. In addition, recently, as an information processing apparatus using such a microprocessor, attempts have been made to clarify the roles of an operating system and an application program and to eliminate incompatibilities of hardware including a processor. That is, the access part of the hardware that is difficult to ensure compatibility is entrusted to the operating system in a lump, the start address of the processing is stored in the memory, and the address of this memory is made the same, so that it can be seen from the application program. They try to ensure the identity of their systems. Regarding the processing when an interrupt occurs, it is attempted to maintain the compatibility of the processing for the interrupt request by preparing a memory in which the start address of the interrupt processing is similarly written.

[Problems to be Solved by the Invention] However, when one of the microprocessors having object code compatibility is used, when an application program written for the other microprocessor is executed, a method of generating a return address of interrupt processing is performed. There was a problem that the same software caused different operations due to the differences.

An object of the present invention is to solve the conventional problem by eliminating the incompatibility around a microprocessor or the like and causing the same operation when a specific interrupt occurs.

[Means for Solving the Problems] In order to solve the above problems, an information processing apparatus of the present invention is an information processing apparatus that processes information while performing interrupt processing, and comprises: Storage means for storing a process for resolving incompatibility of the second microprocessor with the myroprocessor; and an access destination accessed by the predetermined interrupt process upon activation in response to use of the second microprocessor. Switching means for previously switching from a first predetermined area accessed by the first microprocessor to a second predetermined area for storing a storage position in the storage means of the processing for eliminating the incompatibility. Detecting means for detecting the occurrence of the predetermined interrupt processing; and detecting the occurrence of the predetermined interrupt processing by the detecting means. Accessing said second predetermined area switched by means, said Incompatibility resolution processing executing means for executing a process to eliminate the incompatibility, the after execution of processing by the incompatibility resolution processing execution means,
Interrupt processing executing means for executing the predetermined interrupt processing.

[Operation] In the information processing apparatus configured as described above, when the second microprocessor is used, at the time of startup, the access destination accessed by the predetermined interrupt processing is switched from the first predetermined area by the switching means. When the predetermined interruption processing is detected by the detection means, the processing is canceled by accessing the second predetermined area, and the incompatibility in the storage means is executed. After that, the predetermined interruption process is executed.
Therefore, when the second microprocessor is used, it is possible to maintain compatibility when executing a predetermined interrupt process.

In the present invention, the following configuration may be added.

An existing microprocessor controls a read / write operation for a memory in which an interrupt vector having a different return address generation method for interrupt processing is written, and
As shown in the figure, at the time of writing, the data is written to the memory (data flows 3, 6). At the time of reading, the memory is switched and the other memory is read (data flows 4, 5).
Or a circuit having a function to switch to a memory and write to another memory as shown in FIG. 2 at the time of writing, and a circuit having a function to read the memory at the time of reading, and to control the circuit and modify the return address. Function to perform

[Example] An example of the present invention will be described below. The information processing apparatus according to the embodiment includes a well-known CPU, ROM, RAM, an input / output device (not shown), and has a function of receiving an interrupt request and executing a predetermined process. FIG. 3 is an embodiment of a memory control circuit as an embodiment for realizing the present invention. In FIG. 3, reference numeral 1 denotes a special interrupt vector address code circuit, which outputs 0 to the signal 35 when the address of the special interrupt vector is selected, and outputs 1 when any other address is selected. Output. Reference numeral 2 denotes a memory select circuit, which determines a BANK signal 30 according to a select signal (not shown) from software. The special interrupt vector is an interrupt vector of an existing microprocessor and an interrupt that differs in a method of generating a return address from interrupt processing.

FIG. 4 shows a memory map. In this figure, the memory 20
Is a special interrupt vector, and the memory 21 is a memory allocated to the same address as the special interrupt vector of the memory 20 and on another bank. Also, MRN (active high)
Is a memory read signal from the CPU, and MWN (active High) is a memory write signal from the CPU, MR0
＼ (Symbol “＼” indicates that the signal is active low; negative logic is indicated by drawing a line above the signal name in the figure. The same applies hereinafter) indicates memory read from the main memory 25. Signal, MR1＼ (active low) is a memory read signal to the memory 21, MW0＼ (active low) is a memory write signal to the memory 25, MW1
＼ (Active low) is a memory write signal to the memory 21.

In this circuit, when the BANK signal 30 is 0 (Low), the signal 31 becomes 1 (High), and the signal 36 becomes equal to the signal 35. When the signal 35 is 0, the gate 42 and the gate 43 are opened, and when the signal 35 is 1, the gate 41 and the gate 43 are opened. When the BANK signal 30 is 1, the signal 36 becomes 1 and the signal 31 becomes equal to the signal 35. In this case, the signal 35 becomes 0
At this time, the gate 41 and the gate 44 are opened, and when the signal 35 is 1, the gate 41 and the gate 43 are opened. Thus, when the special interrupt vector is selected, if the BANK signal 30 is 0,
The memory 21 can be read and written to the memory 20, and if the BANK signal 30 is 1, the memory 20 can be read and written to the memory 21. When the special interrupt vector is not selected, reading and writing is performed in the main memory.
Performed on 25.

An existing processor is referred to as a processor 0, and a processor which is compatible with the processor 0 in object code and generates a return address from interrupt processing differently is referred to as a processor 1.

As shown in FIG. 5, in the processor 0, when a special interrupt is generated in the instruction 51, the address of the next instruction 52 is set as the return address from the processing, and in the processor 1, the address is generated in the instruction 51. Instruction 51 as return address from processing by special interrupt
Its own address is set. In this case, the processor that operates normally in the processor 0 loops at the instruction 51 in the processor 1, and the operation is completely different from that of the processor 0. Therefore, the interrupt vector of the interrupt generated in the instruction 51 is replaced with the vector 53.
In the return address processing routine, the return address from the interrupt processing is corrected to the instruction 52 in the return address processing routine, and the processing is shifted to the original interrupt processing routine (arrow 54). Since the return address is the instruction 52, the processors 0 and 1 have apparently performed the same operation. Therefore, in a system using the circuit shown in FIG.
Is temporarily set to 1, the start address of the return address correction routine is written to the memory 21, and then the BANK signal 35 is set to 0, and then the application program is executed (step 100 in FIG. 6). By doing so, when the special interrupt vector is read from the application program thereafter, the head address of the return address correction routine is read from the memory 21 at the time of reading, and data is written to the memory 20 at the time of writing.

Then, an application program or the like is executed (step 101). If a special interrupt occurs during execution, the special interrupt vector is referred to. At this time, what is read is the memory 21 (step 102), which points to the start address of the return address correction routine. Is transferred to the return address correction routine instead of the processing routine (step 10).
3).

In the return address correction routine, the return address is rewritten so that the return address becomes equal to the operation in the processor 0. Continue, BANK signal
With 35 set to 1, the memory 20 is read (step 104).
As a result, the start address of the original interrupt processing prepared by the application program can be obtained.
Then, the BANK signal is set to 0 (step 104), and control is transferred to the original interrupt processing routine (steps 105 and 106).
Thus, the same operation can be apparently performed. That is, the incompatibility due to the difference in the method of generating the return address from the interrupt processing is eliminated.

Next, Intel microprocessor 80286 CPU
The case of the 8086 CPU will be described as a specific example. 80286 CPU is 8
086CPU and object code compatible, but 0
(Zero) A microprocessor with a different method of generating a return address for division interrupt processing. Therefore, when a divide-by-zero interrupt occurs, incompatibility occurs due to different interrupt processing and different return addresses.

In order to eliminate this incompatibility, a circuit as shown in FIG. 7 is used. This circuit outputs 0 to the signal 35 when the address buses AB2 to AB23 are all 0, and outputs the signal otherwise.
Output 1 to 35. Since the divide-by-zero interrupt vector is stored in the memory addresses 0H to 3H, 0 is output to the signal 35 when the divide-by-zero interrupt vector is selected, and the signal 35 is output when any other address is selected. 1 is output.

In the memory select circuit, address buses AB0 to A
When B3 is all 1 and addresses AB4 to AB7 are all 0,
DB0 when the IOW signal changes from 0 to 1 is output as the BANK signal 30. That is, when 0 is output to the I / O port OFH, BA
When 0 is output to the NK signal 30 and 1 is output to the I / O port OFH, 1 is output to the BANK signal 30.

FIG. 8 shows a memory map at this time. In this figure,
The memory 61 is a main memory of the 80286 CPU, the memory 62 is a memory on the main memory 61 in which a divide-by-zero interrupt vector is written, and the memory 63 is a bank memory corresponding to the memory 61 and having no problem in operation. In FIG. 7, MR0＼
Is a memory read signal for the main memory 61, MR1
＼ Is a memory read signal for bank memory 63, MW0
＼ Is a memory write signal for the main memory 61, MW
1＼ is a memory write signal for the bank memory 63. Both are active low signals.

As described above, in the circuit of FIG. 7, when the divide-by-zero interrupt vector is selected and the BANK signal 30 is 0, the contents of the bank memory 63 are read with respect to the memory read, and the memory write is performed. Is written into the divide-by-zero interrupt vector 62 of the main memory 61. In addition, BANK signal 30
Is 1 when the main memory 61
The contents of the divide-by-zero interrupt vector 62 are read out, and the memory write is written to the bank memory 63. Assuming that BX = 0 in the instruction DIV DX, BX, 8028
The 6CPU and 8086CPU both generate a divide-by-zero interrupt. The return address from the processing routine indicates the instruction that caused the interrupt in the 80286CPU, but in the 8086CPU,
It points to the instruction following the instruction that caused the interrupt. Therefore, when a program written to return to the return address itself for the 8086 CPU is executed on the 80286 CPU, BX
When division is performed with = 0, the 80286 CPU again generates a division-by-zero interrupt, and the program stops. However, in the 8086 CPU, an incompatibility occurs in that processing is shifted to the instruction next to the instruction that caused the interrupt, so that subsequent processing is continued.

When a divide-by-zero interrupt occurs on the 80286 CPU, 0 is used as an interrupt processing vector, just as when other interrupts occur.
The division interrupt vector is read, and control is transferred to the address indicated by the vector. Therefore, at the time of system boot, I / O
If 0 is output to the port OFH, the divide-by-zero interrupt vector read by the 80286 CPU can be set to the value of the bank memory 63.

Next, an actual example of the return address correction routine will be described. A list of this routine is shown in Table 1. In the following description, the three-digit numbers shown in parentheses correspond to the numbers given to the processes in Table 1.

In this return address correction routine, when an interrupt is received, first, 4 bytes of a stack area are secured for branching to the division by 0 interrupt processing routine of the application program (201). Then, each register is saved ( 202).

Since the instruction causing the error and the start address are the return addresses of the interrupt processing, the segment of the address is stored in the DS register, and the address offset is stored in the SIL register (203).

Then, a subroutine for skipping the prefix part of the instruction code is called (204). Since the prefix part is 001xx110b in the binary code, this part is skipped (205).

Next, it is checked whether the instruction that caused the interrupt is a division instruction. In this case, the divide-by-zero instruction is a binary code
Since it is 00xxx110b, it is checked whether the instruction which caused the interrupt is as follows (206). If the instruction is not a divide-by-zero instruction, for example, if it is an INT0 instruction, control is passed to the interrupt processing routine of the application without modifying the return address (207). If the instruction is a division instruction, call the subroutine to determine the instruction length (20
2). In this subroutine, first, looking at the second byte of the instruction, if the code is a binary code and is 00 ××× 110b, it is a memory operand instruction.
If the 7th and 6th bits are 11 or 00, it is a 2-byte instruction, if the 7th and 6th bits are 01, it is a 3-byte instruction, and if the 7th and 6th bits are 10, it is a 4-byte instruction. ,
The start address of the instruction following the instruction that caused the interrupt is known (208). This is written in the area where the return address is written (209), the return address is corrected, and the routine returns from the subroutine call (221).

Then, a subroutine for setting a return address is called (230). In this subroutine, after setting the main memory access mode (231, 232), an area in which the start address of the application division by zero interrupt processing routine written in the division by zero interrupt vector 62 of the main memory 61 is reserved in the stack area for branching (233). Thereafter, the mode is switched to the bank memory access mode (210, 241), and the register is returned (211).
After the above processing, when a return instruction is executed, the processing can be shifted to a division by 0 interrupt processing routine of the application. Then, the return address from the routine is changed from the instruction that caused the divide-by-zero interrupt to the next instruction, so that the 80286 CPU can perform the same operation as the 8086 CPU.

In the example described so far, an example in which a bank memory is used as another memory is shown. However, any other memory such as a memory on a main memory having no operational problem such as EMS may be used as another memory. .

In addition, the interrupt which is in 80286CPU but not in 8086CPU,
For example, for a segment overrun error interrupt, this interrupt can be written in a memory access instruction, such as MOV AX: [BX], where BX = OFFF
This is an interrupt generated by the 80286 CPU when trying to access memory beyond the segment, such as FH. This interrupt does not occur in the 8086 CPU. Therefore, in this case, the same processing as that of the 8086 CPU is performed in the return address correction routine using the present invention, and the return address is returned after the instruction that caused the interrupt. The operation can be performed, and the incompatibility due to the interrupt can be eliminated by using the present invention.

In addition, when the operating system prepares a new BIOS program with the same role as the old BIOS and enhanced functions, the newly added BIOS function call is replaced with the same function as the old BIOS from the viewpoint of compatibility. There are cases where you want to assign to a call (start address). However, if replaced as it is, some old application programs may not be able to cope with the new BIOS function, and may cause erroneous processing. In this case, the new BIOS is replaced with the old BIOS function call.
If it is assumed that it is determined whether or not the application is compatible with the new BIOS, similar to the above embodiment, when the application program calls the BIOS, while apparently performing the same processing, By making the actual processing different, the occurrence of a malfunction can be avoided. In other words, when trying to perform processing using the jump table prepared by the application program, the processing is actually started by referring to the jump table prepared by the operating system, and it is determined that the new BIOS function is not supported. Sometimes the old BIOS (new BIOS
(Assigned to an address different from the address). As a result, new functions can be used beyond the incompatibility of the BIOS without changing the application program.

[Effects of the Invention] According to the present invention, compatibility between processors having different interrupt processes is realized. For this reason, the software for the processor A, which has not been operated conventionally due to the difference in the interrupt processing, now operates also in the processor B, and the usability for the user is greatly improved.

[Brief description of the drawings]

1 and 2 are conceptual diagrams of the operation of a memory read / write control circuit. FIG. 3 is a circuit diagram showing an example of a circuit for implementing the present invention. FIG. 4 is a diagram showing a memory map at that time. FIG. 5 is an operation diagram of an interrupt operation. FIG. 6 is a flowchart of the above embodiment. FIG. 7 is a specific circuit diagram for implementing the present invention. FIG. 8 is a diagram showing a memory map at that time. FIG. 9 is a diagram showing a timing chart of the circuit of FIG. 7; 20: Memory, 21: Memory 25: Main memory, 30: BANK signal 35: BANK signal, 61: Main memory 62: Memory, 63: Bank memory

Claims (1)

(57) [Claims] 1. An information processing apparatus for processing information while performing an interrupt process, wherein said storage device stores a process for eliminating incompatibility of a second microprocessor with a first microprocessor in a predetermined interrupt process. In response to the use of the second microprocessor, at the time of activation, an access destination accessed by the predetermined interrupt processing is changed from a first predetermined area accessed by the first microprocessor to the non- Switching means for previously switching to a second predetermined area for storing a storage position in the storage means of the processing for canceling compatibility; detection means for detecting occurrence of the predetermined interrupt processing; When the occurrence of the interrupt processing is detected, the second predetermined area switched by the switching means is accessed and the incompatible An information processing apparatus comprising: an incompatibility eliminating process executing unit that executes a process for eliminating interoperability; and an interrupt process executing unit that executes the predetermined interrupt process after execution of the process by the incompatibility eliminating process executing unit. .