JP2026008688A - Image Sensor - Google Patents

Abstract

An image sensor having an improved structure for improved efficiency and productivity is provided.
[Solution] An image sensor according to the present invention includes a substrate having opposing first and second surfaces, a plurality of pixel regions including a photoelectric conversion unit located in the substrate and a pixel circuit located adjacent to the first surface of the substrate. The pixel circuit includes a plurality of buried patterns having a buried structure buried within the substrate. The pixel circuit includes a first transistor including a first gate electrode of a vertical transfer gate electrode, and a second transistor including a second gate electrode having a cross-sectional shape different from that of the first gate electrode. The plurality of buried patterns include the first gate electrode and the second gate electrode.
[Selected Figure] Figure 1

Description

The present invention relates to an image sensor, and more particularly to an image sensor with an improved structure.

An image sensor is a semiconductor device that converts optical images into electrical signals. Image sensors can be classified into charge coupled device (CCD) image sensors based on silicon semiconductors and complementary metal oxide semiconductor (CMOS) image sensors (CIS).

Among these, CMOS image sensors have a simple driving method and can integrate signal processing circuits on a single chip, allowing for miniaturization. Their low power consumption also makes them suitable for use in products with limited battery capacity. With the development of the electronics industry, various research efforts are ongoing to improve the performance of CMOS image sensors.

The present invention was made in consideration of the above-mentioned conventional technology, and its object is to provide an image sensor that can improve efficiency and productivity.

An image sensor according to one aspect of the present invention, which has been made to achieve the above object, includes a substrate having a first surface and a second surface opposite to each other, and a plurality of pixel regions including a photoelectric conversion unit located on the substrate and a pixel circuit located adjacent to the first surface of the substrate. The pixel circuit includes a plurality of buried patterns having a buried structure buried within the substrate. The pixel circuit includes a first transistor including a first gate electrode of a vertical transfer gate electrode, and a second transistor including a second gate electrode having a cross-sectional shape different from the first gate electrode. The plurality of buried patterns include the first gate electrode and the second gate electrode.

An image sensor according to another aspect of the present invention, which has been made to achieve the above object, includes a substrate having a first surface and a second surface opposite to each other, and a plurality of pixel regions including a photoelectric conversion unit located on the substrate and a pixel circuit located adjacent to the first surface of the substrate. The pixel circuit includes a plurality of buried patterns having a buried structure buried within the substrate. The pixel circuit includes a first transistor including a first gate electrode, a second transistor including a second gate electrode having a cross-sectional shape different from that of the first gate electrode, and a connection pattern including at least one of a doping connection pattern and a wiring pattern. The plurality of buried patterns include the second gate electrode and the connection pattern.

An image sensor according to yet another aspect of the present invention, which has been made to achieve the above object, includes a substrate having first and second surfaces opposite to each other, a plurality of pixel regions including a photoelectric conversion unit located on the substrate and a pixel circuit located adjacent to the first surface of the substrate, and an isolation portion located corresponding to edges of the plurality of pixel regions. The pixel circuit includes a doped connection pattern connected to the substrate or a doped region located thereon and having an embedded structure embedded within the substrate. The doped connection pattern is formed across at least two pixel regions of the plurality of pixel regions, and at least a portion of the doped connection pattern is located on the isolation portion.

According to the present invention, first transistors, second transistors, and/or connecting patterns having different structures are provided together on a substrate, thereby reducing the number of processes and reducing manufacturing costs. In this regard, the first transistors, second transistors, and/or connecting patterns have an embedded structure, allowing pixel circuits to be formed through simple processes, and the depth of first contact vias can be reduced, thereby reducing electrical resistance. Furthermore, the connecting patterns are formed to be shared by multiple pixel regions, thereby reducing the number of first contact vias and the area of the first wiring layer, and increasing the spacing between the first contact vias, thereby reducing parasitic capacitance. The reduced parasitic capacitance can improve conversion gain.
This can improve the efficiency and productivity of the image sensor.

FIG. 1 is a block diagram illustrating an example of an image sensor. 1 is a partial cross-sectional view showing a portion of an image sensor according to an embodiment; FIG. 3 is a plan view schematically showing a substrate of the image sensor shown in FIG. 2 . FIG. 3 is an enlarged view of a portion D in FIG. 2. FIG. 3 is an enlarged view of a portion E in FIG. 2. 3 is a plan view schematically showing a part of a photoelectric conversion substrate of the image sensor shown in FIG. 2. FIG. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment. 10A to 10C are cross-sectional views illustrating a method for manufacturing an image sensor according to another embodiment. 10A to 10C are cross-sectional views illustrating a method for manufacturing an image sensor according to another embodiment. 10A to 10C are cross-sectional views illustrating a method for manufacturing an image sensor according to another embodiment. 10A to 10C are cross-sectional views illustrating a method for manufacturing an image sensor according to another embodiment. 10A to 10C are cross-sectional views illustrating a method for manufacturing an image sensor according to another embodiment. 10A to 10C are cross-sectional views illustrating a method for manufacturing an image sensor according to another embodiment. FIG. 10 is a plan view schematically illustrating a substrate of an image sensor according to another embodiment;

Various embodiments will now be described in detail with reference to the drawings so that those skilled in the art can easily implement them. The embodiments may be embodied in various forms and are not limited to the embodiments described herein.

In order to clearly describe the present invention, parts that are irrelevant to the description will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components.

Furthermore, the size and thickness of each component shown in the drawings are shown arbitrarily for the convenience of explanation, and the present invention is not limited to the drawings. For the convenience of explanation and/or for simple illustration, the thickness of some layers and regions has been enlarged or exaggerated.

Furthermore, when a layer, film, region, plate, or other part is said to be "on" another part, this does not only mean that it is "directly on top" of that other part, but also includes cases where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" in the opposite direction of gravity.

Also, throughout the specification, when a part is said to "comprise" a certain element, this does not mean that it excludes other elements, but that it may further include other elements, unless specifically stated to the contrary.

In addition, throughout the specification, "on a plane" or "when viewed from a plane" means when the target part is viewed from above, and "on a cross section" or "when viewed from a cross section" means when the target part is cut vertically and viewed from the side.

Hereinafter, an image sensor and a manufacturing method thereof according to one embodiment will be described in detail with reference to Figures 1 to 24.

Figure 1 is a block diagram showing a schematic diagram of one embodiment of an image sensor 10.

Referring to FIG. 1, an image sensor 10 according to one embodiment includes a pixel array 10a and a logic circuit 20 that controls the pixel array 10a. The logic circuit 20 includes circuits for controlling the pixel array 10a, such as a controller 22, a timing generator 24, a row driver 26a, a readout circuit 26b, a ramp signal generator 26c, and a data buffer 28. The image sensor 10 further includes an image signal processor 30. According to one embodiment, the image signal processor 30 is located outside the image sensor 10.

The image sensor 10 converts light received from the outside into an electrical signal to generate an image signal, and the image signal generated by the image sensor 10 is provided to the image signal processor 30.

The image sensor 10 is mounted in an electronic device having an image or light sensing function. For example, the image sensor 10 is mounted in electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, home appliances, tablets, personal digital assistants (PDAs), portable multimedia players (PMPs), navigation systems, drones, or advanced driver assistance systems (ADASs). The image sensor 10 is also mounted in electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, or various measuring instruments.

The pixel array 10a includes a plurality of pixel regions PX, and a plurality of row lines RL and a plurality of column lines CL respectively connected to the plurality of pixel regions PX.

In one embodiment, each pixel region PX includes at least one photoelectric conversion element. The photoelectric conversion element senses incident light and converts the incident light into an electrical signal corresponding to the amount of light, i.e., multiple analog pixel signals. The photoelectric conversion element is a photodiode or a pin diode. Alternatively, the photoelectric conversion element is a single-photon avalanche diode (SPAD) applied to a 3D sensor pixel. The level of the analog pixel signal output from the photoelectric conversion element is proportional to the amount of light provided to each pixel region PX or the amount of charge output from the photoelectric conversion element.

A plurality of row lines RL extend in one direction and are connected to a plurality of pixel regions PX arranged along that direction. For example, a control signal output from the row driver 26a to a row line RL is transmitted to the gates of transistors in a plurality of pixel regions PX connected to the row line RL. A column line CL extends in a direction intersecting the one direction and is connected to a plurality of pixel regions PX arranged along that direction. A plurality of pixel signals output from a plurality of pixel regions PX are transmitted to a readout circuit 26b via a plurality of column lines CL.

In one embodiment, a plurality of pixel regions PX are arranged in a plurality of columns and a plurality of rows to form one unit pixel group. That is, a plurality of pixels arranged in the extension direction of the row line RL and a plurality of pixels arranged in the extension direction of the column line CL form one unit pixel group. For example, one unit pixel group includes a plurality of pixels arranged in the form of two columns and two rows, and one unit pixel group outputs one analog pixel signal. However, the embodiment is not limited to this, and various modifications are possible.

In some embodiments, each pixel region PX includes a pixel circuit that processes the charges generated by the photoelectric conversion element and outputs an electrical signal. The pixel circuit includes a transfer transistor, a reset transistor, a selection transistor, a source follower transistor, and the like. In other embodiments, the pixel circuit may have various structures.

The controller 22 generally controls the timing generator 24, row driver 26a, readout circuit 26b, ramp signal generator 26c, data buffer 28, etc. included in the image sensor 10. For example, the controller 22 controls operation timing using control signals. In one embodiment, the controller 22 receives a mode signal indicating the imaging mode from the application processor, and generally controls the image sensor 10 based on the received mode signal.

The timing generator 24 generates a signal that serves as a reference for the operation timing of the image sensor 10. The timing generator 24 provides control signals that control the timing of the row driver 26a, readout circuit 26b, and ramp signal generator 26c.

The row driver 26a generates control signals for driving the pixel array 10a in response to control signals from the timing generator 24, and provides control signals to multiple pixel regions PX of the pixel array 10a via multiple row lines RL. For example, the row driver 26a generates transfer signals for controlling transfer transistors, reset control signals for controlling reset transistors, and selection control signals for controlling selection transistors, and provides these signals to the pixel array 10a.

The readout circuit 26b converts the pixel signal (or electrical signal) output via the corresponding column line CL into a pixel value indicating the amount of light. The ramp signal generator 26c generates a reference signal or ramp signal and transfers it to the readout circuit 26b. For example, the readout circuit 26b compares the ramp signal with the pixel signal and converts the pixel signal into a pixel value. The pixel value is image data having multiple bits.

The data buffer 28 stores pixel values of the pixel area PX transmitted from the readout circuit 26b and outputs the stored pixel values in response to a signal from the controller 22.

The image signal processor 30 performs image signal processing on the image signal received from the data buffer 28. For example, the image signal processor 30 receives multiple image signals from the data buffer 28 and combines the received image signals to generate a single image.

The image sensor 10 described above is presented only as an example, and the structure and method of the image sensor 10 can be modified in various ways.

Figure 2 is a partial cross-sectional view showing a portion of an image sensor 10 according to one embodiment. Figure 3 is a plan view schematically showing the substrate 110 of the image sensor 10 shown in Figure 2. Figure 2 is a cross-sectional view taken along lines A-A', B-B', and C-C' in Figure 3. Figure 3 is a rear plan view showing the first surface 111 of the substrate 110 adjacent to the wiring portion 170 as a reference. For clear understanding and simplified illustration, the surface insulating layer 110b is omitted from Figure 3.

2 and 3, in one embodiment, the image sensor 10 includes a substrate 110 and a plurality of pixel regions PX. At least one of the plurality of pixel regions PX includes a photoelectric conversion unit 120 located in the substrate 110 and a pixel circuit 130 adjacent to the first surface 111 of the substrate 110. The image sensor 10 or the substrate 110 includes isolation portions 126 located corresponding to edges of the plurality of pixel regions PX. The pixel circuits 130 are located in the plurality of pixel regions PX adjacent to the first surface 111 of the substrate 110. The pixel circuits 130 include a plurality of buried patterns 132 having a buried structure buried within the substrate 110.

In this embodiment, the substrate 110 includes a semiconductor substrate 110a containing a semiconductor material. For example, the semiconductor substrate 110a may be a bulk substrate containing a semiconductor material, a substrate with an epitaxial layer formed on a bulk substrate, or a semiconductor-on-insulator. In this case, the semiconductor material provided in the semiconductor substrate 110a contains a first conductivity type dopant and has a first conductivity type (e.g., p-type or n-type).

The semiconductor material included in the semiconductor substrate 110a includes at least one of a Group IV semiconductor, a Group III-V compound semiconductor, and a Group II-VI compound semiconductor. For example, the semiconductor material included in the semiconductor substrate 110a includes at least one of Si, Ge, SiGe, SiC, GaAs, InAs, GaP, InP, InSb, InGaAs, ZnTe, and CdS. For example, the bulk substrate is a single-crystal or polycrystalline semiconductor substrate and includes Si, Ge, or SiGe. For example, the semiconductor-on-insulator is a silicon-on-insulator (SOI), a germanium-on-insulator (SGOI), or a silicon-germanium-on-insulator (SGOI).

Doped region 120d is located on the first surface 111 side of substrate 110 (e.g., in a portion of semiconductor substrate 110a adjacent to first surface 111).

In the embodiment, the doping region 120d includes at least one of a floating diffusion region 120f and a ground region 120g. The floating diffusion region 120f is a region having a second conductivity type opposite to that of the semiconductor substrate 110a, and is a region where charges generated by the photoelectric conversion unit 120 accumulate. The floating diffusion region 120f is formed in a portion of the first active region 114a. The ground region 120g is disposed in the third active region 114c, which is separated from the floating diffusion region 120f and the plurality of transistors 140. The ground region 120g has the same first conductivity type as that of the semiconductor substrate 110a and a higher doping concentration than the substrate 110 or the second conductivity type well 120a. A ground voltage is applied to the ground region 120g. The positions of the floating diffusion region 120f and the ground region 120g will be described in more detail later.

In the drawings, the doping region 120d is illustrated as including a floating diffusion region 120f and a ground region 120g. However, embodiments are not limited to this, and depending on the embodiment, the floating diffusion region 120f and/or the ground region 120g may not be included. Alternatively, the doping region 120d may further include doping regions other than the floating diffusion region 120f and/or the ground region 120g.

In one embodiment, the semiconductor device further includes a surface insulating layer 110b located on the first surface of the semiconductor substrate 110a adjacent to the first surface 111 of the substrate 110. For example, the surface insulating layer 110b is located while covering the surface of the semiconductor substrate 110a adjacent to the first surface 111 of the substrate 110, the surface of the isolation portion 124, and/or the surface of the isolation portion 126. The surface insulating layer 110b corresponds to an etch stop (end point detection, EPD) layer. However, the embodiment is not limited thereto. As another example, the substrate 110 may be composed of the semiconductor substrate 110a and may not include the surface insulating layer 110b.

In the embodiment, the plurality of pixel regions PX include a first pixel region PX1 and a second pixel region PX2 adjacent to each other in a first direction (the X-axis direction in the drawing), and further include a third pixel region PX3 and a fourth pixel region PX4 adjacent to the first pixel region PX1 and the second pixel region PX2, respectively, in a second direction (the Y-axis direction in the drawing) intersecting the first direction (the X-axis direction in the drawing). For example, the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4 shown in FIG. 3 constitute one unit pixel group, but the embodiment is not limited thereto.

A photoelectric conversion unit 120 for converting externally incident light into an electrical signal is located on the substrate 110.

For example, the photoelectric conversion unit 120 includes a first conductivity type well 120b containing a first conductivity type dopant and having a first conductivity type (e.g., p-type or n-type), and a second conductivity type well 120a containing a second conductivity type dopant and having a second conductivity type (e.g., n-type or p-type) opposite to that of the semiconductor substrate 110a. The first conductivity type well 120b is formed by doping a portion of the semiconductor substrate 110a adjacent to the first surface 111 of the substrate 110 with the first conductivity type dopant, or is formed by a portion of the semiconductor substrate 110a where the second conductivity type well 120a is not provided (disposed). The second conductivity type well 120a is formed by doping a second conductivity type dopant into the semiconductor substrate 110a. A photodiode is formed by the pn junction between the first conductivity type well 120b and the second conductivity type well 120a. The photoelectric conversion unit 120 generates and accumulates charges in proportion to the amount of light provided to each pixel region PX. Depending on the embodiment, the first conductivity type well 120b may not be provided.

The photoelectric conversion units 120 are formed to correspond to each pixel region PX. For example, a separation unit 126 is positioned between the pixel regions PX, penetrating at least a portion of the substrate 110 to separate the pixel regions PX from each other, and one or more photoelectric conversion units 120 are positioned within the substrate 110 in each of the pixel regions PX.

In the embodiment, when viewed from a cross section, the isolation portion 126 penetrates at least a portion of the substrate 110 in the thickness direction. When viewed from a plan view, the isolation portion 126 is formed to penetrate a portion (e.g., an internal portion) of the element isolation portion 124.

The isolation portion 126 is located within a first trench having a relatively deep depth. For example, the first trench is a deep trench (DT), and the isolation portion 126 is a deep trench isolation (deep trench isolation). In one embodiment, the isolation portion 126 includes a front deep trench isolation (FDTI) including a portion adjacent to the first surface 111 of the substrate 110 and/or a back deep trench isolation (BDTI) including a portion adjacent to the second surface 112 of the substrate 110. Although the drawings illustrate an example in which the isolation portion 126 entirely penetrates the semiconductor substrate 110a, including the front deep trench isolation, the embodiment is not limited thereto.

When viewed from a plane, the separator 126 includes a first separator 126a extending in a first direction (the X-axis direction in the drawing) and a second separator 126b extending in a second direction (the Y-axis direction in the drawing). For example, when viewed from a plane, the separator 126 has a lattice shape corresponding to the plurality of pixel regions PX. As a result, when viewed from a plane, each pixel region PX is surrounded by a pair of first separators 126a and a pair of second separators 126b.

In this embodiment, the isolation portion 126 further includes an internal isolation portion 126c extending from the first isolation portion 126a into the pixel region PX. The internal isolation portion 126c separates the first and second portions 121a and 122a of the second conductivity type well 120a within the pixel region PX. However, the embodiment is not limited to this, and the internal isolation portion 126c may not be provided.

The isolation portion 126 includes an insulating layer. The insulating layer of the isolation portion 126 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may include a single layer or multiple layers. However, examples are not limited to this, and the material of the insulating layer of the isolation portion 126 may be changed in various ways.

In one embodiment, the isolation portion 126 further includes a conductive layer. For example, the conductive layer of the isolation portion 126 includes a semiconductor material (e.g., silicon). By applying a negative voltage to the conductive layer of the isolation portion 126, dark current can be improved through hole accumulation. However, the embodiment is not limited thereto. A negative voltage may not be applied to the conductive layer of the isolation portion 126, or the isolation portion 126 may not include a conductive layer.

A sidewall doped region is located in a portion of the semiconductor substrate 110a adjacent to the isolation portion 126. The sidewall doped region is formed adjacent to at least both sidewalls of the isolation portion 126. The sidewall doped region, together with the conductive layer of the isolation portion 126, serves to improve dark current. The sidewall doped region has the same first conductivity type (p-type or n-type) as the semiconductor substrate 110a, for example, p-type. For example, the sidewall doped region includes boron, aluminum, gallium, indium, etc. as a p-type dopant.

The photoelectric conversion unit 120 (e.g., the second conductivity type well 120a) located in each pixel region PX may be composed of one portion or multiple portions. In FIG. 3, the second conductivity type well 120a in one pixel region PX is illustrated as including first and second portions 121a and 122a spaced apart from each other, and a connecting portion 124a connecting the first portion 121a and the second portion 122a. However, the embodiment is not limited to this. Therefore, the second conductivity type well 120a may have three or more spaced apart portions, or the connecting portion 124a may be located in another position, or may not be present at all.

In this embodiment, the isolation portion 124 is located within a second trench having a relatively small depth and defines an active region 114 in each pixel region PX. For example, the second trench is a shallow trench (ST), and the isolation portion 124 is a shallow trench isolation (STI). The isolation portion 124 defines the active region 114 in a portion adjacent to the first surface 111 of the substrate 110 when viewed in cross section. For clarity, the boundary between the isolation portion 124 and the isolation portion 126 is shown in the drawings. As another example, the boundary between the isolation portion 124 and the isolation portion 126 may not be visible, and the isolation portion 124 and the isolation portion 126 may form an integral structure in a portion adjacent to the first surface 111 of the substrate 110.

When viewed from a plane, the element isolation portion 124 is located in an area other than the active region 114. In this embodiment, the active region 114 includes a first active region 114a included in the first transistor 142, a second active region 114b included in the second transistor 144, and a third active region 114c in which the ground region 120g is located.

The element isolation portion 124 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may include one or more layers. However, embodiments are not limited to this. Therefore, the material of the element isolation portion 124 may be varied in various ways, or the element isolation portion 124 may not be provided.

In FIG. 2, the surfaces of the element isolation portion 124 and isolation portion 126 adjacent to the first surface of the semiconductor substrate 110a located on the first surface 111 side of the substrate 110 are illustrated as being located on the same plane as the first surface of the semiconductor substrate 110a. However, the embodiment is not limited to this, and the first surface of the semiconductor substrate 110a and the surfaces of the element isolation portion 124 and/or isolation portion 126 may be located on different planes.

The pixel circuit 130 is located adjacent to the first surface 111 of the substrate 110. The pixel circuit 130 will be described in more detail below with reference to both Figures 4 and 5.

A wiring unit 170 electrically connected to the pixel circuit 130 is located on the first surface 111 of the substrate 110. That is, the wiring unit 170 is located on the first surface 111 side of the substrate 110, opposite the second surface 112 where light is received, so as not to be positioned in the path of light incident on the image sensor 10. This minimizes optical interference caused by the wiring unit 170.

The wiring unit 170 includes a first contact via 172 that penetrates the first interlayer insulating layer 172i and is connected (e.g., electrically connected) to the pixel circuit 130, a first wiring layer 174 that is connected (e.g., electrically connected) to the first contact via 172, one or more second contact vias 176 located on the first wiring layer 174, and/or one or more second wiring layers 178. The second contact via 176 penetrates the second interlayer insulating layer 176i and connects (e.g., electrically connects) the first wiring layer 174 and the second wiring layer 178, or connects (e.g., electrically connects) adjacent second wiring layers 178. The first contact vias 172, first wiring layer 174, second contact vias 176, and second wiring layer 178 of the wiring unit 170 are connected to form a desired circuit. The first contact via 172 is formed in the same process as the first wiring layer 174, or in a separate process from the first wiring layer 174. The second contact via 176 is formed in the same process as the second wiring layer 178, or in a separate process from the second wiring layer 178.

The first interlayer insulating layer 172i or the second interlayer insulating layer 176i includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, and/or a low-k material. Here, a low-k material is a material with a lower dielectric constant than silicon oxide.

The first contact via 172, the first wiring layer 174, the second contact via 176, or the second wiring layer 178 may include at least one of a metal, a metal alloy, a metal nitride, a metal silicide, and a doped semiconductor material. Here, the metal or metal alloy may include at least one of tungsten, molybdenum, aluminum, copper, and cobalt, and the metal nitride may include at least one of tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride. The first contact via 172, the first wiring layer 174, the second contact via 176, or the second wiring layer 178 may further include a metal oxide or metal oxynitride formed by oxidizing the above-mentioned materials. The first contact via 172, the first wiring layer 174, the second contact via 176, or the second wiring layer 178 may be formed as a single layer or as multiple layers.

However, embodiments are not limited to this, and the first interlayer insulating layer 172i or the second interlayer insulating layer 176i may include various insulating materials, and the first contact via 172, the first wiring layer 174, the second contact via 176, or the second wiring layer 178 may include various conductive materials.

A horizontal insulating layer 180, a color filter 182, a filter separator 184, a protective layer 186, and a microlens 188 are located on the second surface 112 of the substrate 110.

More specifically, a horizontal insulating layer 180 is positioned on the second surface 112 of the substrate 110. The horizontal insulating layer 180 is positioned to cover the second surface 112 of the substrate 110 and the separation portion 126. The horizontal insulating layer 180 serves as a type of planarizing layer that flattens the surface, ensuring that the color filters 182, microlenses 188, etc. formed on the horizontal insulating layer 180 are formed stably.

The horizontal insulating layer 180 may include various insulating materials. For example, the horizontal insulating layer 180 may include oxides, nitrides, oxynitrides, and fluorides containing at least one of hafnium, zirconium, aluminum, tantalum, titanium, yttrium, cerium, lanthanum, neodymium, praseodymium, ytterbium, and silicon. As an example, the horizontal insulating layer 180 may also function as an anti-reflective layer, although examples are not limited thereto.

In one embodiment, the horizontal insulating layer 180 includes multiple layers containing different materials and having different thicknesses. For example, the first horizontal insulating layer located adjacent to the second surface 112 of the substrate 110 in the horizontal insulating layer 180 is a fixed charge layer having a negative fixed charge. This allows for hole accumulation around the fixed charge layer, thereby improving dark current. In one embodiment, the first horizontal insulating layer includes a metal oxide or metal fluoride containing at least one of hafnium, zirconium, aluminum, tantalum, titanium, and yttrium. For example, the horizontal insulating layer 180 or anti-reflective layer includes a first horizontal insulating layer containing hafnium oxide, a second horizontal insulating layer containing silicon oxide or silicon nitride, and a third horizontal insulating layer containing hafnium oxide.

However, embodiments are not limited thereto, and the number and thickness of layers included in the horizontal insulating layer 180 may be modified in various ways. As another example, a light-reflecting structure may be formed on the second surface 112 of the substrate 110. For example, a nanoporous structure having a nanometer-level size may be formed on the second surface 112 of the substrate 110 using a laser or etching to reflect light. Here, a nanometer-level size refers to a size (e.g., average width, average diameter, or average pitch) of less than 1 μm. This allows the structure and manufacturing process to be simplified by omitting an anti-reflection layer from the horizontal insulating layer 180. However, embodiments are not limited thereto, and the horizontal insulating layer 180 may include an anti-reflection layer even when a light-reflecting structure is formed on the second surface 112 of the substrate 110.

A filter separator 184 is located on the horizontal insulating layer 180. In one embodiment, the filter separator 184 is formed to surround at least a portion of the color filter 182. As an example, the filter separator 184 has a lattice shape that is the same as or similar to the separator 126, but the embodiment is not limited thereto. The filter separator 184 may be referred to as a fence pattern, grid pattern, etc.

The filter separator 184 prevents light that is obliquely incident on the color filter 182 provided in one of the pixel regions PX from entering the color filter 182 provided in another adjacent pixel region PX. This prevents crosstalk between the pixel regions PX.

In one embodiment, the filter separator 184 includes a material having a refractive index smaller than that of the color filter 182 or silicon oxide, or a material having a refractive index of about 1.0 to about 1.4. When the filter separator 184 includes a material having a small refractive index, light incident on the filter separator 184 is totally reflected and directed toward the interior of the pixel region PX.

For example, the filter separator 184 may include polymethyl methacrylate (PMMA), silicone acrylate, cellulose acetate butyrate (CAB), silica, or fluoro-silicon acrylate (FSA). For example, the filter separator 184 may include a polymer material having silica particles dispersed therein. However, embodiments are not limited thereto, and the filter separator 184 may include materials other than those described above.

A color filter 182 is positioned on the horizontal insulating layer 180. The color filters 182 are separated from each other by filter separators 184. The color filters 182 include, for example, green, blue, and red filters. According to an embodiment, the color filter 182 may include a cyan filter, a magenta filter, a yellow filter, an infrared filter for passing infrared light, etc. Alternatively, a pixel region PX into which all visible light is incident may be provided.

A protective layer 186 is positioned on the color filter 182 and/or the filter separator 184. The protective layer 186 may include various materials such as organic materials, silicon oxide, silicon oxynitride, and aluminum oxide. However, embodiments are not limited to the material of the protective layer 186, and the protective layer 186 may not be provided.

The microlenses 188 located on the color filters 182 and/or the protective layer 186 include convex portions that can focus light incident on the pixel regions PX. The microlenses 188 may be made of various resin materials, such as styrene-based resins, acrylic-based resins, styrene-acrylic copolymer-based resins, or siloxane-based resins.

However, embodiments are not limited thereto, and the shape and material of the microlens 188 may be modified in various ways. As an example, a metalens may be provided instead of the microlens 188. Metalens include nanostructures having nanorod or nanopillar shapes with nanometer-level dimensions. A metalens changes the direction of incident light by using a metasurface formed by periodically arranging meta-atoms smaller than the wavelength of light, thereby directing the light to a specific point. This allows it to function as a lens. Metalens or nanostructures may include Si, SiN, GaN, TiO2, etc.

In the drawings, the microlenses 188 are shown positioned to correspond to multiple pixel regions PX, respectively. However, the embodiment is not limited to this, and one microlens 188 may be positioned to correspond to multiple pixel regions PX. Depending on the embodiment, a protective layer or the like may further be positioned on the outer surface of the microlens 188.

In one embodiment, the relative positions of the pixel region PX and the color filter 182 and/or the relative positions of the pixel region PX and the microlens 188 may differ between the center and the edge of the image sensor 10 when viewed from a plan view. That is, the area of the color filter 182 overlapping the pixel region PX and/or the area of the microlens 188 overlapping the pixel region PX may be smaller in the edge region of the image sensor 10 than in the center region of the image sensor 10 when viewed from a plan view. For example, the area of the color filter 182 overlapping the pixel region PX and/or the area of the microlens 188 overlapping the pixel region PX may become smaller from the center region of the image sensor 10 toward the edge region of the image sensor 10 when viewed from a plan view.

As described above, the relative positions of the pixel region PX and the color filter 182 and/or microlens 188 are adjusted to allow as much light as possible to reach the photoelectric conversion unit 120 in the pixel region PX. For example, the microlens 188, color filter 182, and photoelectric conversion unit 120 in the pixel region PX are positioned so that they overlap with each other along the light path direction. Because light is incident at an oblique angle in the edge region of the image sensor 10, the relative positions of the pixel region PX and the color filter 182 and/or microlens 188 are adjusted to transmit as much of the light incident at an oblique angle as possible to the photoelectric conversion unit 120 in the pixel region PX.

An additional wiring portion 200 is further positioned on the photoelectric conversion substrate 100 (e.g., wiring portion 170). The additional wiring portion 200 includes a substrate 210, a logic circuit portion including transistors 240 and wiring 270, a power supply portion, etc. The transistors 240 included in the additional wiring portion 200 have a different structure from the multiple transistors 140 provided in the photoelectric conversion substrate 100. For example, the transistors 240 of the additional wiring portion 200 have a planar structure in which a gate insulating layer and a gate electrode are located on the substrate 210. The wiring 270 of the additional wiring portion 200 includes an interlayer insulating layer, a wiring layer, a contact via, etc. The descriptions of the first or second interlayer insulating layer 172i, 176i, the first or second wiring layer 174, 178, or the first or second contact via 172, 176 included in the wiring unit 170 apply to the interlayer insulating layer, wiring layer, or contact via included in the wiring 270 of the additional wiring portion 200. However, the embodiments are not limited to this, and the components included in the additional wiring portion 200 can be modified in various ways.

In this embodiment, light incident from the outside on the image sensor 10 is collected by the microlens 188 and enters the photoelectric conversion unit 120 via the color filter 182. The light incident on the photoelectric conversion unit 120 is converted into an electrical signal depending on the amount of light.

Referring to Figures 4 and 5, along with Figures 2 and 3, a pixel circuit 130 including multiple embedded patterns 132 will be described in more detail.

Figure 4 is an enlarged view of portion D in Figure 2, and Figure 5 is an enlarged view of portion E in Figure 2.

Referring to Figures 2 to 5, in this embodiment, the pixel circuit 130 is disposed adjacent to the first surface 111 of the substrate 110. When viewed from a plan view, the pixel circuit 130 is located within the pixel region PX, on the isolation portion 126 and/or the device isolation portion 124, or in the active region 114.

In this embodiment, the pixel circuit 130 includes a plurality of transistors 140 and/or a connecting pattern 150. The pixel circuit 130 also includes a plurality of buried patterns 132 having a buried structure buried within the substrate 110. The connecting pattern 150 is the portion excluding the plurality of transistors 140, and includes all of the doped connecting patterns (e.g., first connecting pattern 152 and/or second connecting pattern 154) connected to the substrate 110 or the doped region 120d, and the wiring patterns connected to the plurality of transistors 140 and/or the doped connecting patterns. The wiring patterns will be described in more detail later with reference to FIG. 25.

In this embodiment, the plurality of transistors 140 includes a first transistor 142 including a first gate electrode 142g, which is a vertical transfer gate (VTG) electrode, and a second transistor 144 including a second gate electrode 144g having a cross-sectional shape different from that of the first gate electrode 142g.

The first transistor 142 is a transfer transistor including a first gate electrode 142g of a vertical transfer gate electrode. In this embodiment, the second transistor 144 is provided in multiple pixel regions PX and includes multiple second transistors 144 that perform different operations. For example, the second transistor 144 includes a third transistor 146 including at least one of a reset transistor 146a and a select transistor 146b, and a fourth transistor 148 including a source follower transistor 148a.

The first transistor 142 transfers the charge generated in the photoelectric conversion unit 120 to the floating diffusion region 120f in response to a transfer signal applied to the first gate electrode 142g. The reset transistor 146a resets the charge stored in the floating diffusion region 120f when a reset control signal is applied. The selection transistor 146b selects the pixel region PX in response to a selection control signal. The source follower transistor 148a generates a pixel signal corresponding to the amount of charge stored in the floating diffusion region 120f.

The first transistor 142 is electrically connected to the photoelectric conversion unit 120 and includes a first gate electrode 142g. When viewed in cross section, the first gate electrode 142g of the vertical transfer gate electrode has a shape in which its length (e.g., maximum length) in the thickness direction of the image sensor 10 (the Z-axis direction in the drawing) is greater than its width in the plane (e.g., minimum width in the X-axis or Y-axis direction in the drawing). The first transistor 142 further includes a gate insulating layer (e.g., first gate insulating layer 140a) located between the first gate electrode 142g and the substrate 110 (e.g., semiconductor substrate 110a).

3 illustrates an example in which one first active region 114a is provided corresponding to the first portion 121a of the second conductivity type well 120a, and another first active region 114a is provided corresponding to the second portion 122a of the second conductivity type well 120a. Also, FIG. 3 illustrates a dual vertical transfer gate (dual VTG) structure in which two first gate electrodes 142g are connected to one first active region 114a. This allows for efficient transfer of charges generated in the photoelectric conversion unit 120. For clarity, FIG. 3 illustrates two first gate electrodes 142g connected to one first active region 114a as being spaced apart from each other, but the embodiment is not limited thereto. As another example, two first gate electrodes 142g connected to one first active region 114a may be connected to each other at a portion adjacent to the first surface 111 of the substrate 110. As yet another example, a single vertical transfer gate (single VTG) structure may be formed in which one first gate electrode 142g is connected to one first active region 114a. Various other modifications are possible.

The second transistor 144 has a different structure or shape from the first transistor 142. Here, "having a different structure or shape" means that the presence or absence, position, and arrangement of electrodes, layers, and doped portions included in or related to the transistor are different, and the cross-sectional structure or cross-sectional shape of the electrodes, layers, and doped portions included in or related to the transistor are different. In other words, differences in width, length, planar shape, etc. alone do not appear to be different structures or shapes.

In this embodiment, the second transistor 144 includes a second gate electrode 144g and source and drain regions located on either side of the second gate electrode 144g and located in the substrate 110 (e.g., semiconductor substrate 110a). The second transistor 144 further includes a gate insulating layer (e.g., first gate insulating layer 140a or second gate insulating layer 140b) located between the second gate electrode 144g and the substrate 110.

The second gate electrodes 144g included in the second transistors 144 (e.g., the selection transistor 146b, the reset transistor 146a, and the source follower transistor 148a) provided in the pixel regions PX have the same cross-sectional structure. Here, having the same cross-sectional structure means that the presence or absence, position, and arrangement of the electrodes, layers, and doped portions included in or associated with the second gate electrodes 144g are the same, or the electrodes, layers, and doped portions included in or associated with the second gate electrodes 144g have a common cross-sectional structure or shape. In other words, they have the same cross-sectional structure or shape even if there are differences in width, length, planar shape, etc.

In the embodiment, the second transistor 144 or the second gate electrode 144g included therein is a three-dimensional (3D) transistor or a three-dimensional gate electrode, respectively. For example, a depth-varying portion, in which the depth changes, is provided in an inner portion located between both side portions in a cross section intersecting (e.g., perpendicular to) the longitudinal direction of the second transistor 144 or the second gate electrode 144g included therein. When a depth-varying portion is provided in the inner portion, the transistor width of the second transistor 144 is wider than the width of the second gate electrode 144g in a plan view (e.g., the width in the Y-axis direction in the drawing, e.g., the minimum width). This allows the area of the second transistor 144 to be reduced while maintaining the characteristics of the second transistor 144, thereby enabling pixel miniaturization.

For example, when viewed from a cross section, the second gate electrode 144g of the second transistor 144 has a recessed portion C1 in the center portion, resulting in a relatively small depth, and protruding portions C2 between the center portion and both side portions, resulting in a relatively large depth. However, the shape of the second gate electrode 144g of the second transistor 144 shown in FIG. 4 is merely an example of a three-dimensional structure, and embodiments are not limited to this. Therefore, the second gate electrode 144g can have various structures with cross-sectional shapes different from those of the first gate electrode 142g.

In this embodiment, the device isolation portions 124 are located on both sides of the second gate electrode 144g of the second transistor 144. More specifically, when viewed in a direction (Y-axis direction in the drawing) that intersects (e.g., perpendicular to) the length direction (X-axis direction in the drawing) of the second gate electrode 144g of the second transistor 144, the device isolation portions 124 are located on both sides of the second gate electrode 144g of the second transistor 144. When viewed from above, the device isolation portions 124 located on both sides of the second transistor 144 include portions that extend in a direction parallel to the length direction of the second gate electrode 144g. This makes it easy to form the second gate electrode 144g of the second transistor 144 with a three-dimensional structure. This will be explained in more detail later in the manufacturing method.

In this embodiment, each pixel region PX is provided with a first transistor 142 and a second transistor 144, and the second transistors 144 located in the pixel regions PX constituting one unit pixel group are shared as transistors that operate differently from each other. For example, the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4 shown in FIG. 3 constitute one unit pixel group. In this case, the second transistors 144 located in the first pixel region PX1 and the third pixel region PX3 each include a source follower transistor 148a, the second transistor 144 located in the second pixel region PX2 includes a selection transistor 146b, and the second transistor 144 located in the fourth pixel region PX4 includes a reset transistor 146a. However, the embodiment is not limited to this and various modifications are possible.

In this embodiment, the connection pattern 150 includes at least one of a first connection pattern 152 electrically and/or physically connected to the ground region 120g and a second connection pattern 154 electrically and/or physically connected to the floating diffusion region 120f.

In this case, the ground region 120g in each pixel region PX is located in at least a portion of the third active region 114c adjacent to the first connecting pattern 152. One or more floating diffusion regions 120f in each pixel region PX are located in at least a portion of the first active region 114a adjacent to the second connecting pattern 154. For example, if the second conductive well 120a has a first portion 121a and a second portion 122a, the floating diffusion region 120f is located in at least a portion of the first active region 114a corresponding to the first portion 121a adjacent to the second connecting pattern 154, and the floating diffusion region 120f is located in at least a portion of the first active region 114a corresponding to the second portion 122a adjacent to the second connecting pattern 154. The floating diffusion region 120f in each pixel region PX is located on at least one side of the first transistor 142 (e.g., the first gate electrode 142g).

The first connecting pattern 152 and/or the second connecting pattern 154 is formed across at least two pixel regions PX among the plurality of pixel regions PX, and at least a portion of the first connecting pattern 152 and/or the second connecting pattern 154 is located on the isolation portion 126. That is, the first connecting pattern 152 and/or the second connecting pattern 154 is shared by at least two pixel regions PX among the plurality of pixel regions PX.

In one embodiment, the first connecting pattern 152 is formed across the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4. The first connecting pattern 152 is connected to a plurality of ground regions 120g located in the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4, respectively.

For example, one first connecting pattern 152 is provided in the center of one unit pixel group where the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4 are adjacent to one another. When viewed from a plane, a ground region 120g is located adjacent to the center of one unit pixel group in each of the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4. This allows the first connecting pattern 152 to be easily connected to multiple (e.g., four) ground regions 120g located in the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4, respectively.

In this case, a portion of the first connecting pattern 152 is located on a portion of the first isolation portion 126a located between the first pixel region PX1 and the third pixel region PX3, a portion of the first isolation portion 126a located between the second pixel region PX2 and the fourth pixel region PX4, a portion of the second isolation portion 126b located between the first pixel region PX1 and the second pixel region PX2, and a portion of the second isolation portion 126b located between the third pixel region PX3 and the fourth pixel region PX4.

In the above description, an example has been given in which the semiconductor substrate 110a is provided with a ground region 120g and the first connecting pattern 152 is connected to the ground region 120g. However, the embodiment is not limited to this, and the semiconductor substrate 110a may not be provided with a ground region 120g, and the first connecting pattern 152 may be connected to the semiconductor substrate 110a or the first conductivity type well 120b. Various other modifications are possible.

In one embodiment, the second connecting pattern 154 includes a first connecting portion 154a and a second connecting portion 154b.

The first connecting portion 154a is formed across the first pixel region PX1 and the third pixel region PX3 and is connected to the floating diffusion region 120f provided in the first pixel region PX1 and the third pixel region PX3.

For example, a first connecting portion 154a is provided in the central portion of the first pixel region PX1 and the third pixel region PX3, which are adjacent in the second direction (the Y-axis direction in the drawing). A floating diffusion region 120f is located adjacent to the first connecting portion 154a in the first active region 114a of each of the first pixel region PX1 and the third pixel region PX3. In this embodiment, since multiple (e.g., two) floating diffusion regions 120f are located in each pixel region PX, the first connecting portion 154a is connected to multiple (e.g., four) floating diffusion regions 120f provided in the first and third pixel regions PX1 and PX3. This allows the first connecting portion 154a to be easily connected to the floating diffusion regions 120f located in each of the first pixel region PX1 and the third pixel region PX3.

In this case, a portion of the first connecting portion 154a is located on a portion of the first separating portion 126a located between the first pixel region PX1 and the third pixel region PX3.

The second connecting portion 154b is formed across the second pixel region PX2 and the fourth pixel region PX4 and is connected to the floating diffusion region 120f provided in the second pixel region PX2 and the fourth pixel region PX4.

For example, the second connecting portion 154b is provided in the central portion of the second pixel region PX2 and the fourth pixel region PX4, which are adjacent in the second direction (the Y-axis direction in the drawing). The floating diffusion region 120f is located adjacent to the second connecting portion 154b in the first active region 114a of each of the second pixel region PX2 and the fourth pixel region PX4. In this embodiment, since multiple (e.g., two) floating diffusion regions 120f are located in each pixel region PX, the second connecting portion 154b is connected to multiple (e.g., four) floating diffusion regions 120f provided in the second and fourth pixel regions PX2 and PX4. This allows the second connecting portion 154b to be easily connected to the floating diffusion regions 120f located in each of the second pixel region PX2 and the fourth pixel region PX4.

In this case, a portion of the second connecting portion 154b is located on a portion of the second separating portion 126b located between the second pixel region PX2 and the fourth pixel region PX4.

In the four pixel regions PX that make up one unit pixel group, when viewed from the first direction (the X-axis direction in the drawing), one first connecting pattern 152 is located between the first connecting portion 154a and the second connecting portion 154b.

In this manner, when the first connecting pattern 152 and/or the second connecting pattern 154 have a structure shared by at least two pixel regions PX, the structure of the connecting pattern 150 and the structure of the wiring part 170 can be simplified. For example, the number of first contact vias 172 can be reduced and the spacing between the first contact vias 172 can be increased. This will be described in more detail later while describing the first contact vias 172 with reference to FIG. 6.

In this embodiment, the connection pattern 150 includes a doped region DR containing a dopant adjacent to a first surface (e.g., a front surface) of the connection pattern 150 adjacent to the first surface 111 of the substrate 110, and further includes an undoped region UR adjacent to a second surface (e.g., an internal surface) of the connection pattern 150 opposite the first surface of the connection pattern 150.

For example, the first connecting pattern 152 includes a first doped region DR1 containing a first conductive type dopant adjacent to a first surface of the first connecting pattern 152, and further includes a first undoped region UR1 or a low concentration region adjacent to a second surface of the first connecting pattern 152. The first doped region DR1 reduces electrical resistance, and the first undoped region UR1 reduces leakage current and prevents unwanted signal generation, etc.

As an example, the depth of the first doped region DR1 is equal to or smaller than the depth of the first undoped region UR1. Here, the depth refers to the depth in the thickness direction of the substrate 110, e.g., the maximum depth. This allows the first undoped region UR1 to be sufficiently secured, effectively reducing leakage current and effectively preventing unwanted signal generation. As another example, the depth of the first doped region DR1 may be greater than the depth of the first undoped region UR1. This allows effective reduction in electrical resistance. Alternatively, the ratio of the depth of the first doped region DR1 to the total depth of the first connecting pattern 152 is 30% to 70% (e.g., 40% to 60%), but embodiments are not limited thereto. Depending on the embodiment, the first undoped region UR1 may not be provided.

For example, the second connecting pattern 154 includes a second doped region DR2 adjacent to a first surface of the second connecting pattern 154 and containing a second conductive type dopant, and further includes a second undoped region UR2 adjacent to a second surface of the second connecting pattern 154. The second doped region DR2 reduces electrical resistance. The second undoped region UR2 reduces leakage current and can prevent unwanted signal generation, etc.

As one example, the depth of the second doped region DR2 is the same as or smaller than the depth of the second undoped region UR2. This ensures sufficient second undoped region UR2, effectively reducing leakage current and effectively preventing unwanted signal generation. As another example, the depth of the second doped region DR2 is greater than the depth of the second undoped region UR2. This effectively reduces electrical resistance. Alternatively, the ratio of the depth of the second doped region DR2 to the total depth of the second connection pattern 154 is 30% to 70% (e.g., 40% to 60%), but embodiments are not limited thereto. Depending on the embodiment, the second undoped region UR2 may not be provided.

In the embodiment, the first gate electrode 142g, the second gate electrode 144g, and/or the connecting pattern 150 (e.g., the first connecting pattern 152 and/or the second connecting pattern 154) correspond to the buried pattern 132 having a buried structure buried inside the substrate 110. That is, the plurality of buried patterns 132 include the first gate electrode 142g, the second gate electrode 144g, and/or the connecting pattern 150 (e.g., the first connecting pattern 152 and/or the second connecting pattern 154). For example, the first transistor 142, the second transistor 144, the third transistor 146, the fourth transistor 148, the reset transistor 146a, the selection transistor 146b, and/or the source follower transistor 148a are referred to as buried transistors, the first gate electrode 142g and/or the second gate electrode 144g are referred to as buried gate electrodes, and the connection pattern 150 is referred to as a buried connection pattern or a buried local interconnector.

Here, having an embedded structure embedded inside the substrate 110 means that it only has a portion located between the first surface 111 and the second surface 112 of the substrate 110 and/or a portion located on the same plane as the first surface 111 of the substrate 110, and does not have a portion located outside the first surface 111 of the substrate 110 or a portion protruding from the first surface 111 of the substrate 110 toward the wiring portion 170.

In the embodiment, the plurality of transistors 140 have a buried structure, which allows for easy formation of the transistors through a simple process. For example, it is not necessary to separately form a capping layer, spacers, etc., which are included in the transistors according to the comparative example. Furthermore, because the plurality of buried patterns 132 do not include a portion located on the first surface 111 of the substrate 110, the thickness of the first interlayer insulating layer 172i can be reduced. That is, in the comparative example in which at least a portion of the plurality of transistors and/or connecting patterns are located on the first surface 111 of the substrate, the first interlayer insulating layer must have a relatively large thickness to insulate the plurality of transistors from the first wiring layer. In contrast, in the embodiment, the plurality of transistors 140 and/or connecting patterns 150 are not located on the first surface 111 of the substrate 110, so the thickness of the first interlayer insulating layer 172i located on the first surface 111 of the substrate 110 can be reduced. This reduces the depth of the first contact via 172, thereby reducing the electrical resistance due to the first contact via 172.

In the embodiment, the multiple buried patterns 132 having a buried structure are formed by the same process. Here, "multiple buried patterns 132 formed by the same process" means that the multiple buried patterns 132 are formed by performing a removal process to remove the portion of the buried layer (reference numeral 132p in FIG. 12 or FIG. 23, the same applies below) that is located above the surface insulating layer 110b and that fills the interiors of the multiple recesses formed in the substrate 110 and includes a portion located above the surface insulating layer 110b. For example, if the multiple buried patterns 132 have a final buried structure formed by the same removal process, such as the same chemical mechanical polishing (CMP) process, they are considered to have been formed by the same process. As an example, the multiple buried patterns 132 have a final buried structure formed by a single chemical mechanical polishing process performed on the first surface 111 side of the substrate 110.

In the embodiment, the multiple buried patterns 132 contain the same base material. Here, base material refers to the material that is contained in the largest amount. In other words, containing the same base material includes cases where the same material is contained, cases where the same material is contained but with slight differences in composition, and cases where there are differences in doping, conductivity type, doping concentration, dopant material, etc. For example, if the multiple buried patterns 132 contain the same semiconductor material but with differences in doping, conductivity type, doping concentration, dopant material, etc., the multiple buried patterns 132 are determined to contain the same base material.

In one embodiment, the plurality of buried patterns 132, e.g., the first gate electrode 142g, the second gate electrode 144g, the first connecting pattern 152, and/or the second connecting pattern 154, include the same base material (e.g., the same semiconductor material). For example, the plurality of buried patterns 132, e.g., the first gate electrode 142g, the second gate electrode 144g, the first connecting pattern 152, and/or the second connecting pattern 154, include a polycrystalline semiconductor (e.g., polycrystalline silicon). The plurality of buried patterns 132 are referred to as buried semiconductor patterns.

In this way, if the plurality of buried patterns 132 includes a semiconductor material, they can be easily formed and can be formed to have a desired conductivity type and/or electrical conductivity depending on the presence or absence of doping and/or the doping concentration. However, embodiments are not limited to this, and the plurality of buried patterns 132 may also include a material other than a semiconductor material as a base material.

In this embodiment, the first surfaces (e.g., the surfaces) of the buried patterns 132 located on the first surface 111 side of the substrate 110 have recesses S1, S2, S3, and S4 having a concave shape to include portions located between the first surface 111 of the substrate 110 and the second surface 112 of the substrate 110. For example, the surface of the first gate electrode 142g has a first recess S1, the surface of the second gate electrode 144g has a second recess S2, the first connecting pattern 152 has a third recess S3, and/or the second connecting pattern 154 has a fourth recess S4. Here, the recesses S1, S2, S3, and S4 are portions formed by the dishing phenomenon during the chemical mechanical polishing process.

In the embodiment, the multiple first surfaces (e.g., multiple surfaces) of the multiple embedded patterns 132 located on the first surface 111 side of the substrate 110 have the same surface characteristics. For example, the surface of the first gate electrode 142g, the surface of the second gate electrode 144g, the surface of the first connecting pattern 152, and/or the surface of the second connecting pattern 154 have the same surface characteristics. Here, having the same surface characteristics means having characteristics that can be determined to have been formed by the same process, such as a chemical mechanical polishing process, having the same or similar traces (e.g., polishing traces), or having a surface roughness within an error range (e.g., within 10%).

In this embodiment, the corners of the buried patterns 132 have rounded portions RP. That is, the interface topology between the buried patterns 132 and the substrate 110 is the same. For example, the corners of the first gate electrode 142g, the second gate electrode 144g, the first connecting pattern 152, and/or the second connecting pattern 154 include the same or similar rounded portions RP. Here, the "corner" refers to the portion of the side of the buried pattern 132 adjacent to the substrate 110 that is located on the first surface 111 of the substrate 110. This is because the recesses formed in the substrate 110 are formed using the same or similar etching process, and the buried layer 132p is partially removed using the same removal process to form the buried patterns 132.

In an embodiment, the plurality of buried patterns 132 may differ in the presence or thickness of a gate insulating layer. Even if the plurality of buried patterns 132 performing different functions or roles have the same buried structure, the presence or thickness of the gate insulating layer may differ depending on the characteristics of the plurality of buried patterns 132. For example, the thickness of the first gate insulating layer 140a included in the first transistor 142 or the third transistor 146 may be greater than the thickness of the second gate insulating layer 140b included in the fourth transistor 148, and the connecting pattern 150 does not include a gate insulating layer due to an ohmic contact. As a result, the plurality of buried patterns 132 may have three or more structures that differ in the presence or thickness of a gate insulating layer. The manufacturing method thereof will be described in more detail later in the manufacturing method of the image sensor 10.

The pixel circuit 130 described above is provided as an example, and embodiments are not limited thereto. Thus, the pixel circuit 130 may have various structures or arrangements.

In this embodiment, the interconnect pattern 150 can reduce the number of first contact vias 172 and increase the spacing between the first contact vias 172. This will be described in more detail with reference to Figures 2 and 3 as well as Figure 6.

Figure 6 is a plan view schematically illustrating a portion of the photoelectric conversion substrate 100 of the image sensor 10 shown in Figure 2. Figure 6 additionally illustrates the portion corresponding to Figure 3, with the first contact via 172 and a portion of the first wiring layer 174 electrically connected to the connection pattern 150. For clearer understanding and simplified illustration, Figure 6 omits the illustration of the second conductivity type well 120a, and omits the illustration of the first contact via 172 and the first wiring layer 174 electrically connected to portions other than the connection pattern 150 (e.g., multiple transistors 140).

Referring to Figures 2, 3, and 6, the first contact via 172 in the embodiment includes a contact via for the connect pattern connected to the connect pattern 150. For example, the contact via for the connect pattern includes a first via 172a (e.g., a ground contact via) connected to the first connect pattern 152 and a second via 172b (e.g., a floating diffusion contact via) connected to the second connect pattern 154. The first wiring layer 174 includes a first wiring portion 174a electrically connected to the first via 172a and a second wiring portion 174b electrically connected to the second via 172b.

In this embodiment, the first connecting pattern 152 and/or the second connecting pattern 154 are formed across at least two pixel regions PX, thereby reducing the number of first vias 172a and/or second vias 172b connected to the first connecting pattern 152 and/or the second connecting pattern 154.

For example, four pixel regions PX constituting one unit pixel group are provided with two second vias 172b respectively connected to the first connecting portion 154a and the second connecting portion 154b of the second connecting pattern 154, and one first via 172a connected to one first connecting pattern 152. For reference, in a comparative example in which one pixel region is provided with two floating diffusion regions and one ground region, and a first via is connected to each ground region and a second via is connected to each floating diffusion region, four first vias and eight second vias are provided in four pixel regions constituting one unit group.

This reduces the number of first vias 172a and/or second vias 172b (i.e., the number of first contact vias 172) connected to the first connecting pattern 152 and/or the second connecting pattern 154. This allows for appropriate response to pixel miniaturization and effectively prevents problems that may arise from reducing the spacing between the first contact vias 172. Furthermore, by increasing the spacing between the first vias 172a and the second vias 172b (i.e., the spacing between the first contact vias 172), the area of the first wiring layer 174 connected to the first contact vias 172 can be reduced. This reduces the parasitic capacitance between the floating diffusion region 120f and the first wiring layer 174. Furthermore, by increasing the spacing between portions of the first wiring layer 174 connected to the first contact vias 172, the parasitic capacitance between the first contact vias 172 or between the first wiring layer 174 can be reduced.

When viewed from a plane, the first via 172a is located in the center of the first connecting pattern 152. For example, when viewed from a plane, one first via 172a is provided in the center of one unit pixel group where the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4 are adjacent to one another. In this case, when viewed from a plane, the first via 172a is located so that it overlaps the intersection of the first isolation portion 126a and the second isolation portion 126b where the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4 are adjacent to one another.

In this way, if the first via 172a is located in the center of the first connecting pattern 152 or one unit pixel group, the electrical transfer path can be effectively reduced.

When viewed from a plane, the second vias 172b are located in the central portion of the second connecting pattern 154. That is, the second vias 172b are located in the central portion of the first connecting portion 154a in the first pixel region PX1 and the third pixel region PX3, and the second vias 172a are located in the central portion of the second connecting portion 154b in the second pixel region PX2 and the fourth pixel region PX4. In this case, when viewed from a plane, one second via 172b is located to overlap a portion (e.g., the central portion) of the first isolation portion 126a located between the first pixel region PX1 and the third pixel region PX3, and the other second via 172b is located to overlap a portion (e.g., the central portion) of the first isolation portion 126a located between the second pixel region PX2 and the fourth pixel region PX4.

In this way, if the second via 172b is located in the second connection pattern 154 or in the center of two pixel regions PX adjacent in the second direction (the Y-axis direction in the drawing), the electrical transfer path can be effectively reduced.

In FIG. 6, the first wiring portion 174a electrically connected to the first via 172a extends in the second direction (the Y-axis direction in the drawing) above the second isolation portion 126b, and the second wiring portion 174b electrically connected to the second via 172a extends in the first direction (the X-axis direction in the drawing) above the first isolation portion 126a. The first and/or second wiring portions 174a, 174b are located above the isolation portion 126, thereby reducing parasitic capacitance.

However, the embodiment is not limited to this, and the planar positions and arrangements of the first via 172a and/or the second via 172b, the first wiring portion 174a and/or the second wiring portion 174b, etc. may be modified in various ways.

In this embodiment, a front end of line (FEOL) including the first transistor 142, the second transistor 144, the connecting pattern 150, and the first contact via 172 connected thereto is formed on the substrate 110. That is, the photoelectric conversion substrate 100 includes all of the elements required for the operation of the image sensor 10. For example, the image sensor 10 has a two-layer stacked structure including the photoelectric conversion substrate 100 and the additional wiring portion 200.

As a result, multiple transistors 140 are formed on the substrate 110, and a separate substrate (e.g., an intermediate substrate located between the wiring portion 170 located on the substrate 110 and the additional wiring portion 200) for forming at least a portion of the multiple transistors 140 is not required. This reduces the number of processes and reduces manufacturing costs. For reference, a comparative example in which a first transistor is formed on a substrate and a separate substrate (e.g., an intermediate substrate) on which a second transistor is formed is located between the wiring portion located on the substrate and the additional wiring portion results in complex processes and high manufacturing costs.

While the above description illustrates an example in which the image sensor 10 has a two-layer stacked structure, the embodiment is not limited thereto. As another example, the wiring portion 170 located on the substrate 110 may include components included in the additional wiring portion 200, and the image sensor 10 may be configured as a single part. As another example, the image sensor 10 may have a stacked structure of three or more layers. In this case, additional elements such as DRAM, a shutter (e.g., a global shutter, a rolling shutter), etc. may be mounted on the substrate located between the wiring portion 170 located on the substrate 110 and the additional wiring portion 200. In this case, the wiring portion 170 formed on the substrate 110 also includes multiple transistors 140 (e.g., a first transistor 142 and a second transistor 144).

According to this embodiment, the first transistor 142, the second transistor 144, and/or the connecting pattern 150, which have different structures, are provided together on the substrate 110, thereby reducing the number of processes and lowering manufacturing costs. In this case, the first transistor 142, the second transistor 144, and/or the connecting pattern 150 have an embedded structure, which allows the pixel circuit 130 to be formed through a simple process and reduces the depth of the first contact via 172, thereby reducing electrical resistance. Furthermore, the connecting pattern 150 is formed to be shared by multiple pixel regions PX, which reduces the number of first contact vias 172 and the area of the first wiring layer 174, and increases the spacing between the first contact vias 172, thereby reducing parasitic capacitance. Reducing parasitic capacitance improves conversion gain. This improves the efficiency and productivity of the image sensor 10.

The manufacturing method of the image sensor 10 described above will be described in detail with reference to Figures 7 to 24. Detailed descriptions of parts that are identical to or very similar to parts already described will be omitted, and only other parts will be described in detail.

Figures 7 to 18 are cross-sectional views showing a method for manufacturing an image sensor 10 according to one embodiment. Figures 7 to 18 show portions corresponding to Figure 2.

As shown in FIG. 7, an element isolation portion 124, an isolation portion 126, a photoelectric conversion portion 120, and a first recess portion R1 are formed in the substrate 110. The substrate 110 includes a semiconductor substrate 110a and a surface insulating layer 110b, and has a first surface 111 and a spare surface 112p.

For example, an element isolation portion 124 and an isolation portion 126 are formed in the semiconductor substrate 110a.

A mask pattern having an opening exposing a region corresponding to the isolation portion 124 is formed on the first surface of the semiconductor substrate 110a adjacent to the first surface 111 of the substrate 110. A shallow trench is formed by etching a portion of the substrate 110 exposed through the opening in the mask pattern. At least a portion of the shallow trench is filled with an insulating layer to form the isolation portion 124 on the first surface of the semiconductor substrate 110a. A mask pattern having an opening exposing a region corresponding to the isolation portion 126 on the first surface of the semiconductor substrate 110a is then formed. A deep trench is formed by etching a portion of the substrate 110 exposed through the opening in the mask pattern. At least a portion of the deep trench is filled with an insulating layer and/or a conductive layer to form the isolation portion 126 on the first surface of the semiconductor substrate 110a. Depending on the embodiment, between the process of forming the deep trench and the process of forming the isolation portion 126, a sidewall doped region located around the isolation portion 126 may be further formed by doping a dopant around the deep trench.

In the embodiments, the element isolation region 124 and/or the isolation region 126 may be formed by various processes, and the element isolation region 124 and/or the isolation region 126 may include various materials.

For example, in a doping process, dopants are doped into a portion of the semiconductor substrate 110a to form a first conductivity type well 120b, a second conductivity type well 120a, and/or a floating diffusion region 120f. The doping process can be performed using various processes (e.g., ion implantation, etc.). Depending on the embodiment, the first conductivity type well 120b and/or the floating diffusion region 120f may not be formed in the doping process, or the first conductivity type well 120b and/or the floating diffusion region 120f may be formed in a subsequent process. The doping process may also include a process of forming a ground region (reference numeral 120g in FIG. 16, the same applies below). Various other modifications are possible.

For example, a surface insulating layer 110b is formed on the first surface of the semiconductor substrate 110a. The surface insulating layer 110b can be formed by various processes (e.g., a vapor deposition process).

For example, an etching process is performed from the first surface 111 side of the substrate 110 to form the first recess portion R1. The first recess portion R1 is a recess portion for forming the first transistor (reference numeral 142 in FIG. 13; the same applies below).

More specifically, a first mask layer having a first opening is formed on the first surface 111 of the substrate 110. The first opening in the first mask layer exposes a portion of the substrate 110 where the first transistor 142 is to be formed. The first mask layer is used to remove a portion of the substrate 110 from the first surface 111 side of the substrate 110 to form a first recess portion R1. After the first recess portion R1 is formed, the first mask layer is removed.

The first mask layer may include various materials (e.g., photosensitive materials). The patterning process for forming the first opening in the first mask layer may be performed by various processes (e.g., photolithography). The process for removing a portion of the substrate 110 through the first opening in the first mask layer may be performed by an etching process (e.g., dry etching). The etching process for forming the first recess portion R1 uses an etching material capable of etching the substrate 110. The process for removing the first mask layer may be performed by various etching processes (e.g., dry etching and/or wet etching).

In the embodiments, the order of forming the element isolation portion 124, isolation portion 126, first conductivity type well 120b, second conductivity type well 120a, floating diffusion region 120f, surface insulating layer 110b, and/or first recess portion R1 may be varied in various ways. For example, at least one of the steps of forming the first mask layer, forming the first recess portion R1, and removing the first mask layer may be performed before the doping step of forming the first conductivity type well 120b, second conductivity type well 120a, and/or floating diffusion region 120f, or after the doping step of forming the first conductivity type well 120b, second conductivity type well 120a, and/or floating diffusion region 120f.

As shown in FIG. 8, a second recess portion R2 and a third recess portion R3 are formed on the first surface 111 side of the substrate 110. The second recess portion R2 is a recess portion for forming a second transistor (reference numeral 144 in FIG. 13, the same applies below), and the third recess portion R3 is a recess portion for forming a connecting pattern (reference numeral 150 in FIG. 13, the same applies below). The second recess portion R2 includes a first recess portion R21 for forming a third transistor (reference numeral 146 in FIG. 13, the same applies below) and a second recess portion R22 for forming a fourth transistor (reference numeral 148 in FIG. 13, the same applies below). The third recess portion R3 includes a first connection recess R31 for forming a first connection pattern (reference numeral 152 in FIG. 13, the same applies hereinafter) connected to the ground region 120g, and a second connection recess R32 for forming a second connection pattern (reference numeral 154 in FIG. 13, the same applies hereinafter) connected to the floating diffusion region 120f.

For example, an etching process is performed from the first surface 111 side of the substrate 110 to form the second recess portion R2 and the third recess portion R3. More specifically, a second mask layer 118a having a second opening 119a is formed on the first surface 111 of the substrate 110. The second opening 119a in the second mask layer 118a exposes the portion of the substrate 110 where the second transistor 144 and the connecting pattern 150 are to be formed. The portion of the substrate 110 exposed by the second opening 119a is removed from the first surface 111 side of the substrate 110 to form the second recess portion R2 and the third recess portion R3. After the second recess portion R2 and the third recess portion R3 are formed, the second mask layer 118a is removed.

The second mask layer 118a may include various materials (e.g., photosensitive materials). The patterning process for forming the second opening 119a in the second mask layer 118a may be performed using various processes (e.g., photolithography). The process for removing a portion of the substrate 110 through the second opening 119a in the second mask layer 118a may be performed using an etching process (e.g., dry etching). The etching process for forming the second recess portion R2 and the third recess portion R3 uses an etching material capable of etching the isolation portion 126 and/or the element isolation portion 124. The process for removing the second mask layer 118a may be performed using various etching processes (e.g., dry etching and/or wet etching). However, the embodiments are not limited thereto, and various modifications are possible.

In this embodiment, the second recess R2 is located between two adjacent device isolation portions 124. The etching material used to form the second recess R2 is a material that can easily etch the device isolation portions 124 (e.g., an insulating layer) and does not etch the substrate 110 or etches the substrate 110 less than the device isolation portions 124. In this manner, a portion of each of the two device isolation portions 124 located on both sides is easily etched to form a convex portion with a relatively large depth, and the substrate 110 located between the two device isolation portions 124 is not etched or is etched to a small extent to form a concave portion with a relatively small depth. This makes it easy to form a three-dimensional second recess R2 that has a concave portion in the center and convex portions between the center and both side portions.

The third recess R3 is positioned to include the portion where the isolation portion 126 and/or the device isolation portion 124 are located, and can be easily formed to have a desired shape. For example, since at least the central portion of the third recess R3 is located above the isolation portion 126 and/or the device isolation portion 124, the third recess R3 can be easily formed in a desired position and shape using an etching material that can etch the isolation portion 126 and/or the device isolation portion 124.

Next, a doping process is performed to form the channel portions of the third transistor 146 (e.g., reset transistor 146a and select transistor 146b).

More specifically, a third mask layer having a third opening is formed on the first surface 111 of the substrate 110. The third opening in the third mask layer exposes a portion of the substrate 110 in which the third transistor 146 will be formed. The portion of the substrate 110 exposed by the third opening is doped with a dopant (e.g., a second conductivity type dopant) to form a channel portion of the third transistor 146. After the channel portion is formed, the third mask layer is removed.

The third mask layer may include various materials (e.g., photosensitive materials). The patterning process for forming the third opening in the third mask layer may be performed by various processes (e.g., photolithography). The doping process may be performed by various processes (e.g., ion implantation process, etc.). The process for removing the third mask layer may be performed by various etching processes (e.g., dry etching and/or wet etching). However, the embodiments are not limited thereto, and various modifications are possible.

In the above description, a doping process for forming the channel portion of the third transistor 146 is performed without forming the channel portion of the fourth transistor 148, but the embodiment is not limited to this. In the doping process for forming the channel portion of the third transistor 146, the channel portion of the fourth transistor 148 may be formed at the same time, or the doping process for forming the channel portion of the fourth transistor 148 may be performed separately from the doping process for forming the channel portion of the third transistor 146. Alternatively, the doping process for forming the channel portion of the third transistor 146 may not be performed.

Next, as shown in FIGS. 9 to 11, a first gate insulating layer 140a or a second gate insulating layer 140b is formed in the first recess portion R1 or the second recess portion R2. In this case, the first gate insulating layer 140a or the second gate insulating layer 140b is not located in the third recess portion R3 where the connecting pattern 150 is located due to the ohmic contact of the connecting pattern 150.

More specifically, as shown in FIG. 9, a first gate insulating layer 140a is formed. The first gate insulating layer 140a has a thickness suitable for the first transistor 142 and the third transistor 146.

The first gate insulating layer 140a includes at least one of oxide, nitride, oxynitride, a high-k material having a higher dielectric constant than silicon oxide, and a low-k material having a lower dielectric constant than silicon oxide. For example, the first gate insulating layer 140a includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, and tantalum oxide. The first gate insulating layer 140a may be composed of a single insulating layer or may include multiple insulating layers.

For example, the first gate insulating layer 140a is formed using a thermal oxidation process or the like. In this case, since the surface insulating layer 110b is not present, the first gate insulating layer 140a is partially formed in the exposed portion of the substrate 110. In this case, the first gate insulating layer 140a includes silicon oxide. However, embodiments are not limited to this, and the first gate insulating layer 140a can be formed using various processes.

As shown in FIG. 10, the first gate insulating layer 140a is removed in the second recess portion R22 where the fourth transistor 148 will be formed, and a second gate insulating layer 140b is formed.

The second gate insulating layer 140b includes at least one of oxide, nitride, oxynitride, a high-k material having a higher dielectric constant than silicon oxide, and a low-k material having a lower dielectric constant than silicon oxide. For example, the second gate insulating layer 140b includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, and tantalum oxide. The second gate insulating layer 140b may be composed of a single insulating layer or may include multiple insulating layers.

For example, a fourth mask layer 118b having a fourth opening 119b is formed on the first surface 111 of the substrate 110. The fourth opening 119b in the fourth mask layer 118b exposes a portion of the substrate 110 where the fourth transistor 148 will be formed. The first gate insulating layer 140a located in the second recess portion R22 exposed by the fourth opening 119b is removed, and a second gate insulating layer 140b is formed in the second recess portion R22. After the second gate insulating layer 140b is formed, the fourth mask layer 118b is removed.

The fourth mask layer 118b may include various materials (e.g., photosensitive materials). The patterning process for forming the fourth opening 119b in the fourth mask layer 118b may be performed using various processes (e.g., photolithography). The process for removing the first gate insulating layer 140a exposed through the fourth opening 119b may be performed using an etching process (e.g., wet etching). For example, the second gate insulating layer 140b may be formed using a thermal oxidation process, etc. The second gate insulating layer 140b is then partially formed in the portion exposed through the fourth opening 119b. In this case, the second gate insulating layer 140b may include silicon oxide. However, embodiments are not limited thereto, and the second gate insulating layer 140b may be formed using various processes. The process for removing the fourth mask layer 118b may be performed using various etching processes (e.g., dry etching and/or wet etching). For example, the process for removing the fourth mask layer 118b may be performed using wet etching. However, the example is not limited to this and various modifications are possible.

As shown in FIG. 11, the first gate insulating layer 140a is removed from the third recess portion R3 where the connecting pattern 150 will be formed.

For example, a fifth mask layer 118c having a fifth opening 119c is formed on the first surface 111 of the substrate 110. The fifth opening 119c of the fifth mask layer 118c exposes a portion of the substrate 110 where the connecting pattern 150 is to be formed. The first gate insulating layer 140a located in the third recess portion R3 exposed by the fifth opening 119c is removed. After removing the first gate insulating layer 140a formed in the third recess portion R3, the fifth mask layer 118c is removed.

The fifth mask layer 118c may include various materials (e.g., photosensitive materials). The patterning process for forming the fifth opening 119c in the fifth mask layer 118c may be performed using various processes (e.g., photolithography). The process for removing the first gate insulating layer 140a exposed by the fifth opening 119c may be performed using an etching process (e.g., wet etching). The process for removing the fifth mask layer 118c may be performed using various etching processes (e.g., dry etching and/or wet etching). However, the embodiments are not limited thereto, and various modifications are possible.

Next, as shown in FIG. 12, a buried layer 132p is formed on the first surface 111 of the substrate 110. The buried layer 132p is formed on the first surface 111 of the substrate 110 while filling the first recess portion R1, the second recess portion R2, and the third recess portion R3.

The buried layer 132p includes a conductive or semiconductor material as a base material that constitutes a buried pattern (reference numeral 132 in FIG. 13; the same applies below) having a buried structure. For example, the buried layer 132p includes an undoped semiconductor material (e.g., an undoped polycrystalline semiconductor, e.g., undoped polycrystalline silicon). The buried layer 132p can be formed by various processes (e.g., deposition).

Next, as shown in FIG. 13, the buried layer located on the first surface 111 of the substrate 110 (portion designated by reference symbol 132p in FIG. 12) is removed to form a buried pattern 132. For example, a chemical mechanical polishing process is performed from the first surface 111 side of the substrate 110 to form buried patterns 132 inside the first recess portion (reference symbol R1 in FIG. 12; the same applies below), the second recess portion (reference symbol R2 in FIG. 12; the same applies below), and the third recess portion (reference symbol R3 in FIG. 12; the same applies below).

In this case, a buried pattern 132 constituting the first gate electrode 142g of the first transistor 142 is formed within the first recess R1, a buried pattern 132 constituting the second gate electrode 144g of the second transistor 144 is formed within the second recess R2, and a buried pattern 132 constituting the connecting pattern 150 is formed within the third recess R3. More specifically, the buried pattern 132 located on the first gate insulating layer 140a within the first recess R21 constitutes the second gate electrode 144g of the third transistor 146 (e.g., the select transistor 146b and/or the reset transistor 146a). The buried pattern 132 located on the second gate insulating layer 140b within the second recess R22 constitutes the second gate electrode 144g of the fourth transistor 148 (e.g., the source follower transistor 148a). The buried pattern 132 located inside the first connecting recess R31 constitutes the first connecting pattern 152, and the buried pattern 132 located inside the second connecting recess R32 constitutes the second connecting pattern 154.

At this time, due to the dishing phenomenon caused by the chemical mechanical polishing process, the surfaces of the multiple filled patterns 132 have recesses (reference symbols S1, S2, S3, and S4 in FIGS. 4 and 5). Furthermore, the surfaces of the multiple filled patterns 132 have the same surface characteristics. Furthermore, the corners of the multiple filled patterns 132 have rounded portions (reference symbol RP in FIG. 4). This indicates that the multiple filled patterns 132 (e.g., first gate electrode 142g, second gate electrode 144g, first connecting pattern 152, and/or second connecting pattern 154) were formed together through the same process (e.g., a single chemical mechanical polishing process).

Next, as shown in FIG. 14, the plurality of transistors 140 are doped with a second conductive type dopant. Thus, the first and second gate electrodes 142g and 144g of the plurality of transistors 140 are doped with the second conductive type dopant, and/or the active regions of the substrate 110 located on both sides of the second gate electrode 144g are doped with the second conductive type dopant to form source and drain regions.

More specifically, a sixth mask layer 118d having sixth openings 119d is formed on the first surface 111 of the substrate 110. The sixth openings 119d in the sixth mask layer 118d expose portions including the first and second gate electrodes 142g, 144g of the plurality of transistors 140. The portions exposed by the sixth openings 119d are doped with a second conductivity type dopant. After the doping process, the sixth mask layer 118d is removed.

The sixth mask layer 118d may include various materials (e.g., photosensitive materials). The patterning process for forming the sixth opening 119d in the sixth mask layer 118d may be performed by various processes (e.g., photolithography). The doping process may be performed by various processes (e.g., ion implantation process, etc.). The process for removing the sixth mask layer 118d may be performed by various etching processes (e.g., dry etching and/or wet etching). However, the embodiments are not limited thereto, and various modifications are possible.

In the above description, the source and drain regions of the second transistor 144 are formed by doping the first and second gate electrodes 142g, 144g of the plurality of transistors 140 with a second conductivity type dopant. However, the embodiment is not limited to this. The source and drain regions of the second transistor 144 may also be formed by a process different from the process of doping the first and second gate electrodes 142g, 144g of the plurality of transistors 140 with a second conductivity type dopant. Alternatively, the source and drain regions of the second transistor 144 may be formed through multiple doping processes.

Next, as shown in FIG. 15, the second connecting pattern 154 is doped with a second conductivity type dopant.

More specifically, a seventh mask layer 118e having a seventh opening 119e is formed on the first surface 111 of the substrate 110. The seventh opening 119e of the seventh mask layer 118e exposes the second connecting pattern 154. The second connecting pattern 154 exposed through the seventh opening 119e is doped with a second conductive dopant. In this embodiment, a second doped region DR2 is formed in a portion of the second connecting pattern 154 adjacent to the first surface 111 of the substrate 110, and a second undoped region UR2 is located below the second doped region DR2. After the doping process, the seventh mask layer 118e is removed.

The seventh mask layer 118e may include various materials (e.g., photosensitive materials). The patterning process for forming the seventh opening 119e in the seventh mask layer 118e may be performed by various processes (e.g., photolithography). The doping process may be performed by various processes (e.g., ion implantation process, etc.). The process for removing the seventh mask layer 118e may be performed by various etching processes (e.g., dry etching and/or wet etching). However, examples are not limited to these, and various modifications are possible.

Next, as shown in FIG. 16, the first connecting pattern 152 is doped with a first conductivity type dopant. A ground region 120g is then formed on the first surface 111 side of the substrate 110.

More specifically, an eighth mask layer 118f having an eighth opening 119f is formed on the first surface 111 of the substrate 110. The eighth opening 119f of the eighth mask layer 118f exposes the first connecting pattern 152 and/or an adjacent portion of the substrate 110. The first connecting pattern 152 exposed through the eighth opening 119f is doped with a first conductive dopant and/or the portion of the substrate 110 exposed through the eighth opening 119f is doped with a first conductive dopant to form the ground region 120g. In this embodiment, when the first connecting pattern 152 is doped with the first conductive dopant, a first doped region DR1 is formed in the portion of the substrate 110 adjacent to the first surface 111, and a first undoped region UR1 is located below the first doped region DR1. After the doping process, the eighth mask layer 118f is removed.

The eighth mask layer 118f may include various materials (e.g., photosensitive materials). The patterning process for forming the eighth opening 119f in the eighth mask layer 118f may be performed by various processes (e.g., photolithography). The doping process may be performed by various processes (e.g., ion implantation process, etc.). The process for removing the eighth mask layer 118f may be performed by various etching processes (e.g., dry etching and/or wet etching). However, examples are not limited to these, and various modifications are possible.

In the above description, the ground region 120g is formed by doping the first connecting pattern 152 with a first conductive type dopant. However, the embodiment is not limited to this. The ground region 120g may also be formed by a process different from the process of doping the first connecting pattern 152 with a first conductive type dopant. Alternatively, the ground region 120g may be formed through multiple doping processes.

In the embodiment, the doping process of the first and second gate electrodes 142g, 144g of the plurality of transistors 140, the doping process of the second connecting pattern 154, and the doping process of the first connecting pattern 152 are performed in this order. However, the embodiment is not limited to this, and the order of the doping process of the first and second gate electrodes 142g, 144g of the plurality of transistors 140, the doping process of the second connecting pattern 154, and the doping process of the first connecting pattern 152 may be changed in various ways.

Next, as shown in FIG. 17, a wiring portion 170 electrically connected to the pixel circuit 130 is formed on the first surface 111 of the substrate 110. Various processes can be used to form the wiring portion 170.

Next, as shown in FIG. 18, a portion of the substrate 110 where the preliminary surface of the substrate 110 (reference symbol 112p in FIG. 17, the same applies below) is located is removed. For example, a grinding process, polishing process, grinding process, etching process, etc. is performed on the preliminary surface 112p of the substrate 110, and a portion of the substrate 110 is removed up to the portion where the separation portion 126 is located. As an example, a portion of the substrate 110 is removed so that the separation portion 126 is located on the second surface 112 of the substrate 110.

An additional wiring portion 200 is formed on the first surface 111 of the substrate 110, and an optical receiving portion including a color filter 182, microlenses 188, etc. is formed on the second surface 112 of the substrate 110. Various processes can be used to form the additional wiring portion 200 and/or the optical receiving portion. The order of the process of forming the additional wiring portion 200 and the process of forming the optical receiving portion can be varied in various ways.

According to this embodiment, multiple buried patterns 132 having three or more structures, each with a gate insulating layer and/or varying thickness, can be formed through a simple process. This improves the productivity of image sensors 10 with excellent efficiency.

Figures 19 to 24 are cross-sectional views showing a method for manufacturing an image sensor according to another embodiment. Figures 19 to 24 show parts corresponding to Figure 2. Detailed descriptions of parts that are the same as or very similar to those described with reference to Figures 7 to 18 will be omitted, and only other parts will be described in detail.

As shown in FIG. 19, the element isolation region 124, isolation region 126, photoelectric conversion region 120, first recess region R1, second recess region R2, and third recess region R3 are formed in the substrate 110, and the first gate insulating layer 140a and/or second gate insulating layer 140b are formed. In this regard, the explanations for the processes shown in FIGS. 7 to 10 apply as is.

Next, as shown in FIG. 20, a doped buried layer 132q is formed on the first surface 111 of the substrate 110. The doped buried layer 132q is formed on the first surface 111 of the substrate 110 while filling the first recess portion R1, the second recess portion R2, and the third recess portion R3.

For example, doped buried layer 132q may include a doped semiconductor layer containing a doped semiconductor material (e.g., a doped polycrystalline semiconductor, such as doped polycrystalline silicon). The doped semiconductor layer may include a second conductivity type dopant and have the second conductivity type, although examples are not limited thereto. Doped buried layer 132q may be formed by various processes (e.g., deposition).

Next, as shown in FIG. 21, the doped buried layer 132q is removed from the portion corresponding to the third recess portion R3. This exposes the third recess portion R3.

For example, a fifth mask layer 118c having a fifth opening 119c on the doped buried layer 132q is formed on the first surface 111 of the substrate 110. The fifth opening 119c in the fifth mask layer 118c exposes a portion corresponding to the third recess R3. The portion of the doped buried layer 132q exposed through the fifth opening 119c is removed. After removing the doped buried layer 132q, the fifth mask layer 118c is removed.

Next, as shown in FIG. 22, the first gate insulating layer 140a located in the third recess portion R3 exposed to the outside after the doped buried layer 132q is removed is removed. The process of removing the first gate insulating layer 140a is performed by an etching process (e.g., wet etching). However, the embodiment is not limited to this and various modifications are possible.

As described above, after forming the doped buried layer 132q, the first gate insulating layer 140a formed in the third recess portion R3 is removed. During the process of removing the first gate insulating layer 140a, the doped buried layer 132q can protect the first gate insulating layer 140a or the second gate insulating layer 140b formed in the first recess portion R1 and the second recess portion R2. This allows the first gate insulating layer 140a or the second gate insulating layer 140b to have excellent characteristics, and the multiple transistors (reference numeral 140 in FIG. 24) to have excellent characteristics.

Next, as shown in FIG. 23, an undoped buried layer 132r is formed on the doped buried layer 132q. The undoped buried layer 132r is formed on the doped buried layer 132q while filling the third recess R3. This allows the formation of a buried layer 132p including the doped buried layer 132q and the undoped buried layers 132r and 132q.

For example, the undoped buried layer 132r includes an undoped semiconductor material (e.g., an undoped polycrystalline semiconductor, such as undoped polycrystalline silicon). The undoped buried layer 132q may be formed by various processes (e.g., deposition).

In one embodiment, where the first recess R1 and the second recess R2 are located, the interiors of the first recess R1 and the second recess R2 are filled with a doped buried layer 132q, and an undoped buried layer 132q is located thereon. Where the third recess R3 is located, the interior of the third recess R3 is filled with an undoped buried layer 132r.

Next, as shown in FIG. 24, a portion of the buried layer (reference symbol 132p in FIG. 23) located on the first surface 111 of the substrate 110 is removed to form a buried pattern 132. For example, a chemical mechanical polishing process is performed from the first surface 111 side of the substrate 110 to form buried patterns 132 inside the first recess portion (reference symbol R1 in FIG. 23; the same applies below), the second recess portion (reference symbol R2 in FIG. 23; the same applies below), and the third recess portion (reference symbol R3 in FIG. 23; the same applies below).

At this time, a buried pattern 132 constituting the first gate electrode 142g of the first transistor 142 is formed inside the first recess R1, a buried pattern 132 constituting the second gate electrode 144g of the second transistor 144 is formed inside the second recess R2, and a buried pattern 132 constituting the connecting pattern 150 is formed inside the third recess R3. The first gate electrode 142g and the second gate electrode 144g are formed from a doped buried layer (reference symbol 132q in FIG. 23), and the buried pattern 132 constituting the connecting pattern 150 is formed from an undoped buried layer (reference symbol 132r in FIG. 23).

Then, the second connecting pattern 154 is doped with a second conductive type dopant and/or the first connecting pattern 152 is doped with a first conductive type dopant. In this regard, the description with reference to FIGS. 15 and 16 applies accordingly.

Next, the wiring portion 170 is formed, and a portion of the substrate 110 where the spare surface 112p of the substrate 110 is located is removed to form the additional wiring portion 200 and the optical receiving portion. The explanations given with reference to Figures 17 and 18 apply accordingly.

According to this embodiment, a plurality of buried patterns 132 having three or more structures, each with a gate insulating layer and varying thicknesses, can be formed through a simple process. Furthermore, in the process of removing the first gate insulating layer 140a in the third recess portion R3 where the connecting pattern 150 is formed, the first gate insulating layer 140a and the second gate insulating layer 140b can be protected, maintaining excellent characteristics. This improves the productivity of the image sensor 10, which has excellent efficiency.

Hereinafter, an image sensor according to an embodiment different from the embodiment described above will be described in more detail with reference to Figure 25. Detailed descriptions of parts that are the same as or very similar to parts already described will be omitted, and only other parts will be described in detail.

Figure 25 is a plan view schematically illustrating a substrate of an image sensor according to yet another embodiment. Figure 25 shows the portion corresponding to Figure 3.

Referring to FIG. 25, in this embodiment, a plurality of buried patterns 132 or connecting patterns 150 include a wiring pattern 156 having an embedded structure embedded within the substrate 110. The wiring pattern 156 is formed by the same process as the first gate electrode 142g of the first transistor 142, the second gate electrode 144g of the second transistor 144, the first connecting pattern 152, and/or the second connecting pattern 154.

The wiring pattern 156 includes the same base material as the first gate electrode 142g of the first transistor 142, the second gate electrode 144g of the second transistor 144, the first connecting pattern 152, and/or the second connecting pattern 154. The surface of the wiring pattern 156 includes recesses having the same or similar shapes as the recesses formed on the surfaces of the first gate electrode 142g of the first transistor 142, the second gate electrode 144g of the second transistor 144, the first connecting pattern 152, and/or the second connecting pattern 154. The surface of the wiring pattern 156 has the same surface characteristics as the surfaces of the first gate electrode 142g of the first transistor 142, the second gate electrode 144g of the second transistor 144, the first connecting pattern 152, and/or the second connecting pattern 154. The corners of the wiring pattern 156 have rounded portions that are the same as or similar to the corners of the first gate electrode 142g of the first transistor 142, the second gate electrode 144g of the second transistor 144, the first connecting pattern 152, and/or the second connecting pattern 154.

For example, the wiring pattern 156 connects the second gate electrode 144g of the second transistor 144 (e.g., source follower transistor 148a) to the second connecting pattern 154 (e.g., first connecting portion 154a) in the first pixel region PX1 and/or the third pixel region PX3. This simplifies the structure of the wiring section and the image sensor manufacturing process, thereby improving the productivity of the image sensor.

In one embodiment, the wiring pattern 156 has the same second conductivity type as the second gate electrode 144g and/or the second connecting pattern 154. For example, the wiring pattern 156 is doped together with the doping process for doping the second gate electrode 144g, the doping process for forming the source and drain regions of the second transistor 144, and/or the doping process for doping the second connecting pattern 154 with a second conductivity type dopant. However, the embodiment is not limited to this, and various modifications are possible.

In FIG. 25, the wiring pattern 156 includes a first wiring portion connecting the source follower transistor 148a located in the first pixel region PX1 to the second connecting pattern 154, and a second wiring portion connecting the source follower transistor 148a located in the third pixel region PX3 to the second connecting pattern 154. However, the embodiment is not limited to this. As an example, the wiring pattern 156 may include one of the first wiring portion and the second wiring portion. As another example, the wiring pattern 156 may include wiring portions other than the first wiring portion and the second wiring portion. For example, the wiring pattern 156 may include wiring portions connecting various elements, members, units, components, etc. included in the image sensor.

Although the embodiments have been described in detail above, the technical scope of the present invention is not limited to these. Various modifications and improvements made by those skilled in the art using the basic concept of the present invention also fall within the technical scope of the present invention.

10: Image sensor 20: Logic circuit 30: Image signal processor 100: Photoelectric conversion substrate 110: Substrate 120: Photoelectric conversion section 130: Pixel circuit 170: Wiring section 200: Additional wiring section 110, 210: Substrate 120: Photoelectric conversion section 130: Pixel circuit 132: Embedded pattern

Claims (10)

a substrate having a first surface and a second surface opposite each other;
a plurality of pixel regions including a photoelectric conversion unit located on the substrate and a pixel circuit located adjacent to the first surface of the substrate;
Including,
the pixel circuit includes a plurality of embedded patterns having embedded structures embedded within the substrate;
the pixel circuit includes a first transistor including a first gate electrode of a vertical transfer gate electrode, and a second transistor including a second gate electrode having a cross-sectional shape different from that of the first gate electrode;
The plurality of buried patterns include the first gate electrode and the second gate electrode. the plurality of embedded patterns include the same base material;
a plurality of surfaces of the plurality of embedded patterns each having a recess having a concave shape including a portion located between the first surface of the substrate and the second surface of the substrate;
the surfaces of the embedded patterns have the same surface characteristics;
2. The image sensor according to claim 1, wherein each of the plurality of embedded patterns has a plurality of rounded corners. The image sensor of claim 1, wherein the second gate electrode has a depth-varying portion in an inner portion located between both side portions. the second transistor includes a third transistor including at least one of a reset transistor and a selection transistor, and a fourth transistor including a source follower transistor;
2. The image sensor of claim 1, wherein a thickness of the gate insulating layer of the first transistor or the third transistor is greater than a thickness of the gate insulating layer of the fourth transistor. a doping region including at least one of a floating diffusion region and a ground region is located on the first surface side of the substrate;
The image sensor of claim 1 , wherein the plurality of buried patterns include at least one of a first connecting pattern connected to the ground region and a second connecting pattern connected to the floating diffusion region. further comprising separation portions positioned to correspond to edges of the plurality of pixel regions;
the first or second connecting pattern is formed across at least two pixel regions among the plurality of pixel regions, and at least a portion of the first or second connecting pattern is located on the separation portion;
a wiring portion located on the first surface of the substrate and including a first contact via electrically connected to the pixel circuit;
Separation portions located to correspond to edges of the plurality of pixel regions;
further comprising
6. The image sensor of claim 5, wherein at least a portion of the first contact via is connected to the first or second connection pattern at a position overlapping the separation portion when viewed from above. the plurality of pixel regions include a first pixel region and a second pixel region adjacent to each other in a first direction, and a third pixel region and a fourth pixel region adjacent to the first pixel region and the second pixel region, respectively, in a second direction intersecting the first direction;
the first connecting pattern is formed across the first, second, third, and fourth pixel regions and is connected to the ground regions provided in the first, second, third, and fourth pixel regions, respectively;
6. The image sensor of claim 5, wherein the second connecting pattern includes a first connecting portion formed across the first and third pixel regions and connected to the floating diffusion regions provided in the first and third pixel regions, respectively, and a second connecting portion formed across the second and fourth pixel regions and connected to the floating diffusion regions provided in the second and fourth pixel regions, respectively. The image sensor of claim 1, wherein the plurality of buried patterns have a buried structure buried within the substrate and include a second connecting pattern connected to a floating diffusion region located adjacent to the first surface of the substrate, and a wiring pattern connecting the second gate electrode of the second transistor to the second connecting pattern. a substrate having a first surface and a second surface opposite each other;
a plurality of pixel regions including a photoelectric conversion unit located on the substrate and a pixel circuit located adjacent to the first surface of the substrate;
Including,
the pixel circuit includes a plurality of embedded patterns having embedded structures embedded within the substrate;
the pixel circuit includes a first transistor including a first gate electrode, a second transistor including a second gate electrode having a cross-sectional shape different from that of the first gate electrode, and a connection pattern including at least one of a doping connection pattern and a wiring pattern;
The plurality of buried patterns include the second gate electrode and the connecting pattern. a substrate having a first surface and a second surface opposite each other;
a plurality of pixel regions including a photoelectric conversion unit located on the substrate and a pixel circuit located adjacent to the first surface of the substrate;
Separation portions located to correspond to edges of the plurality of pixel regions;
Including,
the pixel circuit includes a doping connection pattern connected to the substrate or a doping region located in the substrate and having a buried structure buried within the substrate;
The image sensor, wherein the doped connection pattern is formed across at least two pixel regions among the plurality of pixel regions, and at least a portion of the doped connection pattern is located on the isolation portion.