JP2025010714A - Switch Circuit - Google Patents

Abstract

To suppress transmission delay at the time of turning off a circuit current and an output switching element.SOLUTION: A switch circuit (100) includes: an output switching element (M1); a driving voltage generation circuit (120) for generating a driving voltage (VBST) for tuning on the output switching element; a level shifter (LVS1) for generating a shifted control signal by shifting the level of an original control signal (CNT) using the driving voltage; and a driver circuit (130) for driving the output switching element based on the driving voltage, according to the shifted control signal. The level shifter includes a pull-up resistor (R1) and a transistor for shifting (M2) connected to the pull-up resistor in series, and generates the shifted control signal for turning off the output switching element by turning on the transistor for shifting to flow current through the pull-up resistor when the original control signal designates turning off of the output switching element.SELECTED DRAWING: Figure 8

Description

This disclosure relates to a switch circuit.

The switch circuit has an output switching element inserted between two nodes, and turns the output switching element on or off in response to a given control signal to establish or block conduction between the two nodes.

JP 2022-188429 A

[overview]
In a switch circuit, a drive signal for driving an output switching element is generated based on a control signal. It is required to shorten the propagation delay when the contents of the control signal are propagated to the drive signal. It is especially required to shorten the propagation delay when switching the output switching element from on to off. At the same time, it is also required to suppress the circuit current.

A switch circuit according to one aspect of the present disclosure includes an output switching element provided between a first node and a second node, a drive voltage generation circuit configured to generate a drive voltage for turning on the output switching element, a level shifter configured to generate a shift control signal by level-shifting an original control signal that specifies the state of the output switching element using the drive voltage, and a drive circuit configured to drive the output switching element according to the shift control signal based on the drive voltage, the level shifter having a pull-up resistor and a shift transistor connected in series to the pull-up resistor, and generating the shift control signal that turns off the output switching element by turning on the shift transistor and flowing a current through the pull-up resistor when the original control signal specifies that the output switching element is to be turned off.

FIG. 1 is a schematic configuration diagram of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is an external perspective view of the semiconductor device according to the embodiment of the present disclosure. FIG. 3 is a circuit diagram of an overvoltage detection circuit according to an embodiment of the present disclosure. FIG. 4 is a configuration diagram of a switch circuit according to a first reference example. FIG. 5 is a timing chart when an overvoltage abnormality occurs according to the first reference example. FIG. 6 is a configuration diagram of a switch circuit according to the second reference example. FIG. 7 is a configuration diagram of a switch circuit according to a third reference example. FIG. 8 is a configuration diagram of a switch circuit according to a first example of the embodiment of the present disclosure. FIG. 9 is a diagram showing an internal configuration of a driver for an output transistor according to a first example of the embodiment of the present disclosure. FIG. 10 is a configuration diagram of a switch circuit according to a second embodiment of the present disclosure. FIG. 11 is a partial configuration diagram of a semiconductor device related to an internal power supply circuit according to a second example of the embodiment of the present disclosure. FIG. 12 is a configuration diagram of a switch circuit according to a third embodiment of the present disclosure. FIG. 13 is a configuration diagram of a switch circuit according to a third embodiment of the present disclosure.

Detailed Description
Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.

First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as a metal. The potential of 0V is sometimes called the ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents the potential as seen from ground.

Level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal, when the signal is at a high level, the inverted signal of that signal is at a low level, and when the signal is at a low level, the inverted signal of that signal is at a high level.

For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Also, unless otherwise specified, the backgate of any MOSFET can be considered to be shorted to the source.

Hereinafter, the on and off states of any transistor may be simply referred to as on and off. Also, for any transistor, the period during which the transistor is in the on state will be referred to as the on period, and the period during which the transistor is in the off state will be referred to as the off period.

For any signal that has a high or low signal level, the period during which the signal is at a high level is called a high-level period, and the period during which the signal is at a low level is called a low-level period. The same applies to any voltage that has a high or low voltage level.

Unless otherwise specified, connections between multiple parts that form a circuit, such as any circuit elements, wiring, nodes, etc., can be understood to refer to electrical connections.

If any two voltages to be compared are voltages v1 and v2, then "v1>v2" indicates that voltage v1 is higher than voltage v2, and "v1<v2" indicates that voltage v1 is lower than voltage v2. The same applies to other equations that include physical quantities other than voltage.

1 is a schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure. FIG. 2 is an external perspective view of the semiconductor device 1. The semiconductor device 1 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and a plurality of external terminals exposed to the outside of the semiconductor device 1 from the housing CS. The semiconductor device 1 is formed by sealing the semiconductor chip in the housing CS made of resin. Note that the number of external terminals of the semiconductor device 1 and the type of the housing CS of the semiconductor device 1 shown in FIG. 2 are merely examples, and can be designed arbitrarily. In FIG. 1, an input terminal IN, an output terminal OUT, a ground terminal GND, and an enable terminal EN are shown as some or all of the external terminals provided in the semiconductor device 1. Other external terminals may also be provided in the semiconductor device 1.

The wiring provided outside the semiconductor device 1 is specifically referred to as external wiring, and the wiring provided inside the semiconductor device 1 is specifically referred to as internal wiring.

An input voltage V _IN is supplied to an input terminal IN through an external wiring from a voltage source VS provided outside the semiconductor device 1. The input voltage V _IN has a positive voltage value. An output capacitor C _OUT is provided outside the semiconductor device 1. A first end of the output capacitor C _OUT is connected to the output terminal OUT, and a second end of the output capacitor C _OUT is connected to ground. The voltage at the output terminal OUT is called an output voltage V _OUT . Therefore, the output voltage V _OUT is applied across both ends of the output capacitor C _OUT . Note that the semiconductor device 1 may be provided with two or more external terminals functioning as the input terminal IN. The semiconductor device 1 may be provided with three or more external terminals functioning as the output terminal OUT. The ground terminal GND is connected to ground.

The semiconductor device 1 mainly includes a switch circuit 10, an internal power supply circuit 20, and a protection circuit 30. An enable signal _{S_EN} is supplied to an enable terminal EN from an external circuit (not shown) of the semiconductor device 1. The enable signal _{S_EN} is input to the switch circuit 10.

The switch circuit 10 establishes or breaks conduction between the input terminal IN and the output terminal OUT in response to an enable signal S _EN . When the input terminal IN and the output terminal OUT are connected to each other, in a steady state, an output voltage V _OUT having substantially the same voltage value as the input voltage _VIN is generated at the output terminal OUT, and the output voltage V _OUT is supplied to an arbitrary load (not shown) connected to the output terminal OUT. After establishing conduction between the input terminal IN and the output terminal OUT, if the input terminal IN and the output terminal OUT are cut off from each other, the output voltage V _OUT drops toward 0V.

The internal power supply circuit 20 generates one or more internal power supply voltages based on an input voltage _VIN supplied to an input terminal IN. The protection circuit 30 detects various abnormalities that may occur in the semiconductor device 1. The detection results of the protection circuit 30 are transmitted to the switch circuit 10. The switch circuit 10 and the protection circuit 30 are driven using any of the internal power supply voltages generated by the internal power supply circuit 20.

In this way, the semiconductor device 1 functions as a switch device for establishing or breaking electrical continuity between the input terminal IN and the output terminal OUT. The semiconductor device 1 may be a device classified as an electronic fuse, or may be a high-side switch device inserted into any power supply bus. The semiconductor device 1 may be used in applications where hot swapping (live insertion and removal) is anticipated. Here, attention is focused on one switch circuit 10, but multiple switch circuits 10 may be provided within the semiconductor device 1.

The enable signal _{S_EN} has a value of "1" or "0". When the enable signal _{S_EN} has a value of "0", the switch circuit 10 cuts off the connection between the input terminal IN and the output terminal OUT. When the enable signal _{S_EN} has a value of "1", the switch circuit 10, in principle, brings the input terminal IN and the output terminal OUT into conduction. Even when the enable signal _{S_EN} has a value of "1", if a specific abnormality is detected by the protection circuit 30, the switch circuit 10 cuts off the connection between the input terminal IN and the output terminal OUT.

An example of the specific abnormality is an overvoltage abnormality. An overvoltage abnormality refers to a state in which the input voltage V _IN is excessively high. FIG. 3 shows the configuration of an overvoltage detection circuit 31 capable of detecting an overvoltage abnormality. The overvoltage detection circuit 31 can be provided in the protection circuit 30. The overvoltage detection circuit 31 includes resistors 31a and 31b and a comparator 31c. A first end of the resistor 31a is connected to the input terminal IN and receives the input voltage V _IN . A second end of the resistor 31a and a first end of the resistor 31b are connected to each other. A second end of the resistor 31b is connected to the reference potential end. The voltage at the reference potential end is the voltage VSS. The reference potential end is connected to the ground terminal GND. Therefore, the reference potential end is equivalent to the ground and has a voltage of 0V. A voltage V _DIV, which is a divided voltage of the input voltage V _IN, is generated at the connection node between the resistors 31a and 31b.

A voltage V _DIV is input to a non-inverting input terminal of the comparator 31c, and a predetermined judgment reference voltage V _OVP is input to an inverting input terminal of the comparator 31c. A reference voltage generating circuit provided in the semiconductor device 1 generates the judgment reference voltage V _OVP from the input voltage V _IN or the internal power supply voltage. The comparator 31c compares the voltage V _DIV with the judgment reference voltage V _OVP , and generates and outputs an overvoltage detection signal S _OVP according to the comparison result. The overvoltage detection signal S _OVP has a value of "1" or "0". Here, it is assumed that a high-level overvoltage detection signal S _OVP has a value of "1", and a low-level overvoltage detection signal S _OVP has a value of "0".

A hysteresis characteristic is applied in the comparison by the comparator 31c. The initial value of the overvoltage detection signal S _OVP is "0". When the overvoltage detection signal S _OVP starts from a state having a value of "0" and transitions from a state where "V _DIV < V _OVP " is satisfied to a state where "V _DIV > V _OVP " is satisfied, the comparator 31c switches the value of the overvoltage detection signal S _OVP from "0" to "1". After that, the comparator 31c maintains the value of the overvoltage detection signal S _OVP at "1" until "V _DIV < (V _OVP - ΔV _HYS )" is satisfied, and when "V _DIV < (V _OVP - ΔV _HYS )" is satisfied, the comparator 31c switches the value of the overvoltage detection signal S _OVP from "1" to "0". ΔV _HYS is a voltage amount representing a hysteresis width and has a predetermined positive voltage value. As a variant, ΔV _HYS may be 0. An overvoltage detection signal S _OVP of "1" indicates that an overvoltage abnormality has been detected, and an overvoltage detection signal S _OVP of "0" does not indicate that an overvoltage abnormality has been detected.

The overvoltage detection signal _SOVP is input to the switch circuit 10. When the value of the overvoltage detection signal _SOVP is "0", the operation of the switch circuit 10 is as per the principle. When the overvoltage detection signal _SOVP of "1" is output from the comparator 31c, the switch circuit 10 immediately cuts off the connection between the input terminal IN and the output terminal OUT even if the enable signal _SEN has a value of "1", and thereafter continues to cut off the connection between the input terminal IN and the output terminal OUT until a predetermined reset condition is satisfied. For example, the reset condition is satisfied only when the value of the overvoltage detection signal _SOVP returns from "1" to "0". Alternatively, the reset condition may be satisfied by changing the value of the enable signal _SEN from "1" to "0" and then changing the value of the enable signal _SEN back to "1". In addition to the above, the reset condition is arbitrary.

The specific abnormality described above is not limited to an overvoltage abnormality. For example, an overcurrent abnormality in which the current flowing between the input terminal IN and the output terminal OUT becomes excessively large may also be included as a specific abnormality. In addition, for example, a high temperature abnormality in which the temperature at the temperature detection position in the semiconductor device 1 rises above a predetermined temperature may also be included as a specific abnormality. However, in the following, we will focus on an overvoltage abnormality as a specific abnormality.

<<First Reference Example>>
4 shows a switch circuit 910 according to a first reference example. In the switch circuit 910, a charge pump circuit 911 is used to generate a drive voltage Vbst for turning on an output transistor m1, and a driver 912 drives the output transistor m1 using the drive voltage Vbst in accordance with a control signal CNT corresponding to an enable signal _SEN .

5 shows a timing chart when an overvoltage abnormality occurs according to the first reference example. Starting from a state in which the output transistor m1 is controlled to be on by the high-level control signal CNT, when an overvoltage abnormality is detected (when "V _IN >Vovp_th"), the control signal CNT is transitioned from high to low. By transmitting the transition of the control signal CNT to low to the driver 912 via the level shifter 913, the gate voltage Vg of the output transistor m1 is lowered, thereby turning off the output transistor m1. In the process of lowering the gate voltage Vg, the state of the output transistor m1 is switched to off at the point in time when the voltage (Vg-V _OUT ) falls below the gate threshold voltage Vth of the output transistor m1.

Since the input voltage _VIN is supplied to the input terminal IN through a cable or the like, the input voltage _VIN may rise sharply due to the inductance of the cable, etc. For this reason, the operation from when an overvoltage abnormality is detected to when the output transistor m1 is turned off must be performed in a short time.

<<Second Reference Example>>
Fig. 6 shows a switch circuit 920 according to a second reference example. The switch circuit 920 in Fig. 6 is an example of the switch circuit 910 in Fig. 4. A charge pump circuit 921, a driver 922, and a level shifter 923 in Fig. 6 correspond to the charge pump circuit 911, the driver 912, and the level shifter 913 in Fig. 4. However, the driver 922 in Fig. 6 is an inverter circuit.

In the switch circuit 920, a level shifter 923 has a series circuit of a pull-up resistor 924 and a shifting transistor 925. The level shifter 923 shifts the level of the control signal CNT. A voltage v1 at a connection node between the pull-up resistor 924 and the shifting transistor 925 is the control signal after the level shift. The driver 922 sets the gate voltage Vg to the level of the drive voltage Vbst or the level of the output voltage _VOUT in accordance with the level-shifted control signal (v1), thereby setting the output transistor m1 on or off.

During the high-level period of the control signal CNT, the level shifter 923 turns on the shift transistor 925 to pass a current through the pull-up resistor 924, and the control signal (v1) after the level shift is set to a low level. In response to this, the driver 922 supplies a high-level gate Vg to the output transistor m1, turning the output transistor m1 on. Conversely, during the low-level period of the control signal CNT, a low-level gate Vg is supplied to the output transistor m1 through the off-state of the shift transistor 925, and the output transistor m1 is turned off. In the switch circuit 920, a circuit current (current flowing through the resistor 924 and the shift transistor 925) is generated during the on-state of the output transistor m1, but this circuit current is not generated during the off-state of the output transistor m1, so that power consumption during standby can be suppressed.

Consider a situation in which the control signal CNT transitions from high to low in the switch circuit 920. When the control signal CNT transitions from high to low, the shift transistor 925 is switched from on to off, causing the voltage v1 to rise. The faster the rate at which the voltage v1 rises at this time, the quicker the output transistor m1 can be switched from on to off. In other words, when focusing on an overvoltage anomaly, the faster the rate at which the voltage v1 rises, the shorter the time required to turn off the output transistor m1 after the overvoltage anomaly is detected, and therefore it is required to increase the rate at which the voltage v1 rises.

Here, the rate of rise of voltage v1 is determined by pull-up resistor 924 and the parasitic capacitance added to the node where voltage v1 is generated. For this reason, in order to increase the rate of rise of voltage v1, it is necessary to set the value of pull-up resistor 924 small. However, if the value of pull-up resistor 924 is reduced, a large current flows through pull-up resistor 924 during the on-period of output transistor m1, and this necessitates an increase in the current capacity of charge pump circuit 921. This not only leads to an increase in the circuit current, but also leads to an increase in the size of the flying capacitor used in charge pump circuit 921, resulting in an increase in the circuit area. There is a demand for technology that can reduce the time it takes to switch the output transistor from on to off while suppressing the circuit current.

<<Third Reference Example>>
FIG. 7 shows a switch circuit 930 according to a third reference example. The switch circuit 930 in FIG. 7 is an example of the switch circuit 910 in FIG. 4. A charge pump circuit 931, a driver 932, and a level shifter 933 in FIG. 7 correspond to the charge pump circuit 911, the driver 912, and the level shifter 913 in FIG. 4. The level shifter 933 in FIG. 7 is formed of four P-channel MOSFET transistors P1 to P4, two N-channel MOSFET transistors N1 and N2, and two resistors r1 and r2, and generates a voltage v1 by level-shifting the control signal CNT. Using the level shifter 933 makes it possible to suppress the circuit current and reduce the propagation delay.

However, the configuration of the level shifter 933 is complicated, and a high power supply voltage is required to properly operate the level shifter 933. To briefly explain this with focus on the transistors P2 and P3, the output voltage _VOUT is applied to the gate of the transistor P2, the source of the transistor P2 is connected to the gate of the transistor P3, and the drive voltage Vbst is applied to the source of the transistor P3. Therefore, in order to properly operate the level shifter 933, it is necessary to increase the drive voltage Vbst higher than the output voltage _VOUT by the sum (2×Vth) of the gate threshold voltage of the transistor P2 and the gate threshold voltage of the transistor P3 (first necessity).

On the other hand, a current limiting operation that limits the current flowing through the output transistor m1 or a soft start operation that gradually increases the output voltage V _OUT is often required for the switch circuit 930. When performing these operations, it is necessary to control the differential voltage (Vg-V _OUT ) to be close to the gate threshold voltage Vth of the output transistor m1 (second necessity). Basically, since the high-level gate voltage Vg has a potential equivalent to the drive voltage Vbst, it is difficult to simultaneously satisfy the first and second requirements. In other words, it is difficult to apply the level shifter 933 to a switch circuit that should meet the above requirements. Below, several embodiments that take these circumstances into consideration are shown.

<<First Example>>
A first embodiment will be described. FIG. 8 shows the configuration of a switch circuit 100 according to the first embodiment. The switch circuit 100 can be used as the switch circuit 10 in FIG. 1. The switch circuit 100 includes an output transistor M1, which is an output switching element, a shift transistor M2, a control circuit 110, a charge pump circuit 120, a driver 130, which is an output driver (drive circuit), a driver 140, which is a level shift driver, a capacitor C1, and a pull-up resistor R1. The transistors M1 and M2 are N-channel MOSFETs. The shift transistor M2, the driver 140, and the pull-up resistor R1 form a level shifter LVS1.

The node ND1 is connected to the input terminal IN. Therefore, the voltage at the node ND1 is the input voltage V _IN . The node ND2 is connected to the output terminal OUT. Therefore, the voltage at the node ND2 is the output voltage V _OUT . The nodes ND1 and ND2 may be interpreted as the input terminal IN and the output terminal OUT themselves, respectively. The output transistor M1 is provided between the nodes ND1 and ND2. Specifically, the drain of the output transistor M1 is connected to the node ND1 and receives the input voltage V _IN . The source of the output transistor M1 is connected to the node ND2. Therefore, when the output transistor M1 is on, the input terminal IN and the output terminal OUT are electrically connected, and when the output transistor M1 is off, the input terminal IN and the output terminal OUT are electrically disconnected.

The wires WR1 to WR3 are internal wires. The voltage on the wire WR1 is the drive voltage V _BST . The wire WR2 is connected to the node ND2. Therefore, the voltage on the wire WR2 is the output voltage V _OUT . The wire WR3 is connected to the gate of the output transistor M1. The voltage on the wire WR3 is the gate voltage _VG of the output transistor M1, which corresponds to the drive signal for driving the output transistor M1. The capacitor C1 is inserted between the wires WR1 and WR2. That is, the first end of the capacitor C1 is connected to the wire WR1, and the second end of the capacitor C1 is connected to the wire WR2.

The first end of the pull-up resistor R1 is connected to the wiring WR1, and the second end of the pull-up resistor R1 is connected to a node ND3. The voltage at the node ND3 is referred to as voltage V1. The shift transistor M2 is connected in series to the pull-up resistor R1. The shift transistor M2 is inserted between the pull-up resistor R1 and the reference potential end. As described above, the voltage at the reference potential end is voltage VSS, which here coincides with the ground voltage. Specifically, the drain of the shift transistor M2 is connected to the node ND3. Although a resistor can be inserted between the source of the shift transistor M2 and the reference potential end, here, the source of the shift transistor M2 is directly connected to the reference potential end.

The control circuit 110 is a logic circuit that operates with the internal power supply voltage VDD as a positive power supply voltage and the voltage VSS as a negative power supply voltage. The internal power supply voltage VDD is one of the internal power supply voltages generated by the internal power supply circuit 20, and has a positive DC voltage value. An enable signal _{S_EN} and an overvoltage detection signal _{S_OVP} are input to the control circuit 110. The control circuit 110 outputs a control signal CNT according to the enable signal _{S_EN} and the overvoltage detection signal _{S_OVP} .

When the overvoltage detection signal _SOVP has a value of "0", the control circuit 110 outputs a high level control signal CNT when the enable signal _SEN has a value of "1", and outputs a low level control signal CNT when the enable signal _SEN has a value of "0". When the overvoltage detection signal _SOVP of "1" is input to the control circuit 110, the control circuit 110 sets the level of the control signal CNT to a low level regardless of the value of the enable signal _SEN , and thereafter holds the level of the control signal CNT at a low level until a reset condition is established.

The control signal CNT is a signal (original control signal) that specifies the state of the output transistor M1. A high-level control signal CNT specifies that the output transistor M1 is to be set to an on state, and a low-level control signal CNT specifies that the output transistor M1 is to be set to an off state. Thus, the high-level period of the control signal CNT corresponds to an on-designation period that specifies that the output transistor M1 is on, and the low-level period of the control signal CNT corresponds to an off-designation period that specifies that the output transistor M1 is off. A high-level control signal CNT has substantially the potential of the internal power supply voltage VDD, and a low-level control signal CNT has substantially the ground potential (the potential of the voltage VSS).

The charge pump circuit 120 is an example of a drive voltage generating circuit that operates or does not operate according to a control signal CNT from the control circuit 110. The control signal CNT is input to the charge pump circuit 120. During the high level period of the control signal CNT, the charge pump circuit 120 is in an operating state and generates a drive voltage V _BST for turning on the output transistor M1 at the wiring WR1. The charge pump circuit 120 is composed of a combination of an oscillation circuit, a capacitor, and a diode. In the operating state of the charge pump circuit 120, the charge pump circuit 120 supplies charges to the wiring WR1 by a charge pump operation using the oscillation operation of the oscillation circuit, thereby increasing the potential of the wiring WR1 based on the potential of the wiring WR2. As a result, during the high level period of the control signal CNT, a voltage higher than the voltage (V _OUT ) of the node ND2 is generated as the drive voltage V _BST at the wiring WR1. During the low level period of the control signal CNT, the charge pump circuit 120 stops. The charge pump circuit 120 being stopped means that the charge pump circuit 120 is in a stopped state. In the stopped state of the charge pump circuit 120, the oscillation operation of the oscillation circuit is not performed, and the charge pump circuit 120 does not supply electric charge to the wiring WR1.

The driver 130 is connected to the wirings WR1 to WR3 and also to the node ND3. A drive voltage V _BST and an output voltage V _OUT (in other words, the source voltage of the output transistor M1) are supplied to the driver 130. The driver 130 is a buffer circuit that drives the drive voltage V _BST on the wiring WR1 as a positive power supply voltage and the output voltage V _OUT on the wiring WR2 as a negative power supply voltage. The driver 130 supplies a gate voltage V _G corresponding to the voltage V1 of the node ND3 to the gate of the output transistor M1 through the wiring WR3, thereby driving the output transistor M1 (in other words, driving the gate of the output transistor M1). The output transistor M1 is turned on or off by driving the output transistor M1.

The driver 140 is an inverter circuit that drives the internal power supply voltage VDD1 as a positive power supply voltage and the voltage VSS as a negative power supply voltage. The internal power supply voltage VDD1 is one of the internal power supply voltages generated by the internal power supply circuit 20, and has a positive DC voltage value. The internal power supply voltage VDD1 for the driver 140 and the internal power supply voltage VDD for the control circuit 110 may be a common voltage or may be different voltages. A control signal CNT from the control circuit 110 is input to the input terminal of the driver 140. The output terminal of the driver 140 is connected to the gate of the shift transistor M2. The driver 140 supplies an inverted signal of the control signal CNT to the gate of the shift transistor M2. That is, the driver 140 supplies a low-level gate signal to the gate of the shift transistor M2 during the high-level period of the control signal CNT, and supplies a high-level gate signal during the low-level period of the control signal CNT.

The high-level gate signal to the gate of the shift transistor M2 has substantially the potential of the internal power supply voltage VDD1, and the shift transistor M2 is turned on when it receives a high-level gate signal from the driver 140. The low-level gate signal to the gate of the shift transistor M2 has substantially the potential of the voltage VSS, and the shift transistor M2 is turned off when it receives a low-level gate signal from the driver 140.

When the shift transistor M2 is off, the voltage V1 of the node ND3 is equal to the drive voltage V _BST . When the shift transistor M2 is on, a current flows through the pull-up resistor R1, so that the voltage V1 of the node ND3 becomes sufficiently lower than the drive voltage V _{BST, and is substantially 0 V in the configuration of FIG. 8. The level shifter LVS1 generates a shift control signal by level-shifting the control signal CNT using the drive voltage V BST .} The voltage V1 is the voltage of the shift control signal. The shift control signal has a high level or a low level. When the shift transistor M2 is off, the shift control signal has a high level, and when the shift transistor M2 is on, the shift control signal has a low level. For example, when "V1>V _OUT +(V _BST -V _OUT )/2" is satisfied, the shift control signal has a high level, and when "V1<V _OUT +(V _BST -V _OUT )/2" is satisfied, the shift control signal has a low level.

When the shift control signal is at a high level, the driver 130 sets the output transistor M1 to an on state by supplying a high level gate voltage V _G to the gate of the output transistor M1. The high level gate voltage V _G is a voltage based on the drive voltage V _BST , and has a substantial level of the drive voltage V _BST , and may be slightly lower than the drive voltage V _BST . The charge pump circuit 120 is configured such that the difference voltage (V _BST -V _OUT ) is greater than the gate threshold voltage of the output transistor M1 when the charge pump circuit 120 is in an operating state.

When the shift control signal is at a low level, the driver 130 sets the output transistor M1 to an off state by supplying a low-level gate voltage V _G to the gate of the output transistor M1. The low-level gate voltage V _G is a voltage based on the output voltage V _OUT (i.e., a voltage based on the source voltage of the output transistor M1) and has a substantial level of the output voltage V _OUT , and may be slightly higher than the output voltage V _OUT . When the low-level gate voltage V _G is supplied to the output transistor M1, the gate-source voltage of the output transistor M1 is smaller than the gate threshold voltage of the output transistor M1.

As can be understood from the above description, the switch circuit 100 controls the output transistor M1 to be turned off when the control signal CNT has a low level, and to be turned on when the control signal CNT has a high level.

Here, the switch circuit 920 in Fig. 6 is compared with the switch circuit 100 in Fig. 8. In the switch circuit 920 in Fig. 6, when the control signal CNT has a high level, that is, when the output transistor (m1) is turned on, the shift transistor (925) is turned on to allow a current to flow through the pull-up resistor (924). In contrast, in the switch circuit 100 in Fig. 8, when the control signal CNT has a low level, that is, when the output transistor (M1) is turned off, the shift transistor (M2) is turned on to allow a current to flow through the pull-up resistor (R1). Therefore, in the switch circuit 100, when the output transistor M1 is switched from on to off, the voltage V1 is lowered by utilizing the on of the shift transistor M2, so that the rate at which the voltage V1 drops is increased. That is, in the switch circuit 100, the propagation delay from when the control signal CNT switches from high level to low level until the gate voltage _VG of the output transistor M1 switches from high level to low level is shortened, and the output transistor M1 can be quickly turned off when an overvoltage is detected, for example.

On the other hand, when the output transistor M1 is switched from off to on, the shift transistor M2 is switched from on to off, and the parasitic capacitance added to the node ND3 is charged via the pull-up resistor R1, thereby raising the voltage V1 to a high level. Therefore, the propagation delay when the output transistor M1 is turned on (the propagation delay from when the control signal CNT is switched from low to high to when the gate voltage _VG of the output transistor M1 is switched from low to high) is relatively long. However, even if the propagation delay when the output transistor M1 is turned on is somewhat long, it does not cause any problems in terms of application.

In addition, during the on-period of the output transistor M1, except during a transient response, no current flows through the pull-up resistor R1 and the shift transistor M2, so the charge pump circuit 120 only needs to have the current capacity necessary to turn on the output transistor M1. This allows the element size of the charge pump circuit 120 to be reduced.

As a trade-off, when the control signal CNT is at a low level, a current is generated through the pull-up resistor R1 and the shift transistor M2. However, the generation of this current does not lead to an increase in the current capacity of the charge pump circuit 120. This is because the operation of the charge pump circuit 120 is stopped in the first place during the low level period of the control signal CNT. When the control signal CNT switches from a high level to a low level, the charge of the wiring WR1 is pulled out through the pull-up resistor R1 and the shift transistor M2, and when the drive voltage _VBST drops to its lowest point, the circuit current becomes zero, so no problem occurs.

In the process of decreasing the drive voltage _VBST in response to the switching of the control signal CNT from high level to low level, the charge in the wiring WR2 flows through the parasitic diode in the driver 130 toward the wiring WR1 (see FIG. 9) and is discharged through the pull-up resistor R1 and the shift transistor M2, so that the output voltage _VOUT also decreases toward 0 V. FIG. 9 shows a part of the internal configuration of the driver 130. The driver 130 has an output stage consisting of transistors 131 and 132. The transistor 131 is a P-channel MOSFET, and the transistor 132 is an N-channel MOSFET. The parasitic diode in the driver 130 mentioned above refers to the parasitic diodes of the transistors 131 and 132.

The source of the transistor 131 is connected to the wiring WR1, the drains of the transistors 131 and 132 are connected to the wiring WR3, and the source of the transistor 132 is connected to the wiring WR2. In the driver 130 in Fig. 9, during a high-level period of the shift control signal, the transistor 131 is controlled to be on and the transistor 132 is controlled to be off, thereby supplying the drive voltage V _BST to the wiring WR3, and during a low-level period of the shift control signal, the transistor 131 is controlled to be off and the transistor 132 is controlled to be on, thereby supplying the output voltage V _OUT to the wiring WR3. A parasitic diode having a forward direction from the drain to the source is added to the transistor 131. A parasitic diode having a forward direction from the source to the drain is added to the transistor 132.

<<Second Example>>
The second embodiment will be described. The second embodiment and the third and fourth embodiments described below are based on the first embodiment, and for matters not specifically mentioned in the second to fourth embodiments, the description of the first embodiment also applies to the second to fourth embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence over any matters that contradict between the first and second embodiments (the same applies to the third and fourth embodiments described below). As long as there is no contradiction, any combination of the first to fourth embodiments may be used.

Figure 10 shows the configuration of a switch circuit 200 according to the second embodiment. The switch circuit 200 can be used as the switch circuit 10 in Figure 1. The switch circuit 200 differs from the switch circuit 100 in Figure 8 in that a driver 141 and a shift transistor M3 are added to the switch circuit 100, and except for this addition and unless otherwise noted, has the same configuration as the switch circuit 100. In the switch circuit 200, the shift transistors M2 and M3, the drivers 140 and 141, and the pull-up resistor R1 form a level shifter LVS2. The transistor M3 is an N-channel MOSFET. The configuration and operation of the switch circuit 200 will be described, focusing on the differences from the switch circuit 100.

The shift transistor M3 is connected in series to the pull-up resistor R1, similar to the shift transistor M2. Specifically, in the switch circuit 200, the drains of the shift transistors M2 and M3 are connected to the node ND3. A resistor may be inserted between the source of the shift transistor M2 and the reference potential end, but here, the source of the shift transistor M2 is directly connected to the reference potential end. A resistor may be inserted between the source of the shift transistor M3 and the reference potential end, but here, the source of the shift transistor M3 is directly connected to the reference potential end.

The driver 141 is an inverter circuit that drives the internal power supply voltage VDD2 as the positive power supply voltage and the voltage VSS as the negative power supply voltage. The control signal CNT from the control circuit 110 is input to the input terminal of the driver 141. The output terminal of the driver 141 is connected to the gate of the shift transistor M3. The driver 141 supplies an inverted signal of the control signal CNT to the gate of the shift transistor M3. That is, the driver 141 supplies a low-level gate signal to the gate of the shift transistor M3 during the high-level period of the control signal CNT, and supplies a high-level gate signal during the low-level period of the control signal CNT.

The high-level gate signal to the gate of the shift transistor M3 has substantially the potential of the internal power supply voltage VDD2, and the shift transistor M3 is turned on when it receives a high-level gate signal from the driver 141. The low-level gate signal to the gate of the shift transistor M3 has substantially the potential of the voltage VSS, and the shift transistor M3 is turned off when it receives a low-level gate signal from the driver 141.

When both the shift transistors M2 and M3 are off, the voltage V1 of the node ND3 is equal to the drive voltage _{V_BST} . When at least one of the shift transistors M2 and M3 is on, a current flows through the pull-up resistor R1 and the on-state shift transistor, so that the voltage V1 of the node ND3 becomes sufficiently lower than the drive voltage _{V_BST} , and is substantially 0 V in the configuration of FIG. 10. The level shifter LVS2 generates a shift control signal by level-shifting the control signal CNT using the drive voltage _{V_BST} . The voltage V1 is the voltage of the shift control signal. The shift control signal has a high level or a low level. When both the shift transistors M2 and M3 are off, the shift control signal has a high level, and when at least one of the shift transistors M2 and M3 is on, the shift control signal has a low level.

In the switch circuit (100, 200) according to the first or second embodiment, a method is adopted in which the output transistor M1 is turned on when the shift transistors (M2, M3) are off, so that when the power supply of the driver constituting the level shifter is completely lost, the output transistor M1 is fixed in the on state. This is not preferable for the load connected to the output terminal OUT. In the switch circuit 100 according to the first embodiment (see FIG. 8), there is no problem if the internal power supply voltage VDD1 is always generated normally when the input voltage _VIN is equal to or higher than a certain voltage. However, when a relatively high current capacity is required, a capacitor may be externally connected to the semiconductor device 1, and care must be taken in this case. In the second embodiment, it is assumed that an external capacitor is assigned to the internal power supply voltage VDD1.

Fig. 11 shows a partial configuration of the semiconductor device 1 related to the internal power supply circuit 20. The internal power supply circuit 20 according to the second embodiment generates internal power supply voltages VDD, VDD1, and VDD2 based on an input voltage _VIN . In Fig. 11, the internal power supply voltages VDD, VDD1, and VDD2 are shown separately, but the internal power supply voltage VDD and the internal power supply voltage VDD1 may be a common voltage. It is also possible to make the internal power supply voltage VDD and the internal power supply voltage VDD2 a common voltage. The internal power supply voltage VDD may be generated separately from the internal power supply voltages VDD1 and VDD2.

The terminal REG is one of the external terminals in the semiconductor device 1. The terminal REG is provided in the semiconductor device 1 (in other words, provided in the housing CS of the semiconductor device 1) and is a metal terminal exposed from the housing CS of the semiconductor device 1 to the outside of the semiconductor device 1. The internal power supply circuit 20 is connected to the terminal REG and outputs the internal power supply voltage VDD1 to the terminal REG. The terminal REG is connected to a first end of the capacitor C _REG through an external wiring, and the second end of the capacitor C _REG is connected to the ground. The capacitor C _REG accumulates a charge corresponding to the internal power supply voltage VDD1, so that the internal power supply voltage VDD1 can be used as a power supply having a high current capacity. On the other hand, the internal power supply voltage VDD2 is not output to the outside of the semiconductor device 1. That is, the semiconductor device 1 does not have an external terminal to which the internal power supply voltage VDD2 is applied. The current capacity of the internal power supply voltage VDD2 is smaller than the current capacity of the internal power supply voltage VDD1.

When the input voltage _VIN is equal to or higher than a predetermined lower limit voltage, the internal power supply circuit 20 generates the internal power supply voltages VDD1 and VDD2. In the case where the internal power supply voltage VDD is generated separately from the internal power supply voltages VDD1 and VDD2, when the input voltage _VIN is equal to or higher than a predetermined lower limit voltage, the internal power supply voltage VDD is also generated.

When the input voltage _VIN is equal to or higher than a predetermined lower limit voltage and no short circuit abnormality, which will be described later, occurs, the internal power supply voltage VDD1 has a predetermined positive DC voltage value VAL1. When the input voltage _VIN is equal to or higher than a predetermined lower limit voltage, the internal power supply voltage VDD2 always has a predetermined positive DC voltage value VAL2, regardless of whether or not a short circuit abnormality, which will be described later, occurs. The DC voltage values VAL1 and VAL2 basically match each other, but may differ from each other.

The above-mentioned short circuit abnormality refers to a state in which the terminal REG is short-circuited to ground. A short circuit abnormality can occur due to unnecessary solder or the like that may be present on the board on which the semiconductor device 1 is mounted. When a short circuit abnormality occurs, the internal power supply voltage VDD1 becomes 0 V regardless of the magnitude of the input voltage _VIN , and therefore the shift transistor M2 is fixed in the off state. However, the driver 141 operates without being affected by the short circuit abnormality, and therefore the shift transistor M3 can be controlled to be on.

The driver 140, which uses the internal power supply voltage VDD1 with a relatively high current capacity, can operate at a relatively high speed, and when there is no short circuit, the specified contents of the control signal CNT are quickly reflected in the state of the output transistor M1 due to the high-speed operation of the driver 140. The driver 141, which uses the internal power supply voltage VDD2 with a relatively low current capacity, is not suitable for high-speed operation, but even if a short circuit occurs, it can generate a voltage V1 (a low-level shift control signal) for turning off the output transistor M1 by turning on the shift transistor M3. In other words, the switch circuit 200 can safely cut off the connection between the input terminal IN and the output terminal OUT when a short circuit occurs.

In addition, in the case where the internal power supply voltage VDD and the internal power supply voltage VDD1 are common, if a short-circuit abnormality occurs when the input voltage _VIN is equal to or higher than a predetermined lower limit voltage, the control signal CNT is fixed at a low level, so that the shift transistor M3 is turned on and the output transistor M1 is fixed at an off level.

When the input voltage _VIN becomes 0 V, the internal power supply voltage VDD2 is also lost, resulting in a logical state that turns on the output transistor M1, but no problem occurs because the input voltage _VIN is 0 V. In actual operation, when the input voltage _VIN decreases while the control signal CNT is at a low level, the level shifter LVS2 pulls out the charge on the wiring WR1 before the input voltage _VIN has completely decreased, so the output transistor M1 does not turn on.

<<Third Example>>
A third embodiment will now be described. The switch circuit 100 in Fig. 8 may be modified to a switch circuit 100a in Fig. 12. The switch circuit 100a is obtained by adding a resistor R2 and a diode D1 to the switch circuit 100.

The differences between the switch circuits 100 and 100a will be described. In the switch circuit 100a, a resistor R2 is added to the components of the level shifter LVS1. In the switch circuit 100a, the anode of the diode D1 is connected to the wiring WR2, and the cathode of the diode D1 is connected to the node ND3. In the switch circuit 100a, the resistor R2 is inserted between the source of the shift transistor M2 and the reference potential point. That is, in the switch circuit 100a, the source of the shift transistor M2 is connected to the reference potential terminal via the resistor R2.

In the absence of resistor R2 and diode D1, when the shift transistor M2 is set to ON, a voltage drop of the drive voltage V _BST occurs across the resistor R1, so that the resistor R1 is required to have a withstand voltage exceeding the drive voltage V _BST . The withstand voltage requirement for the resistor R1 is relaxed by the installation of resistor R2 and diode D1. That is, in the switch circuit 100a, when the shift transistor M2 is set to ON, the current flowing through the resistor R1 is limited by the resistor R2, and the voltage across the resistor R1 is reduced. In addition, in the switch circuit 100a, the presence of the diode D1 limits the drop in the voltage V1 to a voltage (V _OUT -Vf). Vf represents the forward voltage of the diode D1. It should be noted that the value of resistor R2 affects the propagation delay and the fluctuation range of the voltage V1, so it is preferable to set the value of resistor R2 sufficiently smaller than the value of resistor R1.

Similar to modifying switch circuit 100 into switch circuit 100a, switch circuit 200 in FIG. 10 may be modified into switch circuit 200a in FIG. 13. Switch circuit 200a can be obtained by adding resistors R2 and R3 and diode D1 to switch circuit 200.

The differences between the switch circuits 200 and 200a will be described. In the switch circuit 200a, resistors R2 and R3 are added to the components of the level shifter LVS2. In the switch circuit 200a, the anode of the diode D1 is connected to the wiring WR2, and the cathode of the diode D1 is connected to the node ND3. In the switch circuit 200a, a resistor R2 is inserted between the source of the shift transistor M2 and the reference potential point, and a resistor R3 is inserted between the source of the shift transistor M3 and the reference potential point. That is, in the switch circuit 200a, the source of the shift transistor M2 is connected to the reference potential terminal via the resistor R2, and the source of the shift transistor M3 is connected to the reference potential terminal via the resistor R3.

As described for the switch circuit 100a, the provision of resistors R2 and R3 and diode D1 reduces the withstand voltage requirement for resistor R1. Note that, because the values of resistors R2 and R3 affect the propagation delay and the fluctuation range of voltage V1, it is preferable to set the combined resistance value of resistors R2 and R3 (i.e., the resistance value of the parallel circuit of resistors R2 and R3) to be sufficiently smaller than the value of resistor R1.

<<Fourth Example>>
A fourth embodiment will now be described. In the fourth embodiment, applied techniques, modified techniques, or supplementary matters to the above-mentioned items will be described.

For any signal or voltage, the relationship between their high and low levels may be reversed without compromising the above principles.

The channel types of the FETs (field effect transistors) shown in each embodiment are examples. The channel type of any FET may be changed between P-channel and N-channel without compromising the above-mentioned gist.

The above-mentioned transistors may be any type of transistor, provided that no disadvantage arises. For example, the above-mentioned transistors as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage arises. The transistors have a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

The embodiments of the present disclosure may be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms in the present disclosure or each of the constituent elements are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and can, of course, be changed to various numerical values.

<<Additional Notes>>
Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

A switch circuit (100, 200, 100a, 200a) according to one aspect of the present disclosure includes an output switching element (M1) provided between a first node and a second node, a drive voltage generation circuit (120) configured to generate a drive voltage (V _BST ) for turning on the output switching element, level shifters (LVS1, LVS2) configured to generate a shift control signal by level-shifting an original control signal (CNT) that specifies a state of the output switching element using the drive voltage, and a drive circuit (130) configured to drive the output switching element in accordance with the shift control signal based on the drive voltage, wherein the level shifter has a pull-up resistor (R1) and a shift transistor (e.g., M2) connected in series to the pull-up resistor, and is configured (first configuration) to generate the shift control signal that turns off the output switching element by turning on the shift transistor when the original control signal specifies that the output switching element is to be turned off, thereby flowing a current through the pull-up resistor.

This reduces the circuit current while shortening the propagation delay when switching the output switching element from on to off.

In the switch circuit according to the first configuration, the drive voltage may be supplied to a first end of the pull-up resistor, and the level shifter may be configured (second configuration) to generate the shift control signal at a connection node (ND3) between the second end of the pull-up resistor and the shift transistor.

In the switch circuit according to the second configuration, the level shifter may be configured (third configuration) to turn off the shift transistor during an on-designated period in which the original control signal designates the output switching element to be on, and to turn on the shift transistor and pass a current through the pull-up resistor during an off-designated period in which the original control signal designates the output switching element to be off, thereby lowering the voltage of the shift control signal below that during the on-designated period.

In the switch circuit according to any of the first to third configurations, the output switching element may be an output transistor formed of an N-channel type field effect transistor, the drive voltage and a source voltage (V _OUT ) of the output transistor are supplied to the drive circuit, and the drive circuit receives the shift control signal when the shift transistor is off and supplies a voltage based on the drive voltage to the gate of the output transistor to turn on the output transistor, and receives the shift control signal when the shift transistor is on and supplies a voltage based on the source voltage to the gate of the output transistor to turn off the output transistor (fourth configuration).

In the switch circuit according to any one of the first to fourth configurations, the level shifter may have, as the shift transistors, first and second shift transistors (M2, M3) each connected in series to the pull-up resistor, and may be configured (fifth configuration) to turn on or off the first shift transistor in accordance with the original control signal based on a first power supply voltage (VDD1), turn on or off the second shift transistor in accordance with the original control signal based on a second power supply voltage (VDD2), and generate the shift control signal that turns off the output switching element when at least one of the first shift transistor and the second shift transistor is on.

This makes it possible to turn off the output switching element even if either the first power supply voltage or the second power supply voltage is lost.

In the switch circuit according to the fifth configuration, only one of the first power supply voltage and the second power supply voltage may be output from an external terminal (REG) provided in a housing (CS) that houses the switch circuit and exposed from the housing (sixth configuration).

In the switch circuit according to any of the first to sixth configurations, the drive voltage generating circuit may be a charge pump circuit, and the charge pump circuit may be stopped during the period in which the switching element is controlled to be off (seventh configuration).

1 semiconductor device CS housing 10, 910, 920, 930, 100, 200, 100a, 200a switch circuit 20 protection circuit 30 internal power supply circuit 31 overvoltage detection circuit 31a, 31b resistor 31c comparator VS voltage source C _OUT output capacitor IN input terminal OUT output terminal GND ground terminal EN enable terminal REG terminal V _IN input voltage V _OUT output voltage S _EN enable signal S _OVP overvoltage detection signal V _DIV voltage V _OVP judgment reference voltage VSS voltage 911, 921, 931 charge pump circuit 912, 922, 932 driver 913, 923, 933 level shifter 924 pull-up resistor 925 shift transistors P1 to P6, N1, N2 transistors r1, r2 Resistor CNT Control signal Vbst Drive voltage Vg Gate voltage 110 Control circuit 120 Charge pump circuits 130, 140, 141 Drivers 131, 132 Transistor M1 Output transistors M2, M3 Shift transistor R1 Pull-up resistors R2, R3 Resistor D1 Diodes C1, C _REG capacitors WR1 to WR3 Wiring ND1 to ND3 Node V _BST drive voltage V _G gate voltages VDD, VDD1, VDD2 Internal power supply voltage

Claims (7)

an output switching element provided between the first node and the second node;
a drive voltage generating circuit configured to generate a drive voltage for turning on the output switching element;
a level shifter configured to generate a shift control signal by level-shifting an original control signal that designates a state of the output switching element using the drive voltage;
a drive circuit configured to drive the output switching element in accordance with the shift control signal based on the drive voltage;
The level shifter has a pull-up resistor and a shifting transistor connected in series to the pull-up resistor, and generates the shift control signal that turns off the output switching element by turning on the shifting transistor to flow a current through the pull-up resistor when the original control signal specifies that the output switching element is to be turned off. The drive voltage is supplied to a first end of the pull-up resistor;
2. The switch circuit according to claim 1, wherein the level shifter generates the shift control signal at a connection node between the second end of the pull-up resistor and the shifting transistor. 3. The switch circuit according to claim 2, wherein the level shifter turns off the shifting transistor during an on-designation period in which the original control signal designates the output switching element to be on, and turns on the shifting transistor to cause a current to flow through the pull-up resistor during an off-designation period in which the original control signal designates the output switching element to be off, thereby lowering a voltage of the shift control signal compared to that during the on-designation period. the output switching element is an output transistor formed of an N-channel type field effect transistor,
the drive voltage and the source voltage of the output transistor are supplied to the drive circuit;
The switch circuit according to any one of claims 1 to 3, wherein the drive circuit receives the shift control signal when the shift transistor is off and supplies a voltage based on the drive voltage to the gate of the output transistor to turn on the output transistor, and receives the shift control signal when the shift transistor is on and supplies a voltage based on the source voltage to the gate of the output transistor to turn off the output transistor. 4. The switch circuit according to claim 1, wherein the level shifter has, as the shift transistors, first and second shift transistors, each connected in series to the pull-up resistor, turns on or off the first shift transistor in accordance with the original control signal based on a first power supply voltage, turns on or off the second shift transistor in accordance with the original control signal based on a second power supply voltage, and generates the shift control signal for turning off the output switching element when at least one of the first shift transistor and the second shift transistor is on. 6. The switch circuit according to claim 5, wherein only one of the first power supply voltage and the second power supply voltage is output from an external terminal that is provided in a housing that houses the switch circuit and is exposed from the housing. the drive voltage generating circuit is a charge pump circuit,
4. The switch circuit according to claim 1, wherein the charge pump circuit is stopped during a period in which the switching element is controlled to be turned off.

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