JP2024168109A - Nitride Semiconductor Devices - Google Patents

Abstract

To provide a nitride semiconductor device capable of performing a high-speed operation.SOLUTION: A nitride semiconductor device 1 includes: a substrate 10; a drift layer 12; a p-type block layer 14; a foundation layer 16; a gate opening 20; an electron transit layer 22 and an electron supply layer 24; a p-type semiconductor layer 26 that is provided above the electron supply layer 24 at a position overlapping a bottom surface 20a of the gate opening 20 in a plan view of the substrate 10; a gate electrode 32 that is provided above the electron supply layer 24 at a position overlapping the foundation layer 16 in a plan view of the substrate 10; a source opening 30 that is provided at a position away from the gate electrode 32 in a plan view of the substrate 10; a first source electrode 36 that is provided so as to cover the source opening 30 and that is electrically connected to the block layer 14; a drain electrode 38 that is provided below the substrate 10; and a second source electrode 34 that is provided above the p-type semiconductor layer 26 and that is electrically connected to the first source electrode 36.SELECTED DRAWING: Figure 1

Description

This disclosure relates to nitride semiconductor devices.

Nitride semiconductors, such as GaN, are wide-gap semiconductors with a large band gap, and have the advantages of a large dielectric breakdown field and a high electron saturation drift velocity compared to compound semiconductors such as GaAs or Si semiconductors. For example, the band gaps of GaN and AlN are 3.4 eV and 6.2 eV, respectively, at room temperature. For this reason, research and development of power transistors using nitride semiconductors, which are advantageous for achieving high output and/or high voltage resistance, is currently being actively conducted.

Furthermore, in an AlGaN/GaN heterostructure, spontaneous polarization and piezoelectric polarization on the (0001) plane generate a high concentration of two-dimensional electron gas (2DEG) at the heterointerface, and a sheet carrier concentration of 1×10 ¹³ cm ⁻² or more can be obtained even in an undoped state.

Patent Documents 1 and 2 and Non-Patent Document 1 disclose a vertical FET (Field Effect Transistor) formed using GaN-based semiconductor materials. In the vertical FETs disclosed in Patent Documents 1 and 2, a channel made of two-dimensional electron gas generated at the AlGaN/GaN heterointerface is opened and closed by a gate voltage to achieve transistor operation.

Patent No. 6511645 Patent No. 6755892

Zhu et al., “Vertical GaN Power Transistor With Intrinsic Reverse Conduction and Low Gate Charge for High-Performance Power Conversion”, IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 7, No. 3, September 2019

There is room for improvement in terms of increasing the operating speed of conventional nitride semiconductor devices.

Therefore, the present disclosure provides a nitride semiconductor device capable of high-speed operation.

A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer, a second nitride semiconductor layer provided above the first p-type nitride semiconductor layer, a first opening penetrating the second nitride semiconductor layer and the first p-type nitride semiconductor layer and reaching the first nitride semiconductor layer, an electron transit layer and an electron supply layer provided in this order from below so as to cover an upper surface of the second nitride semiconductor layer and the side and bottom surfaces of the first opening, and an electron supply layer provided above the electron supply layer at a position overlapping the bottom surface of the first opening in a plan view of the substrate. The semiconductor device includes a second p-type nitride semiconductor layer or insulating layer, a gate electrode provided above the electron supply layer at a position overlapping the second nitride semiconductor layer in a planar view of the substrate, a second opening that penetrates the electron supply layer and the electron transit layer at a position away from the gate electrode in a planar view of the substrate and reaches the first p-type nitride semiconductor layer, a first source electrode that is provided to cover the second opening and is electrically connected to the first p-type nitride semiconductor layer, a drain electrode that is provided below the substrate, and a second source electrode that is provided above the second p-type nitride semiconductor layer or the insulating layer and is electrically connected to the first source electrode.

The present disclosure makes it possible to provide a nitride semiconductor device capable of high-speed operation.

FIG. 1 is a cross-sectional view of a nitride semiconductor device according to the first embodiment. FIG. 2A is a cross-sectional view for explaining a parasitic capacitance between the gate and drain of a nitride semiconductor device according to a comparative example. FIG. 2B is a cross-sectional view for explaining the parasitic capacitance between the gate and drain of the nitride semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view of a nitride semiconductor device according to the second embodiment. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to the third embodiment. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a modification of the third embodiment. FIG. 6 is a cross-sectional view of a nitride semiconductor device according to the fourth embodiment. FIG. 7 is a cross-sectional view of a nitride semiconductor device according to a modification of the fourth embodiment.

(Findings that formed the basis of this disclosure)
The present inventors have found that the conventional nitride semiconductor devices described in the "Background Art" section have the following problems.

Vertical transistors are more advantageous than horizontal transistors for high voltage and large current operation. On the other hand, vertical transistors are less advantageous than horizontal transistors for high speed operation, as described below.

Note that a vertical transistor has a structure in which a substrate is disposed between the source and drain. Therefore, in a vertical transistor, the drain current that flows between the source and drain mainly flows in a direction perpendicular to the main surface of the substrate. In contrast, a horizontal transistor has a structure in which the source and drain are disposed side by side in a direction parallel to the main surface of the substrate. Therefore, in a horizontal transistor, the drain current mainly flows in a direction parallel to the main surface of the substrate.

Table 1 shows a comparison of the parasitic capacitance Cgd between the gate and drain of horizontal and vertical transistors. When compared at device sizes with the same on-resistance Ron, the parasitic capacitance Cgd between the gate and drain of vertical transistors is about two orders of magnitude larger than that of horizontal transistors. This is due to the fact that the parallel plate capacitance between the gate and drain is large due to the structure of the vertical transistor, and it is difficult to provide a field plate to terminate the electric field lines from the drain to the gate at the source. If the parasitic capacitance Cgd is large, the rise characteristics of the drain current will deteriorate, making it difficult for the transistor to operate at high speed.

Patent document 2 discloses a structure in which the gate electrode is disposed above the outer edge of the gate opening, rather than inside the gate opening. Patent document 2 shows that this configuration can lower the gate drive voltage and reduce drive loss. However, in this structure, all electric field lines from the drain to the gate are directed toward the gate, so this does not lead to a reduction in parasitic capacitance Cgd.

In addition, Non-Patent Document 1 describes the calculation results of lowering the gate capacitance by providing a Schottky electrode connected to the source electrode on the regrown AlGaN layer in a vertical transistor. However, when the Schottky electrode provided on this regrown AlGaN layer is used as a field plate, the reverse characteristics of the Schottky characteristics have a larger leakage current and a smaller breakdown voltage than the reverse characteristics of a pn diode, which leads to a decrease in the reliability of the transistor.

In view of the above problems, the present disclosure aims to provide a nitride semiconductor device capable of high-speed operation by reducing the parasitic capacitance Cgd while suppressing deterioration in reliability.

To achieve the above objective, each aspect of the nitride semiconductor device disclosed herein has the configuration described below.

The nitride semiconductor device according to the first aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer, a second nitride semiconductor layer provided above the first p-type nitride semiconductor layer, a first opening penetrating the second nitride semiconductor layer and the first p-type nitride semiconductor layer and reaching the first nitride semiconductor layer, an electron transit layer and an electron supply layer provided in this order from below so as to cover an upper surface of the second nitride semiconductor layer and the side and bottom surfaces of the first opening, and an electron supply layer provided above the electron supply layer at a position overlapping the bottom surface of the first opening in a plan view of the substrate. a second p-type nitride semiconductor layer or insulating layer, a gate electrode provided above the electron supply layer at a position overlapping the second nitride semiconductor layer in a planar view of the substrate, a second opening penetrating the electron supply layer and the electron transit layer at a position away from the gate electrode in a planar view of the substrate and reaching the first p-type nitride semiconductor layer, a first source electrode provided to cover the second opening and electrically connected to the first p-type nitride semiconductor layer, a drain electrode provided below the substrate, and a second source electrode provided above the second p-type nitride semiconductor layer or the insulating layer and electrically connected to the first source electrode.

This allows the electric field lines extending from the drain electrode to terminate at the second p-type nitride semiconductor layer, or at the second source electrode provided above the insulating layer and the first p-type nitride semiconductor layer, thereby reducing the parasitic capacitance Cgd between the gate and drain. Therefore, according to this aspect, a nitride semiconductor device capable of high-speed operation can be realized.

In addition, in the nitride semiconductor device according to this embodiment, the reverse characteristics of a pn diode due to the two-dimensional electron gas (n) generated at the interface between the second p-type nitride semiconductor layer (p) and the electron supply layer and electron transport layer can be utilized, so that an increase in leakage current and a decrease in breakdown voltage can be suppressed. Similarly, when an insulating layer is provided instead of the second p-type nitride semiconductor layer, an increase in leakage current and a decrease in breakdown voltage can be suppressed. Thus, a decrease in the reliability of the nitride semiconductor device can be suppressed.

In the nitride semiconductor device according to the second aspect of the present disclosure, in the nitride semiconductor device according to the first aspect, the side of the first opening is inclined with respect to the bottom surface of the first opening, the upper surface of the electron supply layer includes a flat portion along the bottom surface of the first opening and an inclined portion along the side of the first opening, and the second p-type nitride semiconductor layer or the insulating layer continuously covers the flat portion and a part of the inclined portion.

This allows the electric field concentrated in the second nitride semiconductor layer when the device is off to be dispersed, thereby reducing the leakage current when the device is off. In addition to the effect of reducing the parasitic capacitance Cgd between the gate and drain, this embodiment also promotes electric field relaxation when the device is off, resulting in good off characteristics.

The nitride semiconductor device according to the third aspect of the present disclosure is the nitride semiconductor device according to the first or second aspect, and further includes a third p-type nitride semiconductor layer provided between the gate electrode and the electron supply layer and spaced apart from the second p-type nitride semiconductor layer or the insulating layer.

This allows the carrier concentration directly below the gate electrode to be reduced, and the threshold voltage of the transistor to be shifted to the positive side. This makes it easy to realize the nitride semiconductor device according to this embodiment as a normally-off FET.

In the nitride semiconductor device according to the fourth aspect of the present disclosure, in the nitride semiconductor device according to the third aspect, in a plan view of the substrate, the distance between the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer is shorter than the distance between the third p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer.

This allows more of the electric field lines extending from the drain electrode to terminate in the first p-type nitride semiconductor layer, further reducing the parasitic capacitance Cgd between the gate and drain. Therefore, according to this embodiment, a nitride semiconductor device with excellent high-speed operation can be realized.

In the nitride semiconductor device according to the fifth aspect of the present disclosure, in the nitride semiconductor device according to the third aspect, in a plan view of the substrate, the distance between the third p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer is shorter than the distance between the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer.

As a result, although the parasitic capacitance Cgd between the gate and drain increases slightly, the longer gate length improves the breakdown voltage when the device is off. This embodiment makes it possible to realize a nitride semiconductor device that has excellent off characteristics and is capable of high-speed operation.

In the nitride semiconductor device according to the sixth aspect of the present disclosure, in the nitride semiconductor device according to any one of the first to fifth aspects, the distance between the second p-type nitride semiconductor layer or the insulating layer and the drain electrode is shorter than the distance between the first p-type nitride semiconductor layer and the drain electrode.

This can alleviate the electric field concentration during off-state, and reduce the leakage current during off-state. This aspect makes it possible to realize a nitride semiconductor device that has good off-state characteristics and is capable of high-speed operation.

The following describes an embodiment of the present disclosure with reference to the drawings.

The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection forms, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in an independent claim are described as optional components.

In addition, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of each figure do not necessarily match. In addition, in each figure, the same reference numerals are used for substantially the same configuration, and duplicate explanations are omitted or simplified.

In addition, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangular or trapezoidal, and numerical ranges are not expressions that only express a strict meaning, but are expressions that include a substantially equivalent range, for example, a difference of about a few percent.

In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may be referred to as the "lateral direction."

In addition, the side of the substrate on which the gate electrode and source electrode are provided is considered to be the "upper" or "upper side", and the side of the substrate on which the drain electrode is provided is considered to be the "lower" or "lower side".

In this specification, the terms "above" and "below" do not refer to the upward (vertically upward) and downward (vertically downward) directions in an absolute spatial sense, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are not only used when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in close contact with each other and are in contact with each other.

In addition, in this specification, unless otherwise specified, "planar view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, i.e., a view of the main surface of the substrate from the front.

In addition, in this specification, the distance between A and B in a planar view refers to the shortest distance between A and B in a planar view. Specifically, the distance is the length of the shortest line segment among the countless line segments connecting any point on the contour line representing the outer shape of A in a planar view and any point on the contour line representing the outer shape of B.

In addition, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components, unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

In this specification, AlGaN refers to ternary mixed crystal Al _x Ga _1-x N (0<x<1). Hereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, for example, AlInN, GaInN, etc. For example, Al _x Ga _1-x-y In _y N (0<x<1, 0<y<1, and 0<x+y<1), which is an example of a nitride semiconductor, is abbreviated as AlGaInN.

(Embodiment 1)
[composition]
First, the configuration of a nitride semiconductor device according to the first embodiment will be described with reference to FIG.

Figure 1 is a cross-sectional view of a nitride semiconductor device 1 according to this embodiment. In Figure 1, each component, such as a semiconductor layer and an electrode, is shaded with diagonal lines to indicate a cross section.

As shown in FIG. 1, the nitride semiconductor device 1 according to this embodiment is a so-called vertical field effect transistor (FET). Specifically, in the nitride semiconductor device 1, a current flows between the drain electrode 38 and the first source electrode 36 in a direction perpendicular to the main surface of the substrate 10.

The nitride semiconductor device 1 is a device having a laminated structure of nitride semiconductor layers containing nitride semiconductors such as GaN and AlGaN as the main components. Note that "A contains B as the main component" means that the content of B in A is 50% or more.

The nitride semiconductor device 1 according to this embodiment is a normally-off type FET. In the nitride semiconductor device 1, for example, the first source electrode 36 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 38. The potential applied to the drain electrode 38 is, for example, not limited to, 100 V or more and 1200 V or less. When the nitride semiconductor device 1 is in the off state, 0 V or a negative potential (for example, -5 V) is applied to the gate electrode 32. When the nitride semiconductor device 1 is in the on state, a positive potential (for example, +5 V) is applied to the gate electrode 32. The nitride semiconductor device 1 may be a normally-on type FET.

As shown in FIG. 1, the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a block layer 14, an underlayer 16, a gate opening 20, an electron transit layer 22, an electron supply layer 24, a p-type semiconductor layer 26, a threshold adjustment layer 28, a source opening 30, a gate electrode 32, a second source electrode 34, a first source electrode 36, and a drain electrode 38. At the interface between the electron transit layer 22 and the electron supply layer 24, a two-dimensional electron gas (2DEG) 25 that functions as a channel is generated.

The following describes in detail each of the components of the nitride semiconductor device 1.

The substrate 10 is a substrate made of a nitride semiconductor. The planar shape of the substrate 10 is, for example, rectangular, but is not limited to this.

The substrate 10 is, for example, a substrate made of n ⁺ type GaN having a thickness of 300 μm and a carrier concentration of 1×10 ¹⁸ cm ⁻³ . The n type and p type indicate the conductivity type of the semiconductor. The n ⁺ type represents a state in which a semiconductor is doped with a high concentration of n-type dopants, that is, a so-called heavy doping. The n ^- type represents a state in which a semiconductor is doped with a low concentration of n-type dopants, that is, a so-called light doping. Both the n ⁺ type and the n ^- type are examples of n-type, and may be referred to as n-type without distinguishing between them. The same applies to the p ⁺ type and the p ^- type.

The substrate 10 does not have to be a nitride semiconductor substrate. For example, the substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

The drift layer 12 is an example of a first nitride semiconductor layer provided above the substrate 10. The drift layer 12 is, for example, a film made of n ^- type GaN with a thickness of 8 μm. The donor concentration of the drift layer 12 is, for example, 1×10 ¹⁵ cm ^-3 or more and 1×10 ¹⁷ cm ^-3 or less, for example, 1×10 ¹⁶ cm ^-3 . The carbon concentration (C concentration) of the drift layer 12 is, for example, 1×10 ¹⁵ cm ^-3 or more and 2×10 ¹⁷ cm ^-3 or less.

The drift layer 12 is provided, for example, in contact with the upper surface (main surface) of the substrate 10. The drift layer 12 is formed on the main surface of the substrate 10 by crystal growth, for example, by metal organic vapor phase epitaxy (MOVPE) or hydride vapor phase epitaxy (HVPE).

The block layer 14 is an example of a first p-type nitride semiconductor layer provided above the drift layer 12. The block layer 14 is, for example, a film made of p-type GaN having a thickness of 400 nm and a carrier concentration of 1×10 ¹⁷ cm ⁻³ . The block layer 14 is provided in contact with the upper surface of the drift layer 12. The block layer 14 is formed on the drift layer 12 by crystal growth, for example, by MOVPE, HVPE, or the like.

The block layer 14 is formed by crystal growth, but may also be formed, for example, by injecting magnesium (Mg) into the formed i-GaN film. Furthermore, the block layer 14 may not be a p-type nitride semiconductor layer, but may be an insulating layer obtained by injecting iron (Fe) or boron (B), etc.

The block layer 14 suppresses leakage current between the first source electrode 36 and the drain electrode 38. For example, when a reverse voltage is applied to the pn junction formed by the block layer 14 and the drift layer 12, specifically, when the drain electrode 38 has a higher potential than the first source electrode 36, a depletion layer extends to the drift layer 12. This allows the nitride semiconductor device 1 to have a high breakdown voltage. In this embodiment, the drain electrode 38 has a higher potential than the first source electrode 36 in both the off state and the on state, except in the case of reverse conduction. This allows the nitride semiconductor device 1 to have a high breakdown voltage.

In addition, in this embodiment, as shown in FIG. 1, the block layer 14 is in contact with the first source electrode 36. Therefore, the block layer 14 is fixed to the source potential applied to the first source electrode 36. As a result, the block layer 14 can shield the electric field lines extending from the drain electrode 38, which will be described in detail later, and can contribute to reducing the parasitic capacitance Cgd between the gate and drain.

The underlayer 16 is an example of a second nitride semiconductor layer provided above the block layer 14. The underlayer 16 is a high-resistance layer having a higher resistance than the block layer 14. The underlayer 16 is, for example, a film made of undoped GaN (i-GaN) with a thickness of 200 nm. The underlayer 16 is provided in contact with the block layer 14. The underlayer 16 is formed on the block layer 14 by crystal growth using, for example, the MOVPE method, the HVPE method, or the like.

The underlayer 16 is assumed to be an undoped semiconductor layer, but may be an insulating layer or semi-insulating layer. Here, "undoped" means that it is not doped with a dopant such as Si or Mg that changes the polarity of GaN to n-type or p-type. In this embodiment, the underlayer 16 may be doped with carbon (C). For example, the carbon concentration of the underlayer 16 is higher than the carbon concentration of the block layer 14.

For example, the carbon concentration of the underlayer 16 is 3×10 ¹⁷ cm ⁻³ or more, but may be 1×10 ¹⁸ cm ⁻³ or more. In this case, the respective concentrations of silicon (Si) or oxygen (O) which are n-type impurities are lower than the carbon concentration. For example, the silicon concentration or oxygen concentration of the underlayer 16 is 5×10 ¹⁶ cm ⁻³ or less, but may be 2×10 ¹⁶ cm ⁻³ or less. As for the type of ions implanted into the underlayer 16 and the block layer 14, ion species other than those mentioned above can be used to obtain the same effect as long as they are ion species that can increase the resistance of the semiconductor layer.

In addition, a layer for suppressing the diffusion of p-type impurities such as Mg from the block layer 14 may be provided on the upper surface of the underlayer 16. For example, a 20 nm thick AlGaN layer may be provided on the block layer 14.

The gate opening 20 is an example of a first opening that penetrates the underlayer 16 and the block layer 14 and reaches the drift layer 12. The bottom surface 20a of the gate opening 20 is a part of the upper surface of the drift layer 12. As shown in FIG. 1, the bottom surface 20a is located below the lower surface of the block layer 14. The lower surface of the block layer 14 corresponds to the interface between the block layer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the main surface of the substrate 10. When the nitride semiconductor device 1 is on, the drain current flows between the drain electrode 38 and the first source electrode 36 through the bottom surface 20a of the gate opening 20.

In this embodiment, the gate opening 20 is formed so that the opening area increases as it is farther away from the substrate 10. Specifically, the side surface 20b of the gate opening 20 is inclined obliquely. As shown in FIG. 1, the cross-sectional shape of the gate opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 80°, but may be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, and the better the film quality of the electron transit layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the more the gate opening 20 is prevented from becoming too large, and the smaller the nitride semiconductor device 1 can be achieved.

The gate opening 20 is formed by successively depositing the drift layer 12, the block layer 14, and the underlayer 16 in this order on the main surface of the substrate 10, and then removing a portion of each of the underlayer 16 and the block layer 14 so as to partially expose the drift layer 12. At this time, by removing a predetermined thickness (e.g., 300 nm) of the surface portion of the drift layer 12, the bottom surface 20a of the gate opening 20 is formed below the bottom surface of the block layer 14.

The method of removing the base layer 16 and the block layer 14 is to use dry etching such as inductively coupled plasma etching (ICP), and a chlorine-based gas is often used as the process gas.

The electron transit layer 22 is an example of a first regrown layer provided to cover the upper surface of the underlayer 16 and the side surface 20b and bottom surface 20a of the gate opening 20. Specifically, a part of the electron transit layer 22 is provided along the bottom surface 20a and side surface 20b of the gate opening 20, and the other part of the electron transit layer 22 is provided on the upper surface of the underlayer 16. The electron transit layer 22 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that although the electron transit layer 22 is assumed to be undoped, it may be partially made n-type by Si doping or the like.

The electron transit layer 22 is in contact with the drift layer 12 at the bottom surface 20a and the side surface 20b of the gate opening 20. The electron transit layer 22 is in contact with each of the block layer 14 and the underlayer 16 at the side surface 20b of the gate opening 20. Furthermore, the electron transit layer 22 is in contact with the upper surface of the underlayer 16.

The electron transit layer 22 has a channel region. Specifically, a two-dimensional electron gas 25 that serves as a channel is generated near the interface between the electron transit layer 22 and the electron supply layer 24. In FIG. 1, the two-dimensional electron gas 25 is shown diagrammatically by a dashed line. The two-dimensional electron gas 25 is bent along the interface between the electron transit layer 22 and the electron supply layer 24, that is, along the inner surface of the gate opening 20.

Although not shown in FIG. 1, an AlN layer with a thickness of about 1 nm is provided as a second regrown layer between the electron transit layer 22 and the electron supply layer 24. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. Note that the AlN layer is not necessarily required.

The electron supply layer 24 is an example of a third regrown layer provided to cover the upper surface of the underlayer 16 and the side surface 20b and bottom surface 20a of the gate opening 20. The electron transit layer 22 and the electron supply layer 24 are provided in this order from the substrate 10 side. The electron supply layer 24 is, for example, a film made of undoped AlGaN with a thickness of 20 nm.

The electron supply layer 24 is formed with a substantially uniform thickness and conforms to the upper surface of the electron transit layer 22. As shown in FIG. 1, the upper surface of the electron supply layer 24 includes a flat portion 24a, an inclined portion 24b, and an outer edge portion 24c.

The flat portion 24a is a portion along the bottom surface 20a of the gate opening 20. The flat portion 24a is, for example, a plane parallel to the bottom surface 20a. The flat portion 24a is the lowermost portion of the upper surface of the electron supply layer 24.

The inclined portion 24b is a portion that runs along the side surface 20b of the gate opening 20. The inclined portion 24b is, for example, a slope that is parallel to the side surface 20b of the gate opening 20. The inclined portion 24b is provided on both sides of the flat portion 24a.

The outer edge 24c is a portion that extends outward from the upper end of the inclined portion 24b. Here, "outward" refers to the direction from the bottom surface 20a of the gate opening 20 toward the first source electrode 36. The outer edge 24c is a plane parallel to the main surface of the substrate 10. The outer edge 24c is the uppermost portion of the upper surface of the electron supply layer 24.

The flat portion 24a, the inclined portion 24b, and the outer edge portion 24c may each be a curved surface. The flat portion 24a and the inclined portion 24b may be connected to each other in a smoothly curved manner. The outer edge portion 24c and the inclined portion 24b may be connected to each other in a smoothly curved manner.

The electron supply layer 24 has a larger band gap than the electron transit layer 22. Therefore, an AlGaN/GaN heterointerface is formed between the electron supply layer 24 and the electron transit layer 22. The electron supply layer 24 supplies electrons to a channel region (two-dimensional electron gas 25) formed in the electron transit layer 22.

The p-type semiconductor layer 26 is an example of a second p-type nitride semiconductor layer provided above the electron supply layer 24 at a position overlapping the bottom surface 20a of the gate opening 20 in a plan view of the substrate 10. Specifically, the p-type semiconductor layer 26 is provided in contact with the flat portion 24a of the upper surface of the electron supply layer 24. In this embodiment, the p-type semiconductor layer 26 is not in contact with the inclined portion 24b. The p-type semiconductor layer 26 is, for example, a film made of p-type Al _x Ga _1-x N (0≦x≦1) having a thickness of 100 nm and a carrier concentration of 1×10 ¹⁷ cm ⁻³ .

The p-type semiconductor layer 26 is provided at a position away from the threshold adjustment layer 28. Specifically, the p-type semiconductor layer 26 is electrically isolated from the threshold adjustment layer 28. In addition, the lower surface of the p-type semiconductor layer 26 is located at least below the outer edge portion 24c of the upper surface of the electron supply layer 24. For example, at least a portion of the p-type semiconductor layer 26 is located at the same height as the block layer 14.

An insulating layer may be provided instead of the p-type semiconductor layer 26. The insulating layer may be a single layer or a multi-layer structure of an insulating nitride film or oxide _film such as SiN, _SiO2 , AlN, or _Al2O3 .

The threshold adjustment layer 28 is an example of a third p-type nitride semiconductor layer that is provided between the gate electrode 32 and the electron supply layer 24 and separated from the p-type semiconductor layer 26. The threshold adjustment layer 28 is provided on the outer edge portion 24c of the upper surface of the electron supply layer 24 and is in contact with the electron supply layer 24 and the gate electrode 32.

By providing the threshold adjustment layer 28, the potential of the channel portion is increased. This allows the threshold of the transistor to be increased, realizing a normally-off state.

The thickness, composition ratio, and carrier concentration of the threshold adjustment layer 28 are, for example, the same as the thickness, composition ratio, and carrier concentration of the p-type semiconductor layer 26. The threshold adjustment layer 28 is formed by patterning a nitride semiconductor film formed in the same film formation process as the p-type semiconductor layer 26.

It is to be noted that the threshold adjustment layer 28 does not necessarily have to be provided. For example, instead of the threshold adjustment layer 28, an insulating layer such as SiN or _SiO2 may be provided between the gate electrode 32 and the electron supply layer 24. This makes it possible to suppress the gate current and shift the threshold in the positive direction to realize a normally-off operation.

The electron transit layer 22, the electron supply layer 24, the p-type semiconductor layer 26, and the threshold adjustment layer 28 are formed by forming the gate opening 20, and then successively depositing nitride semiconductor films by a crystal regrowth process and patterning them into a predetermined shape. Specifically, the undoped GaN film that is the basis of the electron transit layer 22, the undoped AlGaN film that is the basis of the electron supply layer 24, and the p-type AlGaN film that is the basis of the p-type semiconductor layer 26 and the threshold adjustment layer 28 are successively deposited by MOVPE or HVPE. After deposition, a portion of the p-type AlGaN film is removed by etching until the undoped AlGaN film is exposed, thereby forming the p-type semiconductor layer 26 and the threshold adjustment layer 28. The p-type semiconductor layer 26 and the threshold adjustment layer 28 are electrically isolated from each other. Furthermore, a portion of each of the undoped AlGaN film and the undoped GaN film and a portion of the underlayer 16 are successively removed by etching until the block layer 14 is exposed. This forms a source opening 30 that reaches the block layer 14, and forms the electron supply layer 24 and the electron transit layer 22 that are patterned into a predetermined shape.

The source opening 30 is an example of a second opening that penetrates the electron supply layer 24 and the electron transit layer 22 at a position away from the gate electrode 32 in a plan view of the substrate 10, and reaches the block layer 14. In this embodiment, the source opening 30 is provided at a position away from both the gate opening 20 and the threshold adjustment layer 28 in a plan view of the substrate 10.

The bottom surface 30a of the source opening 30 is part of the upper surface of the block layer 14. In the example shown in FIG. 1, the bottom surface 30a is flush with the lower surface of the underlayer 16, but is not limited to this. The bottom surface 30a may be located lower than the lower surface of the underlayer 16. The lower surface of the underlayer 16 corresponds to the interface between the underlayer 16 and the block layer 14. The bottom surface 30a is, for example, parallel to the main surface of the substrate 10.

As shown in FIG. 1, the source opening 30 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the side surface 30b of the source opening 30 is perpendicular to the bottom surface 30a. In other words, the cross-sectional shape of the source opening 30 is rectangular.

Alternatively, the source opening 30 may be formed so that the opening area increases as it is farther from the substrate 10. Specifically, the side surface 30b of the source opening 30 may be inclined obliquely. For example, the cross-sectional shape of the source opening 30 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side surface 30b with respect to the bottom surface 30a may be, for example, in the range of 30° to 60°. By inclining the side surface 30b obliquely, the contact area between the first source electrode 36 and the electron transit layer 22 (two-dimensional electron gas 25) increases, making it easier to make an ohmic connection. The two-dimensional electron gas 25 is exposed to the side surface 30b of the source opening 30, and is connected to the first source electrode 36 at the exposed portion.

By providing the source opening 30, it is possible to reduce the ohmic contact resistance between the two-dimensional electron gas 25 functioning as a channel and the first source electrode 36. In addition, since the block layer 14 and the first source electrode 36 can be electrically connected, it is possible to stabilize the potential of the block layer 14 and obtain effects such as improved breakdown voltage.

The gate electrode 32 is provided above the electron supply layer 24 at a position overlapping the base layer 16 in a plan view of the substrate 10. Specifically, the gate electrode 32 is provided in contact with the upper surface of the threshold adjustment layer 28.

The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 can be made of a material that makes ohmic contact with the p-type GaN layer. For example, palladium (Pd), nickel (Ni)-based materials, tungsten silicide (WSi), gold (Au), etc. can be used. The gate electrode 32 is formed by forming a conductive film by sputtering or deposition after the threshold adjustment layer 28 is formed, after the source opening 30 is formed, or after the first source electrode 36 and the second source electrode 34 are formed, and then patterning the formed conductive film.

The second source electrode 34 is provided above the p-type semiconductor layer 26. Specifically, the second source electrode 34 is provided in contact with the upper surface of the p-type semiconductor layer 26. The second source electrode 34 is not in contact with the electron supply layer 24.

The second source electrode 34 is electrically connected to the first source electrode 36. That is, the second source electrode 34 is an electrode to which the same source potential as the first source electrode 36 is supplied. The second source electrode 34 is not directly connected to the two-dimensional electron gas 25. The drain current from the drain electrode 38 flows to the first source electrode 36 via the two-dimensional electron gas 25.

The second source electrode 34 is formed using a conductive material such as a metal. The second source electrode 34 can be formed using the same material as the first source electrode 36. The second source electrode 34 is formed, for example, by forming a conductive film by sputtering or vapor deposition, and patterning the formed conductive film.

The first source electrode 36 is provided to cover the source opening 30. Specifically, the first source electrode 36 is provided in contact with the bottom surface 30a and the side surface 30b of the source opening 30 so as to fill the source opening 30. The first source electrode 36 is electrically connected to the block layer 14 exposed at the bottom surface 30a of the source opening 30.

The first source electrode 36 may also be in contact with the outer edge 24c of the upper surface of the electron supply layer 24, which corresponds to the edge of the source opening 30. The first source electrode 36 is in direct contact with the two-dimensional electron gas 25 at the side surface 30b of the source opening 30. This can reduce the contact resistance between the first source electrode 36 and the two-dimensional electron gas 25.

The first source electrode 36 is formed using a conductive material such as a metal. The material of the first source electrode 36 may be, for example, Ti/Al (a laminated structure of a Ti layer and an Al layer), which is ohmically connected to the n-type GaN layer by heat treatment. The first source electrode 36 is formed, for example, by patterning a conductive film formed by sputtering or vapor deposition. The first source electrode 36 is formed, for example, by the same manufacturing process as the second source electrode 34.

The drain electrode 38 is provided below the substrate 10. Specifically, the drain electrode 38 is provided in contact with the lower surface of the substrate 10.

The drain electrode 38 is formed using a conductive material such as a metal. As with the material of the first source electrode 36, the material of the drain electrode 38 may be, for example, a material that makes ohmic contact with n-type GaN, such as Ti/Al. The drain electrode 38 is formed, for example, by forming a conductive film by sputtering or vapor deposition, and patterning the formed conductive film.

[Characteristic configuration]
Next, a main characteristic configuration of the nitride semiconductor device 1 according to the present embodiment will be described.

As described above, in the nitride semiconductor device 1 according to this embodiment, the gate electrode 32 and the threshold adjustment layer 28 are located outside the gate opening 20, and the second source electrode 34 and the p-type semiconductor layer 26 are provided near the bottom surface 20a of the gate opening 20. In other words, the second source electrode 34 and the p-type semiconductor layer 26 are located below the gate electrode 32 and the threshold adjustment layer 28. It is sufficient that at least the lower surface of the p-type semiconductor layer 26 is located below the lower surface of the threshold adjustment layer 28. A part of the second source electrode 34 and the p-type semiconductor layer 26 may be located above one of the gate electrode 32 and the threshold adjustment layer 28.

The following is a detailed explanation of the comparative example using Figures 2A and 2B. Figures 2A and 2B are diagrams for explaining the gate-drain parasitic capacitance Cgd of the nitride semiconductor device according to the comparative example and the present embodiment, respectively.

2A shows the vicinity of the gate opening 20 in the cross-sectional configuration of the nitride semiconductor device 1x according to the comparative example. The nitride semiconductor device 1x according to the comparative example is different from the nitride semiconductor device 1 in that the nitride semiconductor device 1x according to the comparative example includes a gate electrode 32x and a threshold adjustment layer 28x instead of the p-type semiconductor layer 26, the threshold adjustment layer 28, the gate electrode 32, and the second source electrode 34. Specifically, the gate electrode 32x and the threshold adjustment layer 28x are provided along the bottom surface 20a and the side surface 20b of the gate opening 20. More specifically, the threshold adjustment layer 28x is provided so as to cover each of the flat portion 24a, the inclined portion 24b, and the outer edge portion 24c of the upper surface of the electron supply layer 24. The gate electrode 32x is provided in contact with the upper surface of the threshold adjustment layer 28x. Specifically, the gate electrode 32x is provided at a position overlapping the bottom surface 20a of the gate opening 20 in a plan view.

This configuration increases the area where the gate electrode 32x and threshold adjustment layer 28x face the drain electrode 38. This increases the parallel plate capacitance between the gate and drain, and almost all of the electric field lines from the drain to the gate that contribute to the parasitic capacitance Cgd between the gate and drain are terminated at the gate. This makes it difficult to reduce the parasitic capacitance Cgd.

On the other hand, in the configuration according to this embodiment, as shown in FIG. 2B, a second source electrode 34 and a p-type semiconductor layer 26 are provided near the bottom surface 20a of the gate opening 20. Therefore, a part of the electric field lines from the drain to the gate can be terminated at the second source electrode 34 and the p-type semiconductor layer 26. As a result, it is possible to reduce the parasitic capacitance Cgd between the gate and the drain.

As shown in FIG. 1, the block layer 14 is located closer to the p-type semiconductor layer 26 than the threshold adjustment layer 28. Specifically, in a plan view of the substrate 10, the distance D1 between the block layer 14 and the p-type semiconductor layer 26 is shorter than the distance D2 between the threshold adjustment layer 28 and the p-type semiconductor layer 26. In other words, the end of the block layer 14 connected to the first source electrode 36 on the p-type semiconductor layer 26 side is located closer to the p-type semiconductor layer 26 side than the end of the threshold adjustment layer 28 on the p-type semiconductor layer 26 side. This allows the block layer 14 to also shield the electric field lines toward the gate electrode 32. This allows the parasitic capacitance Cgd between the gate and drain to be further reduced, thereby achieving high-speed operation of the transistor.

(Embodiment 2)
Next, a second embodiment will be described.

In the second embodiment, the main difference from the first embodiment is the position of the end of the threshold adjustment layer provided directly below the gate electrode. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

Figure 3 is a cross-sectional view of a nitride semiconductor device 101 according to the second embodiment. As shown in Figure 3, the nitride semiconductor device 101 differs from the nitride semiconductor device 1 shown in Figure 1 in that it includes a threshold adjustment layer 128 instead of the threshold adjustment layer 28. The threshold adjustment layer 128 is an example of a third p-type nitride semiconductor layer, and the position of its end is different from that of the threshold adjustment layer 28.

Specifically, in a plan view of the substrate 10, the distance D2 between the threshold adjustment layer 128 and the p-type semiconductor layer 26 is shorter than the distance D1 between the block layer 14 and the p-type semiconductor layer 26. In other words, the end of the threshold adjustment layer 128 on the p-type semiconductor layer 26 side is located closer to the p-type semiconductor layer 26 side than the end of the block layer 14 on the p-type semiconductor layer 26 side.

According to this configuration, some of the electric field lines from the drain electrode 38 toward the threshold adjustment layer 128 cannot be terminated at the block layer 14 connected to the first source electrode 36. As a result, the gate-drain parasitic capacitance Cgd increases slightly compared to the nitride semiconductor device 1 according to the first embodiment. On the other hand, the gate length can be increased, so that the off-state breakdown voltage of the nitride semiconductor device 101 can be improved.

The gate length corresponds to the length over which the opening and closing of the channel can be controlled by the gate electrode 32 and the threshold adjustment layer 28, and is specifically the length of the threshold adjustment layer 128 in the direction in which the first source electrode 36 and the gate electrode 32 are aligned. The width (horizontal length) of the threshold adjustment layer 28 in the cross-sectional view shown in FIG. 3 corresponds to the gate length. The gate length can be increased by arranging the end of the threshold adjustment layer 128 on the p-type semiconductor layer 26 side closer to the p-type semiconductor layer 26. For example, a portion of the threshold adjustment layer 128 may overlap the bottom surface 20a of the gate opening 20 in a plan view.

As described above, the nitride semiconductor device 101 according to this embodiment can improve the off-state breakdown voltage while reducing the parasitic capacitance Cgd between the gate and drain. Therefore, it is possible to realize a nitride semiconductor device 101 that achieves both high-speed operation and high reliability.

(Embodiment 3)
Next, a third embodiment will be described.

In the third embodiment, the main difference from the first embodiment is the size of the p-type semiconductor layer provided directly below the second source electrode. In the following, the differences from the first embodiment will be mainly described, and the description of the commonalities will be omitted or simplified.

Figure 4 is a cross-sectional view of a nitride semiconductor device 201 according to the third embodiment. As shown in Figure 4, the nitride semiconductor device 201 differs from the nitride semiconductor device 1 shown in Figure 1 in that it includes a p-type semiconductor layer 226 instead of the p-type semiconductor layer 26. The p-type semiconductor layer 226 is an example of a second p-type nitride semiconductor layer, and the range that covers the upper surface of the electron supply layer 24 differs from that of the p-type semiconductor layer 26.

Specifically, the p-type semiconductor layer 226 continuously covers the flat portion 24a and part of the inclined portion 24b of the upper surface of the electron supply layer 24. More specifically, the p-type semiconductor layer 226 continuously covers the entire flat portion 24a and part of the inclined portion 24b. The area that covers the inclined portion 24b is not particularly limited, but is, for example, an area less than the lower half of the inclined portion 24b.

According to this configuration, the p-type semiconductor layer 226 covers the flat portion 24a and part of the inclined portion 24b of the upper surface of the electron supply layer 24, thereby increasing the number of locations where the electric field is likely to concentrate when the transistor is off. Specifically, the electric field can be received by the end of the block layer 14 on the p-type semiconductor layer 226 side, the bottom surface of the p-type semiconductor layer 226, and the end of the p-type semiconductor layer 226. In this way, the electric field concentration can be alleviated, and the off-leakage can be reduced. Also, as in the first embodiment, the p-type semiconductor layer 226 can shield the electric field lines, so that the parasitic capacitance Cgd between the gate and drain can be reduced, and high-speed operation of the transistor can be achieved.

Figure 5 is a cross-sectional view of a nitride semiconductor device 202 according to a modified example of the third embodiment. As shown in Figure 5, compared to the nitride semiconductor device 101 shown in Figure 4, the nitride semiconductor device 202 includes a threshold adjustment layer 128 instead of the threshold adjustment layer 28. The threshold adjustment layer 128 is the same as the threshold adjustment layer 128 shown in Figure 3.

Specifically, in a plan view of the substrate 10, the distance D2 between the threshold adjustment layer 128 and the p-type semiconductor layer 226 is shorter than the distance D1 between the block layer 14 and the p-type semiconductor layer 226. In other words, the end of the threshold adjustment layer 128 on the p-type semiconductor layer 226 side is located closer to the p-type semiconductor layer 226 side than the end of the block layer 14 on the p-type semiconductor layer 226 side.

This makes it possible to reduce off-leakage by mitigating electric field concentration, while increasing the gate length to achieve high voltage resistance. In addition, because the p-type semiconductor layer 226 can shield electric field lines, the parasitic capacitance Cgd between the gate and drain can be reduced, enabling the transistor to operate at high speed.

(Embodiment 4)
Next, a fourth embodiment will be described.

The fourth embodiment differs from the first embodiment mainly in that the bottom of the p-type semiconductor layer provided directly below the second source electrode is closer to the drain electrode than the bottom of the block layer. The following description will focus on the differences from the first embodiment, and will omit or simplify the description of the commonalities.

Figure 6 is a cross-sectional view of a nitride semiconductor device 301 according to this embodiment. As shown in Figure 6, compared to the nitride semiconductor device 1 shown in Figure 1, the nitride semiconductor device 301 has a gate opening 320 instead of the gate opening 20. The gate opening 320 differs from the gate opening 20 in that its bottom surface 320a is closer to the drain electrode 38.

Specifically, the bottom surface 320a of the gate opening 320 is located deep in the drift layer 12. Specifically, the bottom surface 320a of the gate opening 320 is provided such that the distance to the interface between the drift layer 12 and the block layer 14 in a direction perpendicular to the main surface of the substrate 10 is longer than the thickness of the electron transit layer 22 and the electron supply layer 24.

For this reason, the bottom surface of the p-type semiconductor layer 26 covering the flat portion 24a of the upper surface of the electron supply layer 24 is located below the interface between the drift layer 12 and the block layer 14. In other words, the distance D3 between the p-type semiconductor layer 26 and the drain electrode 38 is shorter than the distance D4 between the block layer 14 and the drain electrode 38.

As a result, the p-type semiconductor layer 26 can further reduce the electric field concentration during the off state, making it possible to reduce off-leakage. In addition, the p-type semiconductor layer 26 can shield the electric field lines, so the parasitic capacitance Cgd between the gate and drain can be reduced, enabling the transistor to operate at high speed.

Figure 7 is a cross-sectional view of a nitride semiconductor device 302 according to a modification of the fourth embodiment. As shown in Figure 7, compared to the nitride semiconductor device 301 shown in Figure 6, the nitride semiconductor device 302 includes a p-type semiconductor layer 226 instead of the p-type semiconductor layer 26. The p-type semiconductor layer 226 is the same as the p-type semiconductor layer 226 shown in Figure 4.

Specifically, the p-type semiconductor layer 226 continuously covers the flat portion 24a and a part of the inclined portion 24b of the upper surface of the electron supply layer 24. More specifically, the p-type semiconductor layer 226 continuously covers the entire flat portion 24a and a part of the inclined portion 24b.

As a result, the p-type semiconductor layer 226 can further alleviate the electric field concentration when the transistor is off, making it possible to reduce off-leakage. In addition, the p-type semiconductor layer 226 can shield the electric field lines, so the parasitic capacitance Cgd between the gate and drain can be reduced, enabling the transistor to operate at high speed.

The nitride semiconductor device 301 or 302 may include a threshold adjustment layer 128 instead of the threshold adjustment layer 28. This can improve the off-state breakdown voltage while reducing the parasitic capacitance Cgd between the gate and drain. This makes it possible to realize the nitride semiconductor device 301 or 302 that achieves both high-speed operation and high reliability.

Other Embodiments
Although the nitride semiconductor device according to one or more aspects has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications conceivable by a person skilled in the art to the present embodiment and forms constructed by combining components of different embodiments are also included within the scope of the present disclosure.

For example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the block layer 14 side. The donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si. Alternatively, the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations.

Furthermore, each of the above embodiments may be modified, substituted, added, omitted, etc. in various ways within the scope of the claims or their equivalents.

The nitride semiconductor devices disclosed herein are useful, for example, as power transistors used in power supply circuits, inverter circuits, etc. for equipment.

1, 101, 201, 202, 301, 302 Nitride semiconductor device 10 Substrate 12 Drift layer 14 Block layer 16 Underlayer 20, 320 Gate opening 20a, 30a, 320a Bottom surface 20b, 30b Side surface 22 Electron transit layer 24 Electron supply layer 24a Flat portion 24b Sloped portion 24c Outer edge portion 25 Two-dimensional electron gas 26, 226 P-type semiconductor layer 28, 128 Threshold adjustment layer 30 Source opening 32 Gate electrode 34 Second source electrode 36 First source electrode 38 Drain electrode

Claims (6)

A substrate;
a first nitride semiconductor layer provided above the substrate;
a first p-type nitride semiconductor layer provided above the first nitride semiconductor layer;
a second nitride semiconductor layer provided above the first p-type nitride semiconductor layer;
a first opening that penetrates the second nitride semiconductor layer and the first p-type nitride semiconductor layer and reaches the first nitride semiconductor layer;
an electron transit layer and an electron supply layer provided in this order from below so as to cover an upper surface of the second nitride semiconductor layer and a side surface and a bottom surface of the first opening;
a second p-type nitride semiconductor layer or an insulating layer provided above the electron supply layer at a position overlapping a bottom surface of the first opening in a plan view of the substrate;
a gate electrode provided above the electron supply layer at a position overlapping the second nitride semiconductor layer or the insulating layer in a plan view of the substrate;
a second opening that penetrates the electron supply layer and the electron transit layer at a position away from the gate electrode in a plan view of the substrate and reaches the first p-type nitride semiconductor layer;
a first source electrode provided to cover the second opening and electrically connected to the first p-type nitride semiconductor layer;
a drain electrode provided below the substrate;
a second source electrode provided above the second p-type nitride semiconductor layer or the insulating layer and electrically connected to the first source electrode;
Nitride semiconductor devices. a side surface of the first opening is inclined with respect to a bottom surface of the first opening,
an upper surface of the electron supply layer includes a flat portion along a bottom surface of the first opening and an inclined portion along a side surface of the first opening,
the second p-type nitride semiconductor layer or the insulating layer continuously covers the flat portion and a part of the inclined portion;
The nitride semiconductor device of claim 1 . a third p-type nitride semiconductor layer provided between the gate electrode and the electron supply layer and spaced apart from the second p-type nitride semiconductor layer or the insulating layer;
The nitride semiconductor device according to claim 1 or 2. In a plan view of the substrate, a distance between the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer is shorter than a distance between the third p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer.
The nitride semiconductor device of claim 3 . In a plan view of the substrate, a distance between the third p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer is shorter than a distance between the first p-type nitride semiconductor layer and the second p-type nitride semiconductor layer or the insulating layer.
The nitride semiconductor device of claim 3 . a distance between the second p-type nitride semiconductor layer or the insulating layer and the drain electrode is shorter than a distance between the first p-type nitride semiconductor layer and the drain electrode;
The nitride semiconductor device according to claim 1 or 2.

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