JP2024165802A - Successive approximation type AD conversion circuit - Google Patents

Abstract

To improve accuracy of A/D conversion.SOLUTION: A successive-approximation type A/D conversion circuit (1A) includes: a correction circuit (30) configured to correct a first voltage (V1) corresponding to an analog input signal or a second voltage (V2) to be compared with the first voltage; a comparator (40) configured to generate a comparison result signal by comparing two comparison input voltages obtained through the correction; and a control circuit (50) configured to determine a value of a digital output signal for each bit by binary search from a most significant bit to a least significant bit of the digital output signal on the basis of the comparison result signal. The control circuit sets a correction amount in the correction circuit for each bit of the digital output signal during a successive approximation period.SELECTED DRAWING: Figure 1

Description

This disclosure relates to a successive approximation type AD conversion circuit.

One type of AD conversion circuit is a successive approximation type AD conversion circuit that uses a binary search to perform AD conversion.

JP 2019-80292 A

Improving the accuracy of AD conversion is important in successive approximation AD conversion circuits.

The present disclosure aims to provide a successive approximation type AD conversion circuit that contributes to improving the accuracy of AD conversion (e.g., improving linearity).

The successive approximation type AD conversion circuit according to the present disclosure is a successive approximation type AD conversion circuit configured to convert an analog input signal into a digital output signal, and includes a first voltage generation circuit configured to generate a first voltage corresponding to the analog input signal, a second voltage generation circuit configured to generate a second voltage to be compared with the first voltage, a correction circuit configured to correct the first voltage or the second voltage during a successive approximation period in which a binary search is performed, a comparator configured to receive two comparison input voltages obtained through correction in the correction circuit and generate a comparison result signal by comparing the two comparison input voltages, and a control circuit configured to determine the value of the digital output signal for each bit by binary search from the most significant bit to the least significant bit of the digital output signal based on the comparison result signal, and the control circuit sets the amount of correction in the correction circuit for each bit of the digital output signal during the successive approximation period.

The present disclosure makes it possible to provide a successive approximation type AD conversion circuit that contributes to improving the accuracy of AD conversion (e.g., improving linearity).

FIG. 1 is an overall configuration diagram of an AD converter according to a first embodiment of the present disclosure. FIG. 2 is a diagram showing the internal configuration and peripheral circuits of one switch in a switch array according to the first embodiment of the present disclosure. FIG. 3 is a diagram showing four states of one switch in a switch array according to the first embodiment of the present disclosure. FIG. 4 is a diagram showing the relationship between the capacitance values of a plurality of capacitors in a capacitor array according to the first embodiment of the present disclosure. FIG. 5 is a flowchart of an AD conversion operation according to the first embodiment of the present disclosure. FIG. 6 is a diagram showing a state of the AD converter when a sampling operation is performed according to the first embodiment of the present disclosure. FIG. 7 is a flowchart of a state transition operation according to the first embodiment of the present disclosure. FIG. 8 is a diagram showing states of the AD converter involved in state transition operations according to the first embodiment of the present disclosure. FIG. 9 is a flowchart of a successive approximation operation according to the first embodiment of the present disclosure. FIG. 10 is a configuration diagram of a register in a control circuit according to the first embodiment of the present disclosure. FIG. 11 is a diagram showing a state of the AD converter when a successive approximation operation is performed according to the first embodiment of the present disclosure. FIG. 12 is a diagram illustrating a configuration example of a voltage generating circuit according to the first embodiment of the present disclosure. FIG. 13 is a diagram illustrating another configuration example of the voltage generating circuit according to the first embodiment of the present disclosure. FIG. 14 is a diagram illustrating how the voltage generated by the voltage generating circuit deviates from the ideal voltage according to the first embodiment of the present disclosure. FIG. 15 is a diagram showing the correction amount for each bit according to the first embodiment of the present disclosure. FIG. 16 is a circuit diagram of a correction circuit and its periphery according to an example EX1_1 belonging to the first embodiment of the present disclosure. FIG. 17 is a circuit diagram of a correction circuit and its periphery according to an example EX1_2 belonging to the first embodiment of the present disclosure. FIG. 18 is a circuit diagram of a correction circuit and its periphery according to an example EX1_3 belonging to the first embodiment of the present disclosure. FIG. 19 is a circuit diagram of a correction circuit in a non-correction state and its periphery according to an example EX1_3 belonging to the first embodiment of the present disclosure. FIG. 20 is an overall configuration diagram of an AD converter according to the second embodiment of the present disclosure. FIG. 21 is a diagram showing a state of the AD converter when a sampling operation is performed according to the second embodiment of the present disclosure. FIG. 22 is a circuit diagram of a correction circuit and its periphery according to an example EX2_1 belonging to the second embodiment of the present disclosure. FIG. 23 is a circuit diagram of a correction circuit and its periphery according to an example EX2_2 belonging to the second embodiment of the present disclosure. FIG. 24 is a circuit diagram of a correction circuit and its periphery according to an example EX2_3 belonging to the second embodiment of the present disclosure. FIG. 25 is a circuit diagram of a correction circuit and its periphery according to an example EX2_4 belonging to the second embodiment of the present disclosure. FIG. 26 is an overall configuration diagram of an AD converter according to a third embodiment of the present disclosure. FIG. 27 is a flowchart of a successive approximation operation according to the third embodiment of the present disclosure. FIG. 28 is a circuit diagram of a correction circuit and its periphery according to an example EX3_1 belonging to the third embodiment of the present disclosure. FIG. 29 is a circuit diagram of a correction circuit and its periphery according to an example EX3_2 belonging to the third embodiment of the present disclosure.

Hereinafter, examples of the embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are omitted as a general rule. In this specification, for the sake of simplicity, a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, etc. may be written, and the name of the information, signal, physical quantity, functional part, circuit, element, or part, etc. corresponding to the symbol or code may be omitted or abbreviated. For example, the comparison wiring referred to by "WR1" described later (see FIG. 1) may be written as the comparison wiring WR1 or may be abbreviated as the wiring WR1, but they all refer to the same thing. In this specification, a connection between multiple parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified.

First Embodiment
A first embodiment of the present disclosure will be described. FIG. 1 shows an overall configuration of an AD converter 1A according to the first embodiment of the present disclosure. The AD converter 1A is a successive approximation type A/D conversion circuit. An analog input signal Ain is input to the AD converter 1A. The AD converter 1A performs an AD conversion operation on the analog input signal Ain. In the AD conversion operation on the analog input signal Ain, the analog input signal Ain is converted into a digital signal by a binary search, and the obtained digital signal is output as a digital output signal Dout.

The digital output signal Dout is an N-bit digital signal. That is, the digital output signal Dout has a total of N bits, from the first bit to the Nth bit. N is any integer equal to or greater than 2, for example, 8, 10, 12, 14, or 16. Here, the (i+1)th bit is considered to be the most significant bit when viewed from the ith bit. Therefore, of the first to Nth bits, the first bit is the least significant bit, and the Nth bit is the most significant bit. i represents any integer, and may be interpreted as representing a natural number equal to or less than N.

The AD converter 1A includes a DAC 10, a voltage generating circuit 20, a correction circuit 30, a comparator 40, a control circuit 50, and a switch S _G. The wiring WR_Ain is an analog input wiring to which an analog input signal Ain is applied. The wiring WR_VDD is a power supply wiring to which a predetermined power supply voltage VDD is applied. The wiring WR_GND is connected to the ground. The ground refers to a reference conductive part having a reference potential of 0V (zero volts) or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as metal. The wiring WR_GND is a ground wiring to which a ground voltage is applied. The wiring WR_GND itself may be considered to be the ground. The ground voltage has the potential of the ground, and is therefore 0V. The power supply voltage VDD has a positive DC voltage value (for example, 5V). The analog input signal Ain has a voltage value of 0V or more and less than the power supply voltage VDD.

DAC10 is an example of a first voltage generating circuit. DAC10 is a capacitor-type DAC (capacitor-type digital-to-analog converter). Capacitor-type DACs are also commonly referred to as capacitive DACs. DAC10 includes a capacitor array 11 and a switch array 12. Capacitor array 11 includes capacitors C[1] to C[N], and switch array 12 includes switches S[1] to S[N].

Each of the capacitors C[1] to C[N] has a first end and a second end, and accumulates electric charge between the first end and the second end. In the configuration of FIG. 1, the first ends of the capacitors C[1] to C[N] are all connected to the comparison wiring WR1. Switches S[1] to S[N] are provided corresponding to the capacitors C[1] to C[N], respectively. That is, a switch S[i] is provided corresponding to the capacitor C[i]. Furthermore, the capacitor C[i] corresponds to the i-th bit of the digital output signal Dout. The analog input signal Ain, the power supply voltage VDD, or the ground voltage can be applied to the second ends of the capacitors C[1] to C[N] via the switches S[1] to C[N]. The voltage on the comparison wiring WR1 is referred to as voltage V1. The DAC 10 generates a voltage V1 according to the analog input signal Ain, and outputs the voltage V1 to the comparison wiring WR1.

FIG. 2 shows the connection relationship between the capacitor C[i], the switch S[i], and the wiring WR_Ain, WR_VDD, and WR_GND. Each of the switches S[1] to S[N] has a common terminal T _COM and switching terminals Ta, Tb, and Tc. The common terminals T _COM of the switches S[1] to S[N] are connected to the second ends of the capacitors C[1] to C[N], respectively. That is, for example, the common terminal T _COM of the switch S[1] is connected to the second end of the capacitor C[1], and the common terminal T _COM of the switch S[2] is connected to the second end of the capacitor C[2]. The same is true for the switch S[3], etc. Each switching terminal Ta of the switches S[1] to S[N] is connected to the wiring WR_Ain and receives the analog input signal Ain. Each switching terminal Tb of the switches S[1] to S[N] is connected to the wiring WR_VDD and receives the power supply voltage VDD. Each switching terminal Tc of the switches S[1] to S[N] is connected to a wiring WR_GND and receives the ground voltage.

Under the control of the control circuit 50, in each of the switches S[1] to S[N], the common terminal T _COM is selectively connected to one of the switching terminals Ta, Tb, and Tc. However, in the switch S[i], the common terminal T _COM may not be connected to any of the switching terminals Ta, Tb, and Tc.

3, in the following, in any switch S[i], the states in which the common terminal T _COM is connected to the switching terminals Ta, Tb, and Tc are referred to as a signal input state, a power supply connection state, and a ground connection state, respectively, and the states in which the common terminal T _COM is not connected to any of the switching terminals Ta, Tb, and Tc are referred to as an open state. In the signal input state, power supply connection state, and ground state of the switch S[i], the analog input signal Ain, the power supply voltage VDD, and the ground voltage are respectively applied to the second end of the capacitor C[i]. Note that, as an example, FIG. 1 shows a state in which all of the switches S[1] to S[N] are in the signal input state.

Referring again to FIG. 1, the first end of the switch S _G is connected to the comparison wiring WR1, and a predetermined reference voltage V _REF is applied to the second end of the switch S _G. The reference voltage V _REF has a fixed potential. The reference voltage V _REF may have a positive DC voltage value. The voltage V2 generated by the voltage generating circuit 20 may be the reference voltage V _REF . The reference voltage V _REF may be 0 V. The switch S _G is controlled to an on state or an off state by the control circuit 50. The on state and the off state may be simply expressed as on and off, respectively, hereinafter. When the switch S _G is on, the first end and the second end of the switch S _G are conductive, and the voltage V1 of the comparison wiring WR1 is fixed to the reference voltage V _REF . When the switch S _G is off, the first end and the second end of the switch S _G are cut off (non-conductive). Note that FIG. 1 shows, as an example, a state in which the switch S _G is off.

Each of the switches S[1] to [N] and S _G can be configured with any switching element such as a MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". The switches S[1] to [N] may be multiplexers. Note that with respect to any switch, the control circuit 50 controlling the switch to a certain focused state is synonymous with the control circuit 50 setting the state of the switch to the focused state.

The voltage generating circuit 20 is an example of a second voltage generating circuit. The voltage generating circuit 20 generates a voltage V2 to be compared with the voltage V1, and outputs the generated voltage V2 to the comparison wiring WR2.

The correction circuit 30 can execute a voltage correction process under the control of the control circuit 50. In the voltage correction process, the correction circuit 30 corrects the voltage V1 generated by the DAC 10 or corrects the voltage V2 generated by the voltage generation circuit 20. In the following, for the sake of concrete explanation, the voltage V1 not corrected by the correction circuit 30 is referred to as the original voltage V1, and the voltage V1 after correction by the correction circuit 30 is referred to as the corrected voltage V1. Similarly, the voltage V2 not corrected by the correction circuit 30 is referred to as the original voltage V2, and the voltage V2 after correction by the correction circuit 30 is referred to as the corrected voltage V2.

The comparator 40 has an inverting input terminal, a non-inverting input terminal, and an output terminal. A voltage Vin1, which is a first comparison input voltage, is supplied to the inverting input terminal of the comparator 40, and a voltage Vin2, which is a second comparison input voltage, is supplied to the non-inverting input terminal of the comparator 40. The voltage Vin1 is the source voltage V1 or the correction voltage V1. The voltage Vin2 is the source voltage V2 or the correction voltage V2.

The comparator 40 compares the voltages Vin1 and Vin2, and generates and outputs a comparison result signal S _CMP indicating the comparison result (high/low relationship) of the voltages Vin1 and Vin2. The comparison result signal S _CMP is a binary signal having a value of "0" or "1." It is also possible to modify the comparator 40 so that the voltage Vin1 is supplied to the non-inverting input terminal and the voltage Vin2 is supplied to the inverting input terminal of the comparator 40.

The comparator 40 outputs a comparison result signal S _CMP having a value of "1" from its output terminal when "Vin1<Vin2" is true, and outputs a comparison result signal S _CMP having a value of "0" from its output terminal when "Vin1>Vin2" is true. When "Vin1=Vin2" is true, the comparison result signal S _CMP has a value of "0" or "1.""Vin1>Vin2" indicates that the voltage Vin1 is higher than the voltage Vin2, and "Vin1<Vin2" indicates that the voltage Vin1 is lower than the voltage Vin2. The same applies to other equations that include physical quantities such as voltages.

The control circuit 50 receives the comparison result signal S _CMP . The control circuit 50 controls the overall AD conversion operation and outputs a digital output signal Dout obtained by the AD conversion operation. The control circuit 50 is provided with a register 51, and the value of the digital output signal Dout can be stored in the register 51. The control circuit 50 controls the states of the switches S[1] to S[N] individually by supplying a control signal CNT _DAC (DAC input signal) to the DAC 10. The control circuit 50 controls the state of the switch S _G by supplying a control signal CNT _G to the switch S _G. The control circuit 50 is further provided with a correction control unit 52. The correction control unit 52 controls the execution of the voltage correction process by the correction circuit 30 (details will be described later).

In the DAC 10 of Figure 1, for any integer i, the capacitance value of the capacitor C[i+1] is greater than the capacitance value of the capacitor C[i]. Here, as shown in Figure 4, it is assumed that the capacitor C[i] in the DAC 10 has a capacitance value of "2 ^i-1 ·C _UNT ". Therefore, in the DAC 10 of Figure 1, for any integer i, the capacitance value of the capacitor C[i+1] is twice the capacitance value of the capacitor C[i]. _{C UNT} represents a predetermined unit capacitance value.

Figure 5 shows a flowchart of the AD conversion operation. In the AD conversion operation, first, a sampling operation is performed in step S1, then a state transition operation is performed in step S2, followed by a successive approximation operation in step S3, and finally a result output operation in step S4. Hereinafter, the period during which the sampling operation is performed is referred to as the sampling period, and the period during which the successive approximation operation is performed is referred to as the successive approximation period. The voltage correction process functions effectively when the successive approximation operation is performed, and therefore the correction control unit 52 causes the correction circuit 30 to perform the voltage correction process in the successive approximation period. In steps S1, S2, and S4, the correction control unit 52 does not cause the correction circuit 30 to perform the voltage correction process (however, it may sometimes cause the correction circuit 30 to perform the voltage correction process).

6 shows the state of the AD converter 1A during a sampling period. The sampling period has a predetermined length of time. During the sampling period, the control circuit 50 controls all the switches S[1] to S[N] in the DAC 10 to a signal input state, and controls the switch _S to be on.

During the sampling period, the wiring WR_Ain is connected to the capacitor array 11 via the switch array 12, and electric charges corresponding to the analog input signal Ain are accumulated in each capacitor (C[1] to C[N]) in the capacitor array 11. Since the switch _SG is controlled to be on during the sampling period, each capacitor in the capacitor array 11 is charged by the analog input signal Ain with reference to the reference voltage _VREF . Note that the operation of the voltage generating circuit 20 and the comparator 40 may be stopped during the sampling period.

FIG. 7 shows an example of the flow of the state transition operation in step S2. In the example of FIG. 7, the operations of steps S21, S22, and S23 are executed in this order in the state transition operation. However, the operations of steps S21 and S22 may be executed simultaneously. In step S21, the state of all the switches S[1] to S[N] of the DAC 10 is switched from a signal input state to an open state. In step S22, the state of the switch S _G is switched from on to off. After step S22, the switch S _G is maintained in the off state until the successive approximation operation in step S3 is completed. In step S23, the state of the switches S[1] to S[N] of the DAC 10 is switched to a power supply connection state or a ground connection state.

Figure 8 shows the state of the AD converter 1A after steps S21 to S23. In the example of Figure 8, it is assumed that the states of the switches S[1] to S[N] of the DAC 10 are all switched to the ground connection state in step S23. Note that the operation of step S23 may be omitted.

Figure 9 shows a flowchart of the successive approximation operation in step S3. Figure 10 shows the structure of register 51 (see Figure 1). Register 51 has a storage capacity of N bits and stores values Rg[1] to Rg[N]. Each of values Rg[1] to Rg[N] is either "0" or "1". For any integer i, value Rg[i+1] is the value of the most significant bit of value Rg[i]. In the successive approximation operation, values Rg[1] to Rg[N] are determined bit by bit from the most significant bit side, and the determined value Rg[i] becomes the value of the i-th bit in digital output signal Dout.

During the successive approximation period, the switches S[1] to S[N] are individually set to a power supply connection state or a ground connection state. The charge stored in the capacitor array 11 during the sampling period is distributed to the capacitors C[1] to C[N] during the successive approximation period. The state of distribution depends on the state of the switches S[1] to S[N] during the successive approximation period, and therefore the voltage V1 changes depending on the state of the switches S[1] to S[N] during the successive approximation period. In the successive approximation operation (in other words, during the successive approximation period), the control circuit 50 determines the values Rg[1] to Rg[N] (i.e., the value of the digital output signal Dout) for each bit while sequentially switching the state of the switch array 12 by binary search based on the comparison result signal S _CMP .

In the successive approximation operation of Fig. 9, first, in step S30, a value of N is substituted for a variable j managed by the control circuit 50. Then, the process proceeds to step S31. In step S31, the correction control unit 52 causes the correction circuit 30 to execute a voltage correction process. At this time, the correction control unit 52 sets a correction amount ΔV _C in the correction circuit 30 for each bit of the digital output signal Dout. The correction amount ΔV _C is a voltage amount. The correction amount used in the voltage correction process when determining the value of the j-th bit in the digital output signal Dout is particularly referred to as the correction amount ΔV _C [j]. In the first step S31, "j = N", so the voltage correction process is executed using the correction amount ΔV _C [N].

The correction amount ΔV _C [j] may have a positive voltage value or a negative voltage value. The correction amounts ΔV _C [N] to ΔV _C [1] may be different from each other, or some of the correction amounts ΔV _C [N] to ΔV _C [1] may have the same value. However, at least two or more correction amounts having different values are included in the correction amounts ΔV _C [N] to ΔV _C [1].

When the voltage V1 is corrected by the voltage correction process, the correction voltage V1 is generated by adding the correction amount ΔV _C [j] to the original voltage V1 (i.e., the sum of the original voltage V1 and the correction amount ΔV _C [j] is generated as the correction voltage V1), and the correction voltage V1 is supplied as voltage Vin1 to the inverting input terminal of the comparator 40, and the original voltage V2 is supplied as voltage Vin2 to the non-inverting input terminal of the comparator 40. When the voltage V2 is corrected by the voltage correction process, the correction voltage V2 is generated by adding the correction amount ΔV _C [j] to the original voltage V2 (i.e., the sum of the original voltage V2 and the correction amount ΔV _C [j] is generated as the correction voltage V2), and the correction voltage V2 is supplied as voltage Vin2 to the non-inverting input terminal of the comparator 40, and the original voltage V1 is supplied as voltage Vin1 to the inverting input terminal of the comparator 40.

After step S31, the process proceeds to step S32. In step S32, the control circuit 50 controls switch S[j] to a power supply connected state and controls switches S[1] to S[j-1] to all be connected to ground. However, when the process of step S32 is executed in the state of "j=1", switches S[1] to S[j-1] do not exist, so in step S32, switch S[1] is simply controlled to be in a power supply connected state. As an example, FIG. 11 shows the state of each switch in step S32 when "j=N".

In step S33 following step S32, the control circuit 50 acquires the value of the current comparison result signal S _CMP (i.e., acquires the value of the comparison result signal S _CMP output from the comparator 40 in the state of the most recent step S32). If the acquired value is "1" (Y in step S33), the process proceeds to step S34, where the control circuit 50 performs the processes of steps S34 and S35, whereas if the acquired value is "0" (N in step S33), the process proceeds to step S36, where the control circuit 50 performs the processes of steps S36 and S37.

In step S34, the control circuit 50 determines the value Rg[j] to be "1". In the following step S35, the control circuit 50 maintains the switch S[j] in a power supply connected state. Thereafter, the switch S[j] is maintained in a power supply connected state until the successive comparison operation in FIG. 9 is completed. That is, for example, when step S35 is reached with "j=N" held, the switch S[N] is maintained in a power supply connected state until the successive comparison operation in FIG. 9 is completed. The same is true when step S35 is reached with "j=N-1" held. After step S35, the process proceeds to step S38. Since nothing is actually executed in step S35, step S35 may be omitted.

In step S36, the control circuit 50 determines the value Rg[j] to be "0". In the following step S37, the control circuit 50 switches the state of the switch S[j] from the power supply connected state to the ground connected state. Thereafter, the switch S[j] is maintained in the ground connected state until the successive comparison operation of FIG. 9 is completed. That is, for example, when step S37 is reached with "j=N" held, the switch S[N] is maintained in the ground connected state until the successive comparison operation of FIG. 9 is completed. The same applies when step S37 is reached with "j=N-1" held. After step S37, proceed to step S38.

In step S38, the control circuit 50 checks whether the variable j is 1. If the variable j is not 1 (N in step S38), the process proceeds to step S39, where 1 is subtracted from the variable j, and the process returns to step S31 to repeat the process from step S31 onward. For example, in the second process of step S31, the correction amount used in the voltage correction process is switched from the correction amount ΔV _C [N] to the correction amount ΔV _C [N-1], and in the third process of step S31, the correction amount used in the voltage correction process is switched from the correction amount ΔV _C [N-1] to the correction amount ΔV _C [N-2]. The same applies to step S31 from the fourth time onward. Also, for example, in the second process of step S32, the switch S[N-1] is set to a power supply connection state, and the switches S[1] to S[N-1] are set to a ground connection state. At this time, if "S _CMP = 1" is determined in step S33 for the first time, the switch S[N] is set to a power supply connection state in step S32 for the second time, and if "S _CMP = 0" is determined in step S33 for the first time, the switch S[N] is set to a ground connection state in step S32 for the second time. The same applies to steps S32 for the third time and thereafter.

The process consisting of steps S31 to S37 is referred to as a unit comparison operation. In this case, the successive comparison operation includes the first to Nth unit comparison operations. The unit comparison operation executed when "j=N" is the Nth unit comparison operation, the unit comparison operation executed when "j=N-1" is the (N-1)th unit comparison operation, ..., the unit comparison operation executed when "j=1" is the first unit comparison operation. In the jth unit comparison operation, the value Rg[j] is determined, that is, the value of the jth bit of the digital output signal Dout is determined.

If "j=1" in step S38 (Y in step S38), the successive approximation operation in FIG. 9 ends. At this stage, all values Rg[1] to Rg[N] have been determined.

In the result output operation of step S4 (see FIG. 5), the control circuit 50 outputs a digital signal having values Rg[1] to Rg[N] determined in the successive approximation operation of step S3 as a digital output signal Dout. The digital output signal Dout is output to any circuit (not shown) that uses the digital output signal Dout. The result output operation of step S4 may be started while the successive approximation operation of step S3 is being performed. That is, as soon as the value Rg[N] is determined in the successive approximation operation, the control circuit 50 may output the value Rg[N] in the digital output signal Dout. Similarly, as soon as the value Rg[N-1] is determined in the successive approximation operation, the control circuit 50 may output the value Rg[N-1] in the digital output signal Dout. The same applies to the values Rg[N-2] to Rg[1].

12, the voltage generating circuit 20 may be a reference voltage source 20_1 that generates and outputs a predetermined reference voltage as a voltage V2. In this case, the output terminal of the reference voltage source 20_1 is connected to the comparison wiring WR2, and the reference voltage source 20_1 outputs the voltage V2 to the comparison wiring WR2. The voltage V2 output from the reference voltage source 20_1 is the source voltage V2. The voltage V2 output from the reference voltage source 20_1 may be used as the reference voltage _VREF .

Alternatively, as shown in FIG. 13, the voltage generating circuit 20 may be a DAC 20_2 which is a DA conversion circuit (digital-analog converter). In this case, a digital signal Din is input to the DAC 20_2. The DAC 20_2 converts the digital signal Din into an analog signal, and outputs the obtained analog signal (analog voltage signal) as a voltage V2 to the comparison wiring WR2. The DAC 20_2 may be, for example, an R-2R ladder type DA conversion circuit. The voltage V2 output from the DAC 20_2 is the source voltage V2. The digital signal Din is supplied to the DAC 20_2 from the control circuit 50, or is supplied to the DAC 20_2 from an external circuit (not shown) of the AD converter 1A. Basically, the digital signal Din is unchanged. However, the digital signal Din may be changed. The voltage V2 output from the DAC 20_2 may be used as the reference voltage V _REF .

During the successive approximation period, the voltage V2 (source voltage V2) output from the voltage generating circuit 20 fluctuates from the ideal voltage V _IDEAL due to various fluctuation factors, such as current generation accompanying switching of each switch and changes in the drive current of the AD converter 1A. The value of the ideal voltage V _IDEAL corresponds to the design value of the voltage V2 (source voltage V2) output from the voltage generating circuit 20. The fluctuation from the ideal voltage V _IDEAL is a factor of deterioration of the accuracy (deterioration of linearity) in the AD conversion. The direction and magnitude of the fluctuation change in various ways even during the successive approximation period. Specifically, the direction and magnitude of the fluctuation differ between the execution period of a certain unit comparison operation and the execution period of another unit comparison operation among the first to Nth unit comparison operations. For example, during the execution period of the Nth unit comparison operation, the source voltage V2 is 1 mV higher than the ideal voltage V _IDEAL , whereas during the execution period of the (N-1)th unit comparison operation, the source voltage V2 is 2 mV lower than the ideal voltage V _IDEAL .

The solid polygonal line 610 in FIG. 14 represents various changes in the direction and magnitude of fluctuation of the source voltage V2 as viewed from the ideal voltage V _IDEAL during the execution period of the eighth unit comparison operation (the period for determining the value of the eighth bit of the digital output signal Dout), the execution period of the seventh unit comparison operation, ..., the execution period of the first unit comparison operation.

On the other hand, the direction and magnitude of the fluctuation from the ideal voltage V _IDEAL have a roughly constant tendency depending on the circuit pattern of the AD converter 1A, etc. Therefore, it is possible to evaluate them through experiments, etc., and to determine an appropriate correction amount in advance based on the evaluation results. That is, for example, if it is known that the source voltage V2 is higher than the ideal voltage V _IDEAL by a positive offset voltage ΔV _OFFSET during the execution period of the Nth unit comparison operation, when "j=N" during the successive comparison operation in FIG. 9, a voltage correction process of subtracting the offset voltage ΔV _OFFSET from the source voltage V2 or a voltage correction process of adding the offset voltage ΔV _OFFSET to the source voltage V1 may be executed. The same applies to the (N-1)th to first unit comparison operations.

In practice, it is preferable to provide a non-volatile memory (not shown) storing the correction amount information in the correction control unit 52. The correction amount information is information for specifying the correction amounts ΔV _C [N] to ΔV _C [1], and the correction control unit 52 realizes the process of step S31 by controlling the correction circuit 30 based on the correction amount information. In the design stage of the AD converter 1A, it is preferable to evaluate the offset voltage ΔV _OFFSET for each bit and determine the correction amount information based on the evaluation result.

A solid line 620 in Fig. 15 represents an example of the correction amount ΔV _C specified by the correction amount information. However, the correction amount ΔV _C according to the solid line 620 is a correction amount to be added to the real voltage V2 represented by the solid line 610 in Fig. 14. In other words, by adding the correction amount ΔV _C represented by the solid line 620 in Fig. 15 to the real voltage V2 represented by the solid line 610 in Fig. 14, a correction voltage V2 that coincides with the ideal voltage V _IDEAL can be obtained. Alternatively, the polarity of the correction amount ΔV _C according to the solid line 620 may be inverted and added to the real voltage V1. In any case, the influence of the offset voltage ΔV _OFFSET is offset by the voltage correction process.

The first embodiment includes the following Examples EX1_1 to EX1_3. Unless otherwise specified and unless there is a contradiction, the matters described above in the first embodiment are applied to the following Examples EX1_1 to EX1_3. However, in each example, for matters that contradict the matters described above in the first embodiment, the description in each example may take precedence.

[Example EX1_1]
An example EX1_1 will be described. Fig. 16 is a partial configuration diagram of an AD converter 1A according to the example EX1_1. In the example EX1_1, a correction circuit 30A_1 is used as the correction circuit 30. The correction circuit 30A_1 corrects the voltage V1 generated by the DAC 10 in the voltage correction process. Therefore, in the example EX1_1, in the successive approximation period, the voltage Vin1 is the correction voltage V1, and the voltage Vin2 is the source voltage V2.

The correction circuit 30A_1 may be an adder inserted in series between the wiring WR1 and the inverting input terminal of the comparator 40. In this case, during the execution period of the jth unit comparison operation (see FIG. 9), the correction circuit 30A_1 generates the correction voltage V1 by adding the correction amount ΔV _C [j] to the source voltage V1 output from the DAC 10 (i.e., the sum of the source voltage V1 and the correction amount ΔV _C [j] is generated as the correction voltage V1). During the execution period of the jth unit comparison operation, if "ΔV _C [j]>0", the correction voltage V1 becomes higher than the source voltage V1 by the amount of the correction amount ΔV _C [j], and if "ΔV _C [j]<0", the correction voltage V1 becomes lower than the source voltage V1 by the amount of the correction amount ΔV _C [j]. The correction control unit 52 controls the correction circuit 30A_1 during the execution period of the jth unit comparison operation to set the correction amount ΔV _C [j] as desired.

[Example EX1_2]
An example EX1_2 will be described. Fig. 17 is a partial configuration diagram of an AD converter 1A according to the example EX1_2. In the example EX1_2, a correction circuit 30A_2 is used as the correction circuit 30. The correction circuit 30A_2 corrects the voltage V2 generated by the voltage generation circuit 20 in the voltage correction process. Therefore, in the example EX1_2, in the successive approximation period, the voltage Vin1 is the source voltage V1, and the voltage Vin2 is the correction voltage V2.

The correction circuit 30A_2 may be an adder inserted in series between the wiring WR2 and the non-inverting input terminal of the comparator 40. In this case, during the execution period of the j-th unit comparison operation (see FIG. 9), the correction circuit 30A_2 generates the correction voltage V2 by adding the correction amount ΔV _C [j] to the source voltage V2 output from the voltage generating circuit 20 (i.e., the sum of the source voltage V2 and the correction amount ΔV _C [j] is generated as the correction voltage V2). During the execution period of the j-th unit comparison operation, if "ΔV _C [j]>0", the correction voltage V2 becomes higher than the source voltage V2 by the amount of the correction amount ΔV _C [j], and if "ΔV _C [j]<0", the correction voltage V2 becomes lower than the source voltage V2 by the amount of the correction amount ΔV _C [j]. The correction control unit 52 sets the correction amount ΔV _C [j] as desired by controlling the correction circuit 30A_2 during the execution period of the j-th unit comparison operation.

[Example EX1_3]
An example EX1_3 will be described. Fig. 18 is a partial configuration diagram of an AD converter 1A according to the example EX1_3. In the example EX1_3, a correction circuit 30A_3 is used as the correction circuit 30. The correction circuit 30A_3 corrects the voltage V1 generated by the DAC 10 in the voltage correction process. Therefore, in the example EX1_3, in the successive approximation period, the voltage Vin1 is the correction voltage V1, and the voltage Vin2 is the source voltage V2.

The correction circuit 30A_3 includes M correction unit circuits U _C. Each correction unit circuit U _C includes a correction capacitor C _C and a correction switch S _C. M represents any integer of 2 or more. Usually, M has an integer value of 3 or more, or M has an integer value of 4 or more. The M correction unit circuits U _C are composed of correction unit circuits U _C [1] to U _C [M]. The correction capacitor C _C and the correction switch S _C in the correction unit circuit U _C [i] are referred to as the correction capacitor C _C [i] and the correction switch S _C [i], respectively. The correction unit circuits U _C [1] to U _C [M] have the same configuration. However, the correction capacitors C _C [1] to C _C [M] may include two or more capacitors with different capacitance values, and the capacitance values of the correction capacitors C _C [1] to C _C [M] may all be different from each other.

In the correction circuit 30A_3, the first terminals of the correction capacitors C _C [1] to C _C [M] are connected to the comparison wiring WR1. The correction switch S _C [i] is connected to the power supply wiring WR_VDD and the ground wiring WR_GND and is also connected to the second terminal of the correction capacitor C _C [i], and supplies the power supply voltage VDD or the ground voltage to the second terminal of the correction capacitor C _C [i]. The state of the correction switch S _C [i] is switched between a state in which the power supply voltage _VDD is provided to the second terminal of the correction capacitor C _C [i] (hereinafter referred to as a high-side state) and a state in which the ground voltage is provided to the second terminal of the correction capacitor C _C [i] (hereinafter referred to as a low-side state) according to a control signal CNT C provided from the correction control unit 52 to the correction circuit 30A_3.

The correction control unit 52 provides a control signal CNT _C to the correction circuit 30A_3 to set the states of the correction switches S _C [1] to S _C [M] individually to the high side state or the low side state, thereby controlling, for each correction capacitor C _C , whether the power supply voltage VDD or the ground voltage is supplied to the second terminal of the correction capacitor C _C. In FIG. 18, as an example, a state in which the power supply voltage VDD is supplied to each second terminal of the correction capacitors C _C [1] to C _C [M] is illustrated.

In the sampling period, the correction control unit 52 sets the correction circuit 30A_3 to a non-correction state, which is a reference state. Setting the correction circuit 30A_3 to a non-correction state means setting the states of the correction switches S _C [1] to S _C [M] in the correction circuit 30A_3 to a non-correction state. As shown in FIG. 19, in the non-correction state, among the correction switches S _C [1] to S _C [M], the correction switches S _C [1] to S _C [M _HF ] are set to a low-side state and the correction switches S _C [M _HF +1] to S _C [M] are set to a high-side state. M _HF represents a natural number smaller than M. When M is an even number, "M _HF =M/2" may be satisfied. When M is an odd number, "M _HF =(M+1)/2" or "M _HF =(M-1)/2" may be satisfied. During the sampling period, the switch S _G is turned on, so that charges corresponding to the difference between the reference voltage V _REF and the ground voltage are stored in the correction capacitors C _C [1] to C _C [M _HF ], and charges corresponding to the difference between the reference voltage V _REF and the power supply voltage VDD are stored in the correction capacitors C _C [M _HF +1] to C _C [M] (the manner in which these charges are stored is not shown).

When the switch S _G is off, for an integer i that satisfies "1≦i≦M _HF ," if the correction switch S _C [i] is switched from a low-side state to a high-side state (i.e., if the voltage supplied to the second end of the correction capacitor C _C [i] is switched from the ground voltage to the power supply voltage VDD), the voltage V1 in the comparison wiring WR1 rises, and the magnitude of the rise depends on the capacitance value of the correction capacitor C _C [i]. When the switch S _G is off, for an integer i that satisfies "M _HF +1≦i≦M," if the correction switch S _C [i] is switched from a high-side state to a low-side state (i.e., if the voltage supplied to the second end of the correction capacitor C _C [i] is switched from the power supply voltage VDD to the ground voltage), the voltage V1 in the comparison wiring WR1 falls, and the magnitude of the fall depends on the capacitance value of the correction capacitor C _C [i].

The state in which the correction circuit 30A_3 is in the non-correction state corresponds to a state in which the voltage correction process by the correction circuit 30A_3 is not being performed. During the successive approximation period, the correction control unit 52 changes the state of the correction circuit 30A_3 from the non-correction state to realize the voltage correction process for the voltage V1.

That is, when "ΔV _C [j]>0" in the jth unit comparison operation (see FIG. 9), the correction control unit 52 sets the correction switches S _C [1] to S _{C [M] individually to the low-side state or the high-side state so that the potential of the comparison wiring WR1 increases by the magnitude of the correction amount ΔV C [j] compared to when the correction circuit 30A_3 is set to the non-correction state. For example, when "ΔV C [} j]>0" in the jth unit comparison operation, the correction control unit 52 switches one or more of the correction switches S _C [1] to S _C [M _HF ] from the low-side state to the high-side state according to the magnitude of the correction amount ΔV _C [j], starting from the non-correction state.

Conversely, when "ΔV _C [j]<0" in the jth unit comparison operation (see FIG. 9), the correction control unit 52 sets the correction switches S _C [1] to S _{C [M] individually to the low-side state or the high-side state so that the potential of the comparison wiring WR1 decreases by the magnitude of the correction amount ΔV C [j] compared to when the correction circuit 30A_3 is set to the non-correction state. For example, when "ΔV C [} j]<0" in the jth unit comparison operation, the correction control unit 52 switches one or more of the correction switches S _C [M _HF +1] to S _C [M] from the high-side state to the low-side state according to the magnitude of the correction amount ΔV _C [j], starting from the non-correction state.

<<Second embodiment>>
The second embodiment of the present disclosure will be described. The second embodiment and the third embodiment described later are based on the first embodiment, and for matters not specifically described in the second and third embodiments, the description of the first embodiment also applies to the second and third embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence over any matters that contradict between the first and second embodiments (the same applies to the third embodiment described later).

The configuration and operation of the AD converter 1A shown in the first embodiment may be applied to an AD converter having a differential input configuration. The overall configuration of an AD converter 1B to which this application is applied is shown in FIG. 20. The AD converter 1B is a successive approximation type A/D conversion circuit, similar to the AD converter 1A. Analog input signals AinP and AinN are input to the AD converter 1B. The AD converter 1B performs AD conversion operation on a difference signal ADif between the analog input signals AinP and AinN. The difference signal ADif is an analog signal having the potential of the analog input signal AinP as viewed from the potential of the analog input signal AinN.

In the AD conversion operation for the difference signal Adif, the difference signal Adif is converted into a digital signal by a binary search, and the obtained digital signal is output as the digital output signal Dout. The digital output signal Dout is an N-bit digital signal, as in the first embodiment. The voltage of the analog input signal AinN may be the ground voltage, in which case the difference voltage Adif is equivalent to the analog input signal AinP. Alternatively, the analog input signal AinN may have another fixed potential different from 0 V.

Further alternatively, the analog input signal AinN may be a signal that fluctuates to either the high potential side or the low potential side as viewed from the potential of the analog input signal AinP. In this case, when "AinP = AinN", the digital output signal Dout has a predetermined intermediate value, and when "AinP > AinN", the value of the digital output signal Dout increases from the intermediate value as the magnitude of the difference signal Adif increases, and when "AinP < AinN", the value of the digital output signal Dout decreases from the intermediate value as the magnitude of the difference signal Adif increases.

The AD converter 1B has two voltage generation blocks. Each voltage generation block in the AD converter 1B has the DAC 10 and the switch S _G described in the first embodiment. The configuration of the DAC 10 and the switch S _G in each voltage generation block is the same as the configuration of the DAC 10 and the switch S _G described in the first embodiment. Therefore, in each voltage generation block, the DAC 10 has a capacitor array 11 consisting of capacitors C[1] to C[N] and a switch array 12 consisting of switches S[1] to S[N]. The connection relationship between the capacitors C[1] to C[N] and the switches S[1] to S[N] in each voltage generation block is the same as the connection relationship between the capacitors C[1] to C[N] and the switches S[1] to S[N] in the first embodiment.

In the following, of the two voltage generation blocks provided in the AD converter 1B, the DAC 10 and the switch S _G provided in one voltage generation block will be referred to as DAC 10P and switch S _GP , respectively, and the DAC 10 and the switch S _G provided in the other voltage generation block will be referred to as DAC 10N and switch S _GN , respectively. In addition to the two voltage generation blocks, the AD converter 1B is provided with a correction circuit 30, a comparator 40, and a control circuit 50.

In the AD converter 1B, the wiring WR_AinP is an analog input wiring to which the analog input signal AinP is applied, and the wiring WR_AinN is an analog input wiring to which the analog input signal AinN is applied. As in the first embodiment, the wiring WR_VDD is a power supply wiring to which a predetermined power supply voltage VDD is applied, and the wiring WR_GND is a ground wiring to which a ground voltage is applied. The analog input signals AinP and AinN correspond to the analog input signals Ain for the DACs 10P and 10N, respectively.

In the configuration of FIG. 20, the first ends of the capacitors C[1] to C[N] of DAC 10P are all connected to the comparison wiring WR1, and the first ends of the capacitors C[1] to C[N] of DAC 10N are all connected to the comparison wiring WR2. As in the first embodiment, the voltage in the comparison wiring WR1 is voltage V1 and the voltage in the comparison wiring WR2 is voltage V2. In each of DACs 10P and 10N, a switch S[i] is provided corresponding to the capacitor C[i]. In each of DACs 10P and 10N, the capacitor C[i] corresponds to the i-th bit in the digital output signal Dout.

Each of the switches S[1] to S[N] has a common terminal T _COM and switching terminals Ta, Tb, and Tc (see FIG. 2). In each of the DACs 10P and 10N, the common terminal T _COM of the switch S[i] is connected to the second end of the capacitor C[i]. Each of the switching terminals Ta of the switches S[1] to S[N] in the DAC 10P is connected to the wiring WR_AinP to receive the analog input signal AinP. Therefore, in the DAC 10P, in the signal input state of the switch S[i], the analog input signal AinP is applied to the second end of the capacitor C[i]. Each of the switching terminals Ta of the switches S[1] to S[N] in the DAC 10N is connected to the wiring WR_AinN to receive the analog input signal AinN. Therefore, in the DAC 10N, in the signal input state of the switch S[i], the analog input signal AinN is applied to the second end of the capacitor C[i]. In each of the DACs 10P and 10N, the switching terminals Tb of the switches S[1] to S[N] are connected to the wiring WR_VDD and receive the power supply voltage VDD. In each of the DACs 10P and 10N, the switching terminals Tc of the switches S[1] to S[N] are connected to the wiring WR_GND and receive the ground voltage.

In DAC 10P, when switch S[i] is in the signal input state, power connection state, or ground state, the analog input signal AinP, power supply voltage VDD, and ground voltage are applied to the second end of capacitor C[i] (see FIG. 3). In DAC 10N, when switch S[i] is in the signal input state, power connection state, or ground state, the analog input signal AinN, power supply voltage VDD, and ground voltage are applied to the second end of capacitor C[i] (see FIG. 3). Note that FIG. 20 shows, as an example, a state in which switches S[1] to S[N] in DACs 10P and 10N are all in the signal input state.

A first terminal of the switch _SGP is connected to the comparison wiring WR1, and a predetermined reference voltage _VREF is applied to a second terminal of the switch _SGP . A first terminal of the switch _SGN is connected to the comparison wiring WR2, and a predetermined reference voltage _VREF is applied to a second terminal of the switch _SGN . The reference voltage _VREF is as described in the first embodiment. The switches _SGP and _SGN are controlled to be in an on or off state by the control circuit 50. When the switch _SGP is on, the first terminal and the second terminal of the switch _SGP are conductive, and the voltage V1 of the comparison wiring WR1 is fixed to the reference voltage _VREF . When the switch _SGP is off, the first terminal and the second terminal of the switch _SGP are cut off (non-conductive). When the switch _SGN is on, the first and second terminals of the switch _SGN are conductive, and the voltage V2 of the comparison wiring WR2 is fixed to the reference voltage _VREF . When the switch _SGN is off, the first and second terminals of the switch _SGN are cut off (non-conductive). Note that, as an example, FIG. 20 shows a state in which the switches _SGP and _SGN are off.

As in the first embodiment, the correction circuit 30 can execute a voltage correction process under the control of the control circuit 50. In the voltage correction process, the correction circuit 30 corrects the voltage V1 generated by the DAC 10P or corrects the voltage V2 generated by the DAC 10N. As in the first embodiment, the voltage V1 that has not been corrected by the correction circuit 30 is referred to as the original voltage V1, and the voltage V1 after correction by the correction circuit 30 is referred to as the corrected voltage V1. As in the first embodiment, the voltage V2 that has not been corrected by the correction circuit 30 is referred to as the original voltage V2, and the voltage V2 after correction by the correction circuit 30 is referred to as the corrected voltage V2.

As in the first embodiment, a voltage Vin1, which is a first comparison input voltage, is supplied to the inverting input terminal of the comparator 40, and a voltage Vin2, which is a second comparison input voltage, is supplied to the non-inverting input terminal of the comparator 40. The voltage Vin1 is the source voltage V1 or the correction voltage V1. The voltage Vin2 is the source voltage V2 or the correction voltage V2. The comparator 40 compares the voltages Vin1 and Vin2, and generates and outputs a comparison result signal S _CMP indicative of the comparison result (high-low relationship) of the voltages Vin1 and Vin2. The method of generating the comparison result signal S _CMP in accordance with the high-low relationship of the voltages Vin1 and Vin2 is as described in the first embodiment.

The control circuit 50 receives the comparison result signal S _CMP . The control circuit 50 controls the overall AD conversion operation and outputs a digital output signal Dout obtained by the AD conversion operation. As in the first embodiment, the control circuit 50 is provided with a register 51 and a correction control unit 52. The value of the digital output signal Dout can be stored in the register 51. The control circuit 50 controls the states of the switches S[1] to S[N] individually by supplying a control signal CNT _DAC (DAC input signal) to each of the DACs 10P and 10N. The control circuit 50 controls the states of the switches S _GP and S _GN by supplying a control signal CNT _G to each of the switches S _GP and S _GN .

In each of DACs 10P and 10N, the capacitance values of capacitors C[1] to C[n] are set in the same manner as in the first embodiment (see Figure 4).

In the AD conversion operation in the AD converter 1B, steps S1 to S4 are executed sequentially, as in the first embodiment (see FIG. 5).

21 shows the state of the AD converter 1B during a sampling period. The sampling period has a predetermined length of time. During the sampling period, the control circuit 30 controls all the switches S[1] to S[N] in the DACs 10P and 10N to a signal input state, and controls the switches _SGP and _SGN to be on.

During the sampling period, the wiring WR_AinP is connected to the capacitor array 11 via the switch array 12 in the DAC 10P, and thus, charges corresponding to the analog input signal AinP are stored in each capacitor (C[1] to C[N]) in the capacitor array 11 of the DAC 10P. At this time, each capacitor (C[1] to C[N]) in the capacitor array 11 in the DAC 10P is charged by the analog input signal AinP with reference to the reference voltage V _REF . Similarly, during the sampling period, the wiring WR_AinN is connected to the capacitor array 11 via the switch array 12 in the DAC 10N, and thus, charges corresponding to the analog input signal AinN are stored in each capacitor (C[1] to C[N]) in the capacitor array 11 of the DAC 10N. At this time, each capacitor (C[1] to C[N]) in the capacitor array 11 in the DAC 10N is charged by the analog input signal AinN with reference to the reference voltage V _REF .

In the state transition operation in step S2, the same operation as the state transition operation shown in the first embodiment is performed for each of the two voltage generation blocks. In the state transition operation, the operations of steps S21, S22, and S23 may be performed in this order (see FIG. 7). In the state transition operation for the voltage generation block including DAC 10P, the state of switch _SGP is switched from on to off in step S22. In the state transition operation for the voltage generation block including DAC 10N, the state of switch _SGN is switched from on to off in step S22. After step S22, switches _SGP and _SGN are maintained in the off state until the successive approximation operation is completed.

In the successive approximation operation in step S3, the values Rg[1] to Rg[N] of the register 31 are determined bit by bit from the most significant bit side, and the determined value Rg[i] becomes the value of the i-th bit in the digital output signal Dout. In the successive approximation operation (in other words, during the successive approximation period), the control circuit ₃₀ determines the values Rg[1] to Rg[N] (i.e., the value of the digital output signal Dout) for each bit while sequentially switching the states of the switch arrays 12 of the DACs 10P and 10N by binary search based on the comparison result signal S CMP.

In the AD converter 1B, the flowchart of the successive approximation operation in step S3 is the same as that in FIG. 9, and the successive approximation operation in the first embodiment is also applied to this embodiment. However, if the state of the switch S[j] is controlled, set, maintained, or switched to the power supply connection state in the first embodiment, it is understood that the state of the switch S[j] in each of DAC 10P and DAC 10N is controlled, set, maintained, or switched to the power supply connection state in the second embodiment. Similarly, if the state of the switch S[j] is controlled, set, maintained, or switched to the ground connection state in the first embodiment, it is understood that the state of the switch S[j] in each of DAC 10P and DAC 10N is controlled, set, maintained, or switched to the ground connection state in the second embodiment.

In the result output operation of step S4 (see FIG. 7), the control circuit 30 outputs a digital signal having the values Rg[1] to Rg[N] determined by the successive approximation operation of step S3 as a digital output signal Dout.

The AD converter 1B can be considered as a circuit in which the voltage generating circuit 20 in the AD converter 1A in FIG. 1 is configured with the DAC 10N. In the AD converter 1B, the DACs 10P and 10N are examples of the first and second voltage generating circuits, respectively. In the AD converter 1B, the voltages V1 and V2 are compared in a successive approximation period using the voltage V2 according to the analog input signal AinN. However, in this case as well, similar to the first embodiment, the voltage V2 fluctuates from the ideal due to various fluctuation factors, and the direction and magnitude of the fluctuation also differ between the execution period of a certain unit comparison operation and the execution period of another unit comparison operation among the first to Nth unit comparison operations. For this reason, similar to the AD converter 1A in the first embodiment, a correction amount V _C is set for each bit of the digital output signal Dout.

The second embodiment includes the following Examples EX2_1 to EX2_4. Unless otherwise specified and unless there is a contradiction, the matters described above in the second embodiment are applied to the following Examples EX2_1 to EX2_4. However, in each example, for matters that contradict the matters described above in the second embodiment, the description in each example may take precedence.

[Example EX2_1]
An example EX2_1 will be described. Fig. 22 is a partial configuration diagram of an AD converter 1B according to the example EX2_1. In the example EX2_1, a correction circuit 30B_1 is used as the correction circuit 30. The correction circuit 30B_1 corrects the voltage V1 generated by the DAC 10P in the voltage correction process. Therefore, in the example EX2_1, in the successive approximation period, the voltage Vin1 is the correction voltage V1, and the voltage Vin2 is the source voltage V2.

The correction circuit 30B_1 may be an adder inserted in series between the wiring WR1 and the inverting input terminal of the comparator 40. In this case, during the execution period of the jth unit comparison operation (see FIG. 9), the correction circuit 30B_1 generates the correction voltage V1 by adding the correction amount ΔV _C [j] to the source voltage V1 output from the DAC 10P (i.e., the sum of the source voltage V1 and the correction amount ΔV _C [j] is generated as the correction voltage V1). During the execution period of the jth unit comparison operation, if "ΔV _C [j]>0", the correction voltage V1 becomes higher than the source voltage V1 by the amount of the correction amount ΔV _C [j], and if "ΔV _C [j]<0", the correction voltage V1 becomes lower than the source voltage V1 by the amount of the correction amount ΔV _C [j]. The correction control unit 52 sets the correction amount ΔV _C [j] as desired by controlling the correction circuit 30B_1 during the execution period of the jth unit comparison operation.

[Example EX2_2]
An example EX2_2 will be described. Fig. 23 is a partial configuration diagram of an AD converter 1B according to the example EX2_2. In the example EX2_2, a correction circuit 30B_2 is used as the correction circuit 30. The correction circuit 30B_2 corrects the voltage V2 generated by the DAC 10N in the voltage correction process. Therefore, in the example EX2_2, in the successive approximation period, the voltage Vin1 is the source voltage V1, and the voltage Vin2 is the correction voltage V2.

The correction circuit 30B_2 may be an adder inserted in series between the wiring WR2 and the non-inverting input terminal of the comparator 40. In this case, during the execution period of the j-th unit comparison operation (see FIG. 9), the correction circuit 30B_2 generates the correction voltage V2 by adding the correction amount ΔV _C [j] to the source voltage V2 output from the DAC 10N (i.e., the sum of the source voltage V2 and the correction amount ΔV _C [j] is generated as the correction voltage V2). During the execution period of the j-th unit comparison operation, if "ΔV _C [j]>0", the correction voltage V2 becomes higher than the source voltage V2 by the amount of the correction amount ΔV _C [j], and if "ΔV _C [j]<0", the correction voltage V2 becomes lower than the source voltage V2 by the amount of the correction amount ΔV _C [j]. The correction control unit 52 sets the correction amount ΔV _C [j] as desired by controlling the correction circuit 30B_2 during the execution period of the j-th unit comparison operation.

[Example EX2_3]
An example EX2_3 will be described. Fig. 24 is a partial configuration diagram of an AD converter 1B according to the example EX2_3. In the example EX2_3, a correction circuit 30B_3 is used as the correction circuit 30. The correction circuit 30B_3 corrects the voltage V1 generated by the DAC 10P in the voltage correction process. Therefore, in the example EX2_3, in the successive approximation period, the voltage Vin1 is the correction voltage V1, and the voltage Vin2 is the source voltage V2.

The correction circuit 30B_3 has a configuration similar to that of the correction circuit 30A_3 according to the embodiment EX1_3 (see FIG. 18), and the description of the embodiment EX1_3 is also applied to the embodiment EX2_3. In this application, the correction circuit 30A_3 and the switch _{S_G} in the description of the embodiment EX1_3 are replaced with the correction circuit 30B_3 and the switch _{S_GP} in the embodiment EX2_3.

Similar to the correction circuit 30A_3, the first end of each correction capacitor C _C of the correction circuit 30B_3 is connected to the comparison wiring WR1. During the sampling period, the correction control unit 52 sets the correction circuit 30B_3 (in other words, the state of the correction switches S _C [1] to S _C [M]) to the non-correction state, which is the reference state. The meaning of the non-correction state is as described above (see FIG. 19). The state in which the correction circuit 30B_3 is in the non-correction state corresponds to the state in which the voltage correction process by the correction circuit 30B_3 is not being performed. Note that, since the switch S _GP is turned on during the sampling period, in the correction circuit 30B_3, charges corresponding to the difference between the reference voltage V _REF and the ground voltage are accumulated in the correction capacitors C _C [1] to C _C [M _HF ], and charges corresponding to the difference between the reference voltage V _REF and the power supply voltage VDD are accumulated in the correction capacitors C _C [M _HF +1] to C _C [M] (the manner of accumulation is not shown).

During the successive approximation period, the correction control unit 52 changes the state of the correction circuit 30B_3 from the non-correction state to realize voltage correction processing for the voltage V1.

That is, when "ΔV _C [j]>0" in the jth unit comparison operation (see FIG. 9), the correction control unit 52 sets the correction switches S C [1] to S C [M] in the correction circuit 30B_3 to a low-side state or a high-side state individually so that the potential of the comparison wiring _WR1 rises by the magnitude of the correction amount ΔV _C [j] compared to when the correction circuit 30B_3 is set in the non-correction state. For example, when "ΔV _C [j]>0" in the jth unit comparison operation, the correction control unit 52 switches _one or more of the correction switches S _C [1] to S _C [M _HF ] in the correction circuit 30B_3 from the low-side state to the high-side state according to the magnitude of the correction amount ΔV _C [j], starting from the non-correction state.

Conversely, when "ΔV _C [j]<0" in the jth unit comparison operation (see FIG. 9), the correction control unit 52 sets the correction switches S _{C [1] to S C [M] in the correction circuit 30B_3 to a low-side state or a high-side state individually so that the potential of the comparison wiring WR1 decreases by the magnitude of the correction amount ΔV C [ j] compared to when the correction circuit 30B_3 is set in the non-correction state. For example, when "ΔV C [} j]<0" in the jth unit comparison operation, the correction control unit 52 switches one or more of the correction switches S _C [M _HF +1] to S _C [M] in the correction circuit 30B_3 from the high-side state to the low-side state according to the magnitude of the correction amount ΔV _C [j], starting from the non-correction state.

[Example EX2_4]
An example EX2_4 will be described. Fig. 25 is a partial configuration diagram of an AD converter 1B according to the example EX2_4. In the example EX2_4, a correction circuit 30B_4 is used as the correction circuit 30. The correction circuit 30B_4 corrects the voltage V2 generated by the DAC 10N in the voltage correction process. Therefore, in the example EX2_4, in the successive approximation period, the voltage Vin1 is the source voltage V1, and the voltage Vin2 is the correction voltage V2.

The correction circuit 30B_4 has a configuration similar to that of the correction circuit 30A_3 according to the embodiment EX1_3 (see FIG. 18), and the description of the embodiment EX1_3 is also applied to the embodiment EX2_4. In this application, the correction circuit 30A_3 and the switch _{S_G} in the description of the embodiment EX1_3 are replaced with the correction circuit 30B_4 and the switch _{S_GN} in the embodiment EX2_4.

However, unlike the correction circuit 30A_3, the first end of each correction capacitor C _C of the correction circuit 30B_4 is connected to the comparison wiring WR2. During the sampling period, the correction control unit 52 sets the correction circuit 30B_4 (in other words, the state of the correction switches S _C [1] to S _C [M]) to the non-correction state, which is the reference state. The meaning of the non-correction state is as described above (see FIG. 19). The state in which the correction circuit 30B_4 is in the non-correction state corresponds to a state in which the voltage correction process by the correction circuit 30B_4 is not being performed. In addition, since the switch _SGN is turned on during the sampling period, charges corresponding to the difference between the reference voltage VREF and the ground voltage are stored in the correction capacitors C _C [1] to C _C [ _MHF ] in the correction circuit 30B_4, and charges corresponding to the difference between the reference voltage _VREF and the power supply voltage VDD are stored in the correction capacitors C _C [ _MHF + ₁ ] to C _C [M] (the manner in which these charges are stored is not shown).

During the successive approximation period, the correction control unit 52 changes the state of the correction circuit 30B_4 from the non-correction state to achieve voltage correction processing for the voltage V2.

That is, when "ΔV _C [j]>0" in the jth unit comparison operation (see FIG. 9), the correction control unit 52 sets the correction switches S _{C [1] to S C [M] in the correction circuit 30B_4 to a low-side state or a high-side state individually so that the potential of the comparison wiring WR2 rises by the magnitude of the correction amount ΔV C [ j] compared to when the correction circuit 30B_4 is set in the non-correction state. For example, when "ΔV C [} j]>0" in the jth unit comparison operation, the correction control unit 52 switches one or more of the correction switches S _C [1] to S _C [M _HF ] in the correction circuit 30B_4 from the low-side state to the high-side state according to the magnitude of the correction amount ΔV _C [j], starting from the non-correction state.

Conversely, when "ΔV _C [j]<0" in the jth unit comparison operation (see FIG. 9), the correction control unit 52 sets the correction switches S _{C [1] to S C [M] in the correction circuit 30B_4 to a low-side state or a high-side state individually so that the potential of the comparison wiring WR2 decreases by the magnitude of the correction amount ΔV C [ j] compared to when the correction circuit 30B_4 is set in the non-correction state. For example, when "ΔV C [} j]<0" in the jth unit comparison operation, the correction control unit 52 switches one or more of the correction switches S _C [M _HF +1] to S _C [M] in the correction circuit 30B_4 from the high-side state to the low-side state according to the magnitude of the correction amount ΔV _C [j], starting from the non-correction state.

<<Third embodiment>>
The voltage correction process shown in the first and second embodiments can also be applied to a successive approximation type A/D conversion circuit that does not use a capacitor-type DAC. This will be described in the third embodiment.

Figure 26 shows the overall configuration of an AD converter 1C according to a third embodiment of the present disclosure. The AD converter 1C is a successive approximation type A/D conversion circuit that does not use a capacitor-type DAC. An analog input signal Ain is input to the AD converter 1C. The AD converter 1C performs an AD conversion operation on the analog input signal Ain. In the AD conversion operation on the analog input signal Ain, the analog input signal Ain is converted into a digital signal by a binary search, and the obtained digital signal is output as a digital output signal Dout.

Note that the common symbols "Ain" and "Dout" are used in all of the first to third embodiments, but the analog input signal Ain and digital output signal Dout described in the third embodiment refer to the analog input signal Ain to the AD converter 1C and the digital output signal Dout from the AD converter 1C. The structure of the digital output signal Dout is the same as in the first embodiment. In other words, the digital output signal Dout is an N-bit digital signal.

The AD converter 1C includes an S/H circuit 110, a DAC 120, a correction circuit 130, a comparator 140, and a control circuit 150. The analog input signal Ain has a voltage value within a predetermined dynamic range. The dynamic range is a voltage range from a predetermined lower limit voltage _VMIN to a predetermined upper limit voltage _VMAX . " _VMAX > _VMIN " holds. The lower limit voltage _VMIN may be other than 0V, but it is assumed here that the lower limit voltage _VMIN is 0V.

The S/H circuit 110 is a sample-and-hold circuit and is an example of a first voltage generating circuit. An analog input signal Ain is input to the S/H circuit 110. The S/H circuit 110 samples the analog input signal Ain and generates a voltage Va by holding the analog input signal Ain at the timing when the hold designation signal is received. The voltage Va has the voltage value of the analog input signal Ain at the timing when the hold designation signal is received. The S/H circuit 110 is connected to the comparison wiring WRa and outputs the voltage Va to the comparison wiring WRa. The hold designation signal is supplied to the S/H circuit 110 from the control circuit 150 or from an external circuit (not shown) of the AD converter 1C.

The DAC 120 is an example of a second voltage generating circuit. The DAC 120 generates a voltage Vb to be compared with the voltage Va, and outputs the generated voltage Vb to the comparison wiring WRb. The DAC 120 is a DA conversion circuit (digital-analog converter). For example, the DAC 120 may be an R-2R ladder type DA conversion circuit. The DAC 120 converts a digital control signal DAC _IN supplied from the control circuit 150 into an analog signal by DA conversion, and outputs the obtained analog signal (analog voltage signal) as a voltage Vb to the comparison wiring WRb. The above-mentioned upper limit voltage V _MAX and lower limit voltage V _MIN (here, 0 V) are input to the DAC 120 as a power supply voltage, and the DAC 120 can generate and output a voltage from the lower limit voltage V _MIN to the upper limit voltage V _MAX as a voltage Vb.

The correction circuit 130 can execute a voltage correction process under the control of the control circuit 150. In the voltage correction process, the correction circuit 130 corrects the voltage Va generated by the S/H circuit 110 or corrects the voltage Vb generated by the DAC 120. In the following, for the sake of concrete explanation, the voltage Va that has not been corrected by the correction circuit 130 is referred to as the original voltage Va, and the voltage Va after correction by the correction circuit 130 is referred to as the corrected voltage Va. Similarly, the voltage Vb that has not been corrected by the correction circuit 130 is referred to as the original voltage Vb, and the voltage Vb after correction by the correction circuit 130 is referred to as the corrected voltage Vb.

The comparator 140 has an inverting input terminal, a non-inverting input terminal, and an output terminal. A voltage Vina, which is a first comparison input voltage, is supplied to the inverting input terminal of the comparator 140, and a voltage Vinb, which is a second comparison input voltage, is supplied to the non-inverting input terminal of the comparator 140. The voltage Vina is the source voltage Va or the correction voltage Va. The voltage Vinb is the source voltage Vb or the correction voltage Vb.

The comparator 140 compares the voltages Vina and Vinb, and generates and outputs a comparison result signal S _CMP indicating the comparison result (high/low relationship) of the voltages Vina and Vinb. The comparison result signal S _CMP is a binary signal having a value of "0" or "1". It is also possible to modify the embodiment so that the voltage Vina is supplied to the non-inverting input terminal of the comparator 140 and the voltage Vinb is supplied to the inverting input terminal of the comparator 140. The comparison result signal S _CMP described in the third embodiment is a signal output from the comparator 140.

The comparator 140 outputs a comparison result signal S _CMP having a value of "1" from its output terminal when "Vina<Vinb" is true, and outputs a comparison result signal S _CMP having a value of "0" from its output terminal when "Vina>Vinb" is true. When "Vina=Vinb" is true, the comparison result signal S _CMP has a value of "0" or "1".

The control circuit 150 receives the comparison result signal S _CMP . The control circuit 150 controls the overall AD conversion operation and outputs a digital output signal Dout obtained by the AD conversion operation. The control circuit 150 is provided with a register 151, and the value of the digital output signal Dout can be stored in the register 151. The control circuit 150 supplies a digital control signal DAC _IN (DAC input signal) to the S/H circuit 110, thereby causing the DAC 120 to output a voltage Vb corresponding to the control signal DAC _IN . The control circuit 150 is further provided with a correction control unit 152. The correction control unit 152 controls the execution of voltage correction processing by the correction circuit 130 (details will be described later).

In the AD conversion operation of the AD converter 1C, first, in response to the input of a hold designation signal to the S/H circuit 110, the S/H circuit 110 generates and outputs a voltage Va. Then, a successive comparison operation is performed with the voltage on the comparison wiring WRa maintained at voltage Va.

FIG. 27 shows a flowchart of the successive approximation operation in the AD converter 1C. The register 151 is the same as the register 51 shown in FIG. 10. The values Rg[1] to Rg[N] in the third embodiment are N-bit values stored in the register 151. As in the AD converter 1A or 1B, in the AD converter 1C, the values Rg[1] to Rg[N] are determined bit by bit from the most significant bit side by the successive approximation operation, and the determined value Rg[i] becomes the value of the i-th bit in the digital output signal Dout. The period during which the successive approximation operation is performed is called the successive approximation period. In the successive approximation operation (in other words, in the successive approximation period), the control circuit 150 determines the values Rg[1] to Rg[N] (i.e., the value of the digital output signal Dout ₎ for each bit while sequentially changing the voltage Vb through the change of the control signal DAC _IN by binary search based on the comparison result signal S CMP.

27, first, in step S130, the value of N is substituted for the variable j managed by the control circuit 150. Then, the process proceeds to step S131. In step S131, the control circuit 150 provides the control signal DAC _IN for the jth bit to the DAC 120, and controls the DAC 120 to perform DA conversion of the control signal DAC _IN for the jth bit. As a result, a voltage Vb for determining the value of the jth bit in the digital output signal Dout (i.e., the value R[j]) is generated by the DAC 120 and output to the comparison wiring WRb.

The voltage Vb generated here is a proper voltage based on the binary search method. The digital value of the control signal DAC _IN when "j=N" is constant, but the digital value of the control signal DAC _IN when "j<N" is determined depending on the comparison result signal S _CMP obtained in the past based on the binary search method. After step S131, proceed to step S132.

In step S132, the correction control unit 152 causes the correction circuit 130 to execute the voltage correction process. At this time, the correction control unit 152 sets a correction amount ΔV _C in the correction circuit 130 for each bit of the digital output signal Dout. The correction amount ΔV _C is a voltage amount. As in the first and second embodiments, the correction amount used in the voltage correction process when determining the value of the j-th bit in the digital output signal Dout is particularly referred to as the correction amount ΔV _C [j]. In the first step S132, since "j=N", the voltage correction process is executed using the correction amount ΔV _C [N]. The correction amount ΔV _C [j] may have a positive voltage value or a negative voltage value. The correction amounts ΔV _C [N] to ΔV _C [1] may be different from each other, or the values of some of the correction amounts ΔV _C [N] to ΔV _C [1] may be the same. However, at least the correction amounts ΔV _C [N] to ΔV _C [1] include two or more correction amounts having different values.

When the voltage Va is corrected by the voltage correction process, the correction voltage Va is generated by adding the correction amount ΔV _C [j] to the source voltage Va (i.e., the sum of the source voltage Va and the correction amount ΔV _C [j] is generated as the correction voltage Va), and the correction voltage Va is supplied as voltage Vina to the inverting input terminal of the comparator 140, and the source voltage Vb is supplied as voltage Vinb to the non-inverting input terminal of the comparator 140. When the voltage Vb is corrected by the voltage correction process, the correction voltage Vb is generated by adding the correction amount ΔV _C [j] to the source voltage Vb (i.e., the sum of the source voltage Vb and the correction amount ΔV _C [j] is generated as the correction voltage Vb), and the correction voltage Vb is supplied as voltage Vinb to the non-inverting input terminal of the comparator 140, and the source voltage Va is supplied as voltage Vina to the inverting input terminal of the comparator 140.

In step S133 following step S132, the control circuit 150 acquires the value of the current comparison result signal S _CMP (i.e., acquires the value of the comparison result signal S _CMP output from the comparator 140 in the state of the most recent step S132). If the acquired value is "1" (Y in step S133), the process proceeds to step S134, whereas if the acquired value is "0" (N in step S133), the process proceeds to step S135.

In step S134, the control circuit 150 determines the value Rg[j] to be "0". In step S135, the control circuit 150 determines the value Rg[j] to be "1". After step S134 or S135, the process proceeds to step S136.

In step S136, the control circuit 150 checks whether the variable j is 1. If the variable j is not 1 (N in step S136), the process proceeds to step S137, where 1 is subtracted from the variable j, and the process returns to step S131 to repeat the process from step S131 onwards. For example, in the first process of step S131, the control circuit 150 provides the control signal DAC _IN to the DAC 120 so that "Vb = V _MAX /2" (however, the actual voltage Vb may contain an error). After that, if the value R[N] is determined to be "0", in the second process of step S131, the control circuit 150 provides the control signal DAC _IN to the DAC 120 so that "Vb = V _MAX /4" (however, the actual voltage Vb may contain an error) based on the binary search method. Conversely, if the value R[N] is determined to be "1", in the second processing of step S131, based on the binary search method, the control circuit 150 provides the control signal DAC _IN to the DAC 120 so that "Vb = 3·V _MAX /4" (however, the actual voltage Vb may contain an error). In the third and subsequent processing of steps S131, the voltage Vb is similarly adjusted based on the binary search method.

In the second processing of step S132, the correction amount used in the voltage correction process is switched from the correction amount ΔV _C [N] to the correction amount ΔV _C [N-1], and in the third processing of step S132, the correction amount used in the voltage correction process is switched from the correction amount ΔV _C [N-1] to the correction amount ΔV _C [N-2]. The same applies to the fourth and subsequent processing of step S132.

In the third embodiment, the process consisting of steps S131 to S135 is referred to as a unit comparison operation. In this case, the successive comparison operation includes the first to Nth unit comparison operations. The unit comparison operation executed when "j=N" is the Nth unit comparison operation, the unit comparison operation executed when "j=N-1" is the (N-1)th unit comparison operation, ..., the unit comparison operation executed when "j=1" is the first unit comparison operation. In the jth unit comparison operation, the value Rg[j] is determined, that is, the value of the jth bit of the digital output signal Dout is determined.

If "j=1" in step S136 (Y in step S136), the successive approximation operation in FIG. 27 ends. At this stage, all values Rg[1] to Rg[N] have been determined.

When the successive approximation operation is completed, the control circuit 150 performs a result output operation. In the result output operation, the control circuit 150 outputs a digital signal having values Rg[1] to Rg[N] determined by the successive approximation operation as a digital output signal Dout. The digital output signal Dout is output to any circuit (not shown) that uses the digital output signal Dout. The result output operation may be started while the successive approximation operation is being performed. That is, as soon as the value Rg[N] is determined by the successive approximation operation, the control circuit 150 may output the value Rg[N] in the digital output signal Dout. Similarly, as soon as the value Rg[N-1] is determined by the successive approximation operation, the control circuit 150 may output the value Rg[N-1] in the digital output signal Dout. The same applies to the values Rg[N-2] to Rg[1].

In the AD converter 1C, similarly to the first embodiment, the voltage Vb fluctuates from the ideal due to various fluctuation factors, and the direction and magnitude of the fluctuation differs between the execution period of a certain unit comparison operation and the execution period of another unit comparison operation among the first to Nth unit comparison operations. For this reason, similarly to the first embodiment, a correction amount V _C is set for each bit of the digital output signal Dout.

The third embodiment includes the following Examples EX3_1 and EX3_2. Unless otherwise specified and unless there is a contradiction, the matters described above in the third embodiment are applied to the following Examples EX3_1 and EX3_2. However, in each example, for matters that contradict the matters described above in the third embodiment, the description in each example may take precedence.

[Example EX3_1]
An example EX3_1 will be described. Fig. 28 is a partial configuration diagram of an AD converter 1C according to the example EX3_1. In the example EX3_1, a correction circuit 130_1 is used as the correction circuit 130. The correction circuit 130_1 corrects the voltage Va generated by the S/H circuit 110 in the voltage correction process. Therefore, in the example EX3_1, in the successive approximation period, the voltage Vina is the correction voltage Va, and the voltage Vinb is the source voltage Vb.

The correction circuit 130_1 may be an adder inserted in series between the wiring WRa and the inverting input terminal of the comparator 140. In this case, during the execution period of the jth unit comparison operation (see FIG. 27), the correction circuit 130_1 generates the correction voltage Va by adding the correction amount ΔV _C [j] to the source voltage Va output from the S/H circuit 110 (i.e., the sum of the source voltage Va and the correction amount ΔV _C [j] is generated as the correction voltage Va). During the execution period of the jth unit comparison operation, if "ΔV _C [j]>0", the correction voltage Va becomes higher than the source voltage Va by the amount of the correction amount ΔV _C [j], and if "ΔV _C [j]<0", the correction voltage Va becomes lower than the source voltage Va by the amount of the correction amount ΔV _C [j]. The correction control unit 152 controls the correction circuit 130_1 during the execution period of the jth unit comparison operation to set the correction amount ΔV _C [j] as desired.

[Example EX3_2]
An example EX3_2 will be described. Fig. 29 is a partial configuration diagram of an AD converter 1C according to the example EX3_2. In the example EX3_2, a correction circuit 130_2 is used as the correction circuit 130. The correction circuit 130_2 corrects the voltage Vb generated by the DAC 120 in the voltage correction process. Therefore, in the example EX3_2, in the successive approximation period, the voltage Vina is the source voltage Va, and the voltage Vinb is the correction voltage Vb.

The correction circuit 130_2 may be an adder inserted in series between the wiring WRb and the non-inverting input terminal of the comparator 140. In this case, during the execution period of the jth unit comparison operation (see FIG. 27), the correction circuit 130_2 generates the correction voltage Vb by adding the correction amount ΔV _C [j] to the source voltage Vb output from the DAC 120 (i.e., the sum of the source voltage Vb and the correction amount ΔV _C [j] is generated as the correction voltage Vb). During the execution period of the jth unit comparison operation, if "ΔV _C [j]>0", the correction voltage Vb becomes higher than the source voltage Vb by the amount of the correction amount ΔV _C [j], and if "ΔV _C [j]<0", the correction voltage Vb becomes lower than the source voltage Vb by the amount of the correction amount ΔV _C [j]. The correction control unit 152 sets the correction amount ΔV _C [j] as desired by controlling the correction circuit 130_2 during the execution period of the jth unit comparison operation.

<<Additional Note 1>>
The configuration of the DAC 10 shown in Fig. 1 and the configurations of the DACs 10P and 10N shown in Fig. 20 are merely examples. There are various forms of capacitor-type DACs, and as long as the DACs 10, 10P, and 10N are capacitor-type DACs, their internal configurations can be modified in various ways. Thus, for example, the DAC 10 may be provided with one or more scaling capacitors (which may also be referred to as series capacitances). The same applies to the DACs 10P and 10N.

The embodiments of the present disclosure may be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms in the present disclosure or each of the constituent elements are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and can, of course, be changed to various numerical values.

<<Additional Note 2>>
Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

A successive approximation type AD converter circuit according to one aspect of the present disclosure is a successive approximation type AD converter circuit (1A, 1B, 1C) configured to convert an analog input signal into a digital output signal, the successive approximation type AD converter circuit (10, 10P, 110) configured to generate a first voltage (V1, Va) corresponding to the analog input signal, a second voltage generator circuit (20, 10N, 120) configured to generate a second voltage (V2, Vb) to be compared with the first voltage, a correction circuit (30, 130) configured to correct the first voltage or the second voltage in a successive approximation period in which a binary search is performed, and a comparison result signal (S _CMP a comparator (40, 140) configured to generate a comparison result signal, and a control circuit (50, 150) configured to determine a value of the digital output signal for each bit by binary search from the most significant bit to the least significant bit of the digital output signal based on the comparison result signal, wherein the control circuit is configured (first configuration) to set a correction amount (ΔV _C ) in the correction circuit for each bit of the digital output signal during the successive approximation period.

This is expected to improve the accuracy of AD conversion (improved linearity, etc.).

In the successive approximation type AD conversion circuit according to the first configuration (see FIG. 1), the first voltage generation circuit (10) has a capacitor array (11) and a switch array (12) connected to the capacitor array, and accumulates charges corresponding to the analog input signal in each capacitor in the capacitor array by connecting the wiring (WR_Ain) to which the analog input signal is applied to the capacitor array via the switch array during a sampling period, and generates the first voltage based on the accumulated charges in the capacitor array in a state in which a predetermined power supply voltage or ground voltage is supplied to each capacitor in the capacitor array via the switch array during the successive approximation period after the sampling period, and the control circuit may be configured to determine the value of the digital output signal for each bit based on the comparison result signal while controlling the state of the switch array according to the comparison result signal during the successive approximation period (second configuration).

In the successive approximation type AD conversion circuit according to the second configuration (see FIG. 12), the second voltage generation circuit (20) may be a reference voltage source (20_1) configured to generate a predetermined reference voltage as the second voltage (third configuration).

In the successive approximation type AD converter circuit according to the second configuration (see FIG. 13), the second voltage generating circuit (20) may be a DA converter circuit (20_2) configured to generate the second voltage by converting a supplied digital signal into an analog signal (fourth configuration).

In the successive approximation type AD conversion circuit according to the first configuration (see FIG. 20), the analog input signal is a difference signal (Adif) between a first analog input signal (AinP) and a second analog input signal (AinN), the first voltage generation circuit (10P) has a first capacitor array (11) and a first switch array (12) connected to the first capacitor array, and during a sampling period, a wiring (WR_AinP) to which the first analog input signal is applied is connected to the first capacitor array via the first switch array to accumulate charges corresponding to the first analog input signal in each capacitor in the first capacitor array, and during the successive approximation period after the sampling period, a predetermined power supply voltage or ground voltage is supplied to each capacitor in the first capacitor array via the first switch array, and the first voltage is generated based on the accumulated charges in the first capacitor array, and the second voltage generation circuit The path (10N) has a second capacitor array (11) and a second switch array (12) connected to the second capacitor array, and during the sampling period, a wiring (WR_AinN) to which the second analog input signal is applied is connected to the second capacitor array via the second switch array to accumulate charges corresponding to the second analog input signal in each capacitor in the second capacitor array, and during the successive approximation period, the power supply voltage or the ground voltage is supplied to each capacitor in the second capacitor array via the second switch array, and the second voltage is generated based on the accumulated charges in the second capacitor array, and the control circuit determines the value of the digital output signal for each bit based on the comparison result signal while controlling the states of the first switch array and the second switch array in accordance with the comparison result signal during the successive approximation period (fifth configuration).

In the successive approximation type AD conversion circuit according to the first configuration (see FIG. 26), the first voltage generation circuit (110) generates the first voltage by sampling and holding the analog input signal, the second voltage generation circuit (120) generates the second voltage by converting a digital control signal from the control circuit into an analog signal, and the control circuit (150) may be configured to output the control signal corresponding to the comparison result signal to the second voltage generation circuit during the successive approximation period while determining the value of the digital output signal for each bit based on the comparison result signal (sixth configuration).

In the successive approximation type AD conversion circuit according to any one of the first to sixth configurations (see, for example, FIG. 16), the two comparison input voltages may be the first voltage corrected by the correction circuit and the second voltage generated by the second voltage generation circuit (seventh configuration).

In the successive approximation type AD conversion circuit according to any one of the first to sixth configurations (see, for example, FIG. 17), the two comparison input voltages may be the first voltage generated by the first voltage generation circuit and the second voltage corrected by the correction circuit (configuration eight).

In the successive approximation type AD converter circuit according to the second configuration (see FIG. 18 ), the first voltage generation circuit generates the first voltage on a comparison wiring (WR1), and the correction circuit (30A_3) includes a plurality of correction unit circuits (U C ) each including a correction capacitor (C _C ) having a first end connected to the comparison wiring and a correction switch (S _C ) for applying the power supply voltage or the ground voltage to a second end of the correction capacitor, and may be configured (ninth configuration ₎ to correct the first voltage for each bit of the digital output signal using the plurality of correction unit circuits during the successive approximation period.

This allows the correction circuit for the first voltage to be realized with a simple circuit that is adapted to the configuration of the first voltage generation circuit.

In the successive approximation type AD conversion circuit according to the ninth configuration, the correction circuit may be configured to set the states of the correction switches to a reference state (see FIG. 19) during the sampling period, and then correct the first voltage by changing the states of the correction switches from the reference state during the successive approximation period (tenth configuration).

In the successive approximation type AD converter circuit according to the fifth configuration (see FIG. 24 ), the first voltage generation circuit generates the first voltage on a comparison wiring (WR1), and the correction circuit (30B_3) includes a plurality of correction unit circuits (U C ) each including a correction capacitor (C _C ) having a first end connected to the comparison wiring and a correction switch (S _C ) for applying the power supply voltage or the ground voltage to a second end of the correction capacitor, and may be configured (an eleventh configuration ₎ to correct the first voltage for each bit of the digital output signal using the plurality of correction unit circuits during the successive approximation period.

This allows the correction circuit for the first voltage to be realized with a simple circuit that is adapted to the configuration of the first voltage generation circuit.

In the successive approximation type AD conversion circuit according to the eleventh configuration, the correction circuit may be configured to set the states of the correction switches to a reference state during the sampling period, and then correct the first voltage by changing the states of the correction switches from the reference state during the successive approximation period (twelfth configuration).

In the successive approximation type AD converter circuit according to the fifth configuration (see FIG. 25 ), the second voltage generation circuit generates the second voltage on a comparison wiring (WR2), and the correction circuit (30B_4) may include a plurality of correction unit circuits (U C ) each including a correction capacitor (C _C ) having a first end connected to the comparison wiring and a correction switch (S _C ) for applying the power supply voltage or the ground voltage to a second end of the correction _capacitor , and may be configured to correct the second voltage for each bit of the digital output signal using the plurality of correction unit circuits during the successive approximation period (thirteenth configuration).

This allows the correction circuit for the second voltage to be realized with a simple circuit that is adapted to the configuration of the second voltage generation circuit.

In the successive approximation type AD conversion circuit according to the thirteenth configuration, the correction circuit may be configured to set the states of the correction switches to a reference state during the sampling period, and then correct the second voltage by changing the states of the correction switches from the reference state during the successive approximation period (fourteenth configuration).

1A, 1B AD converter 10, 10P, 10N DAC
11 Capacitor array 12 Switch array S[1] to S[N] Switches C[1] to C[N] Capacitors 20 Voltage generation circuit 20_1 Reference voltage source 20_2 DAC
30, 30A_1 to 30A_3, 30B_1 to 30B_4 Correction circuit 40 Comparator 50 Control circuit 51 Register 52 Correction control section S _G , S _GP , S _GN switch WR1, WR2 Comparison wiring VDD Power supply voltage V _REF reference voltage V1, V2, Vin1, Vin2 Voltage Ain, AinP, AinN Analog input signal Dout Digital output signal S _CMP comparison result signal Adif Difference signal WR_Ain, WR_AinP, WR_AinN, WR_VDD, WR_GND Wiring Ta, Tb, Tc Switching terminal T _COM common terminal 1C AD converter 110 S/H circuit 120 DAC
130, 130_1, 130_2 Correction circuit 140 Comparator 150 Control circuit 151 Register 152 Correction control section Va, Vb, Vina, Vinb Voltage WRa, WRb Comparison wiring

Claims (14)

1. A successive approximation type analog-to-digital converter circuit configured to convert an analog input signal into a digital output signal, comprising:
a first voltage generating circuit configured to generate a first voltage responsive to the analog input signal;
a second voltage generating circuit configured to generate a second voltage to be compared with the first voltage;
a correction circuit configured to correct the first voltage or the second voltage during a successive approximation period in which a binary search is performed;
a comparator configured to receive two comparison input voltages obtained through the correction in the correction circuit and generate a comparison result signal by comparing the two comparison input voltages;
a control circuit configured to determine a value of the digital output signal for each bit by performing a binary search from a most significant bit to a least significant bit of the digital output signal based on the comparison result signal;
The control circuit sets a correction amount in the correction circuit for each bit of the digital output signal during the successive approximation period. the first voltage generation circuit has a capacitor array and a switch array connected to the capacitor array, and accumulates charge corresponding to the analog input signal in each capacitor in the capacitor array by connecting a wiring to which the analog input signal is applied to the capacitor array via the switch array during a sampling period, and generates the first voltage based on the accumulated charge in the capacitor array in a state in which a predetermined power supply voltage or ground voltage is supplied to each capacitor in the capacitor array via the switch array during the successive approximation period after the sampling period,
2. The successive approximation type AD converter circuit according to claim 1, wherein the control circuit determines a value of the digital output signal for each bit based on the comparison result signal while controlling a state of the switch array in response to the comparison result signal during the successive approximation period. 3. The successive approximation type AD converter circuit according to claim 2, wherein the second voltage generating circuit is a reference voltage source configured to generate a predetermined reference voltage as the second voltage. 3. The successive approximation type AD converter circuit according to claim 2, wherein the second voltage generating circuit is a DA converter circuit configured to generate the second voltage by converting a supplied digital signal into an analog signal. the analog input signal is a difference signal between a first analog input signal and a second analog input signal;
the first voltage generation circuit has a first capacitor array and a first switch array connected to the first capacitor array, and accumulates charge corresponding to the first analog input signal in each capacitor in the first capacitor array by connecting a wiring to which the first analog input signal is applied to the first capacitor array via the first switch array during a sampling period, and generates the first voltage based on the accumulated charge in the first capacitor array in a state in which a predetermined power supply voltage or a ground voltage is supplied to each capacitor in the first capacitor array via the first switch array during the successive approximation period after the sampling period,
the second voltage generation circuit has a second capacitor array and a second switch array connected to the second capacitor array, and accumulates charge corresponding to the second analog input signal in each capacitor in the second capacitor array by connecting a wiring to which the second analog input signal is applied to the second capacitor array via the second switch array during the sampling period, and generates the second voltage based on the accumulated charge in the second capacitor array in a state in which the power supply voltage or the ground voltage is supplied to each capacitor in the second capacitor array via the second switch array during the successive approximation period;
2. The successive approximation type AD converter circuit according to claim 1, wherein the control circuit determines a value of the digital output signal for each bit based on the comparison result signal while controlling each state of the first switch array and the second switch array in response to the comparison result signal during the successive approximation period. the first voltage generating circuit generates the first voltage by sampling and holding the analog input signal;
the second voltage generating circuit generates the second voltage by converting a digital control signal from the control circuit into an analog signal;
2. The successive approximation type AD conversion circuit according to claim 1, wherein the control circuit determines a value of the digital output signal for each bit based on the comparison result signal while outputting the control signal corresponding to the comparison result signal to the second voltage generation circuit during the successive approximation period. 7. A successive approximation type AD conversion circuit according to claim 1, wherein the two comparison input voltages are the first voltage corrected by the correction circuit and the second voltage generated by the second voltage generation circuit. 7. The successive approximation type AD conversion circuit according to claim 1, wherein the two comparison input voltages are the first voltage generated by the first voltage generation circuit and the second voltage corrected by the correction circuit. the first voltage generating circuit generates the first voltage on a comparison line;
3. The successive approximation type AD conversion circuit according to claim 2, wherein the correction circuit includes a plurality of correction unit circuits each having a correction capacitor having a first end connected to the comparison wiring and a correction switch that applies the power supply voltage or the ground voltage to a second end of the correction capacitor, and corrects the first voltage for each bit of the digital output signal using the plurality of correction unit circuits during the successive approximation period. 10. The successive approximation type AD conversion circuit according to claim 9, wherein the correction circuit sets states of the plurality of correction switches to a reference state during the sampling period, and then corrects the first voltage by changing states of the plurality of correction switches from the reference state during the successive approximation period. the first voltage generating circuit generates the first voltage on a comparison line;
6. The successive approximation type AD conversion circuit according to claim 5, wherein the correction circuit includes a plurality of correction unit circuits each having a correction capacitor having a first end connected to the comparison wiring and a correction switch that applies the power supply voltage or the ground voltage to a second end of the correction capacitor, and corrects the first voltage for each bit of the digital output signal using the plurality of correction unit circuits during the successive approximation period. 12. The successive approximation type AD conversion circuit according to claim 11, wherein the correction circuit sets states of the plurality of correction switches to a reference state during the sampling period, and then corrects the first voltage by changing states of the plurality of correction switches from the reference state during the successive approximation period. the second voltage generating circuit generates the second voltage on a comparison line;
6. The successive approximation type AD conversion circuit according to claim 5, wherein the correction circuit includes a plurality of correction unit circuits each including a correction capacitor having a first end connected to the comparison wiring and a correction switch that applies the power supply voltage or the ground voltage to a second end of the correction capacitor, and corrects the second voltage for each bit of the digital output signal using the plurality of correction unit circuits during the successive approximation period. 14. The successive approximation type AD conversion circuit according to claim 13, wherein the correction circuit sets states of the plurality of correction switches to a reference state during the sampling period, and then corrects the second voltage by changing states of the plurality of correction switches from the reference state during the successive approximation period.

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