JP2024143711A - Multilayer Ceramic Capacitors - Google Patents

Abstract

[Problem] To provide a multilayer ceramic capacitor that can achieve both large capacitance and reliability while being miniaturized. [Solution] A multilayer ceramic capacitor comprising: a laminate 2 including an effective portion 16 in which a plurality of internal electrode layers 15 face each other via the dielectric layers 14 in a lamination direction Z in which the dielectric layers 14 and the internal electrode layers 15 are laminated; and a pair of external electrodes 3 disposed on the surface of the laminate 2 and connected to the internal electrode layers 15, wherein when the effective portion 16 is divided into three equal parts in the lamination direction Z into three regions, the grain diameter D50 of the crystal grains constituting the dielectric layer 14 in a middle region 16b of the effective portion 16 is larger than the grain diameter D50 of the crystal grains constituting the dielectric layer 14 in the other two regions. [Selected Figure] Figure 2

Description

The present invention relates to a multilayer ceramic capacitor.

Conventionally, multilayer ceramic capacitors, which are widely used in electronic devices such as mobile phones and portable music players, include an inner layer portion in which multiple dielectric layers and multiple internal electrode layers made of ceramic materials are laminated to form a capacitance, outer layer portions arranged on both sides of the inner layer portion in the lamination direction, and side margin portions arranged on both sides of the inner layer portion in the width direction. In recent years, with the trend toward higher performance and smaller size of electronic devices, there is a demand for larger capacity and smaller size of multilayer ceramic capacitors as well.

In order to increase the capacitance of multilayer ceramic capacitors, one method for obtaining a dielectric layer with a high dielectric constant is to grow ceramic particles (crystal particles) (see, for example, Patent Document 1).

On the other hand, in order to meet the demand for miniaturized multilayer ceramic capacitors, multilayer ceramic capacitors that have thin dielectric layers and internal electrode layers have the problem that when grains grow, the dielectric layers become thin in parts, reducing insulation and moisture resistance, and decreasing reliability.

There is therefore a demand for multilayer ceramic capacitors that can be made compact while still achieving high capacitance and reliability.

JP 2014-210685 A

The objective of the present invention is to provide a multilayer ceramic capacitor that is compact while achieving both large capacitance and reliability.

The inventors discovered that when the effective portion of a multilayer ceramic capacitor is divided into three equal parts in the stacking direction and the grain size of the crystal grains in the dielectric layer in the middle region is made larger than the grain size of the crystal grains in the dielectric layer in the other two regions, it is possible to achieve both large capacitance and reliability even when the multilayer ceramic capacitor is miniaturized, and thus completed the present invention.

That is, the present invention provides a multilayer ceramic capacitor comprising: a laminate including an effective portion in which a plurality of internal electrode layers face each other via a dielectric layer in a lamination direction in which the dielectric layers and the internal electrode layers are laminated; and a pair of external electrodes disposed on a surface of the laminate and connected to the internal electrode layers,
When the effective portion is divided into three equal parts in the stacking direction,
In this multilayer ceramic capacitor, the grain size D50 of the crystal grains constituting the dielectric layer in the intermediate region of the effective portion is larger than the grain size D50 of the crystal grains constituting the dielectric layers in the other two regions.

The present invention makes it possible to provide a multilayer ceramic capacitor that is compact while achieving both large capacitance and reliability.

1 is a diagram showing the external appearance of a multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II shown in FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III shown in FIG. 3A and 3B are enlarged views of parts A and B shown in FIG. 2 ((a) is an enlarged view of part A, and (b) is an enlarged view of part B). 2A to 2C are diagrams illustrating a manufacturing process of the multilayer ceramic capacitor 1.

The following describes a multilayer ceramic capacitor 1 as an embodiment of the present invention, but the present invention is not limited thereto. In addition, the drawings may be drawn in a schematic and simplified manner in order to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. In addition, components described in the specification may be omitted in the drawings, or may be drawn with the number of components omitted.

Figure 1 is a schematic perspective view of a multilayer ceramic capacitor 1. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II in Figure 1. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III in Figure 1. Figure 4 is an enlarged view of parts A and B shown in Figure 2. The cross section shown in Figure 2 is also called an XZ cross section, and the cross section shown in Figure 3 is also called a YZ cross section.

The multilayer ceramic capacitor 1 has a generally rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided at both ends of the laminate 2. The laminate 2 also includes an inner layer 11 in which a dielectric layer 14 and an internal electrode layer 15 are laminated.

In the following description, the terms used to indicate the orientation of the multilayer ceramic capacitor 1 are the length direction X, which is the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1, the stacking direction Z, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked, and the width direction Y, which is the direction that intersects both the length direction X and the stacking direction Z. In the embodiment, the width direction Y is perpendicular to both the length direction X and the stacking direction Z.

(Outer surface of laminate 2)
Among the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction Z is referred to as a first main surface 2a1 and a second main surface 2a2, a pair of outer surfaces facing each other in the width direction Y is referred to as a first side surface 2b1 and a second side surface 2b2, and a pair of outer surfaces facing each other in the length direction X is referred to as a first end surface 2c1 and a second end surface 2c2. When it is not necessary to distinguish between the first main surface 2a1 and the second main surface 2a2, they will be collectively referred to as the main surface 2a, when it is not necessary to distinguish between the first side surface 2b1 and the second side surface 2b2, they will be collectively referred to as the side surface 2b, and when it is not necessary to distinguish between the first end surface 2c1 and the second end surface 2c2, they will be collectively referred to as the end surface 2c.

It is preferable that the ridgeline portion R1 of the laminate 2, including the corners, is rounded. The ridgeline portion R1 is the portion where two surfaces of the laminate 2, that is, the main surface 2a and the side surface 2b, the main surface 2a and the end surface 2c, or the side surface 2b and the end surface 2c, intersect.

(Laminate 2)
The laminate 2 includes an inner layer portion 11 that forms a capacitance, outer layer portions 12 arranged on both sides of the inner layer portion 11 in the stacking direction Z, and side gap portions 13 arranged on both sides of the inner layer portion 11 in the width direction Y.

(Inner layer 11)
The inner layer portion 11 includes dielectric layers 14 and internal electrode layers 15 alternately stacked along the stacking direction Z. The inner layer portion 11 also includes an effective portion 16 in which a first opposing portion 152a and a second opposing portion 152b of the internal electrode layer 15 described later face each other via the dielectric layer 14, a first end gap portion 17a in which a first lead portion 151a of the internal electrode layer 15 described later faces each other via the dielectric layer 14, and a second end gap portion 17b in which a second lead portion 151b of the internal electrode layer 15 faces each other via the dielectric layer 14.

(Dielectric layer 14)
The dielectric layer 14 is made of a ceramic material, such as a dielectric ceramic containing _BaTiO3 as a main component.

(Internal electrode layer 15)
The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. The first internal electrode layers 15a and the second internal electrode layers 15b are alternately arranged. The first internal electrode layer 15a includes a first opposing portion 152a facing the second internal electrode layer 15b, and a first lead portion 151a drawn from the first opposing portion 152a to the first end face 2c1 side. An end of the first lead portion 151a is exposed to the first end face 2c1 and is electrically connected to the first external electrode 3a described later. The second internal electrode layer 15b includes a second opposing portion 152b facing the first internal electrode layer 15a, and a second lead portion 151b drawn from the second opposing portion 152b to the second end face 2c2. An end of the second lead portion 151b is electrically connected to the second external electrode 3b described later. Charges are stored in the first opposing portions 152a of the first internal electrode layers 15a and the second opposing portions 152b of the second internal electrode layers 15b.

The internal electrode layer 15 is preferably formed from a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), a silver-palladium (Ag-Pd) alloy, or gold (Au).

(Outer layer portion 12)
The outer layer portion 12 is arranged to sandwich the inner layer portion 11 in the stacking direction Z, and includes a first outer layer portion 12a forming a first main surface 2a1 of the multilayer ceramic capacitor 1, and a second outer layer portion 12b forming a second main surface 2a2 of the multilayer ceramic capacitor 1.
The outer layer portion 12 can be formed of the same material as the dielectric layer 14 of the inner layer portion 11 .

(Side gap portion 13)
The side gap portions 13 are disposed so as to sandwich the inner layer portion 11 in the width direction Y, and include a first side gap portion 13a forming a first side surface 2b1 of the multilayer ceramic capacitor 1, and a second side gap portion 13b forming a second side surface 2b2 of the multilayer ceramic capacitor 1. The side gap portions 13 can be formed of the same material as the dielectric layers 14.

(Measurement of particle diameter D50)
The particle diameter D50 can be measured, for example, by the following method. The multilayer ceramic capacitor 1 is vertically set so that the first side surface 2b1 is exposed, and the periphery of the multilayer ceramic capacitor 1 is hardened with resin. Then, the multilayer ceramic capacitor 1 is polished to approximately the center height with a polishing machine. A scanning electron microscope (SEM) photograph of the obtained cross section is taken at a magnification of 10,000 times, and the D50 of the crystal grains is obtained using image processing software.
Here, D50 is the equivalent circle diameter at which the cumulative distribution of the equivalent circle diameters of crystal grains is 50% on a number basis.
In addition, in the case of SEM photographs, the SEM photographs are binarized using a predetermined threshold value to extract only crystal grains, and their grain diameters (area-equivalent circle diameters) can be evaluated.

When the effective portion 16 is divided into three equal parts in the stacking direction Z, that is, into the upper region 16a, the middle region 16b, and the lower region 16c from the top, the grain diameter D50 of the crystal grains 20 constituting the dielectric layer 14 in the middle region 16b is larger than the grain diameter D50 of the crystal grains 20 constituting the dielectric layer 14 in the other two regions, i.e., the upper region 16a or the lower region 16c. FIG. 4(a) shows an enlarged state of the A part of the upper region 16a of the effective portion 16 shown in FIG. 2, and FIG. 4(b) shows an enlarged state of the B part of the middle region 16b of the effective portion 16 shown in FIG. 2. FIG. 4 shows a comparison between the A part of the upper region 16a of the effective portion 16 and the B part of the middle region 16b, and it can be confirmed that the lower region 16c of the effective portion 16 is substantially in the same state as the upper region 16a.

By making the crystal grains 20 of the dielectric layer 14 in the intermediate region 16b larger than the crystal grains 20 of the dielectric layer 14 in the other two regions, it is possible to achieve both high capacitance and reliability even when the multilayer ceramic capacitor is miniaturized.

It is preferable that the particle diameter D50 of the crystal particles 20 constituting the dielectric layer 14 in the intermediate region 16b is 2 to 20 times the particle diameter D50 of the crystal particles constituting the dielectric layer 14 in the other two regions. When the particle diameter D50 of the crystal particles 20 constituting the dielectric layer 14 in the intermediate region 16b is 2 to 20 times the particle diameter D50 of the crystal particles constituting the dielectric layer 14 in the other two regions, even when the multilayer ceramic capacitor is miniaturized, it is possible to maintain a large capacity, and also to maintain insulation and moisture resistance, thereby maintaining reliability.

The dielectric layer 14 in the intermediate region 16b includes a region 20a in which the number of crystal grains 20 forming one layer of the dielectric layer 14 is one when viewed in the stacking direction Z. As shown in FIG. 4(b), in the region 20a of the dielectric layer 14 in the intermediate region 16b, the number of crystal grains forming one layer of the dielectric layer 14 is one when viewed in the stacking direction Z. By providing such a region 20a in the intermediate region 16b, it is possible to maintain a large capacity even when the multilayer ceramic capacitor 1 is miniaturized.

(External electrode 3)
The external electrode 3 includes a first external electrode 3a provided on the first end face 2c1 and a second external electrode 3b provided on the second end face 2c2. The external electrode 3 covers not only the end face 2c but also a part of the main face 2a and the side face 2b continuing from the end face 2c.

As described above, the end of the first extension portion 151a of the first internal electrode layer 15a is exposed to the first end face 2c1 and is electrically connected to the first external electrode 3a. The end of the second extension portion 151b of the second internal electrode layer 15b is exposed to the second end face 2c2 and is electrically connected to the second external electrode 3b. This results in a structure in which multiple capacitor elements are electrically connected in parallel between the first external electrode 3a and the second external electrode 3b.

The external electrode 3 includes, for example, a base electrode layer 30 and a plating layer 31. Note that it is not necessarily required that the external electrode 3 has such a layered structure.

The base electrode layer 30 is formed, for example, by applying and baking a conductive paste containing copper (Cu). The base electrode layer 30 may also contain glass.

The plating layer 31 includes a nickel (Ni) plating layer 31a disposed on the surface of the base electrode layer 30 and a tin (Sn) plating layer 31b disposed on the Ni plating layer 31a. Note that the configuration of the plating layer 31 is not limited to this.

(Method of Manufacturing Multilayer Ceramic Capacitor 1)
A method for manufacturing the multilayer ceramic capacitor 1 will be described with reference to FIG.

A ceramic slurry containing ceramic powder, binder, and solvent is formed into a sheet on the surface of a carrier film using a die coater, gravure coater, microgravure coater, etc. to create a laminated ceramic green sheet 101 that will become the dielectric layer 14. Next, a conductive paste is printed in strips on the laminated ceramic green sheet 101 by screen printing, inkjet printing, gravure printing, etc., and a conductive pattern 102 that will become the internal electrode layer 15 is printed on the surface of the laminated ceramic green sheet 101 to create a material sheet 103.

Next, as shown in FIG. 5(a), multiple material sheets 103 are stacked so that the conductive patterns 102 face the same direction and are shifted by half a pitch in the length direction between adjacent material sheets 103. Furthermore, outer layer ceramic green sheets 112 that will become the outer layer 12 are stacked on both sides of the multiple stacked material sheets 103.

The stacked material sheets 103 and the outer layer ceramic green sheets 112 are thermally pressed together to create the mother block 110 shown in FIG. 5(b).

Next, the mother block 110 is cut along the cutting line x shown in FIG. 5(b) and along the cutting line y intersecting the cutting line x to produce multiple laminates 2 shown in FIG. 5(c).

According to the above process, the outer layer portion 12 and the side gap portion 13 can be formed simultaneously with the formation of the laminate 2, but it is also possible to first form the inner layer portion 11 in which the ends of the internal electrode layer 15 in the width direction Y are exposed on both sides by cutting out from a mother block member, and then attach the side gap portion 13 to both sides of the inner layer portion 11 so as to cover the exposed ends of the internal electrode layer 15, thereby forming the laminate 2. In this case, the attached side gap portion 13 can be made of the same dielectric ceramic material as the dielectric layer 14. The side gap portion 13 may also be formed by applying a ceramic paste to both sides of the inner layer portion 11.

Next, a conductive paste containing copper (Cu) is applied to the end surface 2c of the laminate 2 and baked to form the base electrode layer 30. The base electrode layer 30 is formed so as to extend not only to the end surfaces 2c on both sides of the laminate 2, but also to the main surface 2a and side surface 2b of the laminate 2, and to cover a part of the end surface 2c side of the main surface 2a.

Next, a nickel (Ni) plating layer 31a is formed on the surface of the base electrode layer 30, and a tin (Sn) plating layer 31b is placed on the Ni plating layer 31a to produce the multilayer ceramic capacitor 1 shown in FIG. 5(d).

Although the embodiment of the present invention has been described above, the present invention is not limited to the embodiment, and can be embodied in various forms without departing from the gist of the present invention.

REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 2a Principal surface 2b Side surface 2c End surface 3 External electrode 11 Inner layer portion 12 Outer layer portion 13 Side gap portion 14 Dielectric layer 15 Internal electrode layer 16 Effective portion 16a Upper region 16b Middle region 16c Lower region 17 End gap portion 20 Crystal grain 20a Region 30 Base electrode layer 31 Plating layer

Claims (3)

A multilayer ceramic capacitor comprising: a laminate including an effective portion in which a plurality of internal electrode layers face each other via a dielectric layer in a lamination direction in which the dielectric layers and the internal electrode layers are laminated; and a pair of external electrodes disposed on a surface of the laminate and connected to the internal electrode layers,
When the effective portion is divided into three equal parts in the stacking direction,
A multilayer ceramic capacitor in which the grain size D50 of the crystal grains constituting the dielectric layer in the intermediate region of the effective portion is larger than the grain size D50 of the crystal grains constituting the dielectric layers in the other two regions. The multilayer ceramic capacitor according to claim 1, wherein the grain size D50 of the crystal grains constituting the dielectric layer in the intermediate region is between 2 and 20 times the grain size D50 of the crystal grains constituting the dielectric layers in the other two regions. 3. The multilayer ceramic capacitor according to claim 1, wherein the dielectric layers in the intermediate region include a region in which the number of crystal grains forming one layer of the dielectric layers is one when viewed in the lamination direction.

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