JP2024096030A - Control device and method for adjusting peak output current - Google Patents

Abstract

An adjustment control device and an adjustment control method for an output current peak value are provided.Solution: The adjustment control device adjusts and controls the output current peak value of a power supply, and includes a first comparison circuit for comparing a first integral value in a first cycle of the output current with a first default value and generating a first comparison result when the first integral value is equal to or greater than the first default value, a second comparison circuit for comparing a second integral value in a second cycle of the output current with a second default value and generating a second comparison result when the second integral value is equal to or greater than the second default value, and a logic control circuit for outputting a drop signal when receiving the first comparison result or the second comparison result, thereby lowering the output current peak value.[Selected Figure] Figure 1B

Description

The present disclosure relates to an adjustment control device and an adjustment control method, and in particular to an adjustment control device and an adjustment control method for an output current peak value of an electronic device for providing output power.

When an electronic product starts up, it often needs the cooperation of an external electronic device to provide a large current to start the operation of the electronic product, which may be, for example, a power supply or a source measure unit (SMU). Although the time that the electronic device provides a large current is not long, the electronic device may still trigger a protection mechanism, which will increase the startup time of the electronic product and even cause the product to fail to start. Therefore, the industry is in urgent need of finding a solution.

The Summary of the Invention is intended to provide a simplified summary of the disclosure to enable the reader to have a basic understanding of the disclosure. This Summary of the Invention is not an exhaustive overview of the disclosure, and is not intended to point out important/key parts of the embodiments of the disclosure or to limit the scope of the disclosure.

One technical aspect of the present disclosure relates to an adjustment control device for adjusting and controlling an output current peak value of an electronic device, the adjustment control device including a first comparison circuit for comparing a first integral value in a first cycle of the output current with a first default value and generating a first comparison result when the first integral value is equal to or greater than the first default value, a second comparison circuit for comparing a second integral value in a second cycle of the output current with a second default value and generating a second comparison result when the second integral value is equal to or greater than the second default value, and a logic control circuit for outputting a reduction signal when the first comparison result or the second comparison result is received, thereby reducing the output current peak value.

In one embodiment, the regulation control device further includes a third comparison circuit for comparing, after the default period, a third integral value in the default period of the output current with a third default value, and generating a third comparison result if the third integral value is smaller than the third default value. Upon receiving the third comparison result, the logic control circuit outputs an increase signal to increase the output current peak value.

In one embodiment, the regulation control device further includes an absolute value circuit for taking the absolute value of the current value of the output current to generate a current absolute value. The first comparison circuit, the second comparison circuit, and the third comparison circuit are used to compare the first integral value in the first period of the current absolute value with a first default value, the second integral value in the second period of the current absolute value with a second default value, and the third integral value in the default period of the current absolute value with a third default value, respectively.

In one embodiment, the regulation control device further includes at least one integrator circuit. The at least one integrator circuit is used to integrate the absolute current value of the output current to generate a first integral value in a first period, a second integral value in a second period, and a third integral value in a default period.

In one embodiment, the regulation control device further includes a peak value adjustment circuit for receiving a decrease signal and generating a peak value adjustment signal to decrease the output current peak value of the output current, or for receiving an increase signal and generating a peak value adjustment signal to increase the output current peak value of the output current.

Another technical aspect of the present disclosure relates to an adjustment control method for adjusting and controlling an output current peak value of an electronic device, the adjustment control method including the steps of: comparing a first integral value in a first cycle of the output current with a first default value, and generating a first comparison result when the first integral value is equal to or greater than the first default value; comparing a second integral value in a second cycle of the output current with a second default value, and generating a second comparison result when the second integral value is equal to or greater than the second default value; and outputting a reduction signal in response to the first comparison result or the second comparison result, thereby reducing the output current peak value.

In one embodiment, the adjustment control method further includes a step of comparing, after the default period, a third integral value in the default period of the output current with a third default value, and generating a third comparison result if the third integral value is smaller than the third default value, and a step of increasing the output current peak value by outputting an increase signal in response to the third comparison result.

In one embodiment, the method further includes a step of comparing a first integral value in a first period of the output current with a first default value, and taking an absolute value of the output current before the step of generating a first comparison result if the first integral value is greater than or equal to the first default value.

In one embodiment, the adjustment control method further includes integrating the absolute current value of the output current to generate a first integral value in the first period, a second integral value in the second period, and a third integral value in the default period.

In one embodiment, the adjustment control method further includes generating a peak value adjustment signal in response to the drop signal to decrease the output current peak value, or generating a peak value adjustment signal in response to the rise signal to increase the output current peak value.

Therefore, according to the technical content of the present disclosure, the adjustment control device and adjustment control method shown in the embodiments of the present disclosure can temporarily increase the output current peak value of the electronic device when the electronic device is started up, and can flexibly adjust and control the time of the output peak value of the output current, thereby achieving the purpose of providing a large current to start the electronic device when it is started up, and can adjust and control the length of time to avoid the power supply end device triggering a protection mechanism, thereby solving the problem of the electronic device taking a long time to start up or being unable to start up.

To make the above and other objects, features, advantages and embodiments of the present disclosure more clear and understandable, reference is made to the accompanying drawings below.
1 is a schematic diagram showing an electronic device, an adjustment control device, and an electronic product according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram illustrating a regulation control device according to an embodiment of the present disclosure. FIG. 2 is a waveform diagram showing relevant parameters of the adjustment control device according to an embodiment of the present disclosure. FIG. 2 is a waveform diagram showing relevant parameters of the adjustment control device according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram showing a process of an adjustment control method according to an embodiment of the present disclosure. FIG. 1 is a schematic diagram showing the process of a regulation control method according to an embodiment of the present disclosure. According to conventional working practices, various features and parts in the drawings are not drawn to scale, and the drawing manner is for the purpose of showing specific features and parts related to the present disclosure in an optimal manner. In addition, the same or similar symbols are used in different drawings to refer to similar parts/members.

To more fully and completely describe the present disclosure, the following illustrative embodiments and specific examples of the present disclosure are not intended to be the only ways in which the specific examples of the present disclosure may be implemented or applied. The embodiments include features of multiple specific examples and method steps and sequences for constructing and operating these specific examples. However, other specific examples may be used to achieve the same or equivalent functions and sequences of steps.

Unless otherwise defined herein, scientific and technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Additionally, unless conflicting with context, the singular forms of nouns used herein include the plural forms of such nouns, and the use of the plural forms of nouns also includes the singular form of such nouns.

As used herein, "coupled" may refer to two or more components being in direct physical or electrical contact with each other, in indirect physical or electrical contact with each other, or in such a way that two or more components operate or move with each other.

Please refer to FIG. 1A and FIG. 1B. FIG. 1A shows a schematic diagram of an electronic device 10, an adjustment control device 100, and an electronic product 200 according to an embodiment of the present disclosure, and FIG. 1B shows a schematic diagram of the adjustment control device 100 according to an embodiment of the present disclosure. As shown in the figure, the adjustment control device 100 is used to adjust and control the output current peak value (i.e., the maximum current point of the output current) of the electronic device 10 to supply power from the electronic device 10 to the electronic product 200. The adjustment control device 100 includes a first comparison circuit 150, a second comparison circuit 160, and a logic control circuit 180. The first comparison circuit 150 and the second comparison circuit 160 are coupled to the logic control circuit 180.

In operation, the first comparison circuit 150 is used to compare a first integral value in a first period of the output current with a first default value, and generate a first comparison result when the first integral value is equal to or greater than the first default value. The second comparison circuit 160 is used to compare a second integral value in a second period of the output current with a second default value, and generate a second comparison result when the second integral value is equal to or greater than the second default value. When the logic control circuit 180 receives the first comparison result or the second comparison result, it outputs a drop signal to drop the output peak value of the output current.

For example, when starting up the electronic device, the output current of the electronic device at the power supply end is temporarily increased to act as a starter for starting up the electronic device. For a given state in this disclosure, the output peak value of the output current is high, and is set to, for example, 5V (volts). At this time, the switch 120 of the adjustment control device 100 is switched to the side (lower side) of the first comparison circuit 150 and the second comparison circuit 160, and the first comparison circuit 150 and the second comparison circuit 160 determine whether or not the output peak value of the output current needs to be switched to low, thereby avoiding damage to the internal components of the power supply end.

The judgment condition of the first comparison circuit 150 is to judge whether or not the integral value of the output current is equal to or greater than a first default value in a first period. For example, the first comparison circuit 150 judges whether or not the integral value of the output current within 10 ms (milliseconds) is equal to or greater than a first default value. If the integral value of the output current is equal to or greater than the first default value, the first comparison circuit 150 generates a first comparison result.

The judgment condition of the second comparison circuit 160 is to judge whether the integral value of the output current is equal to or greater than the second default value in the second period. For example, the second comparison circuit 160 judges whether the integral value of the output current within 500 ms is equal to or greater than the second default value. If the integral value of the output current is equal to or greater than the second default value, the second comparison circuit 160 generates a second comparison result. It should be noted that the first default value and the second default value can also be set to be equal or unequal according to the actual needs of the present disclosure. For example, the first default value may be set to, but is not limited to, 60000A, and the second default value may be set to, but is not limited to, 60000*20A, that is, the second default value may be 20 times the first default value, but the length of time is 50 times (500ms/10ms).

When any of the above judgment conditions is met, the logic control circuit 180 receives the first comparison result transmitted from the first comparison circuit 150 or the second comparison result transmitted from the second comparison circuit 160. At this time, the logic control circuit 180 outputs a drop signal to drop the output peak value of the output current, thereby avoiding damage to the internal components of the electronic device at the power supply end.

In one embodiment, the regulation control device 100 further includes a third comparison circuit 170. The third comparison circuit 170 is coupled to the logic control circuit 180. After the default period, the third comparison circuit 170 compares the third integral value in the default period of the output current with a third default value, and generates a third comparison result if the third integral value is smaller than the third default value. When the logic control circuit 180 receives the third comparison result, it outputs an increase signal to increase the output peak value of the output current.

For example, the judgment conditions of the third comparison circuit 170 are to judge whether the duration exceeds the default period and to judge whether the integral value of the output current in the default period is smaller than the current default value. For example, the third comparison circuit 170 judges whether the duration reaches 500 ms, and after 500 ms, the third comparison circuit 170 judges whether the integral value of the output current within 500 ms is smaller than the default value. If the integral value of the output current is smaller than the default value, the third comparison circuit 170 generates a third comparison result. When the above judgment conditions are achieved, the logic control circuit 180 receives the third comparison result and at this time outputs an increase signal to increase the output peak value of the output current.

In one embodiment, the adjustment control device 100 further includes an absolute value circuit 110. Since the output current of the electronic device at the power supply end may be an AC current, in order to perform the subsequent integration operation, the absolute value circuit 110 needs to take the absolute value of the current value of the output current to generate a current absolute value. For example, the first comparison circuit 150, the second comparison circuit 160, and the third comparison circuit 170 may be used to compare the first integral value in the first period of the current absolute value with a first default value, the second integral value in the second period of the current absolute value with a second default value, and the third integral value in the default period of the current absolute value with a third default value, respectively.

In one embodiment, the regulation control device 100 further includes at least one integrating circuit, for example, a first integrating circuit 130 and a second integrating circuit 140. The at least one integrating circuit is used to integrate the current absolute value of the output current. For example, when the switch 120 is switched to the side (e.g., the lower side) of the first comparison circuit 150 and the second comparison circuit 160, the first integrating circuit 130 generates a first integral value in a first period and transmits it to the first comparison circuit 150 for a subsequent comparison process, and the first integrating circuit 130 generates a second integral value in a second period and transmits it to the second comparison circuit 160 for a subsequent comparison process. When the switch 120 is switched to the side (e.g., the upper side) of the third comparison circuit 170, the second integrating circuit 140 generates a third integral value in a default period and transmits it to the third comparison circuit 170 for a subsequent comparison process. The switch 120 may be set in advance to switch to the side of the first comparison circuit 150 and the second comparison circuit 160 (e.g., the lower side). When the output peak value of the output current switches to low, the switch 120 switches to the side of the third comparison circuit 170 (e.g., the upper side). Then, when the output peak value of the output current switches to high, the switch 120 switches again to the side of the first comparison circuit 150 and the second comparison circuit 160 (e.g., the lower side).

In one embodiment, the regulation control device 100 further includes a peak value adjustment circuit 190 coupled to the logic control circuit 180. The peak value adjustment circuit 190 is used to receive a drop signal by the logic control circuit 180 and generate a peak value adjustment signal Sout to drop the output peak value of the output current. Alternatively, the peak value adjustment circuit 190 is used to receive an increase signal by the logic control circuit 180 and generate a peak value adjustment signal Sout to raise the output peak value of the output current. Note that the present disclosure is not limited to the structure shown in FIG. 1B, and is merely an exemplary embodiment of the present disclosure to facilitate understanding of the technology of the present disclosure, and the claims of the present disclosure are based on the claims of the invention. Modifications and modifications made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit of the present disclosure still fall within the scope of the claims of the present disclosure.

Figure 2 shows a waveform diagram of the relevant parameters of the regulation control device 100 shown in Figure 1B according to one embodiment of the present disclosure. As shown in the figure, the output current of the power supply is Iout. The first integral value in the first period is Intel. The second integral value in the second period is Inte2. The peak value adjustment signal is Sout. In the first period 0S (seconds) to 0.01S (seconds), the first integral value Intel continues to rise, but after one first period, the first integral value Intel is not greater than or equal to the first default value, so the peak value adjustment signal Sout still remains at a high level. Also, since the first integral value Intel in the first period 0S to 0.01S is not greater than or equal to the first default value, the first integral value Intel is then cleared, and the first integral value Intel is recalculated and recompared from another first period 0.01S to 0.02S, and so on. Assuming that the first integral value Intel is equal to or greater than the first default value in any first period, the peak value adjustment signal Sout is adjusted from a high level to a low level, thereby lowering the output peak value of the electronic device.

In the second period from 0S (seconds) to 0.05S (seconds), the second integral value Inte2 continues to rise. As can be seen from the figure, in the section from 0.03S to 0.04S, the second integral value Inte2 is greater than or equal to the second default value, so the peak value adjustment signal Sout is adjusted from high level to low level, thereby lowering the output peak value of the power supply. After the output peak value of the power supply is lowered, it can be seen that the output current Iout is limited to a low level from the section from 0.04S to 0.05S.

FIG. 3 shows a waveform diagram of relevant parameters of the regulation control device 100 shown in FIG. 1B according to an embodiment of the present disclosure. As shown in the figure, the output current of the power supply is Iout. The third integral value in the default period is Inte3. The count value is Tcount, for example, 1 count is 10us. The peak value adjustment signal is Sout. After the default period 0S-0.05S, it is determined whether the third integral value Inte3 is smaller than the third default value. As can be seen from the figure, even if the default period 0S-0.05S continues, the third integral value Inte3 is still smaller than the third default value, so the peak value adjustment signal Sout is adjusted from a low level to a high level to increase the output peak value of the power supply. After the output peak value of the power supply is increased, it can be seen that the output current Iout has already returned to a high level from the section 0.05S-0.06S. Note that the present disclosure is not limited to the parameters shown in Figures 2 and 3, which merely exemplify one of the implementation methods of the present disclosure in order to facilitate understanding of the technology of the present disclosure, and the scope of the claims of the present disclosure is based on the scope of the claims of the invention. Modifications and modifications made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit of the present disclosure still fall within the scope of the claims of the present disclosure.

Figure 4 shows a schematic diagram of the process of the adjustment control method 400 according to one embodiment of the present disclosure. To facilitate understanding of the adjustment control method 400, the detailed process of the adjustment control method 400 will be described below with reference to Figures 1B and 4.

In step 410, the first integral value in the first period of the output current is compared with the first default value, and a first comparison result is generated if the first integral value is equal to or greater than the first default value. For example, the first comparison circuit 150 determines whether the integral value of the output current in the first period (e.g., 10 ms) is equal to or greater than the first default value. If the integral value of the output current is equal to or greater than the first default value, the first comparison circuit 150 generates a first comparison result.

In step 420, the second integral value in the second period of the output current is compared with the second default value, and a second comparison result is generated if the second integral value is equal to or greater than the second default value. For example, the second comparison circuit 160 determines whether the integral value of the output current in the second period (e.g., 500 ms) is equal to or greater than the second default value. If the integral value of the output current is equal to or greater than the second default value, the second comparison circuit 160 generates a second comparison result. Note that the first default value and the second default value can also be set to be equal or unequal according to the actual needs of the present disclosure.

In step 430, in response to the first comparison result or the second comparison result, a drop signal is output to drop the output peak value of the output current. For example, when any of the above judgment conditions is achieved, the logic control circuit 180 receives the first comparison result or the second comparison result, and at this time, the logic control circuit 180 outputs a drop signal to drop the output peak value of the output current, thereby avoiding damage to the internal components of the electronic device at the power supply end and triggering a protection mechanism.

In step 440, after the default period, the third integral value in the default period of the output current is compared with the third default value, and if the third integral value is smaller than the third default value, a third comparison result is generated. For example, the third comparison circuit 170 determines whether the duration reaches 500 ms, and if the duration reaches 500 ms, the third comparison circuit 170 determines whether the integral value of the output current within 500 ms is smaller than the current default value. If the integral value of the output current is smaller than the current default value, the third comparison circuit 170 generates a third comparison result.

In step 450, the output peak value of the output current is increased by outputting an increase signal in response to the third comparison result. For example, when the above judgment condition is achieved, the logic control circuit 180 receives the third comparison result, and at this time, the logic control circuit 180 increases the output peak value of the output current by outputting an increase signal.

In one embodiment, the regulation control method 400 further includes integrating the current absolute value of the output current to generate a first integral value in the first period, a second integral value in the second period, and a third integral value in the default period. For example, the first integration circuit 130 and the second integration circuit 140 each integrate the current absolute value of the output current to generate a first integral value in the first period, a second integral value in the second period, and a third integral value in the default period.

In one embodiment, the regulation control method 400 further includes a step of taking an absolute value for the current value of the output current to generate a current absolute value. Because the output current of the power supply may be an AC current, the absolute value circuit 110 needs to take an absolute value for the current value of the output current to generate a current absolute value in order to perform the subsequent integration operation. For example, the first comparison circuit 150, the second comparison circuit 160, and the third comparison circuit 170 may be used to compare the first integral value in the first period of the current absolute value with a first default value, the second integral value in the second period of the current absolute value with a second default value, and the third integral value in the default period of the current absolute value with a third default value, respectively.

In one embodiment, the regulation control method 400 further includes a step of generating a peak value regulation signal in response to a drop signal to lower the output peak value of the output current, or generating a peak value regulation signal in response to a rise signal to raise the output peak value of the output current. For example, the peak value regulation circuit 190 is used by the logic control circuit 180 to receive a drop signal and generate a peak value regulation signal Sout to lower the output peak value of the output current. Or, the peak value regulation circuit 190 is used by the logic control circuit 180 to receive an increase signal and generate a peak value regulation signal Sout to raise the output peak value of the output current.

Note that the present disclosure is not limited to the process shown in FIG. 4, which merely exemplifies one of the implementation methods of the present disclosure in order to facilitate understanding of the technology of the present disclosure, and the scope of the claims of the present disclosure is based on the scope of the claims of the invention. Modifications and modifications made to the embodiments of the present disclosure by a person skilled in the art without departing from the spirit of the present disclosure still fall within the scope of the claims of the present disclosure.

Figure 5 shows a schematic diagram of the process of the regulation control method 500 according to one embodiment of the present disclosure. For easy understanding of the regulation control method 500, please refer to Figure 1B and Figure 5 together. In step 501, the output peak value is preset to high, for example, the output peak value is preset to 5V. In step 502, the absolute value circuit 110 takes the absolute value of the output current to generate a current absolute value. In step 503, it is determined whether the output peak value is high. If the output peak value is high, the steps on the right side of the figure are executed.

In step 504, a first period integral is performed on the current absolute value to obtain a first integral value. In step 505, the first comparison circuit 150 determines whether the first integral value is greater than or equal to a first default value. If the first integral value is greater than or equal to the first default value, step 506 is performed to lower the output peak value and adjust and control the parameters in the adjustment control method 500 (e.g., the first integral value, the second integral value, the first count value, and the second count value) to 0, and then the process returns to step 502. If the first integral value is not greater than the first default value, step 507 is performed to add 1 to the first count value.

In step 508, it is determined whether the first count value has reached 1000. If the first count value has not reached 1000, the process returns to step 502. If the first count value has reached 1000, step 509 is executed, and the first integral value and the first count value are adjusted to 0, and then the process returns to step 502.

Also, in step 510, a second periodic integration is performed on the current absolute value to obtain a second integral value. In step 511, the second comparison circuit 160 determines whether the second integral value is equal to or greater than the second default value. If the second integral value is equal to or greater than the second default value, step 506 is performed to lower the output peak value and adjust and control the parameters in the adjustment control method 500 (e.g., the first integral value, the second integral value, the first count value, and the second count value) to 0, and then the process returns to step 502 and is executed. If the second integral value is not greater than the second default value, step 512 is performed to add 1 to the second count value.

In step 513, it is determined whether the second count value has reached 50,000. If the second count value has not reached 50,000, the process returns to step 502. If the second count value has reached 50,000, step 514 is executed, and the second integral value and the second count value are adjusted to 0, and then the process returns to step 502.

See step 503. If it is determined that the output peak value is not high, the steps on the left side of the figure are executed. In step 515, a default periodic integration is executed on the current absolute value to obtain a third integral value. In step 516, it is determined whether the third count value has reached 50,000. If the third count value has not reached 50,000, step 517 is executed to add 1 to the third count value, and then the process returns to step 502. If the third count value reaches 50,000, step 518 is executed, and the third comparison circuit 170 determines whether the third integral value is smaller than a third default value. If the third integral value is smaller than the third default value, step 520 is executed to increase the output peak value, and the parameters (e.g., the third integral value and the third count value) in the regulation control method 500 are adjusted to 0, and then the process returns to step 502. If the third integral value is not smaller than the third default value, step 519 is executed to adjust and control the third integral value and the third count value to 0, and then the process returns to step 502. Note that the present disclosure is not limited to the process shown in FIG. 5, which merely exemplifies one of the implementation methods of the present disclosure in order to facilitate understanding of the technology of the present disclosure, and the scope of the claims of the present disclosure is based on the scope of the claims of the invention. Modifications and modifications made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit of the present disclosure still fall within the scope of the claims of the present disclosure.

As can be seen from the above embodiments of the present disclosure, the adoption of the present disclosure has the following advantages. The adjustment control device and adjustment control method shown in the embodiments of the present disclosure can temporarily increase the output current peak value of the electronic device at the power supply end when the electronic device is started up, and can flexibly adjust and control the time for which the output peak value of the output current is temporarily increased, thereby achieving the purpose of providing a large current to start the electronic device when it is started up, and can adjust and control the length of time to avoid damaging the internal components of the electronic device at the power supply end and triggering the protection mechanism.

Although specific examples of the present disclosure have been disclosed in the above embodiments, they are not intended to limit the present disclosure, and a person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure is based on what is defined in the appended claims.

10 Electronic device 100 Adjustment control device 110 Absolute value circuit 120 Switch 130 First integrator circuit 140 Second integrator circuit 150 First comparator circuit 160 Second comparator circuit 170 Third comparator circuit 180 Logic control circuit 190 Peak value adjustment circuit 200 Electronic product 400 Method 410-450 Step 500 Method 501-520 Step Iout Output current Intel First integral value Inte2 Second integral value Inte3 Third integral value Sout Peak value adjustment signal Tcount Count value

Claims (10)

An adjustment control device for adjusting and controlling an output current peak value of an output current of an electronic device,
a first comparison circuit for comparing a first integral value in a first period of the output current with a first default value and generating a first comparison result when the first integral value is equal to or greater than the first default value;
a second comparison circuit for comparing a second integral value in a second period of the output current with a second default value and generating a second comparison result when the second integral value is equal to or greater than the second default value;
a logic control circuit that outputs a reduction signal when receiving the first comparison result or the second comparison result, thereby reducing the output current peak value;
An adjustment control device comprising: a third comparison circuit for comparing a third integral value of the output current in the default period with a third default value after a default period, and generating a third comparison result when the third integral value is smaller than the third default value;
The regulation control device according to claim 1 , wherein the logic control circuit increases the output current peak value by outputting an increase signal when the logic control circuit receives the third comparison result. an absolute value circuit for taking an absolute value of the current value of the output current to generate a current absolute value;
3. The adjustment control device according to claim 2, wherein the first comparison circuit, the second comparison circuit, and the third comparison circuit are used to compare the first integral value in the first period of the current absolute value with the first default value, compare the second integral value in the second period of the current absolute value with the second default value, and compare the third integral value in the default period of the current absolute value with the third default value, respectively. The adjustment control device according to claim 3, further comprising at least one integration circuit for integrating the absolute current value of the output current to generate the first integral value in the first period, the second integral value in the second period, and the third integral value in the default period. The regulation control device according to claim 4, further comprising a peak value adjustment circuit for receiving the drop signal and generating a peak value adjustment signal to drop the output current peak value of the output current, or for receiving the rise signal and generating the peak value adjustment signal to raise the output current peak value of the output current. 1. A method for adjusting and controlling an output current peak value of an output current of an electronic device, comprising:
comparing a first integral value in a first period of the output current with a first default value, and generating a first comparison result when the first integral value is equal to or greater than the first default value;
comparing a second integral value in a second period of the output current with a second default value, and generating a second comparison result when the second integral value is equal to or greater than the second default value;
outputting a reduction signal in response to the first comparison result or the second comparison result, thereby reducing the output current peak value;
The adjustment control method includes: After a default period, comparing a third integral value of the output current during the default period with a third default value, and generating a third comparison result when the third integral value is smaller than the third default value;
increasing the peak output current value by outputting an increase signal in response to the third comparison result;
The method of claim 6 further comprising: prior to the step of comparing a first integral value in the first period of the output current with a first default value and generating the first comparison result when the first integral value is equal to or greater than the first default value;
The method of regulation control of claim 7 , further comprising taking the absolute value of the output current to obtain a current absolute value. The adjustment control method according to claim 8, further comprising a step of integrating the absolute current value of the output current to generate the first integral value in the first period, the second integral value in the second period, and the third integral value in the default period. The regulation control method according to claim 9, further comprising the step of generating a peak value regulation signal in response to the drop signal to lower the output current peak value, or generating the peak value regulation signal in response to the rise signal to raise the output current peak value.

Images