JP2024093764A - Semiconductor Device - Google Patents

Abstract

To provide a semiconductor device that performs power gating, in which shoot-through current and malfunction are prevented while the problems such as operational delay and increased power consumption are eliminated.SOLUTION: A semiconductor device includes: a power domain; and a power controller which is a combination of a P-type transistor and an N-type transistor and which switches between a state in which a power supply voltage is supplied to the power domain and a state in which a power supply voltage is not supplied to the power domain, in response to a control signal input from the outside. An output portion of the power controller is connected to a power supply line or a ground line of the power domain.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device.

In recent years, as various electronic devices equipped with logic circuits have become more mobile, there is a demand for lower power consumption in the logic circuits used in electronic devices. Logic circuits used in electronic devices are often composed of semiconductor integrated circuits such as CMOS (Complementary Metal Oxide Semiconductor).

In recent years, the manufacturing process for CMOS has become finer, with gate widths reduced and oxide films made thinner. As the manufacturing process becomes finer, the leakage current in CMOS increases, and the resulting power consumption can no longer be ignored.

As a countermeasure to this, a method called power gating has been proposed, which cuts off the power supply to each power domain during periods when the logic circuit is not operating, thereby reducing leakage current (see, for example, Patent Document 1, Patent Document 2, or Non-Patent Document 1).

Patent No. 6722986 U.S. Pat. No. 7,694,251

X. Bai et al., "Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation," in IEEE Journal of Solid-State Circuits, vol. 57, no. 7, pp. 2250-2262, July 2022.

Figure 15 is a schematic diagram of an integrated circuit having a conventional configuration in which a power gating transistor is arranged on the power supply line of a power domain. Figure 16 is a schematic diagram of an integrated circuit having a conventional configuration in which a power gating transistor is arranged on the ground line of a power domain.

In the configuration of a conventional semiconductor device 100 as shown in FIG. 15, power gating transistors 120 and 121 are connected to the power supply lines of the power domains 110 and 111, respectively. The transistors 120 and 121 function as power switches that switch the power supply state to the power domains 110 and 111. An isolation cell 130 is inserted between the power domains 110 and 111.

Also, as shown in FIG. 16, even when power gating transistors 120, 121 are connected to the ground lines of power domains 110, 111, respectively, an isolation cell 130 is inserted between power domain 110 and power domain 111 in the same manner.

Figure 17 is a diagram to explain the problem that occurs when an isolation cell is not inserted between power domains 110 and 111 in the conventional configuration shown in Figure 16.

As shown in FIG. 17, when the power supply of the front-stage power domain 110 is off and the power supply of the rear-stage power domain 111 is on, the output signal OUT0 of the power domain 110 becomes unstable, and a through current may occur in the CMOS provided in the rear-stage power domain 111. In addition, the output signal OUT0 with an unstable signal value may propagate to the rear-stage power domain 111, causing a malfunction in the circuit within the power domain 111.

Figure 18 is a diagram for explaining the problem that occurs when an AND circuit is inserted between the power domains 110 and 111 as an example of an isolation cell 130 in the conventional configuration shown in Figure 16. The AND circuit 130 is a circuit that performs a logical AND operation on two input signals.

As shown in FIG. 18, when the control signal ENG0 input to the transistor 120 is set to ground potential (i.e., logical value "0") to turn off the power supply to the preceding power domain 110, the output of the AND circuit 130 becomes "0" regardless of the logical value of the output signal OUT0 of the power domain 110, thereby preventing shoot-through current and malfunction in the following power domain 111.

However, the use of such an isolation cell 130 causes problems in the semiconductor device 100A, such as operational delays and increased power consumption.

The above problem also occurs in a semiconductor device 100 in which power gating transistors 120 and 121 are arranged on the power line side of the power domains 110 and 111, as shown in FIG. 15.

The present invention has been made to solve the above problems, and the object of the present invention is to provide a semiconductor device that performs power gating and prevents shoot-through current and malfunction while eliminating the problems of operational delays and increased power consumption.

The semiconductor device of the present invention comprises a power domain, and a power controller that is a combination of P-type and N-type transistors and that switches between a state in which a power supply voltage is supplied to the power domain and a state in which it is not supplied in response to a control signal input from the outside, and an output section of the power controller is connected to the power supply line or ground line of the power domain.

In the semiconductor device of the present invention, the power domain may have a P-type transistor, and the output of the power controller may be connected to a body terminal of the P-type transistor of the power domain.

The power domain may also have an N-type transistor, and the output of the power controller may be connected to a body terminal of the N-type transistor of the power domain.

The power controller may further include a power switch that switches between a state in which a power supply voltage is supplied to the power domain and a state in which a power supply voltage is not supplied to the power domain in response to a control signal input from the outside, and the output of the power controller is connected to a power supply line or a ground line of a portion of the power domain in the final stage, and the power switch may be connected to a power supply line or a ground line of a portion of the power domain other than the final stage.

The output of the power controller may also be connected to a power supply line or a ground line of the first stage of the power domain.

The power domain may include a first power domain configured with transistors that operate at a first voltage, and a second power domain configured with transistors that operate at a second voltage higher than the first voltage, and the output of the second power domain may be connected to the input of the first power domain.

The second power domain may also include a non-volatile variable resistance element whose resistance state changes depending on the direction of the voltage applied between two electrodes, and a write circuit for performing a write operation to change the resistance state of the non-volatile variable resistance element.

The semiconductor device of the present invention can prevent shoot-through current and malfunctions in a semiconductor device that performs power gating, while resolving the problems of operational delays and increased power consumption.

1 is a diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention; 2 is a diagram for explaining the operation of the semiconductor device shown in FIG. 1; FIG. 1 is a diagram showing a schematic configuration of a semiconductor device according to a modified example of the first embodiment of the present invention. 4 is a diagram for explaining the operation of the semiconductor device shown in FIG. 3; FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a second embodiment of the present invention, showing a hybrid power gating circuit of a power inverter of a power supply type and a power switch of a power supply type. FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a modified example of the second embodiment of the present invention, and shows a hybrid power gating circuit including a ground type power inverter and a power supply type power switch. FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a modified example of the second embodiment of the present invention, and shows a hybrid power gating circuit including a ground type power inverter and a ground type power switch. FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a modified example of the second embodiment of the present invention, and shows a hybrid power gating circuit including a power supply type power inverter and a ground type power switch. FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a third embodiment of the present invention. 10A to 10C are diagrams for explaining the operation of the semiconductor device shown in FIG. 9 . FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a modified example of the third embodiment of the present invention. 12 is a diagram for explaining a power gating mode of the semiconductor device shown in FIG. 11 . 12 is a diagram for explaining a write mode of the semiconductor device shown in FIG. 11 . 12 is a diagram for explaining an application mode of the semiconductor device shown in FIG. 11 . FIG. 1 is a schematic diagram of an integrated circuit having a conventional configuration in which a power gating transistor is arranged in a power supply line of a power domain. FIG. 1 is a schematic diagram of an integrated circuit having a conventional configuration in which a power gating transistor is arranged on a ground line of a power domain. FIG. 17 is a diagram for explaining a problem that occurs when an isolation cell is not inserted between power domains in the conventional configuration shown in FIG. 16 . FIG. 17 is a diagram for explaining a problem that occurs when an AND circuit is inserted between power domains as an example of an isolation cell in the conventional configuration shown in FIG. 16.

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

First Embodiment
First, a semiconductor device 1 according to a first embodiment of the present invention will be described. Fig. 1 is a diagram showing a schematic configuration of the semiconductor device 1 according to the first embodiment of the present invention. Fig. 2 is a diagram for explaining the operation of the semiconductor device 1.

The semiconductor device 1 of this embodiment is an integrated circuit equipped with a power inverter type power gating circuit that uses a power inverter to control the power supply of the power domain.

As shown in FIG. 1, the semiconductor device 1 of this embodiment includes two power domains, a front-stage power domain 10 and a rear-stage power domain 11, and two power inverters 20 and 21 that are formed by combining P-type and N-type transistors and that switch between a state in which a power supply voltage is supplied to the power domains 10 and 11 (power-on state) and a state in which a power supply voltage is not supplied (power-off state) in response to a control signal input from the outside.

Here, "power domain" refers to an area in semiconductor device 1 where the power supply can be switched on and off simultaneously.

As an example, the power inverters 20 and 21 are configured with a CMOS that combines a P-type MOS-FET (Metal Oxide Semiconductor Field Effect Transistor), which is a P-type transistor, and an N-type MOS-FET, which is an N-type transistor.

The power inverters 20 and 21 are an example of a power controller in the technology of the present invention. The power controller is a circuit that combines P-type transistors and N-type transistors, and is not limited to the CMOS inverter configuration described above. Various modifications are possible, such as a CMOS transistor circuit that includes a NOR gate or a NAND gate.

The output section 20a of the power inverter 20 is connected to the power supply line of the power domain 10 in the preceding stage. Also, the output section 21a of the power inverter 21 is connected to the power supply line of the power domain 11 in the following stage. Here, "power supply line" means the part of the power domain 10 and the power domain 11 that is connected to the power supply.

As shown in FIG. 2, the power domain 10 has, as an example, a CMOS 30 that combines a P-type MOS-FET 30P and an N-type MOS-FET 30N, and the output section 20a of the power inverter 20 is connected to the body terminal of the P-type MOS-FET 30P.

Similarly, the power domain 11 has a CMOS 31 that is a combination of a P-type MOS-FET 31P and an N-type MOS-FET 31N, and the output section 21a of the power inverter 21 is connected to the body terminal of the P-type MOS-FET 31P.

Next, the operation of semiconductor device 1 will be described.

As shown in FIG. 2, when the logical value of the control signal END0 input to the power inverter 20 is set to "1 (i.e., the power supply potential VDD)," the potential of the output section 20a of the power inverter 20 becomes the ground potential GND, and the power supply to the power domain 10 is turned off.

At this time, the source terminal and body terminal of the P-type MOS-FET 30P connected to the output section 20a of the power inverter 20 are at ground potential GND, and the drain terminal that is PN junctioned with the body terminal is also at ground potential GND.

Therefore, the output logic value of the output signal OUT0 of the CMOS 30 via the P-type MOS-FET 30P becomes "0 (i.e., ground potential GND)," and the logic value of the output signal OUT0 stabilizes at "0 (i.e., ground potential GND)."

This makes it possible to prevent shoot-through current and malfunction in the CMOS 31 of the subsequent power domain 11. Furthermore, since there is no need to place an isolation cell between the power domain 10 and the power domain 11, it is possible to eliminate operational delays and increased power consumption due to the placement of the isolation cell.

[Modification of the first embodiment]
In the above-described semiconductor device 1, the output section 20a of the power inverter 20 and the output section 21a of the power inverter 21 are connected to the power supply lines of the power domains 10 and 11, respectively, but may be connected to the ground lines of the power domains 10 and 11. Such an embodiment will be described below.

Figure 3 is a diagram showing a schematic configuration of a semiconductor device 1A according to a modified example of the first embodiment of the present invention. Figure 4 is a diagram for explaining the operation of the semiconductor device 1A.

The semiconductor device 1A of the modified embodiment of this embodiment has the same configuration as the semiconductor device 1 described above, except that the output section 20a of the power inverter 20 and the output section 21a of the power inverter 21 are each connected to the ground lines of the power domain 10 and the power domain 11, so a description of the configuration will be omitted.

As shown in FIG. 3, the output section 20a of the power inverter 20 is connected to the ground line of the power domain 10 in the preceding stage. Also, the output section 21a of the power inverter 21 is connected to the ground line of the power domain 11 in the following stage. Here, the "ground line" refers to the portion of the power domain 10 and the power domain 11 that is connected to ground.

As shown in FIG. 4, the power domain 10 has, as an example, a CMOS 30 that combines a P-type MOS-FET 30P and an N-type MOS-FET 30N, and the output section 20a of the power inverter 20 is connected to the body terminal of the N-type MOS-FET 30N.

Similarly, the power domain 11 has a CMOS 31 that is a combination of a P-type MOS-FET 31P and an N-type MOS-FET 31N, and the output section 20a of the power inverter 21 is connected to the body terminal of the N-type MOS-FET 31N.

Next, the operation of semiconductor device 1A will be explained.

As shown in FIG. 4, when the logical value of the control signal ENG0 input to the power inverter 20 is set to "0 (i.e., ground potential)," the potential of the output section 20a of the power inverter 20 becomes the power supply potential VDD, and the power supply of the power domain 10 is turned off.

At this time, the source terminal and body terminal of the N-type MOS-FET 30N connected to the output section 20a of the power inverter 20 are at the power supply potential VDD, and the drain terminal that is PN junctioned with the body terminal is also at the power supply potential VDD.

Therefore, the output signal OUT0 of CMOS 30 has an output logical value of "1 (i.e., power supply potential VDD)" via P-type MOS-FET 30P, and the logical value of the output signal OUT0 stabilizes at "1 (i.e., power supply potential VDD)."

This makes it possible to prevent shoot-through current and malfunction in the CMOS 31 of the subsequent power domain 11. Furthermore, since there is no need to place an isolation cell between the power domain 10 and the power domain 11, it is possible to eliminate operational delays and increased power consumption due to the placement of the isolation cell.

Second Embodiment
Next, a semiconductor device 2 according to a second embodiment of the present invention will be described below. Fig. 5 is a diagram showing a schematic configuration of the semiconductor device 2 according to the second embodiment of the present invention.

The semiconductor device 2 of this embodiment is configured with a hybrid power gating circuit that combines a power inverter and a power switch.

As shown in FIG. 5, the semiconductor device 2 of this embodiment is composed of two power domains, a front-stage power domain 10 and a rear-stage power domain 11, a combination of a P-type MOS-FET and an N-type MOS-FET, and includes two power inverters 20, 21 for switching between a state in which a power supply voltage is supplied to the power domains 10, 11 and a state in which it is not supplied in response to a control signal input from the outside, and power switches 40, 41 for switching between a state in which a power supply voltage is supplied to the power domains 10, 11 and a state in which it is not supplied in response to a control signal input from the outside.

Here, a "power switch" does not refer to an inverter formed by combining two transistors, but rather refers to a single element, such as a transistor, that switches between a state in which a power supply voltage is supplied and a state in which it is not supplied. As an example, the power switches 40 and 41 in this embodiment are formed of P-type MOS-FETs.

The output section 20a of the power inverter 20 is connected to the power supply line of the final stage section 10b of the preceding power domain 10. The output section 21a of the power inverter 21 is connected to the power supply line of the final stage section 11b of the succeeding power domain 11.

The power switch 40 is connected to the power line of the portion 10a of the power domain 10 other than the final stage. The power switch 41 is connected to the power line of the portion 11a of the power domain 11 other than the final stage.

To prevent shoot-through current and malfunction in the CMOS 31 of the subsequent power domain 11, it is sufficient that the power supply of the final stage portion 10b of the preceding power domain 10 is controlled by the power inverter 20, and there is no need to use a power inverter for power supply control of the portions 10a other than the final stage.

Therefore, for the parts 10a other than the final stage, the power supply is controlled by a power switch 40 made of a P-type MOS-FET, which is smaller in size than the power inverter (CMOS in this example), thereby making it possible to reduce the size of the circuit area required for power gating.

[Modification of the second embodiment]
In this embodiment, the power inverter and the power switch are not limited to being connected to the power supply line of the power domain, and may be connected to the ground line of the power domain.

Hereinafter, the power inverter and power switch connected to the power line will be referred to as the power supply type power inverter and power switch. Also, the power inverter and power switch connected to the ground line will be referred to as the ground type power inverter and power switch.

For example, a hybrid power gating circuit may be used that combines ground-type power inverters 20, 21 and power supply-type power switches 40, 41, as in the semiconductor device 2A shown in FIG. 6.

Also, as shown in FIG. 7, a hybrid power gating circuit may be used that combines ground type power inverters 20, 21 with ground type power switches 40, 41, as in semiconductor device 2B.

Also, as shown in FIG. 8, a hybrid power gating circuit may be used that combines power supply type power inverters 20, 21 with ground type power switches 40, 41, as in semiconductor device 2C.

Third Embodiment
Next, a semiconductor device 3 according to a third embodiment of the present invention will be described. Fig. 9 is a diagram showing a schematic configuration of the semiconductor device 3 according to the third embodiment of the present invention. Fig. 10 is a diagram for explaining the operation of the semiconductor device 3.

The semiconductor device 3 of this embodiment is configured with the hybrid power gating circuit shown in the second embodiment, with the rear power domain being a core voltage power domain 11 configured with transistors that operate at the core voltage, and the front power domain being a high voltage power domain 10 configured with transistors that operate at a voltage higher than the core voltage.

The high voltage power domain 10 is an example of a second power domain in the technology of the present invention. Also, the core voltage power domain 11 is an example of a first power domain in the technology of the present invention.

When the operating voltage of the high voltage power domain 10 is VHV and the operating voltage of the core voltage power domain 11 is VDD, the operating voltage VHV is set within a range that satisfies the following conditional expression (1).
VHV≦2×VDD

As shown in Figures 9 and 10, the semiconductor device 3 of this embodiment is composed of two power domains, a front-stage high-voltage power domain 10 and a rear-stage core voltage power domain 11, a combination of P-type MOS-FETs and N-type MOS-FETs, and includes two power inverters 20, 21 for switching between a state in which a power supply voltage is supplied to the high-voltage power domain 10 and the core voltage power domain 11 and a state in which it is not supplied in response to a control signal input from the outside, and power switches 40, 41 for switching between a state in which a power supply voltage is supplied to the high-voltage power domain 10 and the core voltage power domain 11 and a state in which it is not supplied in response to a control signal input from the outside.

The output section 20a of the power inverter 20 is connected to the power supply line of the final stage section 10b of the preceding high voltage power domain 10. The output section 21a of the power inverter 21 is connected to the ground lines of the first stage section 11a and the final stage section 11c of the following core voltage power domain 11.

The power switch 40 is connected to the power supply line of the portion 10a of the high-voltage power domain 10 other than the final stage. The power switch 41 is connected to the ground line of the intermediate portion 11b of the power domain 11 of the subsequent stage.

The output 10c of the high voltage power domain 10 is connected to the input 11d of the core voltage power domain 11.

Next, the operation of the semiconductor device 3 of this embodiment will be described.

When the power supply of the front-stage high-voltage power domain 10 is on and the power supply of the rear-stage core voltage power domain 11 is off, a high voltage is applied to the gate terminal of a transistor included in the first-stage portion 11a of the core voltage power domain 11, which may cause the circuit of the core voltage power domain 11 to fail.

In the semiconductor device 3 of this embodiment, as shown in FIG. 10, when the logical value of the control signal ENG1 input to the power inverter 21 is set to "0 (i.e., ground potential GND)," the potential of the output section 21a of the power inverter 21 becomes VDD, and the power supply of the core voltage power domain 11 is turned off.

At this time, the potential of the source terminal and body terminal of the N-type MOS-FET 31N connected to the output section 21a of the power inverter 21 becomes VDD, and the potential of the drain terminal that is PN junctioned with the body terminal also becomes VDD.

Therefore, even if a high voltage VHV (where VHV≦2×VDD) is applied from the output section 10c of the high voltage power domain 10 to the gate terminals of the P-type MOS-FET 31P and N-type MOS-FET 31N included in the first-stage portion 11a of the core voltage power domain 11, the potential difference between the gate terminal and source terminal, the potential difference between the gate terminal and body terminal, and the potential difference between the gate terminal and drain terminal of the P-type MOS-FET 31P and N-type MOS-FET 31N are lower than VDD, so failure of the transistors included in the core voltage power domain 11 can be prevented.

In addition, because the power supply control of the final stage portion 10b of the high-voltage power domain 10 is performed by the power inverter 20, as described in the first embodiment, the output signal is stabilized at "0 (i.e., ground potential)" when the power supply of the high-voltage power domain 10 is in the off state.

Therefore, when the power supply of the front-stage high-voltage power domain 10 is in an off state and the power supply of the rear-stage core voltage power domain 11 is in an on state, it is possible to prevent the occurrence of shoot-through current and malfunction in the CMOS 31 of the rear-stage core voltage power domain 11. Furthermore, since it is not necessary to place an isolation cell between the high-voltage power domain 10 and the core voltage power domain 11, it is possible to eliminate operational delays and increased power consumption due to the placement of the isolation cell.

[Modification of the third embodiment]
FIG. 11 is a diagram showing a schematic configuration of a semiconductor device 3A according to a modification of the third embodiment of the present invention.

In the semiconductor device 3 of this embodiment, the high-voltage power domain 10 may be configured to include a nonvolatile variable resistance element whose resistance state changes depending on the direction of the voltage applied between two electrodes, and a write circuit for performing a write operation to change the resistance state of the nonvolatile variable resistance element. Below, a semiconductor device 3A including a nonvolatile variable resistance element and a write circuit will be described.

As shown in FIG. 11, the high-voltage power domain 10 in the semiconductor device 3A includes a crossbar 50 having nonvolatile variable resistance elements 51 arranged at the intersections of wiring arranged in the row and column directions, address transistors 52 for connecting to any of the nonvolatile variable resistance elements 51, and a write circuit 60 for performing a write operation to change the resistance state of the nonvolatile variable resistance elements 51. This high-voltage power domain 10 is also called an FPGA (Field Programmable Gate Array) routing block, and has a data signal routing function.

The high-voltage power domain 10 does not require power gating by a power inverter because it does not use CMOS internally. Therefore, the power supply of the high-voltage power domain 10 is controlled only by the power switch 40 connected to the power line.

The core voltage power domain 11 has a first stage 11a configured with an input buffer, a middle stage 11b configured with an FPGA logic block, and a final stage 11c configured with an output buffer. As shown in Non-Patent Document 1, the FPGA logic block of the middle stage 11b is configured with a look-up table and a D-flip-flop, etc., and has the functionality of an arbitrary logic function and a sequential circuit.

The buffers in the first stage portion 11a and the last stage portion 11c of the core voltage power domain 11 are powered by a power inverter 21 connected to the ground line. The FPGA logic block in the middle portion 11b of the core voltage power domain 11 is powered by a power switch 41 connected to the ground line.

Next, the operation of the semiconductor device 3A according to the modified example of this embodiment will be described.
12 is a diagram for explaining the power gating mode of the semiconductor device 3A. Here, the power gating mode refers to a mode in which the power supplies of the high voltage power domain 10 and the core voltage power domain 11 are turned off.

As shown in FIG. 12, by setting the logical value of the control signal ENH0 input to the power switch 40 connected to the power line of the high-voltage power domain 10 to "1 (i.e., power supply potential VHV)," the connection between the power switch 40 and the high-voltage power domain 10 becomes a high impedance state. As a result, the power supply to the high-voltage power domain 10 becomes an off state.

In addition, by setting the logical value of the control signal ENG1 input to the power inverter 21 and power switch 41 connected to the ground line of the core voltage power domain 11 to "0 (i.e., ground potential GND)," the potential of the output section 21a of the power inverter 21 becomes the power supply potential VDD, and the connection section of the power switch 41 with the core voltage power domain 11 becomes in a high impedance state. As a result, the power supply of the core voltage power domain 11 becomes in an off state.

Figure 13 is a diagram for explaining the write mode of the semiconductor device 3A. Here, the write mode refers to a mode in which a write operation is performed to change the resistance state of the nonvolatile variable resistance element 51 that constitutes the FPGA routing block of the high-voltage power domain 10.

As shown in FIG. 13, in the write mode, for example, when writing to the non-volatile resistance change element 51a at the bottom right of the crossbar to the on state (low resistance state), the logical value of the control signal ENH0 is set to "0 (i.e., ground potential GND)" to turn on the power supply to the high-voltage power domain 10.

In addition, when the X-axis input section of the write circuit 60 is set to a high voltage potential VHV for writing, the Y-axis input section is set to ground potential GND, and the address transistor 52 (X1 and Y1 in FIG. 13) corresponding to the nonvolatile resistance change element 51a at the bottom right is set to ON, the potential of the nonvolatile resistance change element 51a becomes VHV and the potential of the other end becomes GND, and writing is performed to turn the nonvolatile resistance change element 51a ON.

At this time, the power supply potential VHV is also applied to the first-stage buffer of the core voltage power domain 11. However, as explained above, by controlling the power supply of the first-stage portion 11a of the core voltage power domain 11 by the power inverter 21, even when the power supply of the core voltage power domain 11 is in an off state, it is possible to prevent the occurrence of shoot-through current and malfunction in the CMOS 31 of the subsequent core voltage power domain 11. Furthermore, since it is not necessary to place an isolation cell between the high voltage power domain 10 and the core voltage power domain 11, it is possible to eliminate operational delays and increased power consumption due to the placement of an isolation cell.

Figure 14 is a diagram for explaining the application mode in the FPGA of the semiconductor device 3A. Here, the application mode means a mode in which the FPGA logic block of the core voltage power domain 11 performs calculations on signals obtained from the FPGA routing block of the high voltage power domain 10.

As shown in FIG. 14, in the application mode, the logical value of the control signal ENH0 input to the power switch 40 connected to the power line of the high-voltage power domain 10 is set to "1 (i.e., power supply potential VHV)," thereby turning off the power supply to the high-voltage power domain 10.

In addition, the logical value of the control signal ENG1 input to the power inverter 21 and power switch 41 connected to the ground line of the core voltage power domain 11 is set to "1 (i.e., power supply potential VDD)," turning on the power supply for the core voltage power domain 11.

In this state, a data signal with a logical value of "1 (i.e., power supply potential VDD)" or a logical value of "0 (i.e., ground potential GND)" is input to the input buffer of the first stage portion 11a of the core voltage power domain 11 via a non-volatile resistance change element (e.g., 51a) in the on state.

The data signal input to the core voltage power domain 11 is used for calculations in the FPGA logic block in the middle portion 11b of the core voltage power domain 11.

The above description and illustrations are a detailed explanation of the parts related to the technology of the present disclosure, and are merely an example of the technology of the present disclosure. For example, the above explanation of the configuration, function, action, and effect is an explanation of an example of the configuration, function, action, and effect of the parts related to the technology of the present disclosure. Therefore, it goes without saying that unnecessary parts may be deleted, new elements may be added, or replacements may be made to the above description and illustrations, within the scope of the gist of the technology of the present disclosure. Also, in order to avoid confusion and to make it easier to understand the parts related to the technology of the present disclosure, the above description and illustrations omit explanations of technical common knowledge that do not require particular explanation to enable the implementation of the technology of the present disclosure.

1, 1A, 2, 2A, 2B, 2C, 3, 3A Semiconductor device 10 Power domain/high voltage power domain 11 Power domain/core voltage power domain 20 Power inverter 20a Output section 21 Power inverter 21a Output section 40 Power switch 41 Power switch 50 Crossbars 51, 51a Nonvolatile variable resistance element 52 Address transistor 60 Write circuit

Claims (7)

The power domain,
a power controller including a combination of P-type transistors and N-type transistors, for switching between a state in which a power supply voltage is supplied to the power domain and a state in which a power supply voltage is not supplied to the power domain in response to a control signal input from an external device;
The output section of the power controller is connected to a power supply line or a ground line of the power domain. the power domain includes a P-type transistor;
2. The semiconductor device according to claim 1, wherein an output section of the power controller is connected to a body terminal of a P-type transistor in the power domain. the power domain has an N-type transistor;
2. The semiconductor device according to claim 1, wherein an output section of the power controller is connected to a body terminal of an N-type transistor in the power domain. a power switch that switches between a state in which a power supply voltage is supplied to the power domain and a state in which a power supply voltage is not supplied to the power domain in response to a control signal input from an external device;
an output of the power controller is connected to a power supply line or a ground line of a final stage portion of the power domain;
The semiconductor device according to claim 1 , wherein the power switch is connected to a power supply line or a ground line in a portion of the power domain other than the final stage. 5. The semiconductor device according to claim 4, wherein an output of the power controller is further connected to a power supply line or a ground line of a first stage portion of the power domain. the power domains include a first power domain configured with transistors operating at a first voltage, and a second power domain configured with transistors operating at a second voltage higher than the first voltage;
The semiconductor device according to claim 5 , wherein an output section of the second power domain is connected to an input section of the first power domain. 7. The semiconductor device according to claim 6, wherein the second power domain comprises: a nonvolatile variable resistance element whose resistance state changes depending on a direction of a voltage applied between two electrodes; and a write circuit for performing a write operation to change the resistance state of the nonvolatile variable resistance element.