JP2024077670A - Cell Multi-Inverter - Google Patents

Abstract

[Problem] In a cell-multiplexed inverter in which a plurality of cells are connected in a star connection to each phase of an AC system, even when an unbalanced AC voltage occurs or when an unbalanced AC voltage is intentionally output, it is not necessary to input a cell to the corresponding phase or to raise the cell DC voltage only for the corresponding phase, and common mode current is suppressed. [Solution] Phase voltage detection signals vU, vV, vW or voltage command values vU*, vV*, vW* are converted into values on a rotating coordinate system synchronized with the system frequency and values on a rotating coordinate system rotating in the opposite direction to the system frequency to extract DC components. Zero-phase voltage d-axis component V0d and zero-phase voltage q-axis component V0q are calculated based on the DC components, which are positive-phase d-axis component V1d, positive-phase q-axis component V1q, negative-phase d-axis component V2d, and negative-phase q-axis component V2q. The zero-phase voltage d-axis component V0d and the zero-phase voltage q-axis component V0q are multiplied by a cosine wave and a sine wave, and the results are added to the voltage command values vU*, vV*, and vW* to obtain the corrected voltage command values vU*', vV*', and vW*'. [Selected figure] Figure 2

Description

The present invention relates to a cell-multiplexed inverter in which multiple cells are multiplexed and connected to each phase of an AC system using star wiring.

One example of a multi-cell inverter is a modular multilevel cascade converter (MMCC) with a single-star bridge cell (SSBC) that is connected to a three-phase AC system. There is also a known configuration in which a separate power supply, DC/DC converter, etc. is connected to the DC side of the full-bridge cell of the MMCC-SSBC.

A typical example of this configuration is the solid-state transformer (SST) described in Patent Document 1. Figure 1 shows an SST consisting of three cells per phase that combines an MMCC-SSBC and a dual active bridge (DAB) type bidirectional isolated DC/DC converter.

High-voltage AC power is converted into DC power using cells connected in series, the DC power is converted into high-frequency AC power, and then the power is converted back into DC power by isolating and rectifying it using a transformer. Reverse power interchange is also possible. Because SST uses a high-frequency transformer, it can be made smaller than conventional commercial frequency transformers.

Another application is the high-voltage multiple inverter described in Patent Document 2.

When connecting to an unbalanced three-phase AC system using an SST, or when intentionally outputting an unbalanced three-phase AC voltage using a high-voltage multiple inverter, the phase voltage amplitude of a certain phase increases, and the AC voltage that the cell connected to that phase should output also increases.

To address this, it is necessary to increase the DC voltage of the cells, but this also requires the components to have an increased voltage resistance, which leads to increased costs and size. Using switching devices with a high voltage resistance for the cells can also lead to increased losses.

In addition, some equipment may require continued operation even if some cells fail.

Patent Document 1 discloses the main circuit configuration of an SST, and Patent Document 2 discloses the configuration of a high-voltage multiple inverter.

Patent documents 3 and 4 disclose methods for continuing operation when a cell fails. In both documents, the failed cell is first short-circuited. However, this alone reduces the AC voltage amplitude that can be output from the phase with the failed cell. Therefore, in patent document 3, a spare cell prepared in advance is inserted into the relevant phase. In patent document 4, the DC voltage of the non-faulty cells in the relevant phase is increased.

Patent documents 5 and 6 disclose technology that addresses voltage imbalances by using zero-phase voltages in MMCC-SSBCs. The purpose of this technology is to balance the capacitor voltages of each cell.

Patent Document 7 describes a technology that reduces the peak of the voltage command value by superimposing a zero-phase voltage on the voltage command value of a single three-phase inverter that does not perform cell multiplexing. It can also be used when outputting an unbalanced three-phase AC voltage, and can equalize the peak voltage command value of each phase. The technology in Patent Document 7 can be applied to MMCC-SSBCs and high-voltage multiplexed inverters.

Japanese Patent Application Laid-Open No. 10-75580 Japanese Patent Application Laid-Open No. 11-122943 JP 2012-147613 A WO2017/094379 A1 JP 2013-5694 A JP 2021-19481 A Japanese Patent Application Laid-Open No. 3-107373

However, Patent Documents 1 and 2 do not specifically mention how to connect to an unbalanced grid, how to output an unbalanced voltage, or how to deal with cell failures.

In Patent Document 3, it is necessary to incorporate a spare cell into the device, and a switch is also required to turn on the spare cell, which increases costs and size. If no failure occurs, the spare cell will not be used and may be wasted.

In Patent Document 4, the DC voltage of other cells in the corresponding phase is increased, so the cells must be designed with this in mind, which leads to problems with cost, size, and increased losses. Furthermore, neither Patent Document 3 nor Patent Document 4 describes a method for dealing with voltage imbalance.

In Patent Documents 5 and 6, only a capacitor is connected to the DC side of each cell, and applications that do not handle active power, such as reactive power compensation devices, are envisioned. However, high-voltage multiple inverters and SSTs have a separate path through which active power passes, and this path can be used to exchange power between cells and balance the capacitor voltages. This reduces the importance of the technology in Patent Documents 5 and 6. Furthermore, neither Patent Document 5 nor 6 describes a method for dealing with cell failures.

In Patent Document 7, harmonics of an odd multiple of three are superimposed as the zero-phase voltage. However, the higher the frequency of the superimposed zero-phase voltage, the larger the common-mode current flows through the stray capacitance of the circuit. This can cause many problems, such as increased heat generation in components, reduced efficiency, malfunction of the ground fault detector, insulation breakdown in the high-frequency transformer, and electromagnetic interference with other equipment. For this reason, it is necessary to lower the frequency of the superimposed zero-phase voltage. Patent Document 7 also does not describe a method for dealing with cell failures.

As described above, in a cell-multiplexed inverter in which multiple cells are connected in a star connection to each phase of an AC system, even when an unbalanced AC voltage occurs or when an unbalanced AC voltage is intentionally output, the challenge is to eliminate the need to input a cell to the relevant phase or to increase the DC voltage of the cell only in the relevant phase, and to suppress the common-mode current.

The present invention was devised in view of the above-mentioned problems of the related art. One aspect of the present invention is a multi-cell inverter including a plurality of cells connected in a star-connected manner to each phase of an AC system, a correction voltage command value generating unit that generates a correction voltage command value by superimposing a zero-phase voltage of the same frequency as the fundamental wave on a voltage command value, and a gate signal generating unit that generates a gate signal for the cell based on the correction voltage command value, and the correction voltage command value generating unit is characterized in that it superimposes the zero-phase voltage of the same frequency as the fundamental wave on the voltage command value so as to reduce the amplitude difference of the correction voltage command value for each phase.

In another aspect, a multiple-cell inverter includes a plurality of cells connected in multiplex with star connection to each phase of an AC system, a correction voltage command value generating unit that generates a correction voltage command value by superimposing a zero-phase voltage of the same frequency as the fundamental wave on a voltage command value, and a gate signal generating unit that generates a gate signal for the cell based on the correction voltage command value, and is characterized in that the correction voltage command value generating unit superimposes the zero-phase voltage of the same frequency as the fundamental wave so that the difference between the amplitude of the correction voltage command value for each phase multiplied by the number of cells in each phase and divided by the number of cells in each phase that are operating without failure is small among the three phases.

In one embodiment, the correction voltage command value generating unit includes a phase output unit that outputs a phase ωt synchronized with the AC voltage of the system; a first dq converter that converts a value obtained by multiplying the phase voltage detection signal or the voltage command value, or the phase voltage detection signal or the voltage command value, by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system synchronized with the system frequency; a second dq converter that converts a value obtained by multiplying the phase voltage detection signal or the voltage command value, or the phase voltage detection signal or the voltage command value, by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system that rotates in the opposite direction to the system frequency; and a positive-phase d-axis component that extracts a DC component from the output of the first dq converter. The power supply circuit is characterized by comprising: a calculator that calculates a zero-phase voltage d-axis component and a zero-phase voltage q-axis component that equalize the AC output voltage of each cell based on the positive-phase q-axis component, the negative-phase d-axis component and the negative-phase q-axis component obtained by extracting a DC component from the output of the second dq converter; a first multiplier that multiplies the zero-phase voltage d-axis component by cosωt or sinωt; a second multiplier that multiplies the zero-phase voltage q-axis component by sinωt when the first multiplier multiplies by cosωt, and multiplies the zero-phase voltage q-axis component by cosωt when the first multiplier multiplies by sinωt; a first adder that adds the output of the first multiplier and the output of the second multiplier; and a second adder that adds the output of the first adder to the voltage command value and outputs it as a correction voltage command value.

In one aspect, the calculator calculates the d-axis component of the zero-phase voltage and the q-axis component of the zero-phase voltage based on equation (3).

_V0d : d-axis component of zero-phase-sequence voltage _V0q : q-axis component of zero-phase-sequence voltage _V1d : d-axis component of positive-phase-sequence voltage _V1q : q-axis component of positive-phase-sequence voltage _V2d : d-axis component of negative-phase-sequence voltage _V2q : q-axis component of negative-phase-sequence voltage.

In another aspect, the calculator calculates the d-axis component of the zero-phase voltage and the q-axis component of the zero-phase voltage based on equation (4).

_V0d : d-axis component of zero-phase-sequence voltage _V0q : q-axis component of zero-phase-sequence voltage _V1d : d-axis component of positive-phase-sequence voltage _V1q : q-axis component of positive-phase-sequence voltage _V2d : d-axis component of negative-phase-sequence voltage _V2q : q-axis component of negative-phase-sequence voltage.

In another aspect, the calculator calculates the d-axis component of the zero-phase voltage and the q-axis component of the zero-phase voltage based on equation (5).

V _0d : d-axis component of zero-phase-sequence voltage V _0q : q-axis component of zero-phase-sequence voltage V _2d : d-axis component of negative-phase-sequence voltage V _2q : q-axis component of negative-phase-sequence voltage V ₁ : positive-phase voltage component.

In one aspect, the corrected voltage command value generating unit sets the zero-sequence voltage d-axis component V _0d =-V _1d /2 and the zero-sequence voltage q-axis component V _0q =0 when the negative-phase-sequence d-axis component V _2d =V _1d /2 and the negative-phase-sequence q-axis component V _2q =0, sets the zero-sequence voltage d-axis component V _0d =V _1d /4 and the zero-sequence voltage q-axis component V _0q =√3V _1d /4 when the negative-phase-sequence d-axis component V _2d =-V _1d /2 and the negative-phase-sequence q-axis component V _2q =√3V _1d /2, and sets the zero-sequence voltage d-axis component V _0d =V 1d /4 when the negative-phase-sequence d-axis component V _2d =-V _1d /2 and the negative-phase-sequence q-axis component V _2q =√3V _1d / ₂ /4, and the zero-phase voltage q-axis component V _0q =-√3V _1d /4.

According to the present invention, in a cell-multiplexed inverter in which multiple cells are multiplexed and connected in a star connection to each phase of an AC system, even if an unbalanced AC voltage occurs or an unbalanced AC voltage is intentionally output, it is not necessary to input a cell to the relevant phase or to increase the DC voltage of the cell only in the relevant phase, and it is also possible to suppress common mode current.

FIG. 4 is a circuit diagram showing a main circuit configuration of the first to third embodiments. FIG. 4 is a block diagram showing a correction voltage command value generating unit according to the first embodiment. FIG. 11 is a block diagram showing a correction voltage command value generating unit according to a second embodiment. FIG. 13 is a diagram showing the operation when one U-phase cell fails. FIG. 11 is a block diagram showing a correction voltage command value generating unit according to a third embodiment.

Below, embodiments 1 to 3 of the cell multiplexing inverter of the present invention will be described in detail with reference to Figs. 1 to 5.

[Embodiment 1]
First, as an example of a multiple cell inverter, the main circuit configuration of an MMCC-SSBC shown in FIG. 1 will be described.

As shown in Fig. 1(a), cells cellu1, cellu2, and cellu3 are connected in series to the U-phase of the AC system AC via a reactor Lu. Similarly, cells cellv1, cellv2, and cellv3 are connected in series to the V-phase of the AC system AC via a reactor Lv, and cells cellw1, cellw2, and cellw3 are connected in series to the W-phase of the AC system AC via a reactor Lw. Here, AC phase voltages (phase voltage detection signals) are denoted as _vU , _vV , and _vW .

The DC terminals of cells cellu1, cell cellu2, cell cellu3, cell cellv1, cell cellv2, cell cellv3, cell cellw1, cell cellw2, and cell cellw3 are connected in parallel. The DC voltage of cells cellu1 to cellw3 is V _DC .

Figure 1(b) shows the configuration of one cell. One end of switching devices S1 and S3 is connected to one AC terminal of the cell. One end of switching devices S2 and S4 is connected to the other AC terminal of the cell. The other ends of switching devices S1 and S2 are connected to one end of the first capacitor C1. The other ends of switching devices S3 and S4 are connected to the other end of the first capacitor C1.

Switching devices S5 and S7 are connected in series between one end and the other end of the first capacitor C1. In addition, switching devices S6 and S8 are connected in series between one end and the other end of the first capacitor C1.

One end of reactor L1 is connected to the connection point of switching devices S5 and S7. One end of reactor L2 is connected to the connection point of switching devices S6 and S8. The primary winding of transformer Tr is connected between the other end of reactor L1 and the other end of reactor L2.

A second capacitor C2 is connected between one DC terminal and the other DC terminal of the cell. Switching devices S9 and S11 are connected in series between one end and the other end of the second capacitor C2. In addition, switching devices S10 and S12 are connected in series between one end and the other end of the second capacitor C2.

One end of reactor L3 is connected to the connection point of switching devices S9 and S11. One end of reactor L4 is connected to the connection point of switching devices S10 and S12. The secondary winding of transformer Tr is connected between the other end of reactor L3 and the other end of reactor L4. Note that reactors L1 to L4 in FIG. 1(b) may be omitted.

Figure 2 shows a block diagram of the correction voltage command value generation unit of this embodiment 1. This embodiment 1 equalizes the voltage responsibilities of each cell in applications where it is not necessary to equalize the power responsibilities of each cell.

A phase output unit (for example, a PLL: Phase-Locked Loop) 1 outputs a phase ωt synchronized with the AC voltage of the system from phase voltage detection signals v _U , v _V , and v _W of the AC system AC.

The phase voltage detection signals _vU , _vV , and _vW may be converted into phase voltages by detecting line voltages and calculating them. Also, instead of the phase voltage detection signals _vU , _vV , and _vW , voltage command values _vU *, _vV *, and _vW *, which will be described later, may be input to the phase output unit 1. Furthermore, the system AC voltage input to the phase output unit 1 may be only one representative phase.

In motor drive applications of high-voltage multiple inverters, the phase ωt may be detected from a rotary encoder or resolver, or the phase ωt estimated by an observer or the like may be used. In the following, phase output unit 1 refers to PLL 1.

The first low-pass filter 2 removes switching noise and the like from the phase voltage detection signals _vU , _vV , and _vW (voltage command values _vU *, _vV *, and _vW *).

The first dq converter 3 converts the phase voltage detection signals _vU , _vV , and _vW , which have been subjected to the first low-pass filter 2, into values on a rotating coordinate system synchronized with the system frequency based on the phase ωt.

The second low-pass filters 4 and 5 extract only the DC component from the output of the first dq converter 3. The d-axis component of the outputs of the second low-pass filters 4 and 5 becomes the positive-phase d-axis component _V1d of the phase voltage detection signals _vU , _vV , _vW , and the q-axis component becomes the positive-phase q-axis component _V1q . If the PLL 1 is operating normally, the positive-phase q-axis component _V1q of the output of the second low-pass filter 5 is zero and is therefore not used.

The second dq converter 6 converts the phase voltage detection signals _vU , _vV , and _vW to which the first low-pass filter 2 has been applied, based on the phase -ωt, into values on a rotating coordinate system that rotates in the opposite direction to the system frequency.

The third low-pass filters 7 and 8 extract only the DC component from the output of the second dq converter 6. The outputs of the third low-pass filters 7 and 8 become the negative-phase d-axis component _V2d and the negative-phase q-axis component _V2q of the phase voltage detection signals _vU , _vV , and _vW , respectively.

The calculator 9 calculates the zero-phase voltage d-axis component _V0d and the zero-phase voltage q-axis component _V0q from the obtained positive-phase d-axis component _V1d , positive-phase q-axis component _V1q , negative-phase d-axis component _V2d , and negative-phase q-axis component _V2q using equation (3) described later. The zero-phase voltage d-axis component _V0d and the zero-phase voltage q-axis component _V0q may be calculated using equations (4) and (5) instead of equation (3). When the amplitudes of the positive and negative phase components of the AC voltage are approximately equal, the calculator 9 outputs _V0d = _V0q = 0.

The oscillator 10 outputs a sine wave sinωt and a cosine wave cosωt from a phase ωt.

The first multiplier 11 multiplies the d-axis component of the zero-phase-sequence voltage V _0d by the cosine wave cosωt, and the second multiplier 12 multiplies the q-axis component of the zero-phase-sequence voltage V _0q by the sine wave sinωt.

The first adder 13 obtains the sum of V _0d cos ωt output by the first multiplier 11 and V _0q sin ωt output by the second multiplier 12 .

The second adders 14, 15, and 16 add _V0d cosωt+ _V0q sinωt calculated by the first adder 13 to the voltage command values _vU *, _vV *, and _vW *, respectively. The voltage command values _vU *, _vV *, and _vW * may be given as fixed sine waves, or may be obtained by feedback control of voltage or current. The outputs _vU *', _vV *', and _vW *' of the second adders 14, 15, and 16 are corrected voltage command values.

The corrected voltage command values _vU *', _vV *', and _vW *' are used in the subsequent stage (gate signal generator) to generate gate signals (on/off command signals) by comparing carrier triangular waves or the like, and are input to the switching devices of each cell.

In the first embodiment, a zero-phase voltage having the same frequency as the fundamental wave is superimposed on the three-phase voltage command values _vU *, _vV *, and _vW * so that the amplitudes of the corrected voltage command values _vU *', _vV *', and _vW *' of the respective phases are equal (the difference is small). The zero-phase voltage required for this purpose is calculated. Assuming that the voltage command values _vU *, _vV *, and _vW * are approximately equal to the AC phase voltages (phase voltage detection signals) _vU , _vV , and _vW , the AC phase voltages (phase voltage detection signals) _vU , _vV , and _vW are defined as in the following formula (1).

Here, _V1d is the positive-phase d-axis component of the AC voltage, _V2d is the negative-phase d-axis component, and _V2q is the negative-phase q-axis component. _V1q is the positive-phase q-axis component, but is zero if the PLL1 is operating normally.

V _0d and V _0q are the d-axis component and q-axis component of the zero-phase-sequence voltage to be superimposed according to the present embodiment 1. Since the objective is to equalize the amplitudes of the defined AC voltages, the d-axis component V _0d of the zero-phase-sequence voltage and the q-axis component V _0q of the zero-phase-sequence voltage that satisfy the formula (2) are obtained.

Solving this equation gives us equation (3).

If the positive-phase q-axis component _V1q is close to zero, equation (3) can be approximated to equation (4).

If the positive-sequence q-axis component _V1q is equal to zero, then equation (3) can be simplified to equation (5), where _V1 represents the positive-sequence component of the AC voltage.

In the first embodiment, the necessary zero-phase voltage d-axis component _V0d and zero-phase voltage q-axis component _V0q are calculated based on the formula (3) and superimposed on the voltage command values _vU *, _vV *, and _vW *. First, the AC phase voltage detection signals _vU , _vV , and _vW are detected, or the voltage command values _vU *, _vV *, and _vW * are directly input, and converted into values on a rotating coordinate system synchronized with the system frequency to extract DC components, thereby obtaining the positive-phase d-axis component _V1d and the positive-phase q-axis component _V1q . In addition, the negative-phase d-axis component _V2d and the negative-phase q-axis component _V2q are obtained by extracting DC components from values on a rotating coordinate system that rotates in the opposite direction to the system frequency.

Then, the zero-phase-sequence voltage d-axis component _V0d and the zero-phase-sequence voltage q-axis component _V0q are calculated using equation (3), and the zero-phase-sequence voltages to be superimposed are obtained from the products of the cosine wave cosωt and the sine wave sinωt, respectively, and added to the voltage command values _vU *, _vV *, and _vW *. In grid-connection applications, since the positive-sequence q-axis component _V1q is zero if the PLL is operating normally, the zero-phase-sequence voltage d-axis component _V0d and the zero-phase-sequence voltage q-axis component _V0q may be calculated using equations (4) and (5).

In equations (3), (4), and (5), when the denominators are zero, i.e., when the amplitudes of the positive-sequence voltage and the negative-sequence voltage are equal, there is no solution, and the amplitudes of the voltage command values _vU *, _vV *, and _vW * of each phase cannot be made equal. Therefore, when the amplitudes of the positive-sequence voltage and the negative-sequence voltage are approximately equal, the zero-sequence voltage d-axis component _V0d and the zero-sequence voltage q-axis component _V0q are set to zero.

With this embodiment 1, in a star-connected cell multiplexed inverter such as an MMCC-SSBC, the AC output voltages of the cells can be made equal even when an unbalanced AC voltage occurs or when an unbalanced AC voltage is intentionally output. This eliminates the need to insert a cell into a phase when the voltage amplitude of the phase increases, or to raise the cell DC voltage of only the phase. In addition, because the superimposed zero-phase voltage is only the fundamental wave component, common mode current can be suppressed.

In this embodiment 1, the DC voltage of all cells must be increased or raised in advance, but the increase in DC voltage can be significantly suppressed compared to conventional technology, and the increase in cell voltage resistance can be minimized, reducing costs and size.

In addition, the zero-phase voltage to be superimposed in this embodiment 1 is determined by feedforward, so even if there is a fluctuation in the AC voltage, it can quickly follow up, and in principle the device is highly stable.

[Embodiment 2]
3 shows a block diagram of a correction voltage command value generating unit of the present embodiment 2. The present embodiment 2 differs from the embodiment 1 in the following points.

In the coefficient multiplier 17, the phase voltage detection signals _vU , _vV , _vW (or the voltage command values _vU *, _vV *, _vW *) are multiplied by coefficients N/ _nU , N/ _nV , N/ _nW . The numerator N of the coefficient is the number of cells in each phase. In the example of FIG. 1, N=3. The denominators _nU , _nV , _nW of the coefficient are the number of cells in each phase that are operating without failure. The phase voltage detection signals _vU , _vV , _vW (or the voltage command values _vU *, _vV *, _vW *) used in the first dq converter 3 and the second dq converter 6 use values multiplied by these coefficients.

In this second embodiment, a function to reduce the voltage duty of a phase in which a faulty cell is located is added to the first embodiment. The required zero-phase voltage would normally need to be calculated by solving equation (6).

However, equation (6) has problems in that the number of variables increases, making it difficult to derive a solution, and the derived equation becomes very complicated, making it difficult to implement in the control program.

Therefore, the phase voltage detection signals _vU , _vV , and _vW are multiplied by coefficients to make the AC voltage of the phase containing the faulty cell appear larger in accordance with the number of faulty cells, thereby obtaining the positive-sequence d-axis component _V1d , positive-sequence q-axis component _V1q , negative-sequence d-axis component _V2d , and negative-sequence q-axis component _V2q . These are then substituted into equation (3) to approximately obtain the required zero-sequence voltage d-axis component _V0d and zero-sequence voltage q-axis component _V0q .

The amplitude of the voltage command value for a phase in which a fault occurs can be reduced by superimposing _the zero-phase-sequence voltage d-axis component _V0d and the zero-phase-sequence voltage q-axis component _V0q on the voltage command values _vU *, vV*, and _vW *. Here, N/ _nU , N/ _nV , and N/ _nW are used as example coefficients, respectively.

The effect of the second embodiment will be described with reference to Fig. 4. Fig. 4(a) is a phasor diagram of the voltage command value when the number of cells in each phase is N = 3, the AC voltage is three-phase balanced, and there is no negative sequence voltage ( _V2d = _V2q = 0).

Now consider the case where one U-phase cell fails, resulting in n _U = 2. Figure 4(b) shows the case where the line voltage is maintained by applying Patent Document 4, and the remaining two U-phase cells need to output 1.5 times the AC voltage. To accommodate this, the DC voltage of the U-phase cells also needs to be increased by 1.5 times.

4C shows a case where the technique of the second embodiment is applied. The output voltage of the U-phase cell can be reduced by superimposing the d-axis component _V0d of the zero-phase voltage and the q-axis component _V0q of the zero-phase voltage on the voltage command values _vU *, _vV *, and _vW *. Although the cell output voltages of the V-phase and W-phase increase, the same line voltage can be maintained by multiplying the AC voltages of all cells, including the U-phase, by about 1.15 times.

In other words, a zero-sequence voltage of the same frequency as the fundamental wave is superimposed so that the difference between the amplitudes of the corrected voltage command values _vU *', _vV *', _vW *' for each phase is reduced by multiplying the amplitude of the corrected voltage command values vU*', vV*', vW*' for each phase by the number of cells N in each phase and dividing the result by the number of cells _nU , _nV , _nW that are operating without failure in each phase.

The gate signal is generated based on FIG. 3 for healthy cells that are not faulty. For faulty cells, the high-voltage AC side turns on switching devices S1 and S3, or turns on switching devices S2 and S4 to output zero voltage, or performs short-circuit treatment with an external switch. Switching devices S5 to S12 are turned off.

In addition to the effects of embodiment 1, this embodiment 2 can equalize the AC output voltage of the cells even if some of the cells fail and short-circuit treatment is performed. Operation can be continued even if more cells fail than with conventional technology.

[Embodiment 3]
5 shows a block diagram of a correction voltage command value generating unit of the present embodiment 3. The configuration before the calculator 9 is the same as that of the embodiment 1 or 2. The present embodiment 3 differs from the embodiment 1 or 2 in the following points.

In the third embodiment, the calculator 9 for determining the d-axis component V _0d of the zero-phase-sequence voltage and the q-axis component V _0q of the zero-phase-sequence voltage uses the formula (5).

The comparator 18 determines whether the negative phase d-axis component _V2d is equal to the positive phase d-axis component _V1d . The comparator 19 determines whether the negative phase d-axis component _V2d is equal to _-V1d /2. The comparator 20 determines whether the negative phase q-axis component _V2q is equal to 0. The comparator 21 determines whether the negative phase q-axis component _V2q is equal to _-√3V1d /2. The comparator 22 determines whether the negative phase q-axis component _V2q is equal to _√3V1d /2.

The comparator 18 may be configured to set a threshold value in advance and to consider the negative phase d-axis component _V2d and the positive phase d-axis component _V1d as equal if the difference between them is smaller than the threshold value. The threshold value may have a hysteresis characteristic. The same applies to the comparators 19 to 22.

The AND element 23 outputs 1 if the negative-phase-sequence d-axis component _V2d is equal to _-V1d /2 and the negative-phase-sequence q-axis component _V2q is equal to _√3V1d /2, and outputs 0 otherwise. The switch SW1 outputs _V1d /4 as the zero-phase-sequence voltage d-axis component _V0d if the output of the AND element 23 is 1, and outputs the result of equation (5) if the output is 0. The switch SW2 outputs _-√3V1d /4 as the zero-phase-sequence voltage q-axis component _V0q if the output is 1, and outputs the result of equation (5) if the output is 0.

The AND element 24 outputs 1 if the negative-phase-sequence d-axis component _V2d is equal to _-V1d /2 and the negative-phase-sequence q-axis component _V2q is equal to _-√3V1d /2, and outputs 0 otherwise. If the output of the AND element 24 is 1, the switch SW3 outputs _V1d /4 as the zero-phase-sequence voltage d-axis component _V0d , and if it is 0, the switch SW3 outputs the result of the switch SW1. If the output of the AND element 24 is 1, the switch SW4 outputs _√3V1d /4 as the zero-phase-sequence voltage q-axis component _V0q , and if it is 0, the switch SW4 outputs the result of the switch SW2.

The AND element 25 outputs 1 if the negative-phase-sequence d-axis component _V2d is equal to the positive-phase-sequence d-axis component _V1d and the negative-phase-sequence q-axis component _V2q is equal to 0, and outputs 0 otherwise. If the output of the AND element 25 is 1, the switch SW5 outputs _-V1d /2 as the zero-phase-sequence voltage d-axis component _V0d , and if it is 0, the switch SW5 outputs the result of the switch SW3. If the output of the AND element 25 is 1, the switch SW6 outputs 0 as the zero-phase-sequence voltage q-axis component _V0q , and if it is 0, the switch SW6 outputs the result of the switch SW4.

Table 1 shows the d-axis component V _0d of the zero-phase voltage finally output by the switch SW5 and the q-axis component V _0q of the zero-phase voltage finally output by the switch SW6.

In the equations (3), (4), and (5) used in the first and second embodiments, when the amplitudes of the positive-sequence voltage and the negative-sequence voltage are equal, the denominator becomes zero and there is no solution. However, if the numerator is also zero, there is a possibility that there is a solution. Therefore, for simplification, when a grid-connected application is assumed and a condition is found in which both the numerator and denominator in equation (5) become zero, equation (7) is obtained as one of them.

By substituting equation (7) into equation (1) and determining again the zero-phase voltage that satisfies equation (2) under the condition of V _1q =0, equation (8) is obtained.

At this time, the q-axis component _V0q of the zero-phase voltage may be any value, and it shows that there are an infinite number of solutions. Among these infinite solutions, the one that minimizes the amplitude of the zero-phase voltage is given by equation (9).

In addition to equation (7), there are two other conditions for both the numerator and denominator to be zero. The combinations of conditions and solutions are shown in equations (10) and (11).

Examples of the conditions of equations (7), (10), and (11) are a line-to-line short circuit and a two-phase to ground fault.
In the third embodiment, the voltage conditions of the formulas (7), (10), and (11) are detected, and a zero-phase sequence voltage is superimposed to equalize the amplitude of the voltage command value of each phase. In the grid interconnection, there are applications where operation continuity is required even in the event of a short circuit or ground fault as a fault-return (FRT) requirement, and the third embodiment can also be used for such applications.

With this embodiment 3, the effects of embodiments 1 and 2 can be obtained even if a line-to-line short circuit or a two-phase ground fault occurs in the AC system.

Although the present invention has been described in detail above only with respect to the specific examples, it will be clear to those skilled in the art that various modifications and alterations are possible within the scope of the technical concept of the present invention, and it goes without saying that such modifications and alterations fall within the scope of the claims.

AC...AC system 1...PLL (Phase-Locked Loop)
2, 4, 5, 7, 8... 1st to 3rd low-pass filters 3... 1st dq converter 6... 2nd dq converter 9... Calculator 10... Oscillator 11, 12... 1st and 2nd multipliers 13 to 16... 1st and 2nd adders 17... Coefficient calculator 18 to 22... Comparators 23 to 25... AND elements SW1 to SW6... Switches

Claims (7)

A multiple-cell inverter including a plurality of cells multiplexedly connected to each phase of an AC system by star connection, a correction voltage command value generating unit that generates a correction voltage command value by superimposing a zero-phase sequence voltage having the same frequency as a fundamental wave on a voltage command value, and a gate signal generating unit that generates a gate signal for the cell based on the correction voltage command value,
The correction voltage command value generating unit
A multi-cell inverter comprising: a zero-phase voltage having the same frequency as a fundamental wave and superimposed on the voltage command value so as to reduce an amplitude difference between the corrected voltage command values of each phase. A multiple-cell inverter including a plurality of cells multiplexedly connected to each phase of an AC system by star connection, a correction voltage command value generating unit that generates a correction voltage command value by superimposing a zero-phase sequence voltage having the same frequency as a fundamental wave on a voltage command value, and a gate signal generating unit that generates a gate signal for the cell based on the correction voltage command value,
The correction voltage command value generating unit
A multi-cell inverter characterized in that the zero-sequence voltage of the same frequency as the fundamental wave is superimposed so that the difference between the amplitude of the correction voltage command value for each phase multiplied by the number of cells in each phase and divided by the number of cells in each phase that are operating without failure becomes small among the three phases. The correction voltage command value generating unit
A phase output unit that outputs a phase ωt synchronized with the AC voltage of the system;
a first dq converter that converts a value obtained by multiplying a phase voltage detection signal or the voltage command value, or a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system synchronized with a system frequency;
a second dq converter that converts the phase voltage detection signal or the voltage command value, or a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system that rotates in a direction opposite to the system frequency;
a calculator that calculates a zero-phase d-axis component and a zero-phase q-axis component that make the AC side output voltages of the cells uniform, based on a positive-phase d-axis component and a positive-phase q-axis component that are DC components extracted from the output of the first dq converter, and a negative-phase d-axis component and a negative-phase q-axis component that are DC components extracted from the output of the second dq converter;
a first multiplier that multiplies the d-axis component of the zero-phase voltage by cosωt or sinωt;
a second multiplier that multiplies the q-axis component of the zero-phase voltage by sinωt when the first multiplier multiplies cosωt, and multiplies the q-axis component of the zero-phase voltage by cosωt when the first multiplier multiplies sinωt;
a first adder that adds an output of the first multiplier and an output of the second multiplier;
a second adder that adds an output of the first adder to the voltage command value and outputs the result as a corrected voltage command value;
3. The multiple cell inverter according to claim 1, further comprising: 4. The multi-cell inverter according to claim 3, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (3).

_V0d : d-axis component of zero-phase-sequence voltage _V0q : q-axis component of zero-phase-sequence voltage _V1d : d-axis component of positive-phase-sequence voltage _V1q : q-axis component of positive-phase-sequence voltage _V2d : d-axis component of negative-phase-sequence voltage _V2q : q-axis component of negative-phase-sequence voltage 4. The multi-cell inverter according to claim 3, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (4).

_V0d : d-axis component of zero-phase-sequence voltage _V0q : q-axis component of zero-phase-sequence voltage _V1d : d-axis component of positive-phase-sequence voltage _V1q : q-axis component of positive-phase-sequence voltage _V2d : d-axis component of negative-phase-sequence voltage _V2q : q-axis component of negative-phase-sequence voltage 4. The multi-cell inverter according to claim 3, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (5).

V _0d : d-axis component of zero-phase-sequence voltage V _0q : q-axis component of zero-phase-sequence voltage V _2d : d-axis component of negative-phase-sequence voltage V _2q : q-axis component of negative-phase-sequence voltage V ₁ : positive-phase voltage component The correction voltage command value generating unit
When the negative-phase-sequence d-axis component V _2d =V _1d and the negative-phase-sequence q-axis component V _2q =0, the zero-phase-sequence voltage d-axis component V _0d =-V _1d /2 and the zero-phase-sequence voltage q-axis component V _0q =0;
When the negative-phase-sequence d-axis component V _2d =-V _1d /2 and the negative-phase-sequence q-axis component V _2q =-√3V _1d /2, the zero-phase-sequence voltage d-axis component V _0d =V _1d /4 and the zero-phase-sequence voltage q-axis component V _0q =√3V _1d /4,
The multi-cell inverter according to claim 6, characterized in that when the negative-phase-sequence d-axis component V _2d = -V _1d /2 and the negative-phase-sequence q-axis component V _2q = √3V _1d /2, the zero-phase-sequence voltage d-axis component V _0d = V _1d /4 and the zero-phase-sequence voltage q-axis component V _0q = -√3V _1d /4.

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