JP2023135370A - Ceramic electronic component and method for manufacturing the same - Google Patents

Abstract

The present invention provides a ceramic electronic component that can improve insulation reliability and a method for manufacturing the same. SOLUTION: A ceramic electronic component includes a laminated chip in which dielectric layers containing barium titanate and internal electrode layers are alternately laminated, and the internal electrode layer includes a main component element and a layer including a main component element. The dielectric layer includes a plurality of crystal grains, and a segregation part in which the subelement is segregated is formed in a shell part and a grain boundary of the plurality of crystal grains, The internal electrode layer includes a high concentration layer containing the sub-element at a high concentration near the interface with the dielectric layer, and in the high-concentration layer, the concentration of the sub-element in the direction in which the internal electrode layer extends The variation range is 30% or less of the average concentration of the sub-element in the entire high-concentration layer. [Selection diagram] Figure 6

Description

The present invention relates to a ceramic electronic component and a method for manufacturing the same.

As electronic devices become smaller, ceramic electronic components such as multilayer ceramic capacitors installed in electronic devices are also required to be further miniaturized. In order to increase the capacitance value, which is a basic characteristic, it is possible to (1) increase the dielectric constant of the dielectric layer, (2) increase the capacitance defining area, or (3) make the dielectric layer thinner. There are ways to think about it. When the dielectric constant and element size are fixed, the thinner the dielectric layer is, the larger the capacitance value per layer can be. Since the number can be increased, it is advantageous for increasing capacity.

JP 2021-9993 Publication

As the dielectric layer becomes thinner, the electric field strength applied to the dielectric layer increases, which may reduce insulation reliability. In ceramic electronic components, the insulation properties of the element are often ensured by subelements segregated in the grain boundaries and shells of the dielectric. For example, when a subelement is mixed into a dielectric slurry, the dispersion of the subelement tends to be non-uniform. A leak path may be generated at a site where an excessive amount of the subelement is present, weakening the insulation. In regions where the subelement is insufficient, the resistance of grain boundaries and shells cannot be sufficiently increased, and a desired insulating state may not be obtained. Since the locations of excess and deficiency occur randomly, it has been difficult to uniformly disperse the subelements.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a ceramic electronic component that can improve insulation reliability and a method for manufacturing the same.

A ceramic electronic component according to the present invention includes a laminated chip in which dielectric layers containing barium titanate and internal electrode layers are alternately laminated, and the internal electrode layer includes a main component element and a layer including a main component element. The dielectric layer includes a plurality of crystal grains, and the sub-element is segregated in shell portions and grain boundaries of the plurality of crystal grains, so that the concentration of the sub-element is as low as the concentration of the sub-element. A segregation part is formed in which the concentration of the sub-element is 1.5 times or more higher than that of the entire dielectric layer, and the internal electrode layer has a concentration of the sub-element higher than the internal electrode layer near the interface with the dielectric layer. The concentration layer has a high concentration layer that is 1.5 times or more higher than the concentration in the entire electrode layer, and in the high concentration layer, the variation range of the concentration of the sub-element in the direction in which the internal electrode layer extends is It is characterized in that the average concentration of the sub-element in the entire high-concentration layer is 30% or less.

In the low concentration layer other than the high concentration layer of the internal electrode layer of the ceramic electronic component, the variation range of the concentration of the subelement in the direction in which the internal electrode layer extends is such that the range of variation in the concentration of the subelement in the entire low concentration layer is It may be 30% or less of the average concentration of.

In the dielectric layer of the ceramic electronic component, the variation range of the concentration of the sub-element in the direction in which the dielectric layer extends is 30% or less of the average concentration of the sub-element in the entire dielectric layer. Good too.

In the above ceramic electronic component, the average concentration of the sub-element in the entire internal electrode layer may be higher than the average concentration of the sub-element in the entire dielectric layer.

In the above ceramic electronic component, the concentration of the sub-element may be in the order of the high concentration layer, the segregation portion, the low concentration layer, and the region other than the segregation portion of the dielectric layer.

In the above ceramic electronic component, the concentration of the sub-element in the high concentration layer, the concentration of the sub-element in the segregated portion, the concentration of the sub-element in the low-concentration layer, and the concentration of the sub-element in the dielectric layer other than the segregated portion. The difference in concentration of each of the subelements may be 0.1 at% or more and 2 at% or less.

In the above ceramic electronic component, the dielectric layer may have a thickness of 1 μm or less, and the internal electrode layer may have a thickness of 1 μm or less.

In the above ceramic electronic component, the main component element of the internal electrode layer may be Ni.

In the ceramic electronic component, the subelements include Ag, As, Au, Co, Cr, Cu, Fe, In, Ir, Mg, Mo, Os, Pd, Pt, Re, Rh, Ru, Se, Sn, and Te. , W, Y, Zn, and Ge.

A method for manufacturing a ceramic electronic component according to the present invention includes forming an internal electrode pattern containing a main component element and a subelement whose content is smaller than the main component element on a dielectric green sheet containing barium titanate. a step of oxidizing the surface of the internal electrode pattern with oxygen plasma; a step of forming a laminate by stacking a plurality of the laminate units; and a step of firing the laminate. It is characterized by including the following.

According to the present invention, it is possible to provide a ceramic electronic component that can improve insulation reliability and a method for manufacturing the same.

FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. 2 is a sectional view taken along line BB in FIG. 1. FIG. (a) is a diagram illustrating core-shell particles, (b) is a schematic cross-sectional view of a dielectric layer, and (c) is a schematic plan view of the dielectric layer. (a) is a diagram showing a position where STEM-EDS line analysis was performed in the vicinity of a grain boundary between crystal grains, and (b) is a diagram showing the results of STEM-EDS line analysis. (a) is a diagram showing the position where STEM-EDS line analysis was performed near the interface between the dielectric layer and the internal electrode layer, and (b) is a diagram showing the results of the STEM-EDS line analysis. FIG. 3 is a diagram illustrating a high concentration layer and a low concentration layer in an internal electrode layer. In a plan view of a high-concentration layer, the sub-element concentration is depicted by the shading of a pattern. FIG. 3 is a diagram illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. (a) to (c) are diagrams illustrating a lamination process. It is a Weibull plot showing the HALT test results of Example 1 and Comparative Examples 1 and 2 as cumulative failure rates.

Hereinafter, embodiments will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a partially sectional perspective view of a multilayer ceramic capacitor 100 according to the first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a sectional view taken along line BB in FIG. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a multilayer chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a and 20b provided on two opposing end surfaces of the multilayer chip 10. . Note that, of the four surfaces of the stacked chip 10 other than the two end surfaces, two surfaces other than the upper surface and the lower surface in the stacking direction are referred to as side surfaces. The external electrodes 20a and 20b extend on the top surface, bottom surface, and two side surfaces of the stacked chip 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.

The laminated chip 10 includes a laminated structure and a cover layer 13. The laminated structure includes a laminated portion in which dielectric layers 11 and internal electrode layers 12 are alternately laminated, and has a substantially rectangular parallelepiped shape, and a plurality of laminated internal electrode layers 12 are alternately exposed on two end faces. It has a structure formed like this. Thereby, each internal electrode layer 12 is alternately electrically connected to the external electrodes 20a and 20b. As a result, multilayer ceramic capacitor 100 has a structure in which a plurality of dielectric layers 11 are stacked with internal electrode layers 12 in between. Further, in the laminated structure of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is arranged as the outermost layer in the lamination direction, and the upper and lower surfaces of the laminated structure are covered with a cover layer 13. The cover layer 13 has a ceramic material as its main component. For example, the cover layer 13 may be made of the same material as the dielectric layer 11 and the ceramic material may have the same main component.

The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, 0.2 mm high, or long. 0.6mm, width 0.3mm, height 0.3mm, or length 0.6mm, width 0.3mm, height 0.110mm, or length 1.0mm, width 0.5mm, height The length is 0.5 mm, or the length is 1.0 mm, the width is 0.5 mm, and the height is 0.1 mm; or the length is 3.2 mm, the width is 1.6 mm, and the height is 1.6 mm; The size is 4.5 mm, the width is 3.2 mm, and the height is 2.5 mm, but the size is not limited to these.

The main component of the internal electrode layer 12 is a base metal such as Ni (nickel), Cu (copper), or Sn (tin). As the main component element of the internal electrode layer 12, noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals may be used. In the internal electrode layer 12, the concentration of the main component elements is approximately 90 at % to 99.99 at %. The internal electrode layer 12 contains a subelement in addition to the main component element. Sub-elements are not particularly limited, but include, for example, Ag, As (arsenic), Au, Co (cobalt), Cr (chromium), Cu, Fe (iron), In (indium), and Ir (iridium). , Mg (magnesium), Mo (molybdenum), Os (osmium), Pd, Pt, Re (rhenium), Rh (rhodium), Ru (ruthenium), Se (selenium), Sn, Te (tellurium), W (tungsten). ), Y (yttrium), Zn (zinc), and Ge (germanium). These subelements exist in the internal electrode layer 12 and also diffuse into the dielectric layer 11, exhibiting the effect of increasing the insulation of the multilayer ceramic capacitor 100. Among these subelements, Au, Co, Cr, Fe, In, Mg, Sn, Y, and Zn greatly exhibit the effect of increasing insulation. The thickness of the internal electrode layer 12 is, for example, 10 nm or more and 1000 nm or less, 20 nm or more and 500 nm or less, and 50 nm or more and 300 nm or less. The thickness of the internal electrode layer 12 is determined by observing the cross section of the multilayer ceramic capacitor 100 with an SEM, measuring the thickness at 10 points for each of the 10 different internal electrode layers 12, and deriving the average value of all the measurement points. can be measured.

The dielectric layer 11 has, for example, a ceramic material having a perovskite structure represented by the general formula _ABO3 as a main phase. Note that the perovskite structure includes ABO _3-α that deviates from the stoichiometric composition. For example, a material containing Ba and Ti and having a perovskite structure can be used as the ceramic material. For example, BaTiO ₃ (barium titanate), Ba _1-x-y Ca _x Sry _{Ti 1-z} Zr _z O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦), which forms a perovskite structure. 1) etc. can be used.

In this embodiment, for example, the thickness of the dielectric layer 11 per layer is 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less. The thickness of the dielectric layer 11 is determined by observing the cross section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thickness of each of the 10 different dielectric layers 11 at 10 points, and calculating the average value of all measurement points. It can be measured by deriving .

As illustrated in FIG. 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region in which capacitance occurs in the multilayer ceramic capacitor 100. . Therefore, the region where the electric capacitance occurs is referred to as a capacitance region 14. That is, the capacitive region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

The region where the internal electrode layers 12 connected to the external electrode 20a face each other without interposing the internal electrode layer 12 connected to the external electrode 20b is referred to as an end margin 15. Further, the end margin 15 is also a region where the internal electrode layers 12 connected to the external electrode 20b face each other without interposing the internal electrode layer 12 connected to the external electrode 20a. That is, the end margin 15 is a region where internal electrode layers 12 connected to the same external electrode face each other without interposing the internal electrode layers 12 connected to a different external electrode. The end margin 15 is an area where no capacitance occurs.

As illustrated in FIG. 3, in the stacked chip 10, the area from the two side surfaces of the stacked chip 10 to the internal electrode layer 12 is referred to as a side margin 16. That is, the side margin 16 is a region provided so as to cover the ends of the plurality of stacked internal electrode layers 12 extending toward the two side surfaces in the stacked structure. The side margin 16 is also a region that does not generate capacitance. Note that in the stacked structure included in the stacked chip 10 described above, the capacitive region 14 and the side margin 16 correspond.

Dielectric layer 11 includes a plurality of crystal grains. At least some of the plurality of crystal grains are core-shell particles 30 having a core-shell structure.

As illustrated in FIG. 4A, the core-shell particle 30 includes a substantially spherical core portion 31 and a shell portion 32 that surrounds and covers the core portion 31. The core portion 31 is a crystalline portion in which the additive element is not dissolved in solid solution or the amount of the additive element in solid solution is small. The shell portion 32 is a crystal portion in which the additive element is dissolved in solid solution and has a higher additive element concentration than the core portion 31 . For example, the core portion 31 is made of barium titanate, and the shell portion 32 has a structure in which barium titanate is the main component and additional elements are dissolved in the barium titanate. The additive elements also include subelements diffused from the internal electrode layer 12. Note that the core portion 31 tends to have lower electrical resistance and higher dielectric constant than the shell portion 32. The shell portion 32 tends to have higher electrical resistance and lower dielectric constant than the core portion 31. The insulation properties of the dielectric layer 11 tend to be dominated by the shell portion 32 rather than the core portion 31 .

FIG. 4(b) is a schematic cross-sectional view of the dielectric layer 11. As illustrated in FIG. 4(b), the dielectric layer 11 includes a plurality of crystal grains 17 of ceramic as the main component. At least some of these crystal grains 17 are the core-shell particles 30 described in FIG. 4(a). Grain boundaries 18 are formed between the plurality of crystal grains 17 .

FIG. 4C is a schematic plan view of the dielectric layer 11. As illustrated in FIG. 4C, the dielectric layer 11 includes a plurality of crystal grains 17 even in plan view. At least some of these crystal grains 17 are the core-shell particles 30 described in FIG. 4(a). Grain boundaries 18 are formed between the plurality of crystal grains 17 .

The subelements of the internal electrode layer 12 become segregated in the grain boundaries 18 and the shell portion 32. Specifically, a segregation area of subelements appears. The segregation portion can be defined as a portion where the subelement concentration is 1.5 times or more the subelement concentration in the entire dielectric layer 11. The segregated portion may appear in the entire grain boundary 18 or in a portion thereof.

FIG. 5(a) shows STEM (scanning transmission electron microscopy)-EDS (energy dispersive X-ray spectroscopy) line analysis performed near the grain boundary 18 between crystal grains 17 and adjacent crystal grains 17. It is a figure showing a position. As an example, the main component of the dielectric layer 11 is barium titanate, the main component element of the internal electrode layer 12 is Ni, and the subelement added to the internal electrode layer 12 is Fe.

FIG. 5(b) shows the results of STEM-EDS line analysis. The dashed-dotted lines represent grain boundaries 18. As shown in FIG. 5(b), inside the crystal grains 17, the Fe concentration and the Ni concentration are approximately constant at low values. When approaching the grain boundaries 18, peaks appear in the Fe and Ni concentrations. In this way, the main component elements and subelements of the internal electrode layer 12 are likely to segregate at the grain boundaries 18. These concentration peaks have a predetermined width. Therefore, it is considered that the main component elements and subelements of the internal electrode layer 12 are also segregated in the shell portions 32 of the core-shell particles 30.

In the multilayer ceramic capacitor 100, the thinner the dielectric layer 11 is, the larger the capacitance value per layer of the dielectric layer 11 can be. Since it becomes possible to increase the size, it is advantageous for increasing the capacity.

However, as the dielectric layer 11 becomes thinner, the electric field strength applied to the dielectric layer 11 increases, which may reduce insulation reliability. In the multilayer ceramic capacitor 100, the insulation of the element is often ensured by subelements that diffuse from the internal electrode layer 12 and segregate in the crystal grain boundaries 18 and shell portion 32 of the dielectric layer 11. If the sub-elements are simply mixed into the dielectric slurry before firing as in the conventional method, the dispersion of the sub-elements tends to be non-uniform. For example, it is difficult to reduce the particle size of the added subelement to 1 nm to several tens of nanometers, so if mixing is insufficient, the amount of the subelement will be biased to a specific location. That is, there is a possibility that lumps of the sub-element having a particle size of at least several tens of nanometers or more may remain locally in the dielectric layer 11, or the amount of the sub-element may locally become insufficient. Leak paths may be generated in areas with excessive amounts of subelements, weakening the insulation. In a region where the subelement is insufficient, the resistance between the grain boundary 18 and the shell portion 32 cannot be sufficiently increased, and a desired insulating state may not be obtained. Since the locations where the sub-elements are in excess or deficiency occur randomly, it has been difficult to obtain a desired insulation state.

Therefore, the multilayer ceramic capacitor 100 according to the present embodiment has a structure that allows diffusion of subelements at the atomic level, thereby improving insulation reliability.

FIG. 6(a) is a diagram showing the positions where STEM-EDS line analysis was performed. As shown in FIG. 6A, line analysis was performed from the dielectric layer 11 toward the internal electrode layer 12 near the interface between the dielectric layer 11 and the internal electrode layer 12. In FIG. 6(a), the portion indicated by the thick black line corresponds to the interface. In this case, as an example, the main component of the dielectric layer 11 is barium titanate, the main component element of the internal electrode layer 12 is Ni, and the subelement added to the internal electrode layer 12 is Fe.

FIG. 6(b) shows the results of STEM-EDS line analysis. A dashed-dotted line represents the interface between the dielectric layer 11 and the internal electrode layer 12. As shown in FIG. 6B, inside the internal electrode layer 12, the Ni concentration is high and approximately constant, and the Fe concentration is low and approximately constant. When approaching the interface between the dielectric layer 11 and the internal electrode layer 12, a peak appears in the Fe concentration. In this way, the internal electrode layer 12 includes the high concentration layer 121 containing the sub-element at a high concentration near the interface with the dielectric layer 11. The high concentration layer 121 is a layer in which the subelement concentration is 1.5 times or more the subelement concentration in the entire internal electrode layer 12 . Note that the concentration of the subelement is the atomic concentration of the subelement relative to the total of the main component element and the subelement in the internal electrode layer 12.

As illustrated in FIG. 7, the internal electrode layer 12 includes a high concentration layer 121 near the interface with the dielectric layer 11 (a predetermined thickness range from the surface of the internal electrode layer 12), and A low concentration layer 122 having a low subelement concentration is provided between two high concentration layers 121 in the direction.

FIG. 8 is a plan view of the high-concentration layer 121, in which the sub-element concentration is depicted by a pattern of shading. The darker the pattern, the higher the concentration of the subelement, and the lighter the pattern, the lower the concentration of the subelement. As illustrated in FIG. 8, although a distribution is seen in the subelement concentration, the difference in the subelement concentration is small overall. Specifically, the variation range of the subelement concentration at each position in the entire high concentration layer 121 when viewed in plan (the variation range of the subelement concentration in the direction in which the internal electrode layer 12 extends) is the same as that of the high concentration layer 121. It is 30% or less of the average concentration of subelements in the whole. That is, when the average concentration of the sub-element is AC, the concentration of the sub-element at each position is AC±30%.

The subelement concentration at each position of the high concentration layer 121 is the average value of the subelement concentration in the thickness direction of the high concentration layer 121 at each position. Each position is, for example, a position separated by an interval of 1 μm.

The variation range of the sub-element concentration at each position in the entire high-concentration layer 121 when viewed in plan is 30% or less of the average concentration of the sub-element in the entire high-concentration layer 121, so that the overall sub-element concentration is The difference between the two elements can be reduced, and the subelements can be distributed almost uniformly. According to this configuration, the subelement is supplied substantially uniformly from the internal electrode layer 12 to the dielectric layer 11, so that the supply state of the subelement becomes substantially uniform in the surface direction of the dielectric layer 11. Since the sub-elements diffuse through the grain boundaries 18, they are efficiently supplied to the grain boundaries 18 and the shell portion 32. Since relatively high-speed grain boundary diffusion can be utilized, uniformity of the subelement concentration in the thickness direction can be ensured simply by adjusting the firing conditions. Since the high concentration layer 121 functions as a buffer for the subelement, excess or deficiency in the amount supplied to the dielectric layer 11 is automatically adjusted.

From the above, since the distribution of the sub-elements in the dielectric layer 11 is made uniform, the occurrence of local leakage paths due to excessive sub-elements is suppressed. In addition, the occurrence of locations lacking subelements is also suppressed, so that a desired insulation state can be obtained. Therefore, the insulation reliability of the dielectric layer 11 can be improved.

From the viewpoint of making the distribution of the subelement concentration in the high concentration layer 121 uniform, the variation range of the subelement concentration at each position in the entire high concentration layer 121 when viewed from above is the average of the subelement in the entire high concentration layer 121. The concentration is preferably 30% or less, more preferably 20% or less.

In order to make the supply of the sub-element to the dielectric layer 11 substantially uniform, it is preferable that the sub-element concentration in the low concentration layer 122 is also substantially uniform. For example, the variation range of the subelement concentration at each position in the entire low concentration layer 122 when viewed in plan (the variation range of the subelement concentration in the direction in which the internal electrode layer 12 extends) is The average concentration of the element is preferably 30% or less, more preferably 20% or less, and even more preferably 10% or less.

From the viewpoint of substantially uniformly distributing the subelement concentration in the dielectric layer 11, the variation range of the subelement concentration at each position in the entire dielectric layer 11 when viewed from above (the subelement concentration in the direction in which the dielectric layer 11 extends) is The variation range of the element concentration is preferably 30% or less, more preferably 20% or less, and 10% or less of the average concentration of the subelement in the entire dielectric layer 11. It is more preferable to be present. Note that the subelement concentration at each position of the dielectric layer 11 is the average value of the subelement concentration in the thickness direction of the dielectric layer 11 at each position. The subelement concentration can be calculated as the atomic concentration of the subelement relative to all elements including the subelement. Each position is, for example, a position separated by an interval of 1 μm.

The average concentration of the sub-elements in the entire internal electrode layer 12 is preferably higher than the average concentration of the sub-elements in the entire dielectric layer 11 . This is because the subelement can be efficiently supplied from the internal electrode layer 12 to the dielectric layer 11.

It is preferable that the sub-element concentration increases in the order of the high concentration layer 121, the segregation part, the low concentration layer 122, and the region other than the segregation part in the dielectric layer 11. This is because it is possible to efficiently supply the subelement from the internal electrode layer 12 to the dielectric layer 11, and to supply a sufficient amount of the subelement to the segregation portion contributing to insulation.

The difference between the subelement concentration in the high concentration layer 121, the subelement concentration in the segregated portion, the subelement concentration in the low concentration layer 122, and the subelement concentration in the dielectric layer 11 other than the segregated portion is 0.1 at% or more. , 2 at% or less. This is because if the difference is too small, the effect will be insufficient, and if the difference is too large, the concentration balance will become unstable.

Note that if the dielectric layer 11 is formed thickly, the sub-element may not be sufficiently diffused from the internal electrode layer 12 to the central portion of the dielectric layer 11, and the insulation properties of the entire dielectric layer 11 may not be sufficiently improved. There is. Therefore, when the dielectric layer 11 is formed thinly, the effects of the present embodiment are significantly exhibited. For example, when the thickness of the dielectric layer 11 is 1 μm or less, the effects of this embodiment are significantly exhibited.

Further, since the distance from the internal electrode layer 12 to the side margin 16 becomes large, the volume ratio of the segregated portion becomes smaller than that of the capacitive region 14. Furthermore, since the number of internal electrode layers 12 is reduced in the end margin 15, the volume ratio of the segregated portion is also smaller in the end margin 15 than in the capacitance region 14.

Next, a method for manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 9 is a diagram illustrating a flow of a method for manufacturing the multilayer ceramic capacitor 100.

(Raw material powder production process)
First, raw material powder for forming the dielectric layer 11, the cover layer 13, and the side margin 16 is prepared. The A-site element and the B-site element contained in the dielectric layer 11, the cover layer 13, and the side margin 16 are usually contained in the form of a sintered body of ABO ₃ particles. BaTiO ₃ is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO ₃ can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods are conventionally known for synthesizing the main component ceramic of the dielectric layer 11, the cover layer 13, and the side margin 16, such as a solid phase method, a sol-gel method, a hydrothermal method, etc. ing. In this embodiment, any of these can be adopted.

Predetermined additional elements are added to the obtained ceramic powder depending on the purpose. Additional elements include Mg (magnesium), Mn (manganese), V (vanadium), Cr, rare earth elements (Y, Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium). ), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)), or Co, Ni, Li (lithium), B (boron), Na (sodium), K (, potassium) ) or oxides containing Si (silicon), or glasses containing Co, Ni, Li, B, Na, K, or Si.

For example, a ceramic material is prepared by wet-mixing a compound containing an additive element with a ceramic raw material powder, drying and pulverizing the mixture. For example, the ceramic material obtained as described above may be pulverized to adjust the particle size, if necessary, or may be combined with a classification process to adjust the particle size. Through the above steps, a raw material powder is obtained.

(Coating process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the raw material powder produced in the raw material powder production process and wet-mixed. Using the obtained slurry, a dielectric green sheet 52 is coated on the base material 51 by, for example, a die coater method or a doctor blade method, and then dried. The base material 51 is, for example, a polyethylene terephthalate (PET) film.

(Printing process)
Next, as illustrated in FIG. 10(a), an internal electrode pattern 53 is formed on the dielectric green sheet 52. The internal electrode pattern 53 contains the main component element and the subelement of the internal electrode layer 12. These main component elements and subelements are contained in the internal electrode pattern 53 in the form of powder. In FIG. 10A, as an example, four layers of internal electrode patterns 53 are formed on a dielectric green sheet 52 at predetermined intervals. The dielectric green sheet 52 on which the internal electrode pattern 53 is formed is a laminated unit.

(oxidation process)
Next, the outermost surface of the internal electrode pattern 53 is oxidized by oxygen plasma to form an oxide film 56. The extreme outermost surface is a region with a thickness of 1 nm or less from the surface, as illustrated in FIG. 10(b). As a result, at the outermost surface, the main component elements and subelements of the internal electrode layer 12 are oxidized to become metal oxides. Note that it is difficult to uniformly oxidize the entire outermost surface by simply exposing the internal electrode pattern 53 to the atmosphere.

Note that during oxidation treatment using oxygen plasma, if the plasma energy is too high or the treatment time is too long, oxidation will progress to the inside rather than the outermost surface, making it difficult for current to flow through the internal electrode layer 12 after firing. There is a risk that this may occur. Therefore, it is preferable to set appropriate treatment conditions to avoid oxidation of the electrode.

(Lamination process)
Next, while peeling the dielectric green sheet 52 from the base material 51, the laminated units are laminated as illustrated in FIG. 10(c).

Next, a predetermined number of cover sheets 54 are laminated on the upper and lower sides of the laminate obtained by laminating the laminate units, thermocompression bonded, and cut into a predetermined chip size (for example, 1.0 mm x 0.5 mm). In the example of FIG. 10(c), cutting is performed along the dotted line. Similar to the dielectric green sheet 52, the cover sheet 54 is made by adding a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer to the raw material powder produced in the raw material powder production process. In addition, it can be obtained by performing wet mixing and using the obtained slurry, coating it on the base material 51 by a die coater method or a doctor blade method and drying it.

(Firing process)
After debinding the ceramic laminate thus obtained in an N ₂ atmosphere, a metal paste that will become the base layer of the external electrodes 20a and 20b is applied by a dip method, and the oxygen partial pressure is 10 ^-5 to 10 ^-8 . Calcinate at 1100 to 1300° C. for 10 minutes to 2 hours in a reducing atmosphere of ATM. In this way, a multilayer ceramic capacitor 100 is obtained.

(Re-oxidation treatment process)
Thereafter, reoxidation treatment may be performed at 600° C. to 1000° C. in an N ₂ gas atmosphere.

(Plating process)
Thereafter, the external electrodes 20a and 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

According to the method for manufacturing the multilayer ceramic capacitor 100 according to the present embodiment, the subelement is supplied to the dielectric layer 11 by thermal diffusion by performing heat treatment in the firing process. Since the outermost surface of the internal electrode pattern 53 is an oxide film, the dielectric layer 11 having an oxide as a main phase also allows subelements to diffuse easily. Therefore, the time lag between the start of diffusion for each position is reduced. Once the diffusion of the sub-elements is started, the sub-elements that have diffused first serve as prime water, making it easier for the subsequent sub-elements to diffuse as well. As a result, the distribution of the sub-elements in the dielectric layer 11 is made uniform, thereby suppressing the occurrence of local leak paths due to excessive sub-elements. In addition, the occurrence of locations lacking subelements is also suppressed, so that a desired insulation state can be obtained. Therefore, the insulation reliability of the dielectric layer 11 can be improved.

Note that in each of the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited thereto. For example, other electronic components such as varistors and thermistors may be used.

Hereinafter, a multilayer ceramic capacitor according to an embodiment was manufactured and its characteristics were investigated.

(Example 1)
A dielectric green sheet containing barium titanate as the main ceramic component was prepared, and a conductive paste was printed on its surface as an internal electrode pattern. As the metal powder in the conductor paste, instead of pure Ni, an alloy containing 1.0 at% Fe was used. The concentration in this case is at% of Fe/(Fe+Ni). The outermost surface of the internal electrode pattern was oxidized by oxygen plasma, but the inside was not oxidized. A plurality of dielectric green sheets on which internal electrode patterns were formed were laminated on a cover sheet prepared in advance. Subsequently, crimping, cutting, application of metal paste for external electrodes, and firing were performed to obtain a multilayer ceramic capacitor element.

In order to analyze the state of fine crystal grains in the obtained multilayer ceramic capacitor, STEM-EDS analysis was performed at five points on each sample. After confirming the entire view of the particles in a viewing range of about 1 μm, the interface between the dielectric layer and the internal electrode layer and the vicinity of the crystal grain boundaries of the dielectric layer were observed at high magnification in a viewing range of about 20 nm□.

When checking a STEM-EDS image near the grain boundaries of the dielectric layer, it was confirmed that Fe and Ni were segregated at the grain boundaries and their vicinity (shell portions).

Furthermore, when checking a STEM-EDS image near the interface between the internal electrode layer and the dielectric layer, it was confirmed that Fe was segregated at the interface. Furthermore, it was confirmed that Fe was contained in the internal electrode layer in areas other than the vicinity of the interface. The fluctuation range of the Fe high concentration layer, which is defined as a high concentration layer in which the concentration of the sub-element in the direction in which the internal electrode layer extends is 1.5 times or more of the concentration in the entire internal electrode layer, is as follows: The average concentration of Fe in the high concentration layer was 30% or less. Further, in the internal electrode layer, the variation range of the Fe concentration in the low concentration layer other than the high concentration layer was 30% or less with respect to the average concentration of Fe in the low concentration layer.

(Example 2)
Au was used instead of Fe as a subelement. Other conditions were the same as in Example 1.

STEM-EDS analysis was performed in the same manner as in Example 1. When checking the STEM-EDS image near the grain boundaries of the dielectric layer, it was confirmed that Au and Ni were segregated at the grain boundaries and their vicinity (shell parts).

Furthermore, when checking a STEM-EDS image near the interface between the internal electrode layer and the dielectric layer, it was confirmed that Au was segregated at the interface. Furthermore, it was confirmed that Au was contained in the internal electrode layer in areas other than the vicinity of the interface. The variation range of the high concentration layer of Au in the direction in which the internal electrode layer extends was 30% or less with respect to the average concentration of Au in the high concentration layer. Further, in the internal electrode layer, the variation range of the Au concentration in the low concentration layer other than the high concentration layer was 30% or less with respect to the average concentration of Au in the low concentration layer.

(Example 3)
Cr was used as a subelement instead of Fe. Other conditions were the same as in Example 1.

STEM-EDS analysis was performed in the same manner as in Example 1. When checking a STEM-EDS image near the grain boundaries of the dielectric layer, it was confirmed that Cr and Ni were segregated at the grain boundaries and their vicinity (shell parts).

Further, when checking a STEM-EDS image near the interface between the internal electrode layer and the dielectric layer, it was confirmed that Cr was segregated at the interface. Furthermore, it was confirmed that Cr was contained in the internal electrode layer in areas other than the vicinity of the interface. The variation range of the high concentration layer of Cr in the direction in which the internal electrode layer extends was 30% or less with respect to the average concentration of Cr in the high concentration layer. Further, in the internal electrode layer, the variation range of the Cr concentration in the low concentration layer other than the high concentration layer was 30% or less with respect to the average concentration of Cr in the low concentration layer.

(Comparative example 1)
In Comparative Example 1, no subelement was added to the conductor paste. That is, pure Ni conductive paste was printed as an internal electrode pattern. Other conditions were the same as in Example 1.

(Comparative example 2)
A dielectric green sheet containing barium titanate as the main ceramic component and to which Fe was added was prepared, and a conductive paste was printed on its surface as an internal electrode pattern. Pure Ni was used for the conductor paste, and no sub-elements were added. That is, pure Ni conductive paste was printed as an internal electrode pattern. The total amount of Fe added to the dielectric green sheet was made equal to that in Example 1. Other conditions were the same as in Example 1.

STEM-EDS analysis was performed in the same manner as in Example 1. Fe was not detected in the internal electrode layer.

When we checked the STEM-EDS image near the interface between the internal electrode layer and the dielectric layer, we found that the variation range of the Fe concentration at the interface was about 50% of the average concentration of Fe at the entire interface. .

(Comparative example 3)
In Comparative Example 3, the outermost surface of the internal electrode pattern was not oxidized. Other conditions were the same as in Example 1.

STEM-EDS analysis was performed in the same manner as in Example 1. When checking a STEM-EDS image near the interface between the internal electrode layer and the dielectric layer, it was confirmed that Fe was segregated at the interface. Furthermore, it was confirmed that Fe was contained in the internal electrode layer in areas other than the vicinity of the interface. The variation range of the Fe concentration in the internal electrode layer other than the interface was 30% or less with respect to the average concentration of Fe in the internal electrode layer other than the interface. However, the variation range of the Fe concentration at the interface was about 40% of the average concentration of Fe at the interface.

A 125C/18V HALT test (accelerated life test) was conducted for each of Examples 1 to 3 and Comparative Examples 1 to 3. The time until the leakage current exceeded 1 mA was defined as the HALT life (failure time). If the HALT life is 5 times or more than the HALT life of Comparative Example 1, it is judged as very good "◎", and if it is 4 times or more and less than 5 times, it is judged as good "○", and 4 If it was less than twice that, it was judged as defective "x".

The measurement results are shown in Table 1. As shown in Table 1, in Comparative Example 2, the HALT life was slightly improved compared to Comparative Example 1, but the improvement was slight. This is considered to be because the variation range of the Fe concentration at the interface between the internal electrode layer and the dielectric layer was as large as about 50% of the average Fe concentration at the entire interface. In Comparative Example 3, the HALT life was slightly improved compared to Comparative Example 1, but the improvement was small. This is also considered to be because the variation range of the Fe concentration at the interface between the internal electrode layer and the dielectric layer was as large as about 50% of the average Fe concentration at the entire interface.

On the other hand, in Examples 1 to 3, the HALT lifespan was significantly improved compared to Comparative Example 1. This is considered to be because the variation range of the Fe concentration at the interface between the internal electrode layer and the dielectric layer was reduced to 30% or less of the average Fe concentration at the entire interface. Note that since the HALT lifespans of Examples 1 and 2 are improved over the HALT lifespan of Example 3, it can be seen that it is preferable to use Fe or Au as the subelement.

FIG. 11 is a Weibull plot showing the HALT test results of Example 1 and Comparative Examples 1 and 2 as cumulative failure rates. The horizontal axis indicates the time until failure occurs. The vertical axis shows the cumulative failure rate. It was confirmed that the state of Example 1, in which the sub-elements were uniformly segregated both in the internal electrodes and near the dielectric grain boundaries, had the longest life. Comparative Example 2 has the second longest lifespan, but because the supply source of the subelement was not the internal electrode, its distribution was uneven and it was not possible to uniformly extend the lifespan of the entire dielectric layer. It can be understood. Comparative Example 1, which did not contain any sub-elements, had the shortest life.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and variations can be made within the scope of the gist of the present invention as described in the claims. Changes are possible.

10 Laminated chip 11 Dielectric layer 12 Internal electrode layer 13 Cover layer 14 Capacitance region 15 End margin 16 Side margin 17 Crystal grain 18 Crystal grain boundary 20a, 20b External electrode 30 Core shell particle 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitor

Claims (10)

Equipped with a multilayer chip in which dielectric layers containing barium titanate and internal electrode layers are alternately stacked,
The internal electrode layer includes a main component element and a sub-element whose content is lower than that of the main component element,
The dielectric layer includes a plurality of crystal grains,
The sub-element is segregated in the shell portions and grain boundaries of the plurality of crystal grains, forming a segregated region in which the concentration of the sub-element is 1.5 times or more the concentration in the entire dielectric layer. Ori,
The internal electrode layer includes a high concentration layer near the interface with the dielectric layer, in which the concentration of the subelement is 1.5 times or more the concentration in the entire internal electrode layer,
In the high-concentration layer, a variation range of the concentration of the sub-element in the direction in which the internal electrode layer extends is 30% or less of the average concentration of the sub-element in the entire high-concentration layer. electronic components. In the low concentration layer other than the high concentration layer of the internal electrode layer, the variation range of the concentration of the subelement in the direction in which the internal electrode layer extends is 30% of the average concentration of the subelement in the entire low concentration layer. % or less, the ceramic electronic component according to claim 1. In the dielectric layer, a variation range of the concentration of the sub-element in the direction in which the dielectric layer extends is 30% or less of an average concentration of the sub-element in the entire dielectric layer. The ceramic electronic component according to claim 1 or claim 2. The ceramic according to any one of claims 1 to 3, wherein the average concentration of the subelement in the entire internal electrode layer is higher than the average concentration of the subelement in the entire dielectric layer. electronic components. The concentration of the sub-element is in the order of the high concentration layer, the segregation part, the low concentration layer, and the region other than the segregation part in the dielectric layer. 4. The ceramic electronic component according to any one of 4. The concentration of the sub-element in the high concentration layer, the concentration of the sub-element in the segregated portion, the concentration of the sub-element in the low-concentration layer, and the concentration of the sub-element in a region other than the segregated portion of the dielectric layer. The ceramic electronic component according to any one of claims 1 to 5, wherein each difference is 0.1 at% or more and 2 at% or less. The thickness of the dielectric layer is 1 μm or less,
The ceramic electronic component according to any one of claims 1 to 6, wherein the internal electrode layer has a thickness of 1 μm or less. The ceramic electronic component according to any one of claims 1 to 7, wherein the main component element of the internal electrode layer is Ni. The subelements include Ag, As, Au, Co, Cr, Cu, Fe, In, Ir, Mg, Mo, Os, Pd, Pt, Re, Rh, Ru, Se, Sn, Te, W, Y, and Zn. The ceramic electronic component according to any one of claims 1 to 8, characterized in that the ceramic electronic component is at least one of , and Ge. forming a laminated unit on a dielectric green sheet containing barium titanate by forming an internal electrode pattern containing a main component element and a subelement whose content is smaller than the main component element;
oxidizing the surface of the internal electrode pattern with oxygen plasma;
forming a laminate by stacking a plurality of the laminate units;
A method for manufacturing a ceramic electronic component, comprising the step of firing the laminate.

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