JP2023039901A - Display device and its control method - Google Patents

Abstract

An object of the present invention is to reduce variations in brightness in a display area.
A display device includes a plurality of pixels and a control circuit that controls brightness of the plurality of pixels. Each pixel of the plurality of pixels includes a light emitting element and a pixel circuit for controlling light emission of the light emitting element. The pixel circuit includes a drive transistor that supplies a current to the light emitting element, and a storage capacitor that holds a voltage that controls the current supplied by the drive transistor to the light emitting element. The control circuit determines a statistical value of brightness of pixels represented by a video frame by a predetermined method, determines a threshold compensation period of a storage capacitor for the driving transistor based on the statistical value, and determines a pixel brightness based on the threshold compensation period. control the circuit.
[Selection drawing] Fig. 6

Description

The present disclosure relates to a display device and its control method.

An OLED (Organic Light-Emitting Diode) element is a current-driven self-luminous element, so it does not require a backlight, and has advantages such as low power consumption, a wide viewing angle, and a high contrast ratio. Expected in the development of flat panel displays.

An active matrix (AM) type OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. A transistor in an OLED display device is a TFT (Thin Film Transistor), and generally a LTPS (Low Temperature Poly-silicon) TFT or an oxide semiconductor TFT is used.

TFTs have variations in threshold voltage and charge mobility. Since the drive transistor determines the emission intensity of the OLED display, variations in these electrical characteristics are problematic. Therefore, a pixel circuit of a general OLED display device is equipped with a correction circuit that compensates for variations and fluctuations in the threshold voltage of the drive transistor.

U.S. Patent Application Publication No. 2016/0275865 U.S. Patent Application Publication No. 2005/0057581 U.S. Patent Application Publication No. 2006/0055335 U.S. Patent Application Publication No. 2017/0352314

In-plane luminance variations in the display area are caused by threshold voltage compensation characteristics of the drive transistor. Therefore, it is important to appropriately set the length of the threshold voltage compensation period of the driving transistor. According to research by the inventors, it has been found that the threshold correction period for minimizing variations in luminance of pixels within the display region varies depending on the value of the current flowing through the drive transistor (luminance of the light emitting element).

A display device of one embodiment of the present disclosure includes a plurality of pixels and a control circuit that controls luminance of the plurality of pixels. Each pixel of the plurality of pixels includes a light emitting element and a pixel circuit that controls light emission of the light emitting element. The pixel circuit includes a drive transistor that supplies a current to the light emitting element, and a storage capacitor that holds a voltage for controlling the current supplied by the drive transistor to the light emitting element. The control circuit determines a statistical value of luminance of pixels represented by a video frame by a predetermined method, determines a threshold compensation period of the storage capacitor for the driving transistor based on the statistical value, and determines the threshold value. The pixel circuit is controlled based on the compensation period.

Another aspect of the present disclosure is a display device control method. The display device includes a plurality of pixels. Each pixel of the plurality of pixels includes a light emitting element and a pixel circuit that controls light emission of the light emitting element. The pixel circuit includes a drive transistor that supplies a current to the light emitting element, and a storage capacitor that holds a voltage for controlling the current supplied by the drive transistor to the light emitting element. The control method determines a statistical value of brightness of pixels represented by a video frame by a predetermined method, determines a threshold compensation period of the storage capacitor for the driving transistor based on the statistical value, and determines the threshold value. The pixel circuit is controlled based on the compensation period.

According to one aspect of the present disclosure, it is possible to reduce luminance variations in the display area.

1 schematically shows a configuration example of an OLED display device. 4 shows a configuration example of a pixel circuit according to an embodiment of the present specification; 4 shows an example of a timing chart of signals for controlling pixel circuits. 4 schematically shows the relationship between the threshold compensation period and the data write period in four consecutive pixel circuit rows. Fig. 3 shows the relationship between the average luminance of a video frame and the optimal threshold compensation period for different pixel circuits; FIG. 3 shows an example functional configuration of an OLED display device that dynamically changes a threshold compensation period; FIG. 4 shows a timing chart of an S1 selection signal and control signals for generating the S1 selection signal. 4 illustrates an example functional configuration of an OLED display that dynamically changes the threshold compensation period, according to one embodiment herein. FIG. 4 is a diagram schematically showing trimming of an STV1 start pulse signal by a trimming controller; 4 illustrates an example functional configuration of an OLED display that dynamically changes the threshold compensation period, according to one embodiment herein. 2 is a configuration diagram schematically showing an internal circuit configuration of a scan driver; FIG. 4 shows a configuration example of a latch circuit; 2 shows a truth table for a latch circuit; 4 shows a circuit configuration example of a latch circuit; 15 shows an example of a timing chart of signals controlling the pixel circuits described with reference to FIGS. 10 to 14. FIG. 4 shows a configuration example of a trimming controller. 17 shows a truth table for the trimming controller shown in FIG. 16; FIG. 17 shows a timing chart of input/output signals of the trimming controller shown in FIG. 16; 4 schematically shows the relationship between the data voltage to the pixel circuit and the drive current (Ioled) of the OLED element for different threshold compensation periods. 4 shows a configuration example of a data voltage correction table; FIG. 3 shows a functional configuration example of an OLED display device having a data voltage correction function according to a threshold compensation period; FIG.

Embodiments are described below with reference to the drawings. The same reference numerals are given to the common components in each figure. In order to make the description easier to understand, the dimensions and shapes of the illustrated objects may be exaggerated.

The following discloses the configuration of a circuit that generates and outputs a control signal for a pixel circuit in a light-emitting display device that uses a light-emitting element that emits light by driving current, such as an OLED (Organic Light-Emitting Diode) display device. be. In an OLED display device, luminance variations can occur among the pixels included in the display area.

This is due to the characteristics of threshold voltage compensation of the driving transistor by the pixel circuit. According to research by the inventors, it has been found that the length of the threshold compensation period for minimizing luminance variations in the display area varies depending on the value of the current flowing through the drive transistor (the luminance of the light emitting element).

A display device according to an embodiment of the present specification determines a threshold compensation period of a drive transistor in a pixel circuit based on luminance of a plurality of pixels included in a display area indicated by video data. This makes it possible to more effectively reduce luminance variations that change according to the luminance of the displayed image.

<Embodiment 1>
An overall configuration of a display device according to an embodiment of the present specification will be described with reference to FIG. In order to make the description easier to understand, the dimensions and shapes of the illustrated objects may be exaggerated. An OLED display device will be described below as an example of the display device.

FIG. 1 schematically shows a configuration example of an OLED display device 10. As shown in FIG. The OLED display device 10 includes a TFT (Thin Film Transistor) substrate 100 on which OLED elements (light emitting elements) are formed, and a sealing structure section 150 for sealing the OLED elements. A control circuit is arranged around the cathode electrode formation region 114 outside the display region 125 of the TFT substrate 100 . Specifically, a scanning driver 131, an emission driver 132, an electrostatic discharge protection circuit 133, a driver IC 134, and a demultiplexer 136 are arranged.

The driver IC 134 is connected to external equipment via an FPC (Flexible Printed Circuit) 135 . A scanning driver 131 drives the scanning lines of the TFT substrate 100 . The emission driver 132 drives emission control lines to control light emission of each pixel. The electrostatic discharge protection circuit 133 prevents electrostatic damage to elements on the TFT substrate. The driver IC 134 is mounted using, for example, an anisotropic conductive film (ACF).

The driver IC 134 supplies power and control signals including timing signals to the scan driver 131 and the emission driver 132 . In addition, driver IC 134 provides power and data signals to demultiplexer 136 . The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 136 drives d times as many data lines as the number of output pins of the driver IC 134 by switching the output destination data line of the data signal from the driver IC 134 d times within the scanning period.

FIG. 2 shows a configuration example of the pixel circuit 107 according to one embodiment of the present specification. The pixel circuit 107 is included in the N-th (N is an integer) pixel circuit row. The pixel circuit 107 includes six transistors (TFTs) M11-M16 with gates, sources and drains. In this example, all transistors M11-M16 are P-type TFTs.

Transistor M11 is a drive transistor that controls the amount of current to OLED element E1. The drive transistor M11 controls the amount of current supplied to the OLED element E1 from the anode power supply that supplies the power supply potential PVDD according to the voltage held by the holding capacitor C10. The holding capacitor C10 holds the written voltage throughout one frame period. A cathode of the OLED element E1 is connected to a power supply line 204 that transmits a power supply potential PVEE from a cathode power supply. The power supply potentials PVDD and PVEE are given from the driver IC 134, for example.

In the configuration example of FIG. 2, the holding capacitor C10 is composed of capacitors C11 and C12 connected in series. One end of the holding capacitor C10 is supplied with the anode power supply potential PVDD, and the other end is connected to the source/drain of the switch transistors M13 and M14. The other end of the holding capacitor C10 is connected to the gate of the driving transistor M11. More specifically, one end of the capacitor C12 is connected to the power line 241 . One end of the capacitor C11 is connected to the source/drain of the switch transistors M13 and M14. An intermediate node of the capacitors C11 and C12 is connected to the gate of the driving transistor M11.

The voltage of the storage capacitor C10 is the voltage between the gate of the drive transistor M11 and the anode power supply line 241 . The source of the drive transistor M11 is connected to the anode power supply line 241, and the source potential is the anode power supply potential PVDD. Therefore, the holding capacitor C10 holds the gate-source voltage of the driving transistor M11. In the configuration example of FIG. 2, the capacitor C12 holds the gate-source voltage of the drive transistor M11.

A transistor M15 is a switch transistor for controlling ON/OFF of light emission of the OLED element E1. The source of the transistor M15 is connected to the drain of the driving transistor M11. The transistor M15 turns ON/OFF the current supply to the OLED element E1 connected to its drain. The gate of the transistor M15 is connected to the Em signal line (light emission control line) 133, and the transistor M15 is controlled by the light emission control signal Em input from the emission driver 132 to the gate.

Transistor M16 operates to supply reset potential Vrst to the anode of OLED element E1. One end of the source/drain of the transistor M16 is connected to the power supply line 242 transmitting the reset potential Vrst, and the other end is connected to the anode of the OLED element E1. The reset potential Vrst is given from the driver IC 134, for example.

A gate of the transistor M16 is connected to the S1 selection signal line 231, and the transistor M16 is controlled by the control signal S1. When the transistor M16 is turned on by the S1 control signal input to its gate from the scan driver 131, it applies the reset potential Vrst transmitted by the power supply line 242 to the anode of the OLED element E1.

In addition, the transistor M16 has a function of supplying the reset potential Vrst to the anode of the OLED element E1 and bypassing the current flowing from the power supply PVDD through M11 and M15 during the reset period to prevent leakage light emission.

The transistor M12 is a switch transistor for writing a voltage for threshold compensation of the drive transistor M11 to the storage capacitor C10, and is a transistor for resetting the gate potential of the drive transistor M11. The source and drain of the transistor M12 connect the gate and drain of the drive transistor M11. Therefore, when the transistor M12 is ON, the driving transistor M11 is in a diode-connected state.

The transistor M14 is a switch transistor for writing a voltage for threshold compensation of the driving transistor M11 to the storage capacitor C10. The transistor M14 controls whether or not the reference potential Vref is supplied to the holding capacitor C10. One end of the source/drain of the transistor M14 is connected to the power supply line 202 that transmits the reference potential Vref, and the other end is connected to one end of the capacitor C11. The gate of the transistor M14 is connected to the S1 selection signal line 231, and the transistor M14 is controlled by the control signal S1 input from the scanning driver 131 to the gate.

Transistors M12, M16 and M14 are controlled by control signal S1. Therefore, these transistors M12, M16 and M14 are turned on/off at the same time. While these are in the ON state, the emission control transistor M15 is turned ON, and after the gate potential of the drive transistor M11 and the potential of the storage capacitor C10 are reset, the emission control transistor M15 is turned OFF. When transistors M12 and M14 are ON, transistor M11 forms a diode-connected transistor. Between the power supply potential PVDD and the reference potential Vref, a threshold compensation voltage is written to the holding capacitor C10.

The transistor M13 is a switch transistor for selecting a pixel circuit to supply a data signal and writing a data signal (data signal voltage) to the storage capacitor C10. One end of the source/drain of the transistor M13 is connected to the data line 237 that transmits the data signal Vdata, and the other end is connected to the storage capacitor C10. More specifically, one end of the source/drain of the transistor M13 is connected to one end of the capacitor C11.

A gate of the transistor M13 is connected to an S2 selection signal line 232 that transmits a control signal S2 that selects a pixel circuit row to write a data signal. The transistor M13 is controlled by a control signal S2 supplied from the scan driver 131. FIG. When the transistor M13 is ON, the transistor M13 applies the data signal Vdata supplied from the driver IC 117 through the data line 237 to the holding capacitor C10.

FIG. 3 shows an example of a timing chart of signals for controlling the pixel circuit 107 shown in FIG. FIG. 3 shows a timing chart for writing the threshold compensation voltage of the drive transistor M11 and the data signal Vdata to the pixel circuits of the N-th pixel circuit row. Specifically, FIG. 3 shows the selection signals S1_N and S2_N for the N-th pixel circuit row to which the data signal Vdata is written, the emission control signal Em_N for the N-th pixel circuit row, and the (N−6)-th pixel FIG. 10 shows a time change of a circuit row selection signal S2_N−6 in one frame. FIG. FIG. 3 shows changes in signal potential level. The selection signal is one of control signals and is also called a scanning signal. The selection signal S1 is the first selection signal, and the selection signal S2 is the second selection signal.

In the timing chart of FIG. 3, the 1H period is the period during which the data signal Vdata is written to the pixel circuit, and the period during which the selection signal S2 is Low. The threshold compensation period is greater than or equal to 1H, and is 5H in the example of FIG.

At time T1, the selection signal S1_N changes from High to Low. Transistors M12, M14 and M16 are turned ON in response to the change in selection signal S1_N. At time T1, the light emission control signal Em_N is Low, so the transistor M15 is ON.

Since the transistors M12 and M14 to M16 are ON, the reset potential Vrst is applied to the anode of the OLED element E1 and to the gate of the drive transistor M11. At time T2, the emission control signal Em_N changes from Low to High. Time T1 to T2 is a reset period of the gate voltage of the driving transistor M11 and the holding capacitor C10.

The potential levels of the signals S1_N, S2_N, and Em_N are maintained from time T2 to time T3. Transistors M12, M14 and M16 are ON and the others including transistor M15 are OFF. During the period from time T2 to time T3, the threshold compensation voltage is written to the storage capacitor C10. A period from time T2 to time T3 is a threshold compensation period, and its length is 5H.

At time T3, the selection signal S2_N changes from High to Low. The selection signal S1_N changes from Low to High. In response to the change in select signal S1_N, transistors M12, M14 and M16 are turned off. After time T3, the selection signal S1_N is maintained at High.

Also, the transistor M13 is turned on from off in response to the change of the selection signal S2_N. This starts the writing of the data signal Vdata to the holding capacitor C10. At time T4, the selection signal S2_N changes from High to Low. As a result, the transistor M13 is turned off from ON, and data writing to the N-th pixel circuit row is completed. Time T3 to T4 is a data writing period to the N-th pixel circuit row, and its length is 1H. After time T4, the selection signal S2_N is maintained at High.

At time T4, the emission control signal Em_N changes from High to Low. This causes the transistor M15 to change from OFF to ON. As a result, a driving current is applied to the OLED element E1, and the OLED element starts to emit light.

FIG. 4 schematically shows the relationship between the threshold compensation period and the data write period in four consecutive pixel circuit rows. In each pixel circuit row, a data write period follows the threshold compensation period. The lengths of the data write period and the threshold compensation period are common to the pixel circuit rows. In the example shown in FIGS. 3 and 4, the length of the data write period is 1H and the length of the threshold compensation period is (q−1)*H. q is an integer of 2 or more. For better threshold compensation, q is set to an integer of 3 or greater. q is 6 in the example described with reference to FIG.

The length of the threshold compensation period changes according to changes in the length of the selection signal S1_N. As described above, the period during which the selection signal S1_N is low is qH, and the threshold compensation period is (q-1)*H. The OLED display 10 can dynamically change q to obtain the appropriate threshold compensation period. As will be described later, the length of the threshold compensation period may not be an integral multiple of the 1H period.

As shown in FIG. 4, data signals are sequentially written to the pixel circuit rows. The data write period for each pixel circuit row starts immediately after the previous data write period ends, and the data write periods for different pixel circuit rows do not overlap. The threshold compensation period overlaps part of the immediately preceding threshold compensation period and the data write period. The threshold compensation period may overlap with the data writing period of several pixel circuit rows from the immediately preceding stage.

In the following, a method for dynamically varying the pixel threshold compensation period is described. The threshold compensation period that minimizes luminance variations within the display area 125 varies according to the luminance of the display area 125 . FIG. 5 shows the relationship between the average luminance of a video frame and the optimum threshold compensation period for different pixel circuits. FIG. 5 shows analysis results of PCA (Principal Component Analysis) simulation.

In the graph of FIG. 5, the horizontal axis indicates the average luminance value of the pixels represented by the image frame, and the vertical axis indicates the optimal length of the threshold compensation period. More specifically, the horizontal axis indicates the average value of luminance represented by the gradation level, and the vertical axis indicates the threshold compensation period in multiples of the 1H period. A 1H period is 4.2 μs. A pixel may display one color at different luminance values. Typically each pixel displays a red, blue or green dot and is sometimes called a sub-pixel.

FIG. 5 shows the analysis results of three different pixel circuit examples. The 7T1C circuit is composed of seven transistors and one capacitive element, and the 6T2C_D pixel circuit and the 6T2C_S pixel circuit are both composed of six transistors and two capacitive elements, and the connection of the components is different. The pixel circuit shown in FIG. 2 is a 6T2C_D pixel circuit.

As shown in FIG. 5, in any pixel circuit, the optimal length of the threshold compensation period can vary according to the luminance value of the display area 125. FIG. According to the research of the inventors, in addition to the average luminance of the display area, the optimum threshold compensation period is determined for changes in various statistical values of the luminance of the display area 125, such as the mode luminance value and the average luminance of a specific color. changes.

The OLED display device 10 according to one embodiment herein dynamically changes the threshold compensation period in the display area 125 during image display. A period during which an image is displayed is a period during which an image composed of continuous image frames is displayed.

For example, OLED display 10 updates the threshold compensation period every video frame or every predetermined number of video frames. OLED display 10 calculates a predetermined statistic of the brightness of the pixels represented by a video frame and determines the threshold compensation period for that video frame or a subsequent video frame based on that statistic. As a result, it is possible to reduce variations in luminance within the screen of the image being displayed and improve the image quality.

FIG. 6 illustrates an example functional configuration of an OLED display 10 that dynamically varies the threshold compensation period, according to one embodiment herein. The OLED display device 10 includes a luminance data calculator 410 and a pulse width controller 400 . The luminance data calculator 410 and the pulse width controller 400 can be included in the driver IC 134 or an external circuit (not shown), for example.

The luminance data calculator 410 receives image data from an external circuit. The luminance data calculator 410 includes a frame memory 411 . The video data is a sequence of video frames, and the luminance data calculation unit 410 stores the sequentially received video frames in the frame memory 411 . A luminance data calculation unit 410 calculates a statistical value of luminance indicated by a video frame. The statistical value calculation may be performed, for example, for each frame, or may be performed intermittently for some video frames.

The statistical value to be calculated may be, for example, average brightness, mode brightness, maximum brightness, or minimum brightness. The average luminance may be, for example, the average luminance of all or part of the pixels in the display area 120, or the average luminance of all or part of the pixels of a specific color. The most frequent luminance may be the luminance value with the largest number of pixels among the luminance values of all pixels indicated by the video frame, or may be the most frequent luminance of a specific color or a specific partial area within the display area 125. . The maximum brightness or minimum brightness may be the maximum or minimum brightness value of all pixels represented by the image frame, or may be the maximum brightness or minimum brightness of a specific color or a specific partial area within the display area 125 .

The pulse width controller 400 includes a compensation period pulse width calculator 401 , an SRAM 402 that is a volatile memory device, and a timing controller (TCON) 403 . The compensation period pulse width calculator 401 receives the luminance statistics of the video frame from the luminance data calculator 410 . The compensation period pulse width calculator 401 determines the threshold compensation period based on the received luminance statistics.

More specifically, the pulse width of the start pulse signal of the S1 selection signal that defines the threshold compensation period is determined. The threshold compensation period is represented by this pulse width. The pulse width calculator 401 can determine the threshold compensation period, for example, by referring to a lookup table or by calculation using a pre-implemented function. Data indicating the start pulse width, that is, data indicating the threshold compensation period is stored in the SRAM 402 .

A timing controller 403 controls the scan driver 131 , the emission driver 132 and the data driver 421 . The data driver 421 is included in the driver IC 134 and outputs a data signal corresponding to video data (video frame) to each data line. In FIG. 6, the multiplexer 136 and protection circuit 133 are omitted.

The timing controller 403 acquires video data from the frame memory 411 and also acquires data indicating the threshold compensation period (start pulse width) from the SRAM 402 . The timing controller 403 generates internal clock signals and start pulse signals to control the scan driver 131 , the emission driver 132 and the data driver 421 . Also, the timing controller 403 generates video data to be transmitted to the data driver 421 according to video data from the outside.

The timing controller 403 transmits video data (video frame), clock signal and start pulse signal (STH signal) to the data driver 421 . The data driver 421 operates according to the clock signal. The data driver 421 outputs a data signal indicating the luminance of each pixel in each pixel row indicated by the video data to the data line at the timing and period according to the STH signal.

The timing controller 403 transmits a clock signal and two start pulse signals (STV1 signal, STV3 signal) to the scanning driver 131 . Scan driver 131 includes two shift register circuits 431 and 432 . For example, the shift register circuit 431 outputs the S1 selection signal according to the received clock signal and STV1 signal. The shift register circuit 432 outputs the S2 selection signal according to the received clock signal and STV3 signal.

The STV1 and STV2 signals define the length of the low states of the S1 select and S2 select signals, respectively. As will be described later, the pulse width control section 400 can change the length of the threshold compensation period by changing the length of the Low state of the S1 selection signal.

The timing controller 403 transmits a clock signal and a start pulse signal (STV2 signal) to the emission driver 132 . The emission driver 132 includes a shift register circuit and outputs a light emission control signal (Em signal) according to the received clock signal and STV2 signal. The STV2 signal defines the length of the high state of the Em signal.

In one embodiment of the present specification, the pulse width control section 400 changes the length of the threshold compensation period by changing the length of the low state of the S1 selection signal. The length of the emission control signal Em is kept constant. FIG. 7 shows a timing chart of the S1 selection signal and the control signals that generate the S1 selection signal. A timing chart 601 shows the time change of the signal in the video frame 1, and a timing chart 602 shows the time change of the signal in the video frame 2 different from the video frame 1. FIG.

FIG. 7 shows temporal changes of the two clock signals (CK signal and CKB signal), the start pulse signal (STV1 signal), and the S1 selection signal. FIG. 7 shows, as an example, temporal changes of the S1 selection signals S1_1, S1_2, S1_3 and S1_4 for four consecutive pixel rows.

The S1 select signal is generated from two clock signals (CK and CKB) and the STV1 signal. The CK signal and CKB signal are generated by the scan driver 131 from the CKL signal from the timing controller 403 . The CK signal and the CKB signal have the same pulse width (low state length), and their phases are shifted by half a cycle.

As shown in FIG. 7, the pulse width of the start pulse signal (STV1 signal) of the S1 selection signal, that is, the length of the Low state of the STV1 signal, corresponds to the pulse width of the S1 selection signal, that is, the length of the Low state of the S1 selection signal. Define length. The shorter the pulse width of the S1 selection signal, the shorter the threshold compensation period, and the longer the pulse width of the S1 selection signal, the longer the threshold compensation period.

In the timing chart 601 of frame 1, the width from the first falling edge of the CKB signal to the last rising edge while the STV1 signal is Low is the pulse width (low period length) of the S1 selection signal. In frame 1, the pulse width of the S1 select signal corresponds to one pulse of the CKB clock signal.

The pulse of the S1 selection signal S1_1 for the first pixel row starts at the first falling edge of the CKB signal when the STV1 signal is Low. The scanning driver 131 starts outputting the S1 selection signals for the second and subsequent pixel rows in response to the falling edges of the CK clock signal and the CKB clock signal. The pulse width of the S1 selection signal for all pixel rows is common.

As in frame 1, in frame 2, the width from the first falling edge of the CKB signal to the last rising edge during the period when the STV1 signal is Low is the pulse width (low period length) of the S1 selection signal. Become. In the timing chart 602 of frame 2, the pulse width of the STV1 signal is longer than the pulse width of the STV1 signal in the timing chart 601 of frame 1 . Therefore, the pulse width of the S1 select signal in frame 2 is longer than the pulse width of the S1 select signal in frame 1 . In the example of FIG. 7, in frame 2, the pulse width of the S1 select signal corresponds to 3 pulses of the CKB clock signal.

The pulse of the S1 selection signal S1_1 for the first pixel row starts at the first falling edge of the CKB signal when the STV1 signal is Low. The scanning driver 131 starts outputting the S1 selection signals for the second and subsequent pixel rows in response to the falling edges of the CK clock signal and the CKB clock signal. The pulse width of the S1 selection signal for all pixel rows is common.

In the example shown in FIG. 7, the falling edge of the STV1 signal is synchronized with the frame period. The pulse width control section 400 changes the rising edge of the STV1 signal according to the brightness of the display area 125 indicated by the video frame. The start of the threshold compensation period is synchronized with the frame period and the end of the threshold compensation period is shifted forward or backward.

In the configuration examples described with reference to FIGS. 6 and 7, the scan driver 131 controls the pulse width of the S1 selection signal, that is, the threshold compensation period, according to the pulse width of the start pulse signal transmitted from the pulse width control unit 400. to decide. The pulse width control section 400 determines the pulse width of the start pulse signal based on the statistical value of the pixels in the display area 125 indicated by the video frame. As a result, more appropriate threshold compensation can be performed according to the luminance of the pixels in the display area 125, and variations in luminance within the display area 125 can be reduced.

The above example maintains the rising edge of the S1 selection signal and changes the falling edge to change the low period of the S1 selection signal. Another example may vary the rising edge of the S1 select signal and keep the falling edge. In this example, the rising edge of the light emission control signal Em changes according to the change of the rising edge of the S1 selection signal.

<Embodiment 2>
FIG. 8 illustrates an example functional configuration of an OLED display device 10 that dynamically varies the threshold compensation period, according to one embodiment herein. Differences from the configuration example shown in FIG. 6 will be mainly described below. The OLED display device 10 includes a pulse width control section 450 instead of the pulse width control section 400 shown in FIG. The luminance data calculator 410 may operate in the same manner as the configuration in FIG.

The pulse width controller 450 includes a timing controller (TCON) 451 , a trimming width calculator 452 and a trimming controller 453 . Unlike the configuration example shown in FIG. 6 , the timing controller (TCON) 451 generates the STV1 start pulse signal without referring to the luminance statistics of the video frame from the luminance data calculation section 410 . The pulse width of the STV1 start pulse signal is constant. Generation of other control signals is similar to the configuration example shown in FIG.

The trimming width calculator 452 acquires the luminance statistical value of the video frame from the luminance data calculator 410 . The trimming width calculator 452 determines the threshold compensation period based on the luminance statistics. Specifically, the trimming width calculator 452 determines the trimming width that defines the threshold compensation period. The trimming width represents the threshold compensation period. The trimming width calculator 452 transmits a trimming signal indicating the trimming width to the trimming controller 453 . The trimming width determination can be calculated using, for example, a lookup table or a predetermined function.

The trimming controller 453 acquires the STV1 start pulse signal from the timing controller and acquires the trimming signal from the trimming width calculator 452 . The trimming controller 453 trims the pulses of the STV1 start pulse signal according to the trimming signal. This shortens the pulse width of the STV1 start pulse signal.

FIG. 9 is a diagram schematically showing trimming of the STV1 start pulse signal by the trimming controller 453. As shown in FIG. An STV1 start pulse signal having a pulse width W1 is input to trimming controller 453 . The trimming controller 453 shortens the pulse width of the STV1 start pulse signal by the trimming width indicated by the trimming signal. The output STV1 start pulse signal has a pulse width W2. Pulse width W2 is shorter than pulse width W1 by a specified trimming width.

As described above, this configuration example adjusts the pulse width of the STV1 start pulse signal by trimming the STV1 start pulse signal from the trimming controller 453 . This eliminates the need to implement a function for adjusting the pulse width of the start pulse in the trimming controller 453 . A conventional trimming controller can be utilized. Note that the pulse width control section 450 may include a function of extending the pulse width of the start pulse signal instead of or in addition to the function of trimming the pulse width of the start pulse signal.

<Embodiment 3>
FIG. 10 illustrates an example functional configuration of an OLED display 10 that dynamically varies the threshold compensation period, according to one embodiment herein. Differences from the configuration example shown in FIG. 6 will be mainly described below. The OLED display device 10 includes a scan driver 475 instead of the scan driver 131 shown in FIG. Scan driver 475 includes shift register circuit 432 , selector circuit 476 and latch circuit 478 . Details of the scan driver 475 will be described later with reference to FIG.

The OLED display device 10 includes a pulse width control section 470 instead of the pulse width control section 400 shown in FIG. The luminance data calculator 410 may operate in the same manner as the configuration in FIG. The pulse width controller 470 includes a timing controller (TCON) 471 and a pulse width calculator 472 . The OLED display device 10 includes an emission driver 137 instead of the emission driver 132 shown in FIG.

As mentioned above, the shift register circuit 431 is omitted from the scan driver 475 shown in FIG. Therefore, the STV1 start pulse signal is omitted from the control signal shown in FIG. 6 generated and output by the timing controller (TCON) 471 . Other control signals (CLK, STV2, STV3, STH) generated by the timing controller 471 are the same as in the configuration example shown in FIG.

The pulse width calculator 472 acquires the luminance statistical value of the display area 125 indicated by the video frame from the luminance data calculator 410 . The pulse width calculator 472 determines the threshold compensation period based on the acquired luminance statistic. Specifically, the pulse width calculator 472 determines the pulse width of the STV1 start pulse signal that defines the threshold compensation period. As will be described later, the scan driver 475 outputs control signals to the selector circuit 476 . This control signal is referred to herein as a selector signal.

The selector signal selects one of the control terminals of selector circuit 476, as described below. The scan driver 475 outputs an S1 selection signal with a pulse width corresponding to the selected control terminal. By selecting different control terminals, S1 selection signals with different pulse widths are generated. The pulse width calculator 472 can determine the threshold compensation period according to the luminance statistic by determining the control terminal to be selected from the selector circuit 476 based on the obtained luminance statistic.

A SET signal for each pixel circuit row, which will be described later, is transmitted from the scanning driver 475 to the emission driver 137 . The emission driver 137 generates a light emission control signal Em for each pixel circuit row based on the STV2 signal and the SET signal for each pixel circuit row.

FIG. 11 is a configuration diagram schematically showing the internal circuit configuration of the scan driver 475. As shown in FIG. The scanning driver 475 includes an initial stage shift register circuit (SR circuit) 432 , a subsequent stage selector circuit 476 and a final stage latch circuit 478 . The shift register circuit 432 includes a plurality of shift register units 481 connected in series. Only one shift register unit is indicated at 481 in FIG.

FIG. 11 shows the (N−4)th shift register unit 481 to the (N+2)th shift register unit 481 . N is an integer. These shift register units 481 correspond to the pixel circuit rows of the same stage. Each shift register unit 481 outputs the S2 selection signal to the S2 selection signal line 232 of the corresponding pixel row, and also outputs the same signal to the selector circuit 476 and one corresponding latch unit 300 .

According to the CK clock signal and the CKB clock signal, data bits move from the shift register unit 481 in the previous stage to the shift register unit 481 in the next stage. A shift register unit 481 holding data bits outputs a signal pulse.

Latch circuit 478 includes a plurality of latch units 300 . Only one latch unit is indicated at 300 in FIG. FIG. 11 shows the (N-2)th latch unit 300 to the (N+2)th latch unit 300 . These latch units 300 correspond to the pixel circuit rows of the same stage and output S1 selection signals to the S1 selection signal lines 231 of the corresponding pixel circuit rows.

The selector circuit 476 switches the connection between the shift register unit 481 and the latch unit 300 between the shift register circuit 432 and the latch circuit 478 . Selector circuit 476 has a switch matrix structure consisting of a plurality of switch transistors 483 . In FIG. 11, one switch transistor is indicated at 483 by way of example. In the example of FIG. 11, the switch transistor is a P-type TFT, but any type of switch transistor can be used.

In the configuration example of FIG. 11, the selector circuit 476 includes three switch columns each made up of switch transistor groups arranged in the vertical direction. The gate of one switch row is connected to control terminal A0, the gate of another switch row is connected to control terminal A1, and the gate of another switch row is connected to control terminal A2. All the switch transistors in each switch row are simultaneously turned on/off by a potential from one corresponding control terminal.

One of the source/drain of each switch transistor 483 connected to the control terminal A0 is connected to the k-th stage latch unit 300, and the other is connected to the (k-2)-th stage shift register unit 481. FIG. k is an integer. One of the source/drain of each switch transistor 483 connected to the control terminal A1 is connected to the k-th latch unit 300, and the other is connected to the (k-3)-th shift register unit 481. FIG. One of the source/drain of each switch transistor 483 connected to the control terminal A2 is connected to the k-th stage latch unit 300 and the other is connected to the (k-4)-th stage shift register unit 481 .

The switch transistors 483 of each switch column are connected to different latch units 300 and different shift register units, respectively. Three switch transistors 483 are connected to each latch unit 300 and belong to different switch columns.

Three switch transistors 483 are connected to each shift register unit 481 and belong to different switch columns. Each shift register unit 481 is connected to the corresponding latch unit 300 . The same number of stages is assigned to the connected shift register unit 481 and latch unit 300 unit. Each shift register unit 481 is further connected to the S2 selection signal line 232 of the corresponding pixel row.

The shift register circuit 432 includes a shift register unit 481 corresponding to each pixel circuit row. The shift register unit 481 corresponding to the pixel circuit row outputs signal pulses to the corresponding pixel circuit row and the two latch units 300 . The number of shift register units 481 is greater than the number of pixel circuit rows. Some shift register units 481 are not connected to pixel circuit rows and output signals only to the latch unit 300 .

Two input terminals of each latch unit 300 are supplied with output signals of shift register units 481 at different stages. Specifically, a signal from the corresponding shift register unit 481 is input to the RST terminal. A signal from the preceding shift register unit 481 selected by the selector circuit 476 is input to the SET terminal. The RST terminal is the first terminal and the SET terminal is the second terminal.

In the configuration example shown in FIG. 11, the output of the Nth stage shift register unit 481 is input to the RST terminal of the Nth stage latch unit 300 . The output of the (NL)th stage shift register unit 481 selected by the selector circuit 476 is input to the SET terminal of the Nth stage latch unit 300 . L is an integer of 2 or more, and is 2, 3 or 4 in the example of FIG.

FIG. 12 shows a configuration example of the latch unit 300. As shown in FIG. The latch unit 300 outputs the S1 selection signal to the Nth pixel circuit row. Latch unit 300 includes a SET terminal 301 and an RST terminal 302 to which signals are input, and a Q terminal 303 to output signals.

A selection signal S2_NL for the (NL)-th pixel circuit row from the shift register circuit 111 is input to the SET terminal 301 . A selection signal S2_N for the N-th pixel circuit row is input to the RST terminal 302 . The latch unit 300 outputs the selection signal S1_N from the Q terminal 303 to the S1 selection signal line 231 of the Nth pixel circuit row.

FIG. 13 shows the truth table of the latch unit 300. As shown in FIG. In the truth table of FIG. 13, L indicates a logical low level and H indicates a logical high level. In the configurations described with reference to FIGS. 3 and 7, the high potential level of the S1 selection signal and the S2 selection signal corresponds to logic low, and the low potential level corresponds to logic high.

The Q output is low when the SET input is low and the RST input is low. When the SET input is H and the RST input is L, the Q output is H, and the Q output is held H even if the SET input changes thereafter. The Q output is low when the SET input is low and the RST input is high. The state where the SET input and the RST input are high is prohibited.

FIG. 14 shows a circuit configuration example of the latch unit 300. As shown in FIG. In the configuration example of FIG. 14, the latch unit 300 is composed of four transistors and one capacitive element. The four transistors M21-M24 are P-type transistors. Transistor M21 is in a diode-connected state and receives input from SET terminal 301 at its drain. Transistor M22 is connected between transistor M21 and a power supply applying power supply potential PVEE, and receives an input from RST terminal 302 at its gate.

The transistor M23 is connected between the power supply supplying the power supply potential PVDD and the Q terminal 303, and its gate is connected to the intermediate node between the transistors M21 and M22. Transistor M24 is connected between transistor M23 and a power supply providing power supply potential PVEE, and has its gate receiving RST input. Capacitive element Cb is connected between the gate of transistor M23 and Q terminal 303 . An intermediate node between transistors M23 and M24 is connected to Q terminal 303 .

11, the N-th shift register unit 481 includes the RST terminal of the N-th latch unit 300, the SET terminal of the (N+L)-th latch unit 300 selected by the selector circuit 476, and the N-th stage shift register unit 481. A signal pulse is simultaneously output to the S2 selection signal line 232 of the second pixel row.

The N-th latch unit 300 outputs the S1 selection signal to the N-th pixel circuit row. The N-th latch unit 300 starts to pulse the S1 selection signal in response to the signal pulse from the (NL)-th shift register unit 481, and responds to the signal pulse from the N-th shift register unit 481. Terminate the pulse accordingly.

When the control terminal A0, A1 or A2 is selected for the Nth stage S2 selection signal line 232 and the latch unit 300, the corresponding (N−2)th stage, (N−3)th stage or (N -4) The shift register unit of the stage is selected.

Stated more generally, the output of the Nth stage latch unit 300 is set by a pulse from the Kth stage shift register unit and reset by a signal pulse from the (K+p)th stage shift register unit. K is an integer and p is an integer of 2 or more. The threshold compensation period is (p-1)*H.

The output of the (N+q)th stage latch unit is set by a signal pulse from the (K+q)th stage shift register unit and reset by a signal pulse from the (K+q+p)th stage shift register unit. q is an integer of 1 or more. The pulse from latch unit 300 has a pulse width of p*H. Also, the pulse from the (N+q)th stage latch unit 300 has a time delay of q*H with respect to the pulse from the Nth stage latch unit 300 . The threshold compensation period is (p-1)*H.

In the above example, the value of p is selected from (2, 3, 4) by selecting one of the control terminals (A0, A1, A2) with the selector signal. That is, the shift register output corresponding to the selected p is selected. As described above, different pulse width S1 select signals are generated for different p, ie, different threshold compensation periods. A combination of selectable values of p is determined according to the design and does not have to consist of consecutive natural numbers.

FIG. 15 shows an example of a timing chart of signals controlling the pixel circuit 107 described with reference to FIGS. FIG. 15 shows a timing chart for writing the threshold compensation voltage of the driving transistor M11 and the data signal Vdata to the pixel circuits of the N-th pixel circuit row.

Specifically, FIG. 15 shows the selection signals S1_N and S2_N for the N-th pixel circuit row to which the data signal Vdata is written, the emission control signal Em_N for the N-th pixel circuit row, and the (N−6)-th pixel FIG. 10 shows a time change of a circuit row selection signal S2_N−6 in one frame. FIG. Select signal S2_N-6 is an example of a shift register unit output selected in selector circuit 476. FIG.

The rise of the light emission control signal Em_N synchronizes (coincides) with the rise of the SET signal of the latch unit 300 of the Nth stage. As described above, the emission driver 137 generates the emission control signal based on the input SET signal. In the example of FIG. 15, the selection signal S2_N-6 is the SET signal of the latch unit 300 of the Nth stage.

In the timing chart of FIG. 15, the 1H period is the period during which the data signal Vdata is written to the pixel circuit and the period during which the S2 selection signal is Low. The threshold compensation period is 1H or longer, and 5H in the example of FIG.

At time T1, the selection signal S2_N-6 changes from High to Low. The selection signal S1_N changes from High to Low in accordance with the change in the selection signal S2_N-6. Transistors M12, M14 and M16 are turned ON in response to the change in selection signal S1_N. At time T1, the light emission control signal Em_N is Low, so the transistor M15 is ON.

Since transistors M12, M14 to M16 are ON, reset potential Vrst is applied to the anode of OLED element E1 and to the gate of drive transistor M11. At time T2, the emission control signal Em_N changes from Low to High. Time T1 to T2 is a reset period of the gate voltage of the driving transistor M11. At time T2, the selection signal S2_N-6 also changes from Low to High. Times T1 to T2 are periods during which data signals are written to the (N−6)th pixel circuit row. The period from time T1 to T2 is 1H.

From time T2 to time T3, the potential levels of signals S1_N, S2_N, Em_N, and S2_N-6 are maintained. Transistors M12, M14 and M16 are ON and the others including transistor M15 are OFF. During the period from time T2 to time T3, the threshold compensation voltage is written to the storage capacitor C10. A period from time T2 to time T3 is a threshold compensation period, and its length is 5H.

At time T3, the selection signal S2_N changes from High to Low. As will be described later, the selection signal S1_N changes from Low to High in response to the change in the selection signal S2_N. In response to the change in select signal S1_N, transistors M12, M14 and M16 are turned off. After time T3, the selection signal S1_N is maintained at High.

In response to the change in selection signal S2_N, transistor M13 turns from OFF to ON. This starts the writing of the data signal Vdata to the holding capacitor C10. At time T4, the selection signal S2_N changes from High to Low. As a result, the transistor M13 is turned off from ON, and data writing to the N-th pixel circuit row is completed. Time T3 to T4 is a data writing period to the N-th pixel circuit row, and its length is 1H. After time T4, the selection signal S2_N is maintained at High.

At time T4, the emission control signal Em_N changes from High to Low. This causes the transistor M15 to change from OFF to ON. As a result, a driving current is applied to the OLED element E1, and the OLED element starts to emit light.

As understood from the description with reference to FIGS. 10 to 15, the shift register circuit 432 sequentially outputs pulses of the S2 selection signal to corresponding pixel circuit rows. The pulse width is 1H. Each latch unit 300 outputs an S1 selection signal to the corresponding pixel circuit row.

As described above, the N-th stage latch unit 300 receives the Low potential level (H logic level) pulse of the selected preceding stage selection signal S2_N-q at the SET terminal 301, and receives the selection signal from the Q terminal 303. S1_N is changed to the Low potential level. After that, the selection signal S2_N-q changes to the High potential level (L logic level), but the input S2_N to the RST terminal 302 is at the High potential level, and the selection signal S1_N from the Q terminal 303 is maintained at the Low potential level. be done.

After that, the latch unit 300 receives a Low potential level (H logic level) pulse of the selection signal S2_N of the N-th pixel circuit row at the RST terminal 302, and changes the selection signal S1_N from the Q terminal 303 to a High potential level ( L logic level). The pulse width of the S1_N signal output from the latch unit 300 is qH.

As described above, by using the selector circuit and the latch circuit, the S1 selection signal and the S2 selection signal can be generated from one shift register circuit. As a result, the area required by the circuit for generating the S1 selection signal and the S2 selection signal can be reduced.

In the above example, the emission driver 137 receives the SET signal generated within the scan driver 475 and generates the emission control signal Em along with the STV2 signal. In another example, the emission driver, like scan driver 475, may include a selector circuit and a latch circuit, which may be used to generate emission control signal Em.

In the above example, the threshold compensation period is changed by changing the fall of the S1 selection signal and the rise of the emission control signal Em. Another configuration example may change the threshold compensation period by fixing the emission control signal Em and changing the rise of the S1 selection signal. The rise of the S1 selection signal is controlled by the RST signal to the Nth stage latch unit.

<Embodiment 4>
FIG. 16 shows a configuration example of the trimming controller 453 . The trimming controller 453 can be implemented using the latch circuit shown in FIG. Thereby, the circuit area of the trimming controller 453 can be reduced. The circuit configuration of latch 300 shown in FIG. 16 is similar to the circuit configuration shown in FIG. 14, and input/output signals are different between them.

As shown in FIG. 16, the STV1 signal is input to SET terminal 301 . A trimming signal (STRIM signal) is input to the RST terminal 302 . The trimmed STV1 signal is output from Q terminal 303 .

FIG. 17 shows a truth table for the trimming controller 453 shown in FIG. Since the STV1 signal and the STRIM signal are input to the SET terminal 301 and the RST terminal 302, respectively, as described above, FIG. 17 shows them instead of the terminal names. In the truth table, L indicates a logical low level and H indicates a logical high level. High potential levels of the STV1 signal and the STRIM signal correspond to logic low, and low potential levels correspond to logic high.

FIG. 18 shows a timing chart of input/output signals of the trimming controller 453. As shown in FIG. At time T11, the STRIM signal changes from logic H level (potential L level) to logic L level (potential H level). After that, at time T12, the STV1 signal and the trimmed STV1 signal change from logic L level (potential H level) to logic H level (potential L level).

After that, at time T13, the STRIM signal changes from logical L level (potential H level) to logical H level (potential L level). Accordingly, the trimmed STV1 signal changes from logic H level (potential L level) to logic L level (potential H level). After that, at time T14, the STV1 signal changes from logical H level (potential L level) to logical L level (potential H level).

After passing the STV1 pulse, that is, after time T14, the STRIM signal may be either H or L (Don't Care). The STRIM signal may be set to a logical L level at an arbitrary timing before time T12 when the STV1 signal of the next frame is input.

<Embodiment 5>
A technique for reducing luminance fluctuations caused by changing the threshold compensation period (Vth compensation period) will be described below. FIG. 19 schematically shows the relationship between the data voltage to the pixel circuit and the driving current (Ioled) of the OLED element for different threshold compensation periods. The horizontal axis of the graph in FIG. 19 indicates the data voltage, and the vertical axis indicates the log value of the drive current.

As shown in FIG. 19, as a general property of an OLED pixel circuit with a Vth compensation function, the luminance (drive current level) corresponding to the applied data voltage varies with the threshold compensation period. Specifically, the longer the threshold compensation period, the lower the luminance. This tendency is particularly pronounced at low luminance levels.

Therefore, when the threshold compensation period is changed, the change in the data voltage-luminance characteristic can be reduced by correcting the data voltage. One embodiment herein provides a data voltage correction table that indicates grayscale voltages for each of the threshold compensation periods that may be selected.

FIG. 20 shows a configuration example of a data voltage correction table. The data voltage correction table shows different threshold compensation periods and corresponding gradation voltages for each threshold compensation period. A grayscale voltage is a data voltage corresponding to each grayscale level. In the configuration example shown in FIG. 20, grayscale levels from 1 to 255 are defined, and data voltages are shown for each combination of grayscale level and threshold compensation period.

The control circuit of the OLED display device 10 determines the output data voltage from the data driver 421 based on the gradation level indicated by the video data and the threshold compensation period with reference to the data voltage correction table. As a result, it is possible to reduce luminance changes due to changes in the threshold compensation period.

FIG. 21 shows a functional configuration example of an OLED display device having a data voltage correction function according to the threshold compensation period. Differences from the configuration example shown in FIG. 8 will be mainly described below. A control flag signal for selecting the optimum threshold compensation period determined by the trimming width calculator 452 is transferred to the data driver 421 via the timing controller 451 .

The data driver 421 holds the data voltage correction table described with reference to FIG. The data driver 421 selects a gradation voltage curve for the threshold compensation period indicated by the control flag signal from a plurality of gradation voltage curves indicated by the data voltage correction table. The data driver 421 determines the data voltage (grayscale voltage) corresponding to the grayscale level calculated from the video data according to the selected grayscale voltage curve.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above-described embodiments within the scope of the present disclosure. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

10 OLED display device 100 TFT substrate 125 display area 131 scanning drivers 132, 137 emission driver 134 driver IC
300 latch unit 400 pulse width controller 401 compensation period pulse width calculator 402 SRAM
403, 471 timing controller 410 luminance data calculation unit 411 frame memory 431, 432 shift register circuit 450 pulse width control unit 452 trimming width calculation unit 453 trimming controller 470 pulse width control unit 472 pulse width calculation unit 475 scanning driver 476 selector circuit 478 latch circuit 481 shift register unit 483 switch transistor

Claims (13)

A display device,
a plurality of pixels;
a control circuit for controlling luminance of the plurality of pixels;
including
each pixel of the plurality of pixels,
a light emitting element;
a pixel circuit that controls light emission of the light emitting element;
including
The pixel circuit is
a drive transistor that supplies a current to the light emitting element;
a storage capacitor that holds a voltage that controls the current supplied from the drive transistor to the light emitting element;
including
The control circuit is
determining a luminance statistic of pixels represented by a video frame by a predetermined method;
determining a threshold compensation period of the storage capacitance for the drive transistor based on the statistics;
controlling the pixel circuit based on the threshold compensation period;
display device. The display device according to claim 1,
The control circuit is
a shift register circuit that outputs a selection signal for sequentially selecting pixel rows from the plurality of pixels;
a pulse width calculator;
memory;
a timing controller;
including
the pulse width of the select signal defines the length of the threshold compensation period in the selected pixel row;
The pulse width calculation unit determines a pulse width of the selection signal that defines the threshold compensation period based on the statistical value, stores data indicating the pulse width in the memory,
The timing controller reads data indicating the pulse width from the memory, and transmits a start pulse signal having a pulse width corresponding to the data indicating the pulse width to the shift register circuit,
The shift register circuit outputs the selection signal with a pulse width corresponding to the pulse width of the start pulse signal.
display device. The display device according to claim 1,
The control circuit is
a shift register circuit that outputs a selection signal for sequentially selecting pixel rows from the plurality of pixels;
a timing controller;
a trimming controller;
a trimming width calculator;
including
the pulse width of the select signal defines the length of the threshold compensation period in the selected pixel row;
The timing controller outputs a start pulse signal having a constant pulse width,
The trimming width calculation unit determines a trimming width based on the statistical value,
The trimming controller trims the pulse width of the start pulse signal output from the timing controller based on the trimming width,
the shift register circuit outputs the selection signal with a pulse width corresponding to the trimmed pulse width;
display device. The display device according to claim 1,
The control circuit is
a shift register circuit including coupled shift register units for sequentially outputting second selection signals to a plurality of pixel rows formed by the plurality of pixels;
a latch circuit including a latch unit corresponding to each of the plurality of pixel rows;
a selector circuit between the latch circuit and the shift register circuit;
a pulse width calculator;
including
each shift register unit outputs the second selection signal to one pixel row, a first terminal of a latch unit corresponding to the one pixel row, and the selector circuit;
The pulse width calculation unit transmits a selector signal corresponding to the threshold compensation period to the selector circuit,
the selector circuit outputs the output of the shift register unit selected according to the selector signal to a second terminal of each latch unit;
each latch unit outputs a first selection signal having a pulse width corresponding to inputs to the first terminal and the second terminal to the corresponding pixel row;
the pulse width of the first select signal defines the length of the threshold compensation period in the selected pixel row;
display device. The display device according to claim 1,
The statistical value is any one of an average value, a mode value, a maximum value, or a minimum value;
display device. The display device according to claim 1,
the control circuit determines a data voltage for each grayscale level according to the threshold compensation period;
display device. The display device according to claim 3,
the trimming controller includes a second latch unit;
the second latch unit includes a third terminal and a fourth terminal;
The timing controller inputs the start pulse signal to the third terminal,
the trimming width calculation unit inputs a trimming signal indicating a trimming width to the fourth terminal;
The second latch unit outputs a start pulse signal whose pulse width is trimmed based on the trimming width.
display device. A display device control method comprising:
The display device includes a plurality of pixels,
each pixel of the plurality of pixels includes a light emitting element; a pixel circuit for controlling light emission of the light emitting element;
including
The pixel circuit includes a drive transistor that supplies a current to the light emitting element, and a storage capacitor that holds a voltage that controls the current supplied by the drive transistor to the light emitting element,
The control method is
determining a luminance statistic of pixels represented by a video frame by a predetermined method;
determining a threshold compensation period of the storage capacitance for the drive transistor based on the statistics;
controlling the pixel circuit based on the threshold compensation period;
control method. The control method according to claim 8,
The display device includes a memory and a shift register circuit that outputs a selection signal for sequentially selecting pixel rows from the plurality of pixels,
the pulse width of the select signal defines the length of the threshold compensation period in the selected pixel row;
The control method is
determining a pulse width of the selection signal based on the statistical value, storing data indicating the pulse width in the memory;
reading data indicating the pulse width from the memory, transmitting a start pulse signal having a pulse width corresponding to the data indicating the pulse width to the shift register circuit, and outputting a pulse of the start pulse signal from the shift register circuit; outputting the selection signal with a pulse width corresponding to the width;
control method. The control method according to claim 8,
The display device includes a shift register circuit that outputs a selection signal for sequentially selecting pixel rows from the plurality of pixels,
the pulse width of the select signal defines the length of the threshold compensation period in the selected pixel row;
The control method is
Outputting a start pulse signal with a constant pulse width,
determining a trimming width based on the statistics;
trimming the pulse width of the start pulse signal based on the trimming width;
inputting the start pulse signal with the trimmed pulse width to the shift register circuit, and outputting the selection signal with a pulse width corresponding to the trimmed pulse width from the shift register circuit;
control method. The control method according to claim 8,
The display device
a shift register circuit including coupled shift register units for sequentially outputting second selection signals to a plurality of pixel rows formed by the plurality of pixels;
a latch circuit including a latch unit corresponding to each of the plurality of pixel rows;
a selector circuit between the latch circuit and the shift register circuit;
a pulse width calculator;
including
The control method is
each shift register unit outputs the second selection signal to one pixel row, a first terminal of a latch unit corresponding to the one pixel row, and the selector circuit;
The pulse width calculation unit transmits a selector signal corresponding to the threshold compensation period to the selector circuit,
the selector circuit outputs the output of the shift register unit selected according to the selector signal to a second terminal of each latch unit;
Each latch unit outputs a first selection signal having a pulse width corresponding to inputs to the first terminal and the second terminal to the corresponding pixel row, and the pulse width of the first selection signal is the threshold compensation period. to define
control method. The control method according to claim 8,
The statistical value is one of an average value, a mode value, a maximum value, and a minimum value,
control method. A control method according to claim 8,
determining a data voltage for each grayscale level according to the threshold compensation period;
control method.

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