JP2023031643A - Wiring substrate and manufacturing method for the same - Google Patents

Abstract

An object of the present invention is to improve the reliability of a wiring board.
A wiring board (1) includes an insulating layer (2), a conductor pattern (3) formed on an upper surface (7) of the insulating layer (2), a conductor pattern (4) formed on a lower surface (8) of the insulating layer (2), and an insulating layer (2). an electrode 6 formed in the opening. The electrode 6 electrically connects the conductor pattern 3 and the conductor pattern 4 . The electrode 6 is formed integrally with the conductor pattern 3 , and the surface of the electrode 6 is recessed with respect to the surface of the conductor pattern 3 on the upper surface 7 side of the insulating layer 2 .
[Selection drawing] Fig. 1

Description

The present invention relates to a wiring board and its manufacturing method.

Various formation methods have been proposed for circuit formation on wiring boards. Among them, for example, in the additive method, a multilayer board is formed by forming a copper pattern in a necessary place and laminating them via an insulating layer. By the way, in a wiring pattern formed in multiple layers, it is necessary to provide a through hole between layers having a front and back relationship to electrically conduct via filling. Moreover, in these wiring patterns and via fillings, a method of forming a seed layer by electroless plating of copper and then laminating copper by electroplating is generally performed.

On the other hand, recent wiring boards are used for high-speed signal transmission, including 5G, and the insulating layers used accordingly have a lower dielectric constant than conventional wiring boards using FR4 materials. Demand for materials is increasing.

Japanese Patent Application Laid-Open No. 2018-195754 (Patent Document 1) describes a technique related to an interlayer insulating film through electrode.

Japanese Patent Application Laid-Open No. 2019-62113 (Patent Document 2) describes a technique related to a method for manufacturing a wiring layer.

JP 2018-195754 A JP 2019-62113 A

In order to realize a low dielectric constant insulator, for example, there is a material in which SiO ₂ (silicon oxide, silica) is contained as a filler in an epoxy-based base material. In order to establish electrical continuity between the wirings formed on the front and back sides of the insulating layer using this insulating material, it is necessary to form vias at key points to establish electrical continuity between the front and back sides. For example, a through hole is formed in the insulating layer. Here, since the formation of the through hole in the insulating layer by the laser beam is a process accompanied by instantaneous high heat, the epoxy serving as the substrate sublimates on the side wall surface of the through hole and becomes rich in SiO ₂ . If an attempt is made to form a copper seed layer on the side wall of the through-hole in this state by electroless plating, the following concern arises. That is, it is necessary to deposit copper on SiO ₂ by electroless plating, but since the dielectric constant of SiO ₂ itself is about 4, it is classified as a Low-k material. Since it becomes difficult to generate functional groups on SiO ₂ that allow palladium to adhere to the palladium layer by chemical bonding, copper, which is supposed to be a seed layer, cannot be formed. Moreover, even if it can be formed, the adhesion to the side wall surface of the through hole is poor, resulting in a reliability problem.

Furthermore, after the semiconductor element is mounted on the wiring board after the wiring is formed by a technique such as wire bonding or face-down, it is sealed with an epoxy resin. At this time, especially for high-power applications, high heat is involved, and as a result of repeated expansion and contraction, there is concern that the wiring board and sealing resin may separate due to the difference in linear expansion coefficient between each member. be done.

2. Description of the Related Art It is desired to improve the reliability of wiring boards and electronic devices manufactured using the wiring boards.

Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

According to one embodiment, a wiring board includes an insulating layer having an opening, a first conductor pattern formed on a first main surface of the insulating layer, and a second main surface of the insulating layer. and an electrode formed in the opening for electrically connecting the first conductor pattern and the second conductor pattern. The electrode is formed integrally with the second conductor pattern. On the second main surface side, the surface of the electrode is recessed with respect to the surface of the second conductor pattern.

According to one embodiment, a wiring board manufacturing method includes (a) a first main surface and a second main surface, an opening penetrating between the first main surface and the second main surface; (b) forming a second conductor pattern on the second main surface of the insulating layer and forming the second conductor pattern in the opening; forming an electrode in the . The electrode electrically connects the first conductor pattern and the second conductor pattern. The electrode is formed integrally with the second conductor pattern, and the surface of the electrode is recessed with respect to the surface of the second conductor pattern.

According to one embodiment, it is possible to provide a highly reliable wiring board.

1 is a cross-sectional view of a main part of a wiring board according to one embodiment; FIG. FIG. 4 is a cross-sectional view of a main part during a manufacturing process of a wiring board according to one embodiment; FIG. 3 is a cross-sectional view of the main part of the wiring board during the manufacturing process following FIG. 2 ; FIG. 4 is a cross-sectional view of the main part of the wiring board during the manufacturing process following FIG. 3 ; FIG. 5 is a cross-sectional view of the main part of the wiring board during the manufacturing process following FIG. 4 ; FIG. 6 is a cross-sectional view of the main part during the manufacturing process of the wiring board continued from FIG. 5 ; FIG. 7 is a fragmentary cross-sectional view of the wiring board during the manufacturing process following FIG. 6 ; FIG. 3 is a cross-sectional view of a main part showing a wiring board of a study example; FIG. 9 is a cross-sectional view of a main part showing a state in which an insulator is formed on the wiring board of the study example shown in FIG. 8 ; 2 is a cross-sectional view of a main part showing a state in which an insulator is formed on the wiring board shown in FIG. 1; FIG. FIG. 11 is a cross-sectional view of a main part during a manufacturing process of a wiring board according to another embodiment; FIG. 12 is a cross-sectional view of the main part during the manufacturing process of the wiring board continued from FIG. 11; 13 is a cross-sectional view of the main part of the wiring board during the manufacturing process following FIG. 12; FIG. 14 is a cross-sectional view of the main part of the wiring board during the manufacturing process following FIG. 13; FIG. FIG. 11 is a cross-sectional view of a main part during a manufacturing process of a wiring board according to another embodiment; FIG. 16 is a cross-sectional view of the main part during the manufacturing process of the wiring board continued from FIG. 15; FIG. 17 is a fragmentary cross-sectional view of the wiring board during the manufacturing process following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the wiring board during the manufacturing process following FIG. 17 ;

Hereinafter, embodiments will be described in detail based on the drawings. In addition, in all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
<Regarding the structure of the wiring board>
The structure of a wiring board 1 according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view of a wiring board 1 of this embodiment.

A wiring board (printed board) 1 includes an insulating layer 2, a conductor pattern (conductor layer) 3 formed on an upper surface (principal surface) 7 of the insulating layer 2, and a lower surface (principal surface) 8 of the insulating layer 2. It has a formed conductor pattern (conductor layer) 4 and an electrode (via electrode, through electrode) 6 formed in an opening (through hole) 5 of the insulating layer 2 .

Here, the conductor pattern 4 formed on the lower surface 8 of the insulating layer 2 is actually formed on a support plate (corresponding to a support plate 21 described later) using an additive method or the like. structure is not shown.

The opening 5 is formed so as to penetrate the upper surface 7 and the opposite lower surface 8 of the insulating layer 2 having a substantially rectangular parallelepiped cross section. At this time, the opening 5 is formed on the conductor pattern 4 arranged on the lower surface 8 of the insulating layer 2, and the conductor pattern 4 is electrically connected to the conductor pattern 3 formed on the upper surface 7 via the electrode 6. . At this time, the upper surface 7 side of the electrode 6 is provided with a recessed portion 9 . Specifically, it is desirable that the bottom of the recess 9 be lower than the upper surface 7 of the insulating layer 2 .

Further, in order to configure the wiring board 1 as a semiconductor unit, a semiconductor element (semiconductor chip) can be mounted as a bare chip on the upper surface 7 and connected by bump connection or wire bonding. Bare chips, connection forms, etc. are not shown.

A specific description will be given below.

The insulating layer 2 functions as an insulating substrate layer (base layer). An upper surface 7 and a lower surface 8 of the insulating layer 2 are main surfaces located on opposite sides of each other. A wiring, a terminal, an electrode, or the like is formed by the conductor pattern 3 on the upper surface 7 of the insulating layer 2 , that is, on the upper surface side of the wiring substrate 1 . In addition, wiring, terminals, electrodes, and the like are formed on the lower surface 8 of the insulating layer 2 , that is, on the lower surface side of the wiring board 1 by the conductor pattern 4 .

The electrodes 6 are provided to electrically connect the conductor pattern 3 on the upper surface side of the wiring board 1 and the conductor pattern 4 on the lower surface side of the wiring board 1 . For example, in the case of FIG. 1, the conductor pattern 3 on the upper surface side of the wiring board 1 includes conductor patterns 3a and 3b, and the conductor pattern 4 on the lower surface side of the wiring board 1 includes conductor patterns 4a, 4b, and 4c. The conductor pattern 3 a on the upper surface side of the wiring board 1 and the conductor pattern 4 a on the lower surface side of the wiring board 1 are electrically connected via the electrode 6 . Electrode 6 is provided in opening 5 formed in insulating layer 2 . The opening 5 is a through hole formed in the insulating layer 2 and penetrates between the upper surface 7 and the lower surface 8 of the insulating layer 2 . The insulating layer 2 is preferably an insulating layer with a low dielectric constant, and more preferably has a dielectric constant equal to or lower than that of silicon oxide (SiO ₂ ). The insulating layer 2 has a low dielectric constant, for example, by containing a silicon oxide filler (silica filler).

The conductor pattern 4 on the lower surface side of the wiring board 1 is made of a conductive layer, preferably a metal layer, more preferably a copper (Cu) layer. The conductor pattern 3 on the upper surface side of the wiring board 1 is made of a conductive layer, preferably a metal layer, more preferably a copper (Cu) layer. The conductor pattern 3 is composed of a seed layer 11 and a plating layer (electroplating layer) 12 formed on the seed layer 11 . That is, the conductor pattern 3 on the upper surface side of the wiring board 1 is made of a laminated film of the seed layer 11 and the plated layer 12 on the seed layer 11 . The plating layer 12 is an electrolytic plating layer formed by an electrolytic plating method, and is made of metal. The seed layer 11 functions as a seed layer when forming the plating layer 12 by electroplating. The seed layer 11 is preferably made of copper (Cu) or silver (Ag), and the plating layer 12 is preferably made of copper (Cu). Thus, seed layer 11 is preferably a copper or silver seed layer and plating layer 12 is preferably a copper plating layer.

The electrodes 6 in the openings 5 of the insulating layer 2 are formed in the same process as the conductor pattern 3 on the upper surface side of the wiring board 1, and are formed integrally with the conductor pattern 3 on the upper surface side of the wiring board 1. . For example, in the case of FIG. 1, the electrode 6 in the opening 5 of the insulating layer 2 is formed integrally with the conductor pattern 3a on the upper surface side of the wiring board 1. As shown in FIG. Therefore, the electrode 6 in the opening 5 of the insulating layer 2 also consists of the seed layer 11 and the plated layer 12 formed on the seed layer 11 . In the layered film of the seed layer 11 and the plating layer 12 on the seed layer 11, the portion formed (arranged) on the upper surface 7 of the insulating layer 2 is the conductor pattern 3, and the seed layer 11 and the seed layer 11 are formed. The electrode 6 is formed (arranged) in the opening 5 in the layered film with the upper plated layer 12 . That is, the conductor pattern 3 is composed of a seed layer 11 formed (arranged) on the upper surface 7 of the insulating layer 2 and a plated layer 12 thereon. It consists of a seed layer 11 and a plated layer 12 which are formed (arranged) on the surface. In the case of FIG. 1, the seed layer 11 forming the electrode 6 in the opening 5 of the insulating layer 2 is integrally formed with the seed layer 11 forming the conductor pattern 3a on the upper surface 7 of the insulating layer 2. Moreover, the plating layer 12 forming the electrode 6 in the opening 5 of the insulating layer 2 is integrally formed with the plating layer 12 forming the conductor pattern 3 a on the upper surface 7 of the insulating layer 2 .

On the lower surface 8 of the insulating layer 2, the opening 5 of the insulating layer 2 is covered with the conductor pattern 4 (the conductor pattern 4a in the case of FIG. 1). That is, a conductor pattern 4 (a conductor pattern 4 a in the case of FIG. 1) is formed on the lower surface 8 of the insulating layer 2 so as to cover the opening 5 . Therefore, the bottom surface of the opening 5 of the insulating layer 2 is formed by the conductor pattern 4 (the conductor pattern 4a in the case of FIG. 1) covering the opening 5. As shown in FIG. In the opening 5 of the insulating layer 2, the seed layer 11 constituting the electrode 6 is formed on the side walls (side surfaces) of the opening 5 in the insulating layer 2 and on the bottom surface of the opening 5 in the insulating layer 2 (that is, the insulating layer 2). is formed on the conductor pattern 4 covering the opening 5 on the lower surface 8 side of the . A plated layer 12 forming the electrode 6 is formed on the seed layer 11 within the opening 5 of the insulating layer 2 .

The electrode 6 (more specifically, the seed layer 11 forming the electrode 6) is in contact with the conductor pattern 4a covering the opening 5, thereby being electrically connected to the conductor pattern 4a. Further, the electrode 6 (more specifically, the seed layer 11 and the plating layer 12 that make up the electrode 6) is formed on the conductor pattern 3a (more specifically, the seed layer that makes up the conductor pattern 3a) on the upper surface 7 of the insulating layer 2. 11 and the plating layer 12), it is electrically connected to the conductor pattern 3a. Therefore, the conductor pattern 3a on the upper surface 7 of the insulating layer 2 and the conductor pattern 4a on the lower surface 8 of the insulating layer 2 are electrically connected through the electrode 6 in the opening 5 of the insulating layer 2. be. Thereby, the conductor pattern 3 on the upper surface side of the wiring board 1 and the conductor pattern 4 on the lower surface side of the wiring board 1 can be electrically connected as required, and the electrodes in the openings 5 of the insulating layer 2 can be electrically connected. 6 can function as an electrode (via electrode or through electrode) that electrically connects the conductor pattern 3 on the upper surface side of the wiring board 1 and the conductor pattern 4 on the lower surface side of the wiring board 1 .

As shown in FIG. 1, on the upper surface 7 side of the insulating layer 2, the surface (upper surface) of the electrode 6 in the opening 5 is formed integrally with the conductor pattern 3 (in the case of FIG. 1, It is recessed with respect to the surface (upper surface) of the conductor pattern 3a). Specifically, the surface of the plating layer 12 forming the electrode 6 and the conductor pattern 3a integrally formed therewith is recessed at a position overlapping the opening 5 in plan view, and overlaps the opening 5 in plan view. It has a recessed portion (recess) 9 at a position. Here, the surface of the conductor pattern 3 corresponds to the surface of the plating layer 12 forming the conductor pattern 3 , and the surface of the electrode 6 corresponds to the surface of the plating layer 12 forming the conductor pattern 3 . Also, the surface of the plating layer 12 corresponds to the surface of the plating layer opposite to the side in contact with the seed layer 11 . A plan view corresponds to a plane view substantially parallel to the upper surface 7 or the lower surface 8 of the insulating layer 2 .

Moreover, it is preferable that the depth of the recessed part 9 is deep to some extent. Specifically, it is preferable that the bottom of the recess 9 be lower in height than the upper surface 7 of the insulating layer 2 (height in the thickness direction of the wiring substrate 1). That is, on the side of the upper surface 7 of the insulating layer 2 , the surface of the electrode 6 preferably has a portion whose height position is lower than the upper surface 7 of the insulating layer 2 . From another point of view, it is preferable that a part of the surface of the electrode 6 (the bottom of the recessed portion 9 ) is located in the middle of the thickness of the insulating layer 2 in the thickness direction of the insulating layer 2 .

Also, the wiring board 1 can be turned upside down.

<Regarding the manufacturing process of the wiring board>
Next, with reference to FIGS. 2 to 7, manufacturing steps of the wiring board 1 of the present embodiment will be described. 2 to 7 are cross-sectional views of essential parts during the manufacturing process of the wiring board 1 of the present embodiment.

To manufacture the wiring board 1 of the present embodiment, first, as shown in FIG. 2, a support plate (support substrate) 21 is prepared. Since the support plate 21 is used for the purpose of facilitating subsequent processes, it is sufficient that it has robustness. For example, a glass substrate, a metal plate such as a copper plate, or the like can be used as the support plate 21 .

Next, as shown in FIG. 2, the conductor pattern 4 is formed on the upper surface (main surface) 21a of the support plate 21. Next, as shown in FIG. The conductor pattern 4 is made of a metallic material mainly composed of copper, and can be formed by a method such as semi-additive or subtractive.

Next, as shown in FIG. 3, the insulating layer 2 is formed on the upper surface 21a of the support plate 21 so as to cover the conductor pattern 4 through a process such as lamination or resin curing. At this time, the surface (lower surface 8) of the insulating layer 2 on the side of the support plate 21 is in close contact with the conductor pattern 4 and the support plate 21 so as to follow the support plate 21 without any gap, and is the surface opposite to the support plate 21 of the insulating layer 2. The upper surface 7 is formed substantially parallel to the upper surface 21 a of the support plate 21 . Here, the insulating layer 2 is made of a material having insulating properties, and a suitable example thereof is an epoxy-based resin material or the like. In the following description, an epoxy resin containing 50 wt % or more of SiO ₂ is taken as an example of a Low-k material having a dielectric constant of about 4 or less obtained by adding a low dielectric constant to the insulating layer 2 .

The lower surface 8 of the insulating layer 2 is the main surface on the side adjacent to the upper surface 21a of the support plate 21, and the upper surface 21a of the support plate 21 is the main surface on the side opposite to the side adjacent to the upper surface 21a of the support plate 21. be. Since the insulating layer 2 is formed on the upper surface 21 a of the support plate 21 so as to cover the conductive pattern 4 , when the insulating layer 2 is formed, the conductive pattern 4 is formed on the lower surface 8 of the insulating layer 2 . .

Next, as shown in FIG. 4 , openings (through holes) 5 are formed in the insulating layer 2 by irradiating the insulating layer 2 with laser light or the like from above the upper surface 7 of the insulating layer 2 . The opening 5 is provided for electrically connecting the conductor pattern 3 formed on the upper surface 7 side of the insulating layer 2 and the conductor pattern 4 formed on the support plate side 21 . It is formed on the insulating layer 2 .

Therefore, although the opening 5 is formed to penetrate the insulating layer 2, the opening 5 is formed at a position included in the conductor pattern 4 in plan view. In the case of FIG. 4, the opening 5 is formed at a position included in the conductor pattern 4a in plan view. Here, a plan view corresponds to a plane view substantially parallel to the upper surface 7 of the insulating layer 2 , the lower surface 8 of the insulating layer 2 , or the upper surface 21 a of the support plate 21 . The opening 5 penetrates the insulating layer 2 , but does not penetrate the conductor pattern 4 and the support plate 21 , and the conductor pattern 4 remains at the bottom of the opening 5 .

At this time, even if the same epoxy resin is applied to the upper surface 7 of the insulating layer 2 and the side wall of the opening 5 perpendicular to the surface of the conductive pattern 4, the conditions are different. That is, while the upper surface 7 is covered with the epoxy resin, the side wall surfaces of the opening 5 are exposed by the irradiation of the laser beam _. state.

Next, as shown in FIG. 5, a seed layer 11 is formed on the upper surface 7 of the insulating layer 2 and on the side walls (side surfaces) and bottom surface of the opening 5. Next, as shown in FIG. Since the bottom surface of the opening 5 is composed of the conductor pattern 4 (the conductor pattern 4a in the case of FIG. 5), the upper surface 7 of the insulating layer 2, the side wall of the opening 5, and the bottom surface of the opening 5 are covered. A seed layer 11 is formed on the constituting conductor pattern 4 (4a).

Since the side wall of the opening 5 is rich in SiO ₂ , which is classified as a low-k material, it is difficult for functional groups to be generated, and a metal film is formed on the side wall of the opening 5 by a method such as plating. It is very difficult to do. Therefore, the seed layer 11 is preferably formed using a printing method such as screen printing, and the seed layer 11 is formed using a metal paste (thick film paste) by screen printing or the like. By forming the seed layer 11 by a printing method such as screen printing, the surface of the screen to be squeegeeed is close to the upper surface 7 of the insulating layer 2, and the upper surface of the seed layer 11 in the opening 5 is distant. In the opening 5 , the upper surface of the seed layer 11 can be positioned lower than the upper surface 7 of the insulating layer 2 .

When the seed layer 11 is formed using a printing method such as screen printing, specifically, a metal paste for the seed layer 11 is applied onto the upper surface 7 of the insulating layer 2 and inside the opening 5 ( The seed layer 11 is formed by supplying (printing) to the side walls and the bottom surface of the opening 5 and then performing heat treatment (baking).

The metal paste (thick film paste) used when forming the seed layer 11 by printing is a paste material containing metal (metal particles), and may be a copper paste containing copper (copper particles) or silver (silver). Preference is given to silver pastes containing particles). As the metal material (metal particles) contained in the paste material for the seed layer 11, metal nanoparticles are particularly suitable. Silver nanoparticles, which are metal nanoparticles composed of (Ag), are most preferred. Here, typically, a metal material composed of metal particles having an average particle size of less than 1 μm (1 to several hundred nm) is called metal nanoparticles.

Therefore, the metal paste used when forming the seed layer 11 by printing is preferably a frit-type material mainly composed of a metal material having a grain size of less than 1 μm using copper or silver material. By setting the particle size of the copper or silver metal material to less than 1 μm (that is, by using copper nanoparticles or silver nanoparticles), the intermetallic bonding between the copper or silver particles and each can be promoted. The seed layer 11 can be properly formed even by heat treatment at a relatively low temperature (baking after printing). For this reason, if a metal paste using copper nanoparticles or silver nanoparticles is used, the heat treatment after printing can be performed at a temperature lower than the thermal decomposition temperature of the resin constituting the insulating layer 2. Alteration of the insulating layer 2 can be prevented. Specifically, if the insulating layer 2 is an epoxy resin, the maximum thermal decomposition temperature is usually about 300°C. The seed layer 11 can be formed by firing at a low temperature of . Of course, it is possible to form the seed layer 11 even at a firing temperature of about 200° C., but the sintering of copper or silver particles becomes more difficult as the firing temperature decreases, resulting in the wiring resistance value of the seed layer 11. has a high resistance, it is desirable to adjust the firing temperature according to the properties of the epoxy resin used as the insulating layer 2 .

Since seed layer 11 is formed using a metal paste containing a plurality of metal particles, seed layer 11 (seed layer 11 after heat treatment) has a structure in which a plurality of metal particles are bonded. When seed layer 11 is formed using a metal paste containing a plurality of metal nanoparticles, seed layer 11 (seed layer 11 after heat treatment) has a structure in which a plurality of metal nanoparticles are bonded. When seed layer 11 is formed using a copper paste containing a plurality of copper nanoparticles, seed layer 11 (seed layer 11 after heat treatment) has a structure in which a plurality of copper nanoparticles are bonded. When seed layer 11 is formed using a silver paste containing a plurality of silver nanoparticles, seed layer 11 (seed layer 11 after heat treatment) has a structure in which a plurality of silver nanoparticles are bonded. The plurality of metal nanoparticles (copper nanoparticles or silver nanoparticles) are bound together by van der Waals forces and sintering.

Next, as shown in FIG. 6, a plating layer 12 is formed on the seed layer 11 using an electrolytic plating method. The seed layer 11 functions as a seed layer for electrolytic plating. The plating layer 12 is preferably a copper plating layer. The plating layer 12 is formed on the seed layer 11 on the upper surface 7 of the insulating layer 2 and on the seed layer 11 in the opening 5 .

The conductor pattern 3 is formed on the upper surface 7 of the insulating layer 2 by the seed layer 11 on the upper surface 7 of the insulating layer 2 and the plating layer 12 thereon. With layer 12 , electrode 6 is formed in opening 5 of insulating layer 2 . On the upper surface 7 of the insulating layer 2, if the seed layer 11 is also formed in a region where the conductor pattern 3 should not be formed, after forming the seed layer 11 and the plating layer 12, a photoresist technique and An etching technique or the like can be used to remove the seed layer 11 in areas where the conductor pattern 3 is not to be formed.

That is, since the seed layer 11 is formed using the printing method, the seed layer 11 can be selectively formed. For this reason, when the seed layer 11 is formed in the opening 5 and on a predetermined region (region where the conductor pattern 3 is to be formed) of the upper surface 7 of the insulating layer 2, the seed layer 11 is formed in the opening 5 and on the entire upper surface 7 of the insulating layer 2. The seed layer 11 may be formed in both cases. When the seed layer 11 is formed in the opening 5 and on the entire upper surface 7 of the insulating layer 2 in the seed layer 11 forming step, the plating layer 12 is formed on the entire seed layer 11 in the plating layer 12 forming step. , a laminated film of the seed layer 11 and the plating layer 12 is formed in the opening 5 and on the entire upper surface 7 of the insulating layer 2 . In this case, after forming the plating layer 12, the conductor pattern 3 and the electrode 6 can be formed by patterning the laminated film of the seed layer 11 and the plating layer 12 using a photoresist technique and an etching technique. can. On the other hand, when the seed layer 11 is selectively formed in the regions where the conductor pattern 3 and the electrode 6 are to be formed in the seed layer 11 forming step, the plating layer 11 is selectively formed on the seed layer 11 in the plating layer 12 forming step. 12 is formed, and the laminated film of the seed layer 11 and the plating layer 12 forms the conductor pattern 3 and the electrode 6 . In this case, the patterning process (patterning process of the laminated film of the seed layer 11 and the plating layer 12) using a photoresist technique and an etching technique after forming the plating layer 12 may not be performed.

Since the seed layer 11 is made of copper or silver metal paste (thick film paste), the metal particles are sintered during firing after printing, and the seed layer 11 is in a porous state. Furthermore, if the baking temperature after printing is lowered, the sintering of the metal particles is weakened, resulting in an increase in wiring resistance. However, by integrally forming copper (plating layer 12) on the seed layer 11 by electroplating, the copper plating (plating layer 12) penetrates into the porous portion of the seed layer 11, and it becomes an electrical connection. It works as an anchor as well. As a result, the adhesion strength between the seed layer 11 and the plating layer 12 can be increased, and the conductor pattern 3 with increased density can be formed.

Furthermore, the seed layer 11 and the plating layer 12 are in a laminated state, so that they are electrically in parallel. That is, even if the wiring resistance increases as a result of setting the baking temperature of the seed layer 11 to a lower value, since the plating layers 12 are connected in parallel, the combined resistance is the bulk value of copper. It becomes possible to approach 2 μΩcm.

Next, by peeling off the supporting plate 21 from the structure composed of the conductor pattern 4, the insulating layer 2, the conductor pattern 3 and the electrodes 6, the wiring board 1 can be obtained as shown in FIG. Moreover, a plurality of wiring boards 1 may be obtained by cutting the wiring board after removing the support plate 21 . Moreover, the support plate 21 may also be used as a part of the wiring board 1 without peeling off the support plate 21. 21 is preferably made of an insulator.

<Main features and effects>
Next, main features and effects of this embodiment will be described.

Wiring board 1 of the present embodiment includes insulating layer 2, conductor pattern 3 formed on one main surface (here, upper surface 7) of insulating layer 2, and the other main surface of insulating layer 2 (here, upper surface 7). It has a conductor pattern 4 formed on the lower surface 8 ) and an electrode 6 formed in the opening 5 of the insulating layer 2 and electrically connecting the conductor pattern 3 and the conductor pattern 4 .

One of the main features of this embodiment is that the electrodes 6 formed in the openings 5 of the insulating layer 2 correspond to the conductor patterns 3 ( In the case of FIG. 1, it is integrally formed with the conductor pattern 3a), and the surface of the electrode 6 in the opening 5 is recessed with respect to the surface of the conductor pattern 3 (in the case of FIG. 1, the conductor pattern 3a). That is. Specifically, the surface of the plating layer 12 forming the electrode 6 and the conductor pattern 3a integrally formed therewith is recessed at a position overlapping the opening 5 in plan view, and overlaps the opening 5 in plan view. It has a recess 9 at the position.

FIG. 8 is a cross-sectional view of a main part showing a wiring board 101 of an example studied by the inventors, and corresponds to FIG. 1 described above. The wiring board 101 of the examination example shown in FIG. and an electrode 106 formed in the opening 105 of 102 and electrically connecting the conductor pattern 103 and the conductor pattern 104 . The electrode 106 formed in the opening 105 of the insulating layer 102 is formed integrally with the conductor pattern 103 (conductor pattern 103a in the case of FIG. 8) formed on the upper surface of the insulating layer 102. The surface of the electrode 106 in the portion 105 is not recessed with respect to the surface of the conductor pattern 103 (conductor pattern 103a in the case of FIG. 8). That is, the electrode 106 and the conductor pattern 103 are formed of a layered film of the seed layer 111 and the plated layer 112 thereon. It is formed so as to be substantially flush with the surface of and is not recessed. That is, the surface of the plating layer 112 is not recessed even at a position overlapping the opening 105 in plan view, and is substantially flat across the electrode 106 and the conductor pattern 103a.

The present inventor has found that the following problems may occur when various electronic devices are manufactured using the wiring board 101 having such a structure. FIG. 9 is a fragmentary cross-sectional view showing a state in which an insulator 122 is formed on the wiring substrate 101 of the study example shown in FIG. Various insulators 122 are often formed on the wiring board 101 when various electronic devices are manufactured using the wiring board 101 . The insulator 122 is, for example, a sealing resin formed to seal an electronic component mounted as a bare chip on the wiring board 101 .

In the state where the insulator 122 is formed on the wiring board 101, when the temperature changes, mechanical stress is generated by the bimetallic action at the interface between the wiring board 101 and the insulator 122 due to the difference in thermal expansion coefficient between the two. Especially in applications such as power systems where large currents flow, this becomes even more pronounced. In such a case, peeling may occur at the interface between the wiring board 101 and the insulator 122 . In addition, even if the wiring board 101 and the insulator 122 are not completely peeled off, moisture or the like enters the wiring board 101 from the interface between the wiring board 101 and the insulator 122 due to the capillary phenomenon, which causes a decrease in reliability. This leads to a decrease in reliability of the wiring board 101 and an electronic device manufactured using the wiring board 101 .

FIG. 10 is a fragmentary cross-sectional view showing a state in which insulator 22 is formed on wiring board 1 of the present embodiment shown in FIG. When various electronic devices are manufactured using the wiring board 1, various insulators 22 are often formed on the wiring board 1. FIG. The insulator 22 is, for example, a sealing resin formed to seal an electronic component mounted as a bare chip on the wiring board 1 . The sealing portion can be formed on wiring board 1 so as to cover electronic components mounted on wiring board 1 .

In the wiring board 1 of the present embodiment, the surface of the electrode 6 in the opening 5 is recessed with respect to the surface of the conductor pattern 3 (conductor pattern 3 a ) integrally formed with the electrode 6 . Specifically, the surface of the plating layer 12 forming the electrode 6 and the conductor pattern 3a integrally formed therewith is recessed at a position overlapping the opening 5 in plan view, and overlaps the opening 5 in plan view. It has a recess 9 at the position. Therefore, when the insulator 22 is formed on the wiring substrate 1 as shown in FIG. become. The insulator 22 becomes difficult to peel off from the wiring board 1 due to the anchoring effect of part of the insulator 22 entering the recess 9 . Therefore, it is possible to suppress or prevent peeling of the insulator 22 from the wiring board 1 even if the temperature changes while the insulator 22 is formed on the wiring board 1 . In addition, it is possible to suppress or prevent moisture or the like from entering onto the wiring board 1 from the interface between the wiring board 1 and the insulator 22 due to capillary action. Thereby, the reliability of the wiring board 1 can be improved, and the reliability of an electronic device manufactured using the wiring board 1 can be improved.

In order to improve this anchoring effect, it is effective to make the planar dimensions (flat area, diameter) of the opening 5 larger than the thickness of the insulating layer 2 to some extent. As the planar dimension of the opening 5 is increased, the surface of the electrode 6 in the opening 5 tends to be depressed with respect to the surface of the conductor pattern 3 integrally formed with the electrode 6. If the planar dimension of 5 is made small, it will become difficult to form the recessed portion 9 . Therefore, it is desirable to set the planar dimensions of the opening 5 so that the relationship "(diameter of the opening 5/thickness of the insulating layer 2)≧1" holds. That is, it is desirable to set the diameter of the opening 5 to be equal to or greater than the thickness of the insulating layer 2 . Depending on the thickness of the insulating layer 2, the diameter of the opening 5 (opening diameter) can be set to, for example, about 50 to 80 μm.

In addition, the surface of the electrode 6 in the opening 5 may be integrated with the electrode 6 depending on the viscosity of the metal paste used to form the seed layer 11 and the conditions for forming the plating layer 12 by electroplating. The surface of the conductor pattern 3 (conductor pattern 3a) which is randomly formed tends to be recessed. For this reason, the planar dimensions of the opening 5, the thicknesses of the seed layer 11 and the plating layer 12, the viscosity of the metal paste used to form the seed layer 11, and the By appropriately adjusting the conditions and the like, the surface of the electrode 6 in the opening 5 is recessed with respect to the surface of the conductor pattern 3 (conductor pattern 3a) integrally formed with the electrode 6. be able to.

Moreover, in order to enhance the above-described anchor effect, it is preferable that the depth of the recessed portion 9 is deep to some extent. Specifically, the bottom of the recess 9 is preferably lower than the upper surface 7 of the insulating layer 2 . That is, on the side of the upper surface 7 of the insulating layer 2 , the surface of the electrode 6 preferably has a portion whose height position is lower than the upper surface 7 of the insulating layer 2 . From another point of view, it is preferable that a part of the surface of the electrode 6 (the bottom of the recessed portion 9 ) is located in the middle of the thickness of the insulating layer 2 in the thickness direction of the insulating layer 2 . As a result, since the depth of the recessed portion 9 is increased, the anchor effect due to part of the insulator 22 entering the recessed portion 9 can be enhanced, and the insulator 22 is more difficult to peel off from the wiring substrate 1. Become.

Moreover, in the present embodiment, the conductor pattern 3 has a structure in which the plating layer 12 is formed on the seed layer 11 formed on the insulating layer 2 using a metal paste. As a result, even if the low-dielectric-constant filler such as SiO ₂ contained in the insulating layer 2 is exposed on the sidewall surface of the opening 5, the sidewall of the opening 5 can be removed when the seed layer 11 is formed. Since there is no need to generate a functional group on the exposed SiO ₂ , the conductor pattern 3 can be formed with good adhesion to the side wall of the opening 5 .

Moreover, in this embodiment, the seed layer 11 is formed of a metal paste. Specifically, a metal paste (metal nanopaste) mainly composed of metal nanoparticles (particles of less than 1 μm) made of copper or silver is used for printing, and after printing, it is baked at a temperature of 250 to 300 ° C. (heat treatment ) to form the seed layer 11 . This is because the main component of the insulating layer 2 is a resin such as epoxy, and a temperature of 300° C. or higher is in the range of thermal decomposition temperature in most cases. In addition, it is generally recommended that a metal paste containing metal nanoparticles made of copper or silver as a main component be fired at a temperature of 200° C. or less. However, when a metal paste containing metal nanoparticles made of copper or silver as a main component is used, it promotes intermetallic bonding between metals, and seeding is performed at a temperature much lower than the melting point of the metal (approximately 1000 ° C. or higher). Layer 11 can be formed, but the volume resistivity of seed layer 11 will be higher than the bulk resistivity. Specifically, the volume resistivity of copper or silver is 2 μΩcm in bulk value, but when the baking temperature after printing is 200° C. or lower, the volume resistivity of the seed layer 11 is about 8 to 9 μΩcm. . Here, it has been experimentally confirmed that the seed layer 11 has a volume resistivity of 2 to 3 μΩcm by raising the baking temperature after printing to 250 to 300° C., which is extremely close to the bulk value. Volume resistivity can be realized.

Furthermore, by laminating a plated layer 12 of copper or the like on the seed layer 11, a wiring (conductor pattern 3) having a more stable resistance value can be formed.

(Embodiment 2)
11 to 14 are cross-sectional views of essential parts showing manufacturing steps of the wiring board 1 of the second embodiment. The wiring board 1 of the second embodiment is hereinafter referred to as a wiring board 1a by attaching a reference numeral 1a.

A manufacturing process of the wiring substrate 1a of the second embodiment will be described with reference to FIGS. 11 to 14. FIG.

After obtaining the structure shown in FIG. 4 by performing the steps shown in FIGS. 2 to 4 in substantially the same manner as in the first embodiment, the upper surface 7 of the insulating layer 2 is formed as shown in FIG. A seed layer 11a is formed on the top and on the sidewalls and bottom of opening 5 using an electroless plating method. The seed layer 11a is preferably an electroless plated layer of copper. The seed layer 11a corresponds to the seed layer 11, but unlike the first embodiment, the seed layer 11a is formed by electroless plating instead of using a metal paste. In the first embodiment, the insulating layer 2 preferably contains a silicon oxide (SiO ₂ ) filler, but in the second embodiment, the insulating layer 2 contains silicon oxide (SiO ₂ ) Consists of materials that do not contain fillers.

Next, as shown in FIG. 12, a plated layer 12a is formed on the seed layer 11a by electroplating. The plating layer 12a is preferably an electroplating layer of copper. The plated layer 12a corresponds to the plated layer 12, and is formed by electroplating, as in the first embodiment. If the seed layer 11a and the plating layer 12a are also formed on the upper surface 7 of the insulating layer 2 in areas where the conductor pattern 3 should not be formed, after forming the seed layer 11a and the plating layer 12a, The laminated film of the seed layer 11a and the plating layer 12a is patterned using a photoresist technique, an etching technique, or the like. As a result, as shown in FIG. 13, the seed layer 11a and the plating layer 12a can be removed from the region where the conductor pattern 3 should not be formed.

The conductor pattern 3 is formed on the upper surface 7 of the insulating layer 2 by the seed layer 11a on the upper surface 7 of the insulating layer 2 and the plating layer 12a thereon. An electrode 6 is formed in the opening 5 of the insulating layer 2 by the layer 12a.

The electrode 6 and the conductor pattern 3 of the second embodiment are the same as those of the electrode 6 and the conductor pattern 3 of the first embodiment except that the seed layer 11a corresponding to the seed layer 11 is formed by an electroless plating method. is almost the same as , so the repetitive description thereof is omitted here.

Next, by peeling off the support plate 21 from the structure composed of the conductor pattern 4, the insulating layer 2, the conductor pattern 3 and the electrode 6, the wiring substrate 1a can be obtained as shown in FIG. Also, in the second embodiment, as in the first embodiment, a plurality of wiring boards 1a may be obtained by cutting the wiring board after removing the support plate 21 . Moreover, the support plate 21 may also be used as a part of the wiring substrate 1a without peeling off the support plate 21 .

In the wiring substrate 1a of the second embodiment, the surfaces of the electrodes 6 in the openings 5 are recessed with respect to the surfaces of the conductor patterns 3 (conductor patterns 3a) integrally formed with the electrodes 6. FIG. Specifically, the surface of the plating layer 12a constituting the electrode 6 and the conductive pattern 3a integrally formed therewith is recessed at a position overlapping the opening 5 in plan view, and overlaps the opening 5 in plan view. It has a recess 9 at the position. Therefore, when the insulator 22 is formed on the wiring substrate 1a, part of the insulator 22 enters (fills) the recessed portion 9 thereof. This makes it difficult for the insulator 22 to separate from the wiring substrate 1a due to the anchor effect. It is possible to suppress or prevent peeling from the substrate 1a. Thereby, the reliability of the wiring board 1a can be improved, and the reliability of an electronic device manufactured using the wiring board 1a can be improved.

Moreover, as described in the first embodiment, when the insulating layer 2 contains SiO ₂ filler, it is difficult to form an electroless copper layer on the sidewall of the opening 5 . In fact, as the wiring density increases, the opening diameter becomes smaller. As a result, desmearing is processed in a dry state, but contrary to this, SiO ₂ on the side wall of the opening becomes rich. Therefore, in the first embodiment, the seed layer 11 is formed by printing using a metal paste. However, the insulating layer 2 used in the second embodiment is made of a material that does not contain SiO ₂ or the like that has a low dielectric constant. Therefore, when palladium as a catalyst is deposited on the sidewalls of the openings 5 of the insulating layer 2 as a pretreatment for forming the seed layer 11a by, for example, electroless plating of copper, the functional groups on the sidewalls of the openings 5 , the subsequent electroless copper plating is also stably formed. Therefore, the seed layer 11a can be formed by electroless plating.

On the other hand, when the insulating layer 2 contains SiO ₂ filler, it is desirable to apply the first embodiment.

(Embodiment 3)
15 to 18 are cross-sectional views of essential parts showing manufacturing steps of the wiring board 1 of the third embodiment. The wiring board 1 of Embodiment 3 is hereinafter referred to as a wiring board 1b by attaching a reference numeral 1b.

The manufacturing process of the wiring board 1b of the third embodiment will be described with reference to FIGS. 15 to 18. FIG.

After obtaining the structure shown in FIG. 6 by performing the steps of FIGS. An insulating layer 2 b is formed thereon so as to cover the conductor pattern 3 and the electrodes 6 . The insulating layer 2b is made of, for example, the same material as the insulating layer 2 and can be formed using the same method as the insulating layer 2 described above.

Next, as shown in FIG. 16, openings (through holes) 5b are formed in the insulating layer 2b. Opening 5b can be formed by the same method as opening 5 in the first embodiment, and is formed to penetrate insulating layer 2b. However, the opening 5b is formed at a position included in the conductor pattern 3 (the conductor pattern 3a in the case of FIG. 16) in plan view. It is formed at a position exposing the pattern 3a). The opening 5b penetrates the insulating layer 2b, but does not penetrate the conductor pattern 3 (3a) and the insulating layer 2, and the conductor pattern 3 (3a) remains and is exposed at the bottom of the opening 5b.

Next, as shown in FIG. 17, a seed layer 11b is formed on the upper surface of insulating layer 2b and on the side walls (side surfaces) and bottom surface of opening 5b. Since the bottom surface of the opening 5b is composed of the conductor pattern 3 (the conductor pattern 3a in the case of FIG. 17), the upper surface of the insulating layer 2b, the sidewall of the opening 5b, and the bottom surface of the opening 5b are formed. A seed layer 11b is formed on the conductive pattern 3 (3a). The seed layer 11b can be formed by the same method as the seed layer 11 in the first embodiment (printing method using a metal paste and heat treatment after printing). The method of forming the seed layer 11b and the metal paste used can be the same as those used to form the seed layer 11, and therefore repeated description thereof will be omitted here.

Next, the plating layer 12b is formed on the seed layer 11b using an electrolytic plating method. The method of forming the plating layer 12b is the same as the method of forming the plating layer 12 in the first embodiment. Like the plating layer 12, the plating layer 12b is also preferably a copper (Cu) plating layer. The plating layer 12b is formed on the seed layer 11b on the upper surface of the insulating layer 2b and on the seed layer 11b inside the opening 5b.

A conductor pattern 23 is formed on the upper surface of the insulating layer 2b by the seed layer 11b on the upper surface of the insulating layer 2b and the plating layer 12b thereon. As a result, electrodes (via electrodes, through electrodes) 6b are formed in the openings 5b of the insulating layer 2b. The electrode 6b is formed integrally with a conductor pattern 23 (conductor pattern 23a in the case of FIG. 17) formed on the upper surface of the insulating layer 2b, and the conductor pattern 3 covering the opening 5b on the lower surface side of the insulating layer 2b. (In the case of FIG. 17, it is in contact with the conductor pattern 3a). Therefore, the conductor pattern 23 (23a) on the upper surface of the insulating layer 2b and the conductor pattern 3 (3a) formed between the insulating layers 2 and 2b are electrically connected through the electrode 6b in the opening 5b. Connected.

On the upper surface of the insulating layer 2b, if the seed layer 11b is also formed in a region where the conductor pattern 23 is not to be formed, after forming the seed layer 11b and the plating layer 12b, photoresist technology and etching are performed. Techniques or the like can be used to remove the seed layer 11b in areas where the conductor pattern 23 is not to be formed.

Next, by peeling the support plate 21 from the structure consisting of the conductor pattern 4, the insulating layer 2, the conductor pattern 3, the electrode 6, the insulating layer 2b, the conductor pattern 23 and the electrode 6b, as shown in FIG. A wiring substrate 1b can be obtained. Also, in the third embodiment, as in the first embodiment, a plurality of wiring boards 1b may be obtained by cutting the wiring board after the support plate 21 is peeled off. Moreover, the support plate 21 may also be used as a part of the wiring board 1b without peeling off the support plate 21 .

The wiring substrate 1b of the third embodiment has a plurality of insulating layers 2 and 2b, and electrodes 6 and 6b formed in openings 5 and 5b penetrating through the insulating layers 2 and 2b, respectively. Conductor patterns formed on both sides of 2 and 2b are electrically connected. That is, the conductor patterns 3 and 4 formed on both surfaces (upper surface and lower surface) of the insulating layer 2 are electrically connected by the electrodes 6 formed in the openings 5 of the insulating layer 2, and the openings of the insulating layer 2b are electrically connected. Conductive patterns 23 and 3 formed on both surfaces (upper surface and lower surface) of insulating layer 2b are electrically connected by electrode 6b formed in 5b.

As in the first embodiment, also in the third embodiment, the surface of the electrode 6 in the opening 5 is positioned relative to the surface of the conductor pattern 3 (conductor pattern 3a) integrally formed with the electrode 6. It's hollow. Specifically, the surface of the plating layer 12 forming the electrode 6 and the conductor pattern 3a integrally formed therewith is recessed at a position overlapping the opening 5 in plan view, and overlaps the opening 5 in plan view. It has a recess 9 at the position. Therefore, when the insulating layer 2b is formed, part of the insulating layer 2b enters the recess 9 and is filled. Due to the anchoring effect of part of the insulating layer 2b entering the recess 9, the insulating layer 2b is less likely to separate from the structure below the insulating layer 2b. Therefore, even if the temperature of the wiring board 1b changes, it is possible to suppress or prevent the insulating layer 2b from peeling off from the structure below the insulating layer 2b. Thereby, the reliability of the wiring board 1b can be improved, and the reliability of an electronic device manufactured using the wiring board 1b can be improved.

In the third embodiment, the electrode 6b inside the opening 5b is formed by the same method as the electrode 6 inside the opening 5 and has the same structure as the electrode 6 inside the opening 5. FIG. Therefore, the surface of the electrode 6b in the opening 5b is recessed with respect to the surface of the conductor pattern 23 (conductor pattern 23a in the case of FIG. 18) integrally formed with the electrode 6b. Specifically, the surface of the plating layer 12b that constitutes the electrode 6b and the conductor pattern 23a integrally formed therewith is recessed at a position that overlaps the opening 5b in plan view, and overlaps the opening 5b in plan view. It has a recessed portion 9b (corresponding to the recessed portion 9) at a position. Therefore, when the insulator 22 is formed on the wiring substrate 1b, part of the insulator 22 enters the recess 9b and fills the recess. The insulator 22 becomes difficult to peel off from the wiring substrate 1b due to the anchoring effect of part of the insulator 22 entering the recess 9b. Therefore, even if the temperature of the wiring substrate 1b changes, it is possible to suppress or prevent the insulator 22 from peeling off from the wiring substrate 1b. Thereby, the reliability of the wiring board 1b can be improved, and the reliability of an electronic device manufactured using the wiring board 1b can be improved.

Further, by repeating the steps of FIGS. 15 to 17, the number of insulating layers and conductor patterns (the number of layers) of the wiring board can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and can be variously modified without departing from the gist of the invention. Needless to say.

1 wiring substrates 2, 2b insulating layers 3, 3a, 3b conductor patterns 4, 4a, 4b, 4c conductor patterns 5, 5b openings 6, 6b electrodes 7 upper surfaces 8 lower surfaces 9, 9b depressions 11, 11a, 11b seed layers 12 , 12a, 12b plating layer 21 support plate 22 insulator 23, 23a conductor pattern 101 wiring board 102 insulation layer 103, 103a conductor pattern 104 conductor pattern 105 opening 106 electrode 111 seed layer 112 plating layer 122 insulator

Claims (21)

an insulating layer having a first principal surface, a second principal surface opposite to the first principal surface, and an opening penetrating between the first principal surface and the second principal surface;
a first conductor pattern formed on the first main surface of the insulating layer;
a second conductor pattern formed on the second main surface of the insulating layer;
an electrode formed in the opening for electrically connecting the first conductor pattern and the second conductor pattern;
with
The electrode is formed integrally with the second conductor pattern,
The wiring board, wherein the surface of the electrode is recessed with respect to the surface of the second conductor pattern on the second main surface side. The wiring board according to claim 1,
A wiring board, wherein a part of the first conductor pattern covers the opening on the first main surface side. The wiring board according to claim 1,
The wiring substrate, wherein the surface of the electrode has a portion lower in height position than the second main surface on the second main surface side. The wiring board according to claim 1,
A wiring board, wherein the second conductor pattern and the electrode each have a seed layer and a plating layer formed on the seed layer. In the wiring board according to claim 4,
The wiring board, wherein the seed layer is formed on the second main surface and on sidewalls of the opening. In the wiring board according to claim 5,
The wiring board, wherein the seed layer has a structure in which a plurality of metal particles are bonded. In the wiring board according to claim 5,
The wiring board, wherein the seed layer has a structure in which a plurality of copper particles are bonded. In the wiring board according to claim 5,
The wiring board, wherein the seed layer has a structure in which a plurality of silver particles are bonded. In the wiring board according to claim 5,
The wiring board, wherein the seed layer is formed of a metal paste. In the wiring board according to claim 9,
The wiring board, wherein the metal paste contains metal nanoparticles. (a) a first principal surface, a second principal surface opposite to the first principal surface, an opening penetrating between the first principal surface and the second principal surface; providing an insulating layer having a first conductor pattern formed on the surface;
(b) forming a second conductor pattern on the second main surface of the insulating layer and forming an electrode in the opening;
including
the electrode electrically connects the first conductor pattern and the second conductor pattern;
The electrode is formed integrally with the second conductor pattern,
The method of manufacturing a wiring board, wherein the surface of the electrode is recessed with respect to the surface of the second conductor pattern. In the method for manufacturing a wiring board according to claim 11,
A method of manufacturing a wiring board, wherein part of the first conductor pattern covers the opening on the first main surface side. In the method for manufacturing a wiring board according to claim 11,
The method of manufacturing a wiring board, wherein the surface of the electrode on the second main surface side has a portion whose height position is lower than that of the second main surface. In the method for manufacturing a wiring board according to claim 11,
The step (b) is
(c) forming a seed layer on the second main surface of the insulating layer and on sidewalls of the opening;
(d) forming a plating layer on the seed layer;
including
A method of manufacturing a wiring board, wherein the second conductor pattern and the electrode are formed of the seed layer and the plating layer. In the method for manufacturing a wiring board according to claim 14,
In the step (c), the seed layer is formed using a metal paste,
In the step (d), the method of manufacturing a wiring board, wherein the plating layer is formed by an electrolytic plating method. In the method for manufacturing a wiring board according to claim 15,
The method for producing a wiring board, wherein the metal paste contains metal nanoparticles. In the method for manufacturing a wiring board according to claim 16,
The method for producing a wiring board, wherein the metal nanoparticles are copper nanoparticles or silver nanoparticles. In the method for manufacturing a wiring board according to claim 16,
The step (c) is
(c1) supplying the metal paste onto the second main surface of the insulating layer and onto the side wall of the opening by a printing method;
(c2) a step of subjecting the metal paste to heat treatment after the step (c1) and before the step (d);
A method of manufacturing a wiring board, comprising: In the method for manufacturing a wiring board according to claim 18,
In the step (c2), the method of manufacturing a wiring board, wherein the heat treatment is performed at a temperature in the range of 250°C to 300°C. In the method for manufacturing a wiring board according to claim 15,
The method for manufacturing a wiring board, wherein the insulating layer contains a silica filler. In the method for manufacturing a wiring board according to claim 15,
The method for manufacturing a wiring board, wherein the insulating layer has a dielectric constant equal to or lower than that of silicon oxide.

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