JP2023011348A - Semiconductor chip, semiconductor device, and method for manufacturing semiconductor chip - Google Patents

Abstract

A semiconductor chip capable of improving reliability is provided. A semiconductor chip (10a) includes a first main surface (11a) positioned on one side in the thickness direction and a second main surface (12a) positioned on the other side in the thickness direction. The first main surface 11a includes an active region 17a, a termination region 18a located further outward than an outer edge 24a of the active region 17a, and a dicing region 19a located further outward than an outer edge 35a of the termination region 18a. include. When viewed in the thickness direction of the semiconductor chip 10a, the dicing region 19a includes four corner regions 41a, 42a, 43a and 44a corresponding to the four corners of the semiconductor chip 10a. The thickness of at least one of the corner regions 41a, 42a, 43a, 44a decreases toward the outer edges 31a, 32a, 33a, 34a of the dicing region 19a. [Selection drawing] Fig. 1

Description

The present disclosure relates to a semiconductor chip, a semiconductor device, and a method of manufacturing a semiconductor chip.

2. Description of the Related Art A method of manufacturing a semiconductor device is known in which a plurality of semiconductor elements are formed on a semiconductor substrate and dicing is performed in a dicing region (see, for example, Patent Document 1). According to Patent Document 1, a resin layer covering a semiconductor substrate is formed in an intersection area where belt-shaped dicing areas that partition adjacent semiconductor elements intersect, and dicing is performed in the dicing area between the resin layers.

WO2014/009997

In manufacturing a semiconductor device, a semiconductor chip is sealed with a resin material after being bonded on a substrate. The resin material is in close contact with the surface of the semiconductor chip. Here, the resin material may peel off from the semiconductor chip due to the influence of thermal stress on the semiconductor chip. Even with the method of manufacturing a semiconductor device disclosed in Patent Document 1, the resin layer may peel off from the semiconductor chip due to the difference in material between the semiconductor chip and the covering resin layer. As a result, the dielectric breakdown voltage of the semiconductor device is lowered, resulting in a loss of reliability. Therefore, one object is to provide a semiconductor chip whose reliability can be improved.

A semiconductor chip according to the present disclosure has a plate shape and a rectangular shape when viewed in the thickness direction. The semiconductor chip has a first main surface positioned on one side in the thickness direction, a second main surface positioned on the other side in the thickness direction, a side surface continuous with the first main surface and the second main surface, including. The first main surface includes an active region, a termination region located on the outer peripheral side of the outer edge of the active region, and a dicing region located on the outer peripheral side of the outer edge of the termination region. When viewed in the thickness direction of the semiconductor chip, the dicing region includes four corner regions corresponding to the four corners of the semiconductor chip. A thickness of at least one of the corner regions decreases toward the outer edge of the dicing region.

According to the above semiconductor chip, reliability can be improved.

FIG. 1 is a schematic perspective view of a semiconductor chip according to Embodiment 1. FIG. 2 is a schematic plan view of the semiconductor chip shown in FIG. 1. FIG. 3 is a schematic bottom view of the semiconductor chip shown in FIG. 1. FIG. 4 is a schematic side view showing part of the semiconductor chip shown in FIG. 1. FIG. FIG. 5 is a schematic cross-sectional view showing part of a semiconductor device including the semiconductor chip shown in FIG. FIG. 6 is a flow chart showing typical steps of the method of manufacturing the semiconductor chip according to the first embodiment shown in FIG. FIG. 7 is a schematic perspective view showing a portion of a semiconductor substrate in which active regions, termination regions and dicing regions are formed. FIG. 8 is a schematic perspective view showing a part of the semiconductor substrate in which the depression is formed. FIG. 9 is a schematic cross-sectional view showing a part of the semiconductor substrate in which the depression is formed. FIG. 10 is a schematic perspective view showing a portion of the semiconductor substrate during the dicing process. FIG. 11 is a flow chart showing typical steps of a semiconductor chip manufacturing method according to another embodiment. FIG. 11 is a schematic cross-sectional view showing a state in which a recess is formed in the semiconductor substrate. FIG. 13 is a schematic side view showing part of the semiconductor chip in the second embodiment. FIG. 14 is a schematic side view showing part of the semiconductor chip according to the third embodiment. FIG. 15 is a schematic plan view of a semiconductor chip according to Embodiment 4. FIG. 16 is a schematic plan view showing an enlarged part of the semiconductor chip shown in FIG. 15. FIG. FIG. 17 is a schematic plan view showing part of a semiconductor chip according to the fifth embodiment. FIG. 18 is a schematic plan view showing part of a semiconductor chip according to the sixth embodiment. FIG. 19 is a schematic perspective view showing part of a semiconductor chip according to Embodiment 7. FIG. FIG. 20 is a schematic perspective view showing part of the semiconductor substrate before dicing.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure are listed and described. The semiconductor chip according to the present disclosure has a plate shape and a rectangular shape when viewed in the thickness direction. The semiconductor chip has a first main surface positioned on one side in the thickness direction, a second main surface positioned on the other side in the thickness direction, a side surface continuous with the first main surface and the second main surface, including. The first main surface includes an active region, a termination region located on the outer peripheral side of the outer edge of the active region, and a dicing region located on the outer peripheral side of the outer edge of the termination region. When viewed in the thickness direction of the semiconductor chip, the dicing region includes four corner regions corresponding to the four corners of the semiconductor chip. A thickness of at least one of the corner regions decreases toward the outer edge of the dicing region.

A semiconductor chip is manufactured by cutting a semiconductor substrate into chips by dicing. In the shape cut out by the dicing blade, the semiconductor chip still has sharp corners. Then, when a semiconductor device is manufactured by incorporating a semiconductor chip into a semiconductor device, stress concentrates on this sharp corner, and there is a risk that the resin will peel off starting from this portion.

According to the semiconductor chip of the present disclosure, since the thickness of at least one of the corner regions decreases toward the outer edge of the dicing region, it is possible to reduce the risk of forming sharp corners in the semiconductor chip. Then, in a state where the semiconductor chip is encapsulated in the resin material, the concentration of thermal stress generated in the portion having the sharp corner can be alleviated, and the risk of the resin material peeling off from the semiconductor chip can be reduced. can. Therefore, when it is provided in a semiconductor device, it is possible to reduce the possibility of a decrease in dielectric strength voltage, and to improve reliability.

In the above semiconductor chip, the corner region may have an arcuate first surface when viewed from the side. By doing so, it is possible to achieve a configuration in which the first surface does not include corners. Therefore, stress concentration in the corner region can be further reduced, and reliability can be further improved.

In the above semiconductor chip, the first surface may have a shape recessed toward the inside of the semiconductor chip. By doing so, a semiconductor chip including the above-described first surface can be easily manufactured.

In the above semiconductor chip, the corner region may have a planar second surface when viewed from the side. By doing so, it is possible to reduce the risk of the semiconductor chip having sharp corners.

In the above semiconductor chip, the thickness of the outer edge of the dicing region in the corner region may be 50 μm or more and 350 μm or less. By doing so, stress concentration can be alleviated while ensuring the strength of the semiconductor chip and suppressing cracking and chipping of the semiconductor chip.

In the above semiconductor chip, the ratio of the thickness of the outer edge of the dicing region to the thickness of the active region in the corner region may be 0.5 or more and less than 1.0. By doing so, it is possible to ensure the strength of the semiconductor chip according to the thickness of the active region and to alleviate the concentration of stress.

In addition, the semiconductor chip according to the present disclosure has a plate-like shape, and has a first main surface positioned on one side in the thickness direction, a second main surface positioned on the other side in the thickness direction, and a second main surface positioned on the other side in the thickness direction. a face and a side face contiguous with the second major face. The first main surface includes an active region, a termination region located on the outer peripheral side of the outer edge of the active region, and a dicing region located on the outer peripheral side of the outer edge of the termination region. The semiconductor chip includes corner regions forming the outer edge of the dicing region. The corner region is inside the intersection of the first extension line and the second extension line when viewed in the thickness direction of the semiconductor chip. The first extension line extends in the first direction and is an extension of the first line forming the outer edge of the dicing region. The second extension line extends in a second direction perpendicular to the first direction and is an extension of the second line forming the outer edge of the dicing region.

According to the semiconductor chip of the present disclosure, since the corner region is located inside the intersection of the first extension line and the second extension line, it is possible to reduce the risk of forming sharp corners in the semiconductor chip. , stress concentration can be relieved. By doing so, it is possible to reduce the risk of peeling of the resin material starting from the sharp corners. Therefore, when it is provided in a semiconductor device, it is possible to reduce the possibility of a decrease in dielectric strength voltage, and to improve reliability.

In the above semiconductor chip, the corner region may have an arcuate third surface when viewed in the thickness direction of the semiconductor chip. By doing so, since the third surface does not include sharp corners, stress concentration in the corner regions can be further alleviated, and reliability can be further improved.

In the above semiconductor chip, the third surface may have a shape recessed toward the inside of the semiconductor chip. By doing so, a semiconductor chip including the above-described third surface can be easily manufactured.

In the above semiconductor chip, the corner region may have a planar fourth surface when viewed in the thickness direction of the semiconductor chip. By doing so, it is possible to reduce the risk of the semiconductor chip having sharp corners. Moreover, a semiconductor chip having such a shape can be easily manufactured.

In the above semiconductor chip, the length from the intersection of the first extension line and the second extension line to the corner region may be 5 μm or more and 100 μm or less when viewed in the thickness direction of the semiconductor chip. By doing so, the stress applied to the corner region can be relaxed.

In the above semiconductor chip, the corner regions may be provided at all four corners of the semiconductor chip. By doing so, stress concentration can be alleviated in all the corner regions. Therefore, reliability can be improved more.

In the above semiconductor chip, the angles of the four corners of the second main surface may be right angles. By doing so, it is possible to prevent the area of the second main surface from being reduced, and to secure a large contact area with the second main surface when the semiconductor chip is bonded onto the substrate. Therefore, the semiconductor chip can be more reliably bonded to the substrate, and reliability can be improved.

In the above semiconductor chip, the side surface and the second main surface may be orthogonal. By doing so, it is possible to prevent the area of the second main surface from being reduced, and to secure a large contact area with the second main surface when the semiconductor chip is bonded onto the substrate. Therefore, the semiconductor chip can be more reliably bonded to the substrate, and reliability can be improved.

Also, the semiconductor chip of the present disclosure has a plate shape and a rectangular shape when viewed in the thickness direction. The semiconductor chip has a first main surface positioned on one side in the thickness direction, a second main surface positioned on the other side in the thickness direction, a side surface continuous with the first main surface and the second main surface, including. The first main surface includes an active region, a termination region located on the outer peripheral side of the outer edge of the active region, and a dicing region located on the outer peripheral side of the outer edge of the termination region. The dicing region includes thinned regions that decrease in thickness toward the outer edge of the dicing region. The thin region is provided over the entire circumference of the outer edge of the dicing region. By doing so, it is possible to further suppress the occurrence of corners where stress is concentrated. Therefore, reliability can be further improved.

In the above semiconductor chip, the semiconductor chip may be a wide bandgap semiconductor. Such a wide bandgap semiconductor chip has a high dielectric breakdown voltage and can further improve reliability.

In the above semiconductor chip, the operating layer of the semiconductor chip may be composed of at least one of SiC and GaN. By doing so, the dielectric breakdown voltage can be increased more reliably. Here, although the thermal expansion coefficients of SiC and GaN are not much different from that of Si (silicon), the Young's moduli of SiC and GaN are larger than that of Si. Then, the above-described stress is likely to be applied to the semiconductor chip. However, since the semiconductor chip having the above configuration can alleviate the concentration of stress, it is possible to greatly reduce the risk of peeling of the resin material.

A semiconductor device according to the present disclosure includes the semiconductor chip described above and a resin portion that seals the semiconductor chip. Since the semiconductor device having such a configuration includes the semiconductor chip having the above configuration, stress concentration can be alleviated, and reliability can be improved.

A method for manufacturing a semiconductor chip according to the present disclosure is a method for manufacturing a semiconductor chip that is plate-shaped and rectangular when viewed in the thickness direction. The semiconductor chip has a first main surface positioned on one side in the thickness direction, a second main surface positioned on the other side in the thickness direction, a side surface continuous with the first main surface and the second main surface, including. The first main surface includes an active region, a termination region located on the outer peripheral side of the outer edge of the active region, and a dicing region located on the outer peripheral side of the outer edge of the termination region. A method of manufacturing a semiconductor chip comprises: preparing a semiconductor substrate; The method includes forming a plurality of dicing regions, forming recesses in the dicing regions, and dicing the dicing regions such that the recesses are included in the dicing regions.

According to such a semiconductor chip manufacturing method, the semiconductor chip described above can be manufactured easily and efficiently.

Further, a method for manufacturing a semiconductor chip according to the present disclosure is a method for manufacturing a semiconductor chip that is plate-shaped and rectangular when viewed in the thickness direction. The semiconductor chip has a first main surface positioned on one side in the thickness direction, a second main surface positioned on the other side in the thickness direction, a side surface continuous with the first main surface and the second main surface, including. The first main surface includes an active region, a termination region located on the outer peripheral side of the outer edge of the active region, and a dicing region located on the outer peripheral side of the outer edge of the termination region. A method of manufacturing a semiconductor chip includes steps of preparing a semiconductor substrate, dicing halfway in a thickness direction of the semiconductor substrate on one surface of the semiconductor substrate to form a strip-shaped dicing region, and dividing by the dicing region. forming an active region and a termination region in each of the plurality of regions; forming a recess in the dicing region; and dicing the dicing region in which the recess is formed.

According to such a semiconductor chip manufacturing method, the semiconductor chip described above can be manufactured easily and efficiently.

[Details of the embodiment of the present disclosure]
Next, embodiments of the semiconductor chip of the present disclosure will be described with reference to the drawings. In the following drawings, the same reference numerals are given to the same or corresponding parts, and the description thereof will not be repeated.

(Embodiment 1)
A configuration of the semiconductor chip according to the first embodiment of the present disclosure will be described. FIG. 1 is a schematic perspective view of a semiconductor chip according to Embodiment 1. FIG. 2 is a schematic plan view of the semiconductor chip shown in FIG. 1. FIG. FIG. 2 is a view of the semiconductor chip viewed in the direction opposite to the direction indicated by the arrow Z. FIG. 3 is a schematic bottom view of the semiconductor chip shown in FIG. 1. FIG. FIG. 3 is a view of the semiconductor chip viewed in the direction indicated by arrow Z. FIG. 4 is a schematic side view showing part of the semiconductor chip shown in FIG. 1. FIG. 4 is a view of the semiconductor chip viewed in the direction indicated by arrow Y. FIG. FIG. 5 is a schematic cross-sectional view showing part of a semiconductor device including the semiconductor chip shown in FIG. FIG. 5 is a schematic cross-sectional view taken along a first side surface of a semiconductor chip, which will be described later.

Semiconductor chip 10a according to the first embodiment is a wide bandgap semiconductor chip. A wide bandgap semiconductor chip is a semiconductor chip having, as an operating layer, a semiconductor layer made of a material whose bandgap is larger than that of Si (silicon). Specifically, the operating layer of the semiconductor chip 10a is composed of at least one of SiC (silicon carbide) and GaN (gallium nitride). In this embodiment, the semiconductor chip 10a has a semiconductor layer made of SiC as an operating layer. Such a semiconductor chip 10a has a high dielectric breakdown voltage. Moreover, since the semiconductor chip 10a has high heat resistance, it can be used as a semiconductor device (power module) that can be used even in an environment of 175° C. or lower, for example. The semiconductor chip 10a is specifically a diode chip or a transistor chip, for example.

Next, the shape of the semiconductor chip 10a will be described. 1, 2, 3, 4 and 5, semiconductor chip 10a is plate-shaped. The thickness direction of the semiconductor chip 10a is indicated by the direction indicated by the arrow Z or its opposite direction. A plane perpendicular to the thickness direction of the semiconductor chip 10a is defined as an XY plane. The X direction indicated by the arrow X or its opposite direction is the horizontal direction of the semiconductor chip 10a, and the Y direction indicated by the arrow Y or its opposite direction is the vertical direction of the semiconductor chip 10a. .

The semiconductor chip 10a has a rectangular shape when viewed in the thickness direction. Specifically, the semiconductor chip 10a has a square shape when viewed in the thickness direction. The semiconductor chip 10a has a first main surface 11a positioned on one side in the thickness direction, a second main surface 12a positioned on the other side in the thickness direction, and the first main surface 11a and the second main surface 12a. a first side 13a, a second side 14a, a third side 15a and a fourth side 16a respectively contiguous with. That is, the semiconductor chip 10a includes four side surfaces. The first side surface 13a and the third side surface 15a are each parallel to the XZ plane and spaced apart in the Y direction. The second side 14a and the fourth side 16a are each parallel to the YZ plane and spaced apart in the X direction. The side surfaces 13a, 14a, 15a, 16a and the second main surface 12a are orthogonal to each other. When viewed in the thickness direction, the X-direction length L1 of the semiconductor chip 10a is the length from the _second side surface 14a to the fourth side surface 16a. The length L2 of the semiconductor chip 10a in the Y direction is the length from the _first side surface 13a to the third side surface 15a, and is _equal to the length L1.

The second main surface 12a is planar (see FIG. 3 in particular). The external shape of the second main surface 12a has four sides 21a, 22a, 23a and 24a and four corners 26a, 27a, 28a and 29a when the semiconductor chip 10a is viewed in the thickness direction. The side 21a is located at the intersection of the second main surface 12a and the first side surface 13a. The side 22a is located at the intersection of the second main surface 12a and the second side surface 14a. The side 23a is located at the intersection of the second main surface 12a and the third side surface 15a. The side 24a is located at the intersection of the second main surface 12a and the fourth side surface 16a. Side 21a and side 23a are parallel. Side 22a and side 24a are parallel. The side 21a and the sides 22a and 24a are orthogonal to each other. The side 23a and the sides 22a and 24a are orthogonal to each other. The angle of the corner 26a where the side 21a and the side 24a intersect is 90 degrees. The angle of the corner 27a where the side 21a and the side 22a intersect is 90 degrees. The angle of the corner 28a where the side 22a and the side 23a intersect is 90 degrees. The angle of the corner 29a where the side 23a and the side 24a intersect is 90 degrees. That is, the angles of the four corners 26a, 27a, 28a, and 29a of the second main surface 12a are right angles.

The first main surface 11a includes an active region 17a, a termination region 18a located further outward than an outer edge 25a of the active region 17a, and a dicing region 19a located further outward than an outer edge 35a of the termination region 18a. include. An outer edge 25a of the active region 17a is indicated by a dashed line. An outer edge 35a of the termination region 18a is indicated by a two-dot chain line. Various layers for functioning as the semiconductor chip 10a, such as an operating layer made of SiC, are formed in the active region 17a. Active region 17a is arranged in the center of first main surface 11a. The active region 17a also has a rectangular shape when viewed in the thickness direction of the semiconductor chip 10a. A field stop layer is formed in the termination region 18a. Termination region 18a is arranged to surround active region 17a. The active region 17a and the termination region 18a are sometimes called a device region. Dicing region 19a is arranged to surround termination region 18a. The dicing region 19a is arranged on the outermost side of the semiconductor chip 10a. The dicing region 19a is a region provided as a cutting allowance when forming a plurality of semiconductor chips 10a on a substrate described later and dicing each semiconductor chip 10a into chips. That is, the dicing region 19a is formed by, for example, forming a plurality of active regions 17a and terminal regions 18a on a disk-shaped substrate with a space therebetween, and cutting the semiconductor chips 10a by a dicing blade. This is the remaining area. The thickness T1 of the active region 17a in the semiconductor chip 10a is indicated by the length in the Z direction from the _first main surface 11a to the second main surface 12a.

When the semiconductor chip 10a is viewed in the thickness direction from the first main surface 11a side, the outer edges 31a, 32a, 33a and 34a of the first main surface 11a are the outer edges 31a, 32a, 33a and 34a of the dicing region 19a. , outer edges 31a, 32a, 33a and 34a of the semiconductor chip 10a.

Here, when viewed in the thickness direction of the semiconductor chip 10a, the dicing region 19a includes four corner regions 41a, 42a, 43a and 44a corresponding to the four corners 36a, 37a, 38a and 39a of the semiconductor chip 10a. include. The thickness of the corner regions 41a, 42a, 43a, 44a decreases toward the outer edges 31a, 32a, 33a, 34a of the dicing region 19a. In the present embodiment, each of the corner regions 41a, 42a, 43a, 44a is a recess recessed from the first main surface 11a. The first surfaces 46a, 47a, 48a, and 49a forming the corner regions 41a, 42a, 43a, and 44a are shaped to form part of a spherical surface. The first surface 46a continues to the first main surface 11a, the first side surface 13a, and the second side surface 14a. The first surface 47a continues to the first main surface 11a, the second side surface 14a, and the third side surface 15a. The first surface 48a continues to the first main surface 11a, the third side surface 15a, and the fourth side surface 16a. The first surface 49a continues to the first main surface 11a, the first side surface 13a, and the fourth side surface 16a.

The corner regions 41a, 42a, 43a, 44a respectively have arcuate first surfaces 46a, 47a, 48a, 49a when viewed from the side surfaces 13a, 14a, 15a, 16a. In FIG. 4, a value of 5 μm or more and 150 μm or less is selected as the radius _R1 of the first surface 46a which is a circular arc surface. The first surfaces 46a, 47a, 48a, and 49a are recessed toward the inside of the semiconductor chip 10a. That is, the rate at which the thicknesses of the corner regions 41a, 42a, 43a, and 44a decrease as they approach the outer edges 31a, 32a, 33a, and 34a decreases. Further, the thickness T2 of the outer edges 31a, 32a, 33a, 34a of the dicing region 19a in the corner regions 41a, 42a, 43a, 44a is 50 μm or _more and 350 μm or less. _The ratio of the thickness T2 of the outer edges 31a, 32a, 33a, and 34a of the dicing region 19a in the corner regions 41a, 42a, 43a, and 44a to the thickness T1 of the active region 17a is not less _than 0.5 and less than 1.0. may be

According to the semiconductor chip of the present disclosure, the thickness of the corner regions 41a, 42a, 43a, 44a decreases toward the outer edges 31a, 32a, 33a, 34a of the dicing region 19a. It is possible to reduce the risk of forming corners. Then, in a state where the semiconductor chip 10a is sealed with the resin material, the concentration of thermal stress can be alleviated, and the risk of the resin material peeling off from the semiconductor chip 10a can be reduced. Therefore, when it is provided in a semiconductor device, it is possible to reduce the possibility of a decrease in dielectric strength voltage, and to improve reliability.

In this embodiment, the corner regions 41a, 42a, 43a, 44a have arcuate first surfaces 46a, 47a, 48a, 49a when viewed from the side surfaces 13a, 14a, 15a, 16a. Therefore, the first surfaces 46a, 47a, 48a, and 49a can be configured without corners. Therefore, stress concentration in the corner regions 41a, 42a, 43a, and 44a can be further alleviated, and reliability can be further improved.

In this embodiment, the first surfaces 46a, 47a, 48a, and 49a are recessed toward the inside of the semiconductor chip 10a. Therefore, the semiconductor chip 10a including the first surfaces 46a, 47a, 48a and 49a can be easily manufactured. This will be discussed later.

_In this embodiment, the thickness T2 of the outer edges 31a, 32a, 33a, 34a of the dicing region 19a in the corner regions 41a, 42a, 43a, 44a is 50 μm or more and 350 μm or less. Therefore, stress concentration can be alleviated while suppressing cracking and chipping of the semiconductor chip 10a while ensuring the strength of the semiconductor chip 10a.

_In the present embodiment, the _ratio of the thickness T2 of the outer edges 31a, 32a, 33a, 34a of the dicing region 19a in the corner regions 41a, 42a, 43a, 44a to the thickness T1 of the active region 17a is 0.5. It is 5 or more and less than 1.0. Therefore, it is possible to secure the strength of the semiconductor chip 10a according to the thickness of the active region 17a and to alleviate the stress concentration.

In this embodiment, the corner regions 41a, 42a, 43a, and 44a are provided at all four corners of the semiconductor chip 10a. Therefore, stress concentration can be alleviated in all the corner regions 41a, 42a, 43a, and 44a. Therefore, reliability can be improved more.

In this embodiment, the angles of the four corners 26a, 27a, 28a, 29a of the second main surface 12a are right angles. Therefore, it is possible to prevent the area of the second main surface 12a from being reduced, and to secure a large contact area with the second main surface 12a when the semiconductor chip 10a is bonded onto the substrate. Therefore, the semiconductor chip 10a can be more reliably bonded to the substrate, and reliability can be improved.

In this embodiment, the side surfaces 13a, 14a, 15a, 16a and the second main surface 12a are orthogonal to each other. Therefore, it is possible to prevent the area of the second main surface 12a from being reduced, and to secure a large contact area with the second main surface 12a when the semiconductor chip 10a is bonded onto the substrate. Therefore, the semiconductor chip 10a can be more reliably bonded to the substrate, and reliability can be improved.

Further, a semiconductor device 50a of the present disclosure includes the above-described semiconductor chip 10a and a resin portion 51a. The material of the resin portion 51a is, for example, epoxy resin. The resin portion 51a is arranged in close contact with the first main surface 11a and the side surfaces 13a, 14a, 15a, 16a of the semiconductor chip 10a. The resin portion 51a seals the semiconductor chip 10a.

According to such a semiconductor device 50a, since the semiconductor chip 10a described above is included, it is possible to reduce the possibility that the resin portion 51a is peeled off from the semiconductor chip 10a, thereby improving the reliability.

Next, a method for manufacturing the above-described semiconductor chip 10a will be described. FIG. 6 is a flow chart showing typical steps of a method for manufacturing semiconductor chip 10a according to the first embodiment shown in FIG.

Referring to FIG. 6, first, in the method of manufacturing semiconductor chip 10a according to the first embodiment, a substrate preparation step is performed as step (S10). In this step (S10), a semiconductor substrate made of disk-shaped SiC, also called a wafer, is prepared. A semiconductor substrate having an area capable of forming a plurality of semiconductor chips is prepared.

Next, as step (S20), an active region, termination region and dicing region formation step is performed. In this step (S20), a plurality of active regions, a plurality of termination regions and a plurality of dicing regions are formed on one surface of the semiconductor substrate such that strip-shaped dicing regions are arranged between adjacent termination regions. . FIG. 7 is a schematic perspective view showing a portion of a semiconductor substrate in which active regions, termination regions and dicing regions are formed. 7, one surface 53a of a semiconductor substrate 52a has four active regions 61a, 62a, 63a and 64a, four terminal regions 66a, 67a, 68a and 69a and two dicing regions 54a and 55a. formed. As for the active regions 61a, 62a, 63a, 64a and the terminal regions 66a, 67a, 68a, 69a, which are the device regions, the terminal regions 66a, 67a, 68a are formed so as to surround the respective active regions 61a, 62a, 63a, 64a. , 69a are provided. The end regions 66a, 67a, 68a, 69a are each spaced apart. The four active regions 61a, 62a, 63a, 64a, the four termination regions 66a, 67a, 68a, 69a and 2 are arranged so that the strip-shaped dicing regions 54a, 55a are arranged between the termination regions 66a, 67a, 68a, 69a. Two dicing regions 54a and 55a are formed. The dicing region 54a has a strip shape extending in the X direction. The dicing region 55a has a strip shape extending in the Y direction. Dicing region 54a and dicing region 55a intersect at region 56a.

Next, as a step (S30), a depression forming step is performed. In this step (S30), a recess is formed in the dicing region. FIG. 8 is a schematic perspective view showing a part of the semiconductor substrate in which the depression is formed. FIG. 9 is a schematic cross-sectional view showing a part of the semiconductor substrate in which the depression is formed. 9 is a cross-sectional view taken along the line IX-IX in FIG. 8. FIG. 8 and 9, recess 57a is formed in region 56a where dicing region 54a and dicing region 55a intersect. The depression 57a is formed by digging a region 56a of the semiconductor substrate 52a from one surface 53a of the semiconductor substrate 52a into a hemispherical shape using a laser dicing apparatus. The depression 57a does not penetrate the semiconductor substrate 52a.

Next, as a step (S40), a dicing step is performed. In this step (S40), the dicing region is diced so that the dent is included in the dicing region. FIG. 10 is a schematic perspective view showing a portion of the semiconductor substrate during the dicing process. Referring to FIG. 10, in the dicing step, dicing is performed along dashed lines 58a extending in the X direction and dashed lines 59a extending in the Y direction. Dashed lines 58a and 59a each have a width corresponding to the thickness of the dicing blade. The point where the dashed line 58a and the dashed line 59a intersect is the depression 57a, specifically, the bottommost portion of the depression 57a. In this manner, a plurality of semiconductor chips 10a are produced by dicing the active regions 61a, 62a, 63a, 64a and the terminal regions 66a, 67a, 68a, 69a with the laser dicing apparatus. The resulting semiconductor chip 10a is diced with the recesses 57a formed in the dicing regions 54a and 55a. It becomes the shape shown in form 1.

Thus, the semiconductor chip 10a is manufactured. According to such a method for manufacturing the semiconductor chip 10a, the semiconductor chip 10a having the shape described above can be manufactured easily and efficiently.

The semiconductor chip can also be manufactured as follows. FIG. 11 is a flow chart showing typical steps of a semiconductor chip manufacturing method according to another embodiment.

Referring to FIG. 11, first, as a step (S50), a substrate preparation step is performed. In this step (S50), first, a semiconductor substrate made of disk-shaped SiC, which is also called a wafer, is prepared in the same manner as in the above-described step (S10).

Next, as a step (S60), a dicing region forming step is performed. In this step (S60), one surface of the semiconductor substrate is diced halfway in the thickness direction of the semiconductor substrate to form a strip-shaped dicing region.

Next, as step (S70), a device region forming step, that is, a step of forming an active region and a termination region is performed. In this step (S70), an active region and a termination region, which are device regions, are respectively formed in a plurality of regions partitioned by the dicing regions.

Next, as a step (S80), a depression forming step is performed. In this step (S80),
A recess is formed in the dicing area. FIG. 12 is a schematic cross-sectional view showing a state in which a recess is formed in the semiconductor substrate. Referring to FIG. 12, a device region 74a including a JTE (Junction Termination Extension) region 72a and a field stop region 73a is formed on one surface 71a of a semiconductor substrate 70a. A GR (Guard Ring) region may be formed instead of the JTE region 72a. A dicing region 75a is formed between the device region 74a and the field stop region 73a. The dicing region 75a is cut one step lower in the dicing region forming process, and the dicing region 75a is in a state of being dug down one step from the device region 74a. A recess 76a is formed in the dicing region 75a.

Next, as a step (S90), a dicing step is performed. In this step (S90), the dicing region 75a in which the depression 76a is formed is diced.

Thus, a semiconductor chip is manufactured. According to such a semiconductor chip manufacturing method, a semiconductor chip having the above-described shape can be manufactured easily and efficiently.

(Embodiment 2)
Next, Embodiment 2, which is another embodiment, will be described. FIG. 13 is a schematic side view showing part of the semiconductor chip in the second embodiment. The semiconductor chip of the second embodiment differs from that of the first embodiment in that the shape of the corner region is different.

Referring to FIG. 13, in semiconductor chip 10b according to the second embodiment, corner region 41a has an arcuate first surface 46b when viewed from side surface 13a. The first surface 46b has a shape protruding outward from the semiconductor chip 10b. That is, the rate at which the thickness of the corner region 41a decreases increases as it approaches the outer edge. By doing so, the concentration of stress can also be alleviated.

(Embodiment 3)
Next, Embodiment 3, which is still another embodiment, will be described. FIG. 14 is a schematic side view showing part of the semiconductor chip according to the third embodiment. The semiconductor chip of the third embodiment differs from those of the first and second embodiments in that the shape of the corner region is different.

Referring to FIG. 14, in semiconductor chip 10c according to the third embodiment, corner region 41a has a planar second surface 46c when viewed from side surface 13a. Due to this second surface 46c, the thickness of the corner region 41a is reduced toward the outer edge of the dicing region. By doing so, it is possible to reduce the risk of the semiconductor chip 10c having sharp corners. Therefore, stress concentration can be relaxed. Moreover, the semiconductor chip 10c having such a shape can be easily manufactured.

(Embodiment 4)
Next, Embodiment 4, which is still another embodiment, will be described. FIG. 15 is a schematic plan view of a semiconductor chip according to Embodiment 4. FIG. 16 is a schematic plan view showing an enlarged part of the semiconductor chip shown in FIG. 15. FIG. The semiconductor chip of the fourth embodiment differs from that of the first embodiment in that the shape of the corner region is different.

15 and 16, semiconductor chip 10d in the fourth embodiment includes corner region 41a forming the outer edge of dicing region 19a. The corner region 41a is inside the intersection 83a between the first extension line 86a and the second extension line 87a when viewed in the thickness direction of the semiconductor chip 10d. The first extension line 86a extends in the first direction and is an extension of the first line 81a forming the outer edge 31a of the dicing region 19a. The second extension line 87a extends in a second direction orthogonal to the first direction and is a line obtained by extending the second line 82a forming the outer edge 32a of the dicing region 19a. The same applies to the other corner regions 42a, 43a, 44a. Here, the inner side of the intersection point 83a means the side closer to the center of the semiconductor chip 10d than the intersection point 83a when viewed in the thickness direction of the semiconductor chip 10d.

Further, the corner regions 41a, 42a, 43a, 44a have arcuate third surfaces 46d, 47d, 48d, 49d when viewed in the thickness direction of the semiconductor chip 10d. The third surface 46d has a shape recessed toward the inside of the semiconductor chip 10d. In FIG. 16, when viewed in the thickness direction of the semiconductor chip 10d, the length from the intersection 83a between the first extension line 86a and the second extension line 87a to the corner region 41a is 5 μm or more and 100 μm or less.

With this configuration, the corner regions 41a, 42a, 43a, and 44a are located inside the intersection point 83a between the first extension line 86a and the second extension line 87a, so that the semiconductor chip 10d has an acute angle. It is possible to reduce the risk of forming corners, and to alleviate stress concentration. By doing so, it is possible to reduce the risk of peeling of the resin material starting from the sharp corners. Therefore, when it is provided in a semiconductor device, it is possible to reduce the possibility of a decrease in dielectric strength voltage, and to improve reliability.

In this embodiment, the corner regions 41a, 42a, 43a, 44a have arcuate third surfaces 46d, 47d, 48d, 49d when viewed in the thickness direction of the semiconductor chip 10d. Therefore, since the third surfaces 46d, 47d, 48d, and 49d do not include sharp corners, stress concentration in the corner regions 41a, 42a, 43a, and 44a can be further alleviated, further improving reliability. can be achieved.

In this embodiment, the third surfaces 46d, 47d, 48d, and 49d have a shape recessed toward the inside of the semiconductor chip. Therefore, it is possible to easily manufacture the semiconductor chip 10d including the third surfaces 46d, 47d, 48d and 49d described above.

In this embodiment, when viewed in the thickness direction of the semiconductor chip 10d, the length from the intersection 83a between the first extension line 86a and the second extension line 87a to the corner region 41a is 5 μm or more and 100 μm or less. be. Therefore, the stress applied to the corner regions 41a, 42a, 43a, 44a can be relaxed.

(Embodiment 5)
Next, Embodiment 5, which is still another embodiment, will be described. FIG. 17 is a schematic plan view showing part of a semiconductor chip according to the fifth embodiment. FIG. 17 differs from Embodiment 4 in that the shape of the corner region is different.

Referring to FIG. 17, in semiconductor chip 10e according to the fifth embodiment, corner region 41a has an arcuate third surface 46e when viewed in the thickness direction of semiconductor chip 10e. The third surface 46e has a shape protruding outward from the semiconductor chip 10e. By doing so, the concentration of stress can also be alleviated.

(Embodiment 6)
Next, Embodiment 6, which is still another embodiment, will be described. FIG. 18 is a schematic plan view showing part of a semiconductor chip according to the sixth embodiment. FIG. 18 differs from Embodiments 4 and 5 in that the shape of the corner region is different.

Referring to FIG. 18, in semiconductor chip 10f according to the sixth embodiment, corner region 41a has a planar fourth surface 46f when viewed in the thickness direction of semiconductor chip 10f. Therefore, it is possible to reduce the possibility that the semiconductor chip 10f has a sharp corner. Also, the semiconductor chip 10f having such a shape can be easily manufactured.

(Embodiment 7)
Next, Embodiment 7, which is still another embodiment, will be described. FIG. 19 is a schematic perspective view of a semiconductor chip according to Embodiment 7. FIG. The semiconductor chip of the seventh embodiment differs from that of the first embodiment in that the recesses are continuous in the circumferential direction.

Referring to FIG. 19, in semiconductor chip 10g according to the seventh embodiment, dicing region 19a includes thin regions 84a whose thickness decreases toward outer edges 31a, 32a, 33a and 34a of dicing region 19a. The thin region 84a is provided over the entire circumference of the outer edges 31a, 32a, 33a, 34a of the dicing region 19a. By doing so, it is possible to further suppress the occurrence of corners where stress is concentrated. Therefore, reliability can be further improved.

The semiconductor chip 10g having such a configuration is manufactured, for example, as follows. FIG. 20 is a schematic perspective view showing part of the semiconductor substrate before dicing. Referring to FIG. 20, on one surface 53a of a semiconductor substrate 52a, grooves 88a and 89a corresponding to thin regions 84a are previously formed in portions corresponding to dicing regions 54a and 55a. By dicing along broken lines 58a and 59a, the semiconductor chip 10g of the seventh embodiment shown in FIG. 19 can be easily manufactured.

(Other embodiments)
In the above embodiment, the thickness of the four corner regions is reduced toward the outer edge of the dicing region. It may be smaller towards the outer edge of the region. That is, in any one corner region, it may become smaller toward the outer edge of the dicing region.

Further, in the above embodiments, the semiconductor chip has a square shape when viewed in the thickness direction. It is also possible to have

In the above embodiment, the arc-shaped depression is formed, but the present invention is not limited to this, and the depression may be formed by other curved surfaces, or may be a depression including a flat surface and a curved surface. may be Also, after dicing into chips, the chip may be processed into a shape having the recesses described above.

It should be understood that the embodiments disclosed this time are illustrative in all respects and are not restrictive in any aspect. The scope of the present invention is defined by the scope of the claims rather than the above description, and is intended to include all modifications within the meaning and range of equivalents of the scope of the claims.

A semiconductor chip, a semiconductor device, and a method for manufacturing a semiconductor chip according to the present disclosure can be applied particularly advantageously when improvement in reliability is required.

10a, 10b, 10c, 10d, 10e, 10f, 10g semiconductor device 11a first main surface 12a second main surface 13a, 14a, 15a, 16a side surfaces 17a, 61a, 62a, 63a, 64a active regions 18a, 66a, 67a, 68a, 69a end regions 19a, 54a, 55a, 75a dicing regions 21a, 22a, 23a, 24a sides 25a, 31a, 32a, 33a, 34a, 35a outer edges 26a, 27a, 28a, 29a, 36a, 37a, 38a, 39a corners 41a, 42a, 43a, 44a corner regions 46a, 46b, 47a, 48a, 49a first surface 46c second surfaces 46a, 46b, 47a, 48a, 49a third surface 46f fourth surface 50a Semiconductor device 51a Resin portions 52a, 70a Semiconductor substrate 53a, 71a Surfaces 56a, 72a Regions 58a, 59a Broken line 73a Field stop region 74a Device region 81a First line 82a Second line 83a Intersection 84a Thin region 86a First extension line 87a _Second extension lines 88a, 89a _Grooves L1, L2 Length _T1 , T2 Thickness _R1 , _{R2 Radius} X, Y, Z direction

Claims (20)

A semiconductor chip having a plate shape and a rectangular shape when viewed in a thickness direction,
a first main surface located on one side in the thickness direction;
a second main surface located on the other side in the thickness direction;
a side surface contiguous with the first main surface and the second main surface;
The first main surface is
an active region;
a termination region located on the outer peripheral side of the outer edge of the active region;
a dicing region located on the outer peripheral side of the outer edge of the termination region,
When viewed in the thickness direction of the semiconductor chip, the dicing region includes four corner regions corresponding to the four corners of the semiconductor chip,
The semiconductor chip, wherein the thickness of at least one of the corner regions decreases toward the outer edge of the dicing region. 2. The semiconductor chip according to claim 1, wherein said corner region has an arc-shaped first surface when viewed from said side surface. 3. The semiconductor chip according to claim 2, wherein said first surface has a shape recessed toward the inside of said semiconductor chip. 2. The semiconductor chip according to claim 1, wherein said corner region has a planar second surface when viewed from said side surface. 5. The semiconductor chip according to claim 1, wherein the thickness of the outer edge of said dicing region in said corner region is 50 [mu]m or more and 350 [mu]m or less. 6. The semiconductor according to claim 1, wherein a ratio of the thickness of the outer edge of said dicing region to the thickness of said active region in said corner region is 0.5 or more and less than 1.0. chips. A plate-like semiconductor chip,
a first main surface located on one side in the thickness direction;
a second main surface located on the other side in the thickness direction;
a side surface contiguous with the first main surface and the second main surface;
The first main surface is
an active region;
a termination region located on the outer peripheral side of the outer edge of the active region;
a dicing region located on the outer peripheral side of the outer edge of the termination region,
The semiconductor chip is
Including a corner region forming the outer edge of the dicing region,
the corner region is located inside an intersection of a first extension line and a second extension line when viewed in the thickness direction of the semiconductor chip;
The first extension line is a line extending in the first direction and extending from the first line forming the outer edge of the dicing region,
The semiconductor chip, wherein the second extension line extends in a second direction orthogonal to the first direction and is a line obtained by extending a second line forming an outer edge of the dicing region. 8. The semiconductor chip according to claim 7, wherein said corner region has an arcuate third surface when viewed in the thickness direction of said semiconductor chip. 9. The semiconductor chip according to claim 8, wherein said third surface has a shape recessed toward the inside of said semiconductor chip. 8. The semiconductor chip according to claim 7, wherein said corner region has a planar fourth surface when viewed in the thickness direction of said semiconductor chip. 7. The length from the intersection of the first extension line and the second extension line to the corner region when viewed in the thickness direction of the semiconductor chip is 5 μm or more and 100 μm or less. Item 11. The semiconductor chip according to any one of Item 10. 12. The semiconductor chip according to claim 1, wherein said corner regions are provided at all four corners of said semiconductor chip. 13. The semiconductor chip according to claim 1, wherein angles of four corners of said second main surface are each right angles. 14. The semiconductor chip according to claim 1, wherein said side surface and said second main surface are perpendicular to each other. A semiconductor chip having a plate shape and a rectangular shape when viewed in a thickness direction,
a first main surface located on one side in the thickness direction;
a second main surface located on the other side in the thickness direction;
a side surface contiguous with the first main surface and the second main surface;
The first main surface is
an active region;
a termination region located on the outer peripheral side of the outer edge of the active region;
a dicing region located on the outer peripheral side of the outer edge of the termination region,
The dicing region includes a thin region whose thickness decreases toward the outer edge of the dicing region,
The semiconductor chip, wherein the thin region is provided along the entire circumference of the outer edge of the dicing region. 16. The semiconductor chip according to claim 1, wherein said semiconductor chip is a wide bandgap semiconductor. 17. The semiconductor chip according to any one of claims 1 to 16, wherein the operating layer of said semiconductor chip is composed of at least one of SiC and GaN. A semiconductor chip according to any one of claims 1 to 17;
and a resin portion that seals the semiconductor chip. A method for manufacturing a semiconductor chip having a plate shape and a rectangular shape when viewed in a thickness direction,
The semiconductor chip is
a first main surface located on one side in the thickness direction;
a second main surface located on the other side in the thickness direction;
a side surface contiguous with the first main surface and the second main surface;
The first main surface is
an active region;
a termination region located on the outer peripheral side of the outer edge of the active region;
a dicing region located on the outer peripheral side of the outer edge of the termination region,
The method for manufacturing the semiconductor chip comprises:
preparing a semiconductor substrate;
forming a plurality of the active regions, a plurality of the termination regions and a plurality of the dicing regions such that the band-shaped dicing regions are arranged between the adjacent termination regions on one surface of the semiconductor substrate; ,
forming a recess in the dicing region;
dicing the dicing region so that the recess is included in the dicing region. A method for manufacturing a semiconductor chip having a plate shape and a rectangular shape when viewed in a thickness direction,
The semiconductor chip is
a first main surface located on one side in the thickness direction;
a second main surface located on the other side in the thickness direction;
a side surface contiguous with the first main surface and the second main surface;
The first main surface is
an active region;
a termination region located on the outer peripheral side of the outer edge of the active region;
a dicing region located on the outer peripheral side of the outer edge of the termination region,
The method for manufacturing the semiconductor chip comprises:
preparing a semiconductor substrate;
a step of dicing halfway in the thickness direction of the semiconductor substrate on one surface of the semiconductor substrate to form a strip-shaped dicing region;
forming the active region and the termination region respectively in a plurality of regions partitioned by the dicing region;
forming a recess in the dicing region;
and a step of dicing the dicing region in which the recess is formed.

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