JP2023007361A - Ternary inverter and manufacturing method thereof - Google Patents

Abstract

A ternary inverter that occupies a small area and has high energy efficiency and a method for manufacturing the same are provided. A ternary inverter (10) includes a first source (S1) and a first drain (D1), an interlayer insulating film (340) positioned on the first source, and a second source (S2) and a second drain positioned on the interlayer insulating layer. D2, a first channel C1 interposed between the first source and the first drain, separated from the first channel and located above the first channel and interposed between the second source and the second drain; the gate insulating film 320 covering the second channel C2, the outer side surface of the first channel, and the outer side surface of the second channel; and a gate electrode G interposed therebetween. [Selection drawing] Fig. 1

Description

The present invention relates to a ternary inverter and a manufacturing method thereof, and more particularly, to a ternary inverter that occupies a small area and has high energy efficiency and a manufacturing method thereof.

2. Description of the Related Art Conventionally, binary logic-based digital systems have focused on increasing bit density through miniaturization of CMOS devices in order to rapidly process a large amount of data. However, recently, even with the integration under 30 nm, there is a limit to increase the information density due to leakage current and increased power consumption due to quantum tunneling effect. In order to overcome the limitation of information density, interest in ternary logic elements and circuits thereof, which are one of multi-valued logics, is rapidly increasing. There is active development into the Standard Ternary Inverter (STI) as the basic unit for . However, unlike existing binary inverters that use two CMOS for one voltage source, the prior art involving standard ternary inverters requires more voltage sources, complex circuitry, There is a problem that the area occupied is large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a ternary inverter that occupies a small area and has high energy efficiency, and a method of manufacturing the same. . However, such issues are exemplary and are not intended to limit the scope of the invention.

According to one aspect of the present invention, a first source and a first drain spaced apart from each other; an interlayer insulating layer positioned on the first source; a second source positioned on the interlayer insulating layer; a second drain positioned above the first drain; interposed between the first source and the first drain, the 1-1 end face in the direction of the first source being in contact with the first source; a first channel having a 1-2 end surface in a first drain direction contacting the first drain; separated from the first channel and positioned above the first channel; the second source and the second channel; The 2-1 end face in the direction of the second source contacts the second source, and the 2-2 end face in the direction of the second drain is interposed between the drain and the second drain. the outer surface of the first channel, the outer surface of the second channel, and the surface of the first source facing the first drain, other than the portion that contacts the first channel. , a portion of the surface of the second source in the second drain direction other than the portion in contact with the second channel, and a surface of the first drain in the first source direction of the first a gate insulating film covering a portion other than the portion in contact with the channel, and a portion of the surface of the second drain facing the second source in the direction other than the portion in contact with the second channel; and the first source; a gate electrode interposed between the first drain and between the second source and the second drain; a ternary inverter is provided.

The first source and the second source are also doped with different conductivity types.

The first drain and the first source are also doped with different conductivity types.

The first drain and the second drain are also doped with different conductivity types.

The gate electrode may fill between the first channel and the second channel.

The gate electrode may surround a portion of the gate insulating layer surrounding the first channel and a portion of the gate insulating layer surrounding the second channel.

A constant current forming layer is further provided, and the first source and the first drain are also located on the constant current forming layer.

According to another aspect of the invention, a first sacrificial layer on a substrate, a first channel on the first sacrificial layer, a second sacrificial layer on the first channel, and a second sacrificial layer on the second sacrificial layer. forming a gate structure extending in a first direction including a channel and a third sacrificial layer over the second channel; forming a gate structure extending in a second direction intersecting the first direction; forming intersecting dummy gates; forming a first source on one side of the dummy gates contacting the 1-1 end surface of the first channel, and forming a first channel on the other side of the dummy gates; forming a first drain contacting the 1-2 end face of the second channel; forming an interlayer insulating layer on the first source; forming an interlayer insulating layer on the interlayer insulating layer; forming a second source in contact with the edge surface and forming a second drain on the first drain in contact with the 2-2 edge surface of the second channel; removing the dummy gate; removing the first sacrificial layer, the second sacrificial layer and the third sacrificial layer; the outer surface of the first channel; the outer surface of the second channel; Of the portion other than the portion in contact with the first channel, the surface of the second source in the second drain direction, the portion other than the portion in contact with the second channel, and the surface of the first drain in the first source direction, forming a gate insulating film covering a portion other than the portion in contact with the first channel and the portion other than the portion in contact with the second channel on the surface of the second drain in the second source direction; A method is provided for fabricating a ternary inverter including forming a source and a first drain and a gate electrode interposed between the second source and the second drain.

The method may further include doping the first source and the first drain to different conductivity types.

The method may further include doping the second source to a conductivity type different from the first source and doping the second drain to a conductivity type different from the first drain.

forming the gate electrode to fill the space from which the dummy gate is removed between the first source and the first drain and between the second source and the second drain; It is also a stage to

The step of forming the gate electrode is also the step of forming the gate electrode to surround a portion of the gate insulating layer surrounding the first channel and a portion of the gate insulating layer surrounding the second channel.

Other aspects, features and advantages than those mentioned above will become apparent from the following detailed description, claims and drawings.

According to an embodiment of the present invention as described above, it is possible to implement a ternary inverter that occupies a small area and has high energy efficiency and a method of manufacturing the same. It goes without saying that the scope of the present invention is not limited by such effects.

1 is a perspective view schematically illustrating a ternary inverter according to one embodiment of the present invention; FIG. FIG. 2 is a cross-sectional view schematically illustrating a cross section taken along line A-A' of FIG. 1; FIG. 2 is a cross-sectional view schematically illustrating a cross-section taken along line B-B' of FIG. 1; 2 is an equivalent circuit diagram of the ternary inverter of FIG. 1; FIG. 2 is a gate voltage-drain current graph of the ternary inverter of FIG. 1 and a conventional binary inverter; 2 is an input voltage (V _IN ) versus output voltage (V _OUT ) graph of the ternary inverter of FIG. 1 and a conventional binary inverter; 4 is a graph showing voltage input/output characteristics of a ternary inverter according to an embodiment of the present invention; 2 is a perspective view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. 2 is a perspective view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. 2 is a perspective view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. 2 is a perspective view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. 2 is a perspective view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. FIG. 3 is a cross-sectional view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. 3 is a cross-sectional view for explaining a method of manufacturing the ternary inverter of FIG. 1; 2 is a perspective view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. FIG. 3 is a cross-sectional view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. 3 is a cross-sectional view for explaining a method of manufacturing the ternary inverter of FIG. 1; 2 is a perspective view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. FIG. 3 is a cross-sectional view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. 3 is a cross-sectional view for explaining a method of manufacturing the ternary inverter of FIG. 1; 2 is a perspective view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. FIG. 3 is a cross-sectional view for explaining a method of manufacturing the ternary inverter of FIG. 1; FIG. 3 is a cross-sectional view for explaining a method of manufacturing the ternary inverter of FIG. 1;

Although the present invention is capable of various transformations and can have various embodiments, specific embodiments will be illustrated in the drawings and will be described in detail in the detailed description. The advantages and features of the present invention and the manner in which they are achieved will become apparent with reference to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Duplicate explanations related to this will be omitted.

In the following embodiments, when various components such as layers, films, regions, and plates are said to be "above" other components, it is only if they are "directly above" the other components. Instead, it also includes cases in which other components are interposed between them. Also, for convenience of explanation, the size of the constituent elements in the drawings may be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown.

In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes on the orthogonal coordinate system, but are also interpreted in a broader sense including them. For example, the x-, y-, and z-axes may be orthogonal to each other, or may refer to different directions without being orthogonal to each other.

FIG. 1 is a perspective view schematically illustrating a ternary inverter 10 according to one embodiment of the present invention, and FIG. 2 schematically illustrates a cross section taken along line AA' of FIG. 3 is a cross-sectional view schematically illustrating a cross-section taken along line BB' of FIG. 1; FIG.

A ternary inverter according to this embodiment is also formed on the substrate 100 . Substrate 100 is also a semiconductor substrate. For example, substrate 100 may comprise silicon (Si), Ge, SiGe, InGaAs or InAs. At this point, it should be understood that the present invention is not so limited, and that the substrate 100 may comprise a wide variety of other semiconductor materials. The substrate 100 can have a first conductivity type. The first conductivity type is also n-type or p-type. When the conductivity type of the substrate 100 is n-type, the substrate 100 may contain V group elements (eg, P or As) as impurities. If the conductivity type of the substrate 100 is p-type, the substrate 100 may contain Group III elements (eg, B or In) as impurities.

A constant current forming layer 200 may be formed on the substrate 100 if necessary. The constant current forming layer 200 is also an epitaxial layer formed by an epitaxial growth process. Such a constant current forming layer 200 may contain silicon (Si). The constant current forming layer 200 may have a first conductivity type. When the conductivity type of the constant current forming layer 200 is n-type, the constant current forming layer 200 may contain V group elements (for example, P or As) as impurities. When the conductivity type of the constant current forming layer 200 is p-type, the constant current forming layer 200 may contain III group elements (eg, B or In) as impurities. The doping concentration of the constant current forming layer 200 is higher than the doping concentration of the substrate 100 . For example, the doping concentration of the constant current forming layer 200 is 3×10 ¹⁸ cm ⁻³ or more.

A first source S1 and a first drain D1 may be spaced apart from each other on the constant current forming layer 200 . In FIG. 1, a first source S1 and a first drain D1 are shown to be spaced apart from each other along a first direction DR1 parallel to the top surface of the substrate 100. FIG. The first source S1 and the first drain D1 may include doped semiconductor material. For example, the first source S1 and the first drain D1 may comprise doped-poly Si. The first source S1 and the first drain D1 are also epitaxial layers.

The first source S1 and the first drain D1 may be doped with different conductivity types and have different conductivity types. For example, the first source S1 may have a first conductivity type and the first drain D1 may have a second conductivity type. If the first conductivity type is p-type, the second conductivity type is also n-type. For example, the first source S1 may contain Group III elements (eg, B or In) as impurities, and the first drain D1 may contain Group V elements (eg, P or As) as impurities.

The first source S1, the first drain D1, and the constant current formation layer 200 may be electrically connected to each other. For example, each of the first source S1 and the first drain D1 may be in direct contact with the constant current forming layer 200 . An electric field may be formed between the first source S<b>1 , the first drain D<b>1 and the constant current forming layer 200 . The strength of the electric field is also, for example, 10 ⁶ V/cm or more.

The constant current forming layer 200 can generate a constant current between one of the first source S<b>1 and the first drain D<b>1 and the substrate 100 . The constant current is also a BTBT (band-to-band tunneling) current flowing between the first drain D1 and the substrate 100 . Such a constant current is also independent of the gate voltage applied to the gate electrode G. That is, a constant current can flow regardless of the gate voltage. Since the first source S1 is p-type and the first drain D1 is n-type, when the first source S1, the first drain D1 and the gate electrode G constitute an NMOS transistor, the constant current is applied to the first drain From D, it can flow to the substrate 100 via the constant current forming layer 200 . If the first source S1, the first drain D1 and the gate electrode G form a PMOS transistor, the constant current flows from the substrate 100 through the constant current forming layer 200 and also to the first drain D1.

An interlayer insulating layer 340 may be positioned on the first source S1. The interlayer dielectric layer 340 may include various insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, or metal oxides such as aluminum oxide. The interlayer dielectric layer 340 may have a single layer structure or a multi-layer structure.

A second source S2 is located on the interlayer insulating layer 340, and a second drain D2 is located on the first drain D1. The second source S2 and the second drain D2 are spaced apart from each other.

The second source S2 and the second drain D2 may be doped with different conductivity types and have different conductivity types. Also, the second source S2 may be doped with a conductivity type different from that of the first source S1 and may have a conductivity type different from each other. The second drain D2 may be doped with a conductivity type different from that of the first drain D1 and may have a conductivity type different from each other. For example, the second source S2 may have a second conductivity type and the second drain D2 may have a first conductivity type. If the first conductivity type is p-type, the second conductivity type is also n-type. For example, the second source S2 may contain a group V element (eg, P or As) as an impurity, and the second drain D2 may contain a group III element (eg, B or In) as an impurity.

As described above, the constant current forming layer 200 may be formed on the substrate 100 . In this case, an additional constant current forming layer having a conductivity type different from that of the constant current forming layer 200 may also be formed on the second drain D2.

A gate electrode G may be positioned on the constant current forming layer 200 . The gate electrode G may have a shape extending along the second direction DR2 parallel to the top surface 200u of the constant current forming layer 200. As shown in FIG. The gate electrode G also extends along a third direction DR3 perpendicular to the upper surface 200u of the constant current forming layer 200. As shown in FIG. The gate electrode G is also interposed between the first source S1 and the first drain D1 and between the second source S2 and the second drain D2. At this time, the gate electrode G may be separated from the first source S1, the second source S2, the first drain D1, and the second drain D2 in the first direction DR1. The gate electrode G may include an electrically conductive material. For example, the gate electrode G may comprise doped semiconductor materials, metals, alloys, or combinations thereof. For example, gate electrode G may comprise doped polysilicon, tungsten (W), titanium nitride (TiN), or combinations thereof.

In order to separate the gate electrode G from the first source S1, the second source S2, the first drain D1 and the second drain D2 in the first direction DR1, the first source S1 and the second source S2 and the gate electrode G A gate spacer 330 may be interposed between the first drain D1 and the second drain D2 and the gate electrode G. As shown in FIG. Such a pair of gate spacers 330 may be positioned on both sides of the gate electrode G in the first direction DR1.

A gate spacer 330 on one side of the gate electrode G opposite to the first direction DR1 may contact the first source S1 and the second source S2. A gate spacer 330 on the other side of the gate electrode G in the first direction DR1 may contact the first drain D1 and the second drain D2. Each of the pair of gate spacers 330 also extends along the third direction DR3 perpendicular to the top surface 200u of the constant current forming layer 200. As shown in FIG. For example, the distance from the upper surface 200u of the constant current forming layer 200 to the upper surface of each of the pair of gate spacers 330 in the third direction DR3 is It is also the same as the distance to the top surface of

Such gate spacers 330 may include various insulating materials. Gate spacers 330 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride, and may include metal oxides such as aluminum oxide.

It should be appreciated that in some cases such gate spacers 330 may be omitted.

A first channel C1 may be interposed between the first source S1 and the first drain D1. The first channel C1 may have a shape extending in the first direction DR1 and penetrating the gate electrode G. FIG. The 1-1 end face of the first channel C1 in the direction of the first source S1 (-DR1) is in contact with the first source S1, and the 1-2 end face in the direction of the first drain D1 (+DR1) of the first channel C1 is in contact with the first source S1. The end face contacts the first drain D1. Although one first channel C1 is shown interposed between the first source S1 and the first drain D1 in FIG. 1, the present invention is not limited thereto. For example, a plurality of first channels C1 may be arranged between the first source S1 and the first drain D1 and spaced apart in a third direction DR3 perpendicular to the top surface 200u of the constant current forming layer 200. FIG.

A second channel C2 may be interposed between the second source S2 and the second drain D2. The second channel C2 may have a shape extending in the first direction DR1 and penetrating the gate electrode G. FIG. The 2-1 end face of the second channel C2 in the direction of the second source S2 (-DR1) is in contact with the second source S2 and the 2-2 end face in the direction of the second drain D2 of the second channel C2 (+DR1). The end face contacts the second drain D2. Such a second channel C2 may be spaced apart from the first channel C1 and positioned above the first channel C1. Although one second channel C2 is shown interposed between the second source S2 and the second drain D2 in FIG. 1, the present invention is not limited thereto. For example, a plurality of second channels C2 spaced apart in a third direction DR3 perpendicular to the top surface 200u of the constant current forming layer 200 may be disposed between the second source S2 and the second drain D2.

The fact that the first channel C1 and the second channel C2 extend in the first direction DR1 and have a shape penetrating the gate electrode G means that the gate electrode G extends between the first channel C1 and the second channel C2. Also understood as filling. It is also understood that the gate electrode G surrounds a portion surrounding the first channel C1 and a portion surrounding the second channel C2 of the gate insulating film 320, which will be described later.

The first channel C1 and the second channel C2 may comprise semiconductor material. For example, the first channel C1 and the second channel C2 may contain silicon (Si). The first channel C1 may have a first conductivity type and the second channel C2 may have a second conductivity type. For example, the first conductivity type is p-type and the second conductivity type is also n-type. In that case, the first channel C1 may contain Group III elements (eg, B, In) as impurities, and the second channel C2 may contain Group V elements (eg, P, As) as impurities.

A gate insulating layer 320 may be located on the surface of the gate electrode G. As shown in FIG. The gate insulating layer 320 is formed between the gate electrode G and the first channel C1, between the gate electrode G and the second channel C2, between the gate electrode G and the gate spacer 330 located on one side of the gate electrode G, Between the gate electrode G and the gate spacer 330 positioned on the other side of the gate electrode G, between the gate electrode G and the first source S1, between the gate electrode G and the second source S2, between the gate electrode G and the first drain D 1 , between the gate electrode G and the second drain D 2 , and between the gate electrode G and the constant current forming layer 200 .

If the gate spacer 330 were not present, the gate insulating film 320 would cover the outer surface of the first channel C1, the outer surface of the second channel C2, and the surface of the first drain D1 direction DR1 of the first source S1. Of these, the portion other than the portion in contact with the first channel C1, the portion of the surface of the second source S2 in the second drain D2 direction DR1 other than the portion in contact with the second channel C2, and the first drain D1 of the first drain D1. 1 source S1 direction (−DR1) surface other than the portion contacting the first channel C1, and the second source S2 direction (−DR1) surface of the second drain D2, the second channel C2 A portion other than the contact portion and a portion of the upper surface of the constant current forming layer 200 corresponding to the gate electrode G can be covered.

As such, the gate insulating film 320 surrounds the outer surface of the first channel C1 and the outer surface of the second channel C2, and electrically insulates the gate electrode G from the first channel C1 and the second channel C2. be able to. The gate insulating film 320 can electrically insulate the gate electrode G from the gate spacer 330, the first source S1, the second source S2, the first drain D1, the second drain D2, and the constant current forming layer 200. can. For this purpose, the gate insulating layer 320 may include an insulating material. For example, the gate insulating layer 320 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

Such gate insulator 320 may comprise an insulating material having a high-k dielectric. For example, gate insulating layer 320 may include a material having a dielectric constant of approximately 10-25. For example, the gate insulating film 320 may be hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO). , zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO) , barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

In the case of such a ternary inverter according to this embodiment, a TFET formed by a first source S1, a first drain D1, a first channel C1 and a gate electrode G, a second source S2, a second drain D2 and a second channel Since C2 and the TFET formed by the gate electrode G are arranged vertically, it is possible to realize a ternary inverter with high energy efficiency while occupying a small area. In addition, since the first drain D1 and the second drain D2, which can be referred to as output terminals, are in direct contact with each other, the manufacturing process can be simplified and the electrical connection between them can be ensured. At this time, the TFET formed by the first source S1, the first drain D1, the first channel C1, and the gate electrode G is an n-type TFET, and the second source S2, the second drain D2, the second channel C2, and the gate electrode. The TFET formed by G is also a p-type TFET.

FIG. 4 is an equivalent circuit diagram of the ternary inverter 10 of FIG. As shown in FIG. 4, the ternary inverter 10 according to the present embodiment may include an NMOS transistor (hereinafter referred to as "n-type TFET") and a PMOS transistor (hereinafter referred to as "P-type TFET"). good. The n-type TFET corresponds to the first source S1, the first drain D1, the first channel C1 and the gate electrode G described with reference to FIG. 1, and the p-type TFET corresponds to the first source S1 described with reference to FIG. It can correspond to two sources S2, a second drain D2, a second channel C2 and a gate electrode G.

A ground voltage can be applied to the source and substrate of the n-type TFET that such a ternary inverter 10 comprises. That is, a ground voltage may be applied to the first source S1 of FIG. For simplicity of explanation, in the following it is assumed that the ground voltage is 0 volts (V). A drive voltage V _DD may be applied to the source of the p-type TFET. That is, the driving voltage _VDD may be applied to the second source S2 of FIG. An input voltage _V IN can be applied to each of the gate electrode of the n-type TFET and the gate electrode of the p-type TFET. That is, the input voltage _VIN can be applied to the gate electrode G of FIG.

The drain of the n-type TFET may be electrically connected to the drain of the p-type TFET and have the same voltage. In FIG. 1, the first drain D1 and the second drain D2 stacked vertically are shown as being in contact with each other. In FIG. 1, the voltage at the lower first drain D1 and the upper second drain D2 in contact therewith is also the output voltage V _OUT of the ternary inverter 10 .

A constant current can flow from the drain of the n-type TFET, ie, the first drain D1 to the substrate 100 . The constant current is also independent of the input voltage _VIN . As described above, if an additional constant current forming layer having a conductivity type different from that of the constant current forming layer 200 is also formed on the second drain D2, the additional constant current is generated from the drain of the p-type TFT, that is, the second drain D2. A constant current can flow through the current forming layer. The constant current is also independent of the input voltage _VIN .

As an example, a first input voltage can be applied to the gate electrode G such that the channel current of the n-type TFT dominates the channel current of the p-type TFET. At this time, the output voltage V _OUT of the ternary inverter 10 is also the first voltage.

As another example, a second input voltage can be applied to the gate electrode G such that the channel current of the p-type TFT dominates the channel current of the n-type TFET. At this time, the output voltage V _OUT of the ternary inverter 10 is also the second voltage higher than the first voltage.

In yet another example, a third input voltage can be applied to the gate electrode G to have a constant current that dominates the channel current of the n-type TFET and the channel current of the p-type TFET. At this time, the output voltage V _OUT of the ternary inverter 10 is also the third voltage between the first voltage and the second voltage.

A constant current flowing from the first source S1, the first drain D1, the first channel C1, and the drain of the n-type TFET formed in the gate electrode G, that is, the first drain D1 to the substrate 100 is applied to the gate electrode G. It can flow regardless of the gate voltage. Current in the ternary inverter 10 may flow to the substrate 100 through the second drain D2 and the first drain D1. The driving voltage _VDD applied to the second source S2 is also distributed to the resistance between the second source S2 and the second drain D2 and the resistance between the first source S1 and the first drain D1. The output voltage V _OUT is also the voltage applied across the resistor between the first source S1 and the first drain D1. The output voltage V _OUT can have a value between the drive voltage V _DD and 0V.

Depending on the input voltage _VIN , the output voltage _VOUT has 0V (“0” state), a voltage between the drive voltage _VDD and 0V (“1” state), or the drive voltage VDD (“2” state). I can. That is, the ternary inverter 10 according to the present embodiment can have three states according to the input voltage _VIN .

FIG. 5 is a gate voltage-drain current graph of the ternary inverter of FIG. 1 and a conventional binary inverter. Specifically, FIG. 5 shows gate voltage-drain current graphs IGR1, IGR2 of a binary inverter and gate voltage-drain current graphs IGR3, IGR4, IGR5 of a ternary inverter according to the present embodiment. The drain current of a binary inverter does not have a constant current component that flows independently of the gate voltage. The drain current of the ternary inverter according to this embodiment has a constant current component that flows independently of the gate voltage. For example, in the case of the ternary inverter according to the present embodiment, it can be confirmed that a constant current flows even in the OFF state.

FIG. 6 is an input voltage V _IN -output voltage V _OUT graph of the ternary inverter of FIG. 1 and a conventional binary inverter. As can be seen from FIG. 6, the drive voltage _VDD of the ternary inverter and the binary inverter according to this embodiment is 1.0V, and the ground voltage GND is 0V. The input voltage V _IN of the ternary and binary inverters is between 0V and 1.0V.

For a binary inverter, when the input voltage changes from 0V to 1V, the output voltage V _OUT drops sharply from 1V to 0V around an input voltage of 0.5V. That is, a binary inverter has two states (eg, a '0' state and a '1' state).

In the case of the ternary inverter according to this embodiment, when the input voltage changes from 0V to 1V, the output voltage V _OUT drops sharply from 1V to 0.5V, remains at 0.5V, and changes from 0.5V to Another sharp drop to 0V. That is, it can be seen that the ternary inverter according to the present embodiment has three states (eg, '0' state, '1' state and '2' state).

FIG. 7 is a graph showing voltage input/output characteristics of a ternary inverter according to an embodiment of the present invention. Since FIG. 7 is a graph having the same context as that of FIG. 6 described above, the description of the content that overlaps with the description of FIG. 6 will be omitted, and the characteristic points will be mainly described.

In the ternary inverter according to this embodiment, when the input voltage V _IN changes from 0V to 0.3V, the output voltage V _OUT abruptly drops from 0.3V to 0.15V and remains at 0.15V. , dropped from 0.15V to 0V one more time. That is, it can be seen that the ternary inverter according to the present embodiment has three states (eg, '0' state, '1' state, and '2' state). However, the difference from the _{ternary inverter} of the embodiment described with reference to FIG. , it can be confirmed that the operating voltage scaling capability of the ternary inverter is improved.

8 to 23 are perspective views or cross-sectional views for explaining a method of manufacturing the ternary inverter of FIG.

First, as shown in FIG. 8 , a constant current forming layer 200 may be formed on a substrate 100 and a gate structure GS′ may be formed on the constant current forming layer 200 . The constant current forming layer 200 is also formed through an epitaxial growth process. That is, the constant current forming layer 200 is also an epitaxial layer. The constant current forming layer 200 is also a semiconductor layer having the first conductivity type. For example, when the conductivity type of the constant current forming layer 200 is p-type, the constant current forming layer 200 is also a silicon layer containing a group III element (for example, B or In) as an impurity. If the conductivity type of the constant current forming layer 200 is n-type, the constant current forming layer 200 is also a silicon layer containing V group elements (eg, P or As) as impurities. The doping concentration of the constant current forming layer 200 is higher than the doping concentration of the substrate 100 . For example, the doping concentration of the constant current forming layer 200 is 3×10 ¹⁸ cm ⁻³ or more.

A gate structure GS' may be formed on the constant current forming layer 200 . The gate structure GS' may be formed by mutually stacking a sacrificial layer and a channel layer. In FIG. 8, the first sacrificial film SC1′ is located on the constant current forming layer 200, the first channel layer C1′ is located on the first sacrificial film SC1′, and the first channel layer C1′ is located on the first sacrificial film SC1′. A second sacrificial film SC2' is located thereon, a second channel layer C2' is located on the second sacrificial film SC2', and a third sacrificial film SC3' is located on the second channel layer C2'. are shown in position.

The sacrificial layers SC1', SC2', SC3' and the channel layers C1', C2' may include materials having different etch selectivity ratios. For example, the sacrificial films SC1', SC2', SC3' may contain silicon germanium (SiGe), and the channel layers C1', C2' may contain silicon (Si). Such a gate structure GS' can be formed via a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process or an atomic layer deposition (ALD) process. is also formed.

After forming such a gate structure GS', it can be patterned as illustrated in FIG. For example, a mask can be used to etch the rest of the gate structure GS' of FIG. 8 except for the preset portions. When removing a portion of the gate structure GS', etching may proceed until the top surface 200u of the constant current forming layer 200 is exposed in that portion. Accordingly, as shown in FIG. 9, the gate structure GS'' may have a shape extending in the first direction DR1. Such a gate structure GS'' may include sacrificial layers SC1'', SC2'', SC3'' and channel layers C1'', C2''. The sacrificial films SC1'', SC2'' and SC3'' are also formed by etching the sacrificial films SC1', SC2' and SC3'. The channel layers C1'' and C2'' are also formed by etching the channel layers C1' and C2'.

Thereafter, as shown in FIG. 10, a dummy gate 302 and gate spacers 330 on both sides of the dummy gate 302 may be formed on the constant current forming layer 200 . The dummy gate 302 may have a shape extending along the second direction DR2. A portion of the gate structure GS″ may be exposed outside both sides of the dummy gate 302 .

The dummy gate 302 may have a high etch selectivity with respect to the gate spacers 330 on either side of it. For example, dummy gate 302 may comprise silicon nitride with high etch selectivity, and gate spacer 330 may also comprise silicon oxide with low etch selectivity.

The dummy gate 302 may be formed by forming a dummy gate layer covering the gate structure GS'' and patterning it. The patterning of the dummy gate layer may be performed until the top surface of the constant current forming layer 200 is exposed.

Gate spacers 330 located on both sides of the dummy gate 302 may cover both sides of the dummy gate 302 . A portion of the gate structure GS″ may be exposed outside the gate spacer 330 .

The gate spacers 330 are also formed by forming a material layer for the gate spacers 330 on the dummy gate 302, the gate structure GS'' and the constant current forming layer 200 and etching the same. The etching of the material layer for gate spacers 330 may also proceed via an anisotropic dry etching process.

Portions of the gate structure GS'' exposed outside the dummy gate 302 and gate spacers 330 may then be removed to form the gate structure GS as illustrated in FIG. Removal of a portion of the gate structure GS'' can also proceed via an anisotropic etching process using a mask. Thereby, the gate structure GS is composed of a first sacrificial film SC1, a first channel C1 on the first sacrificial film SC1, a second sacrificial film SC2 on the first channel C1, and a second channel C2 on the second sacrificial film SC2. , and the third sacrificial film SC3 on the second channel C2.

After that, as shown in FIGS. 12 to 14, a first source S1 and a first drain D1 are formed, an interlayer insulating film 340 is formed on the first source S1, and an interlayer insulating film 340 is formed. A second source S2 and a second drain D2 above the first drain D1 are formed. The first source S1 is formed on one side of the dummy gate 302 in the opposite direction (-DR1) of the first direction, and the first drain D1 is formed on the other side (DR1) of the dummy gate 302. FIG.

Forming the first source S1 and the first drain D1 may include an epitaxial growth process. After forming the first source S1 and the first drain D1, a process of doping them is performed. For example, the first source S1 is doped with a group III element (eg, B or In) to be p-type, and the first drain D1 is doped with a group V element (eg, P or As) to be n-type. have

Similarly, after forming the second source S2 and the second drain D2, they undergo a doping process. For example, the second source S2 is doped with a group V element (eg, P or As) to be n-type, and the second drain D2 is doped with a group III element (eg, B or In) to be p-type. have

Thereafter, dummy gate 302 is removed, as illustrated in FIGS. 15-17. Removal of dummy gate 302 also proceeds via a wet etching process. At this time, a hydrofluoric acid-based substance can be used as an etchant.

A portion of the gate structure GS is exposed between the gate spacers 330 when the dummy gate 302 is removed. 18 to 20, the first sacrificial layer SC1, the second sacrificial layer SC2 and the third sacrificial layer SC3 included in the gate structure GS are removed. The removal of the first sacrificial layer SC1, the second sacrificial layer SC2 and the third sacrificial layer SC3 may also be performed through a chemical dry etching process or a chemical wet etching process. For example, the chemical dry etching process may also utilize a plasma generated by a radical generator, and the wet etching process may utilize an ammonia-peroxide mixture. In the latter case, H ₂ O ₂ can act as an oxidant and NH ₄ OH as an oxide etchant in the mixture.

By removing the first sacrificial film SC1, the second sacrificial film SC2, and the third sacrificial film SC3, part of the surface of the first source S1 in the direction of the first drain D1 (DR1) and the second sacrificial film of the second source S2 are removed. Part of the surface of the drain D2 direction (DR1), part of the surface of the first drain D1 in the direction of the first source S1 (-DR1), surface of the second drain D2 in the direction of the second source S2 (-DR1) Some of them, the outer surface of the first channel C1 and the outer surface of the second channel C2 may be exposed.

Next, as shown in FIGS. 21-23, a gate insulating layer 320 is formed. Specifically, of the outer surface of the first channel C1, the outer surface of the second channel C2, and the surface of the first source S1 facing the first drain D1, the portions other than the portion that contacts the first channel C1 of the surface of the second source S2 in the direction of the second drain D2, the portion other than the portion in contact with the second channel C2; of the surface of the first drain D1 in the direction of the first source S1, in contact with the first channel C1 A gate insulating film 320 covering a portion other than the portion contacting the second channel C2 on the surface of the second drain D2 facing the second source S2 and the constant current forming layer 200 is formed.

Forming the gate insulating layer 320 may include depositing an electrically insulating material. For example, depositing an electrically insulating material may include performing a thermal oxidation process, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The gate insulating layer 320 so formed may include silicon oxide, silicon nitride, silicon oxynitride, or the like. Alternatively, the gate insulating layer 320 may include an insulating material having a high dielectric constant. For example, gate insulating layer 320 may include a material having a dielectric constant of approximately 10-25. For example, the gate insulating film 320 may be hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO). , zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO) , barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

Next, by forming gate electrodes G, the ternary inverter described with reference to FIGS. 1 to 3 can be manufactured. A gate electrode G is also formed between the gate spacers 330 . The gate electrode G is also formed by filling the space between the gate spacers 330 with a gate electrode forming material. Specifically, the gate electrode G is also formed by filling a region surrounded by the gate insulating film 320 with a conductive material. The gate electrode G may include an electrically conductive material. For example, gate electrode G may comprise metal or polysilicon. The process of forming the gate electrode G may use a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

While the present invention has thus been described with reference to the embodiments illustrated in the drawings, these are exemplary only and a person skilled in the art will appreciate various modifications therefrom. It will be appreciated that variations and other equivalent embodiments are possible. Therefore, the true technical scope of protection of the present invention is defined by the technical ideas of the claims.

100 Substrate 200 Constant Current Forming Layer 320 Gate Insulating Film 330 Gate Spacer 340 Interlayer Insulating Film

Claims (12)

a first source and a first drain spaced apart from each other;
an interlayer insulating film located on the first source;
a second source located on the interlayer insulating layer and a second drain located on the first drain;
It is interposed between the first source and the first drain, the 1-1 end face in the first source direction is in contact with the first source, and the 1-2 end in the first drain direction is in contact with the first source. a first channel, a portion of which contacts the first drain;
It is separated from the first channel, located above the first channel, interposed between the second source and the second drain, and the 2-1 end face in the direction of the second source extends from the first channel. a second channel in contact with two sources, the 2-2 end face in the direction of the second drain in contact with the second drain;
portions of the outer surface of the first channel, the outer surface of the second channel, and the surface of the first source in the first drain direction other than the portion in contact with the first channel; the second source; portion other than the portion in contact with the second channel in the second drain direction surface of the first drain; portion in the first source direction surface of the first drain other than the portion in contact with the first channel; and a gate insulating film covering a portion of the surface of the second drain in the second source direction other than the portion in contact with the second channel;
a gate electrode interposed between the first source and the first drain and between the second source and the second drain. 3. The ternary inverter of claim 1, wherein said first source and said second source are doped to different conductivity types. 3. The ternary inverter of claim 2, wherein said first drain and said first source are doped to different conductivity types. 3. The ternary inverter of claim 2, wherein said first drain and said second drain are doped to different conductivity types. 3. The ternary inverter of claim 1, wherein said gate electrode fills between said first channel and said second channel. 6. The ternary inverter according to claim 5, wherein said gate electrode surrounds a portion of said gate insulating film surrounding said first channel and a portion of said gate insulating film surrounding said second channel. further comprising a constant current formation layer,
2. The ternary inverter as claimed in claim 1, wherein said first source and said first drain are located on said constant current forming layer. A first sacrificial layer, a first channel over the first sacrificial layer, a second sacrificial layer over the first channel, a second channel over the second sacrificial layer, and a third sacrificial layer over the second channel are formed on the substrate. forming a gate structure comprising and extending in a first direction;
forming a dummy gate extending in a second direction intersecting the first direction and intersecting the gate structure;
forming a first source contacting the 1-1 end face of the first channel on one side of the dummy gate and contacting the 1-2 end face of the first channel on the other side of the dummy gate; forming a first drain that
forming an interlayer insulating layer over the first source;
A second source contacting the 2-1 end face of the second channel is formed on the interlayer insulating layer, and a second source contacting the 2-2 end face of the second channel is formed on the first drain. forming a drain;
removing the dummy gate;
removing the first sacrificial layer, the second sacrificial layer and the third sacrificial layer;
a portion of the outer surface of the first channel, the outer surface of the second channel, and the surface of the first source facing the first drain, other than the portion in contact with the first channel; a portion of the surface in the second drain direction other than the portion in contact with the second channel; a portion of the surface in the first source direction of the first drain other than the portion in contact with the first channel; forming a gate insulating film covering a portion of the surface of the second drain in the direction of the second source, other than the portion in contact with the second channel;
forming a gate electrode interposed between the first source and the first drain, and the second source and the second drain. 9. The method of claim 8, further comprising doping the first source and the first drain to different conductivity types. 10. The method of claim 9, further comprising doping the second source to a conductivity type different from the first source and doping the second drain to a conductivity type different from the first drain. forming the gate electrode to fill the space from which the dummy gate has been removed between the first source and the first drain and between the second source and the second drain; 9. The method of manufacturing a ternary inverter as claimed in claim 8, wherein the step of forming. 3. The step of forming the gate electrode is a step of forming the gate electrode to surround a portion of the gate insulating film surrounding the first channel and a portion of the gate insulating film surrounding the second channel. 9. The ternary inverter manufacturing method according to 8.

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