JP2023079064A - backup power system - Google Patents

Abstract

To provide a backup power supply system that achieves downsizing of a circuit.SOLUTION: A first transistor Tr13 and a second transistor Tr14 are connected in series between a source and a reference potential of a second field effect transistor SW3, and a respective emitter is connected to a gate of the second field effect transistor SW3. A first drive circuit 21 operates the second field effect transistor SW3 in an active region by outputting a driving signal S12 based on a current command value S11 and a current value of current flowing through the second field effect transistor SW3 to bases of the first and the second transistors Tr13 and Tr14. A second drive circuit 22 has a first switching element Q14 connected between a corrector and the base of the second transistor Tr14. When the first switching element Q14 is turned ON by an ON signal Son inputted from a control unit 10, the second field effect transistor SW3 is turned ON.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to backup power systems. More particularly, the present disclosure relates to backup power systems that provide power to loads when the main power source fails.

Patent Literature 1 discloses a power backup unit for a main power supply. The power backup unit described in Patent Document 1 charges an auxiliary power supply section from a main power supply section through a diode, a P-channel FET that constitutes a current control switch, and a P-channel FET that constitutes a charge control circuit. have a route. When power is supplied from the auxiliary power supply unit to the electronic control unit, which is a load, a diode connected in parallel to the P-channel FET that constitutes the charge control circuit and the P-channel FET that constitutes the current control switch are connected from the auxiliary power supply unit. Power is supplied to the electronic control unit via a backup path through and.

Japanese Patent Application Laid-Open No. 2006-60950

In the power supply backup unit (backup power supply system) configured as described above, there has been a demand to reduce the size of circuits for driving the P-channel FETs that form the current control switch and the P-channel FETs that form the charging control circuit.

An object of the present disclosure is to provide a backup power supply system with a reduced circuit size.

A backup power supply system according to one aspect of the present disclosure includes a first connection terminal, a second connection terminal, a first field effect transistor, a second N-channel field effect transistor, a control section, a drive circuit, and , provided. A main power supply is connected to the first connection terminal. A load is connected to the second connection terminal. The first field effect transistor is connected between the first connection terminal and the second connection terminal. The second field effect transistor is connected between a connection point of the first field effect transistor and the second connection terminal and an electricity storage device. The drive circuit drives the second field effect transistor. In a non-failure state in which the main power supply has not failed, the control section turns on the first field effect transistor and controls the drive circuit to turn the second field effect transistor into an active region. to charge the storage device through the charging path. The charging path is a path from the main power supply through the first field effect transistor and the second field effect transistor. In a failure state in which the main power supply fails, the control unit controls the first field effect transistor to be off and controls the drive circuit to turn on the second field effect transistor. to supply power to the load via the backup path. The backup path is a path from the storage device through the second field effect transistor. The drive circuit has a push-pull circuit of a first transistor and a second transistor, a first drive circuit, a second drive circuit, and a third drive circuit. The push-pull circuit of the first transistor and the second transistor is connected in series between the positive and negative terminals of a control power supply. The emitters of the first transistor and the second transistor are connected to the gate of the second field effect transistor. The second drive circuit turns on the second field effect transistor. The third drive circuit turns off the second field effect transistor. The first drive circuit outputs a drive signal based on a current command value input from the control unit and a current value of a current flowing through the second field effect transistor to the bases of the first transistor and the second transistor. to operate the second field effect transistor in the active region. The second drive circuit has a first switching element connected between the collector and base of the first transistor and turned on by an ON signal input from the control section.

A backup power supply system according to one aspect of the present disclosure includes a first connection terminal, a second connection terminal, a first field effect transistor, a second P-channel field effect transistor, a control section, and a drive circuit. , provided. A main power supply is connected to the first connection terminal. A load is connected to the second connection terminal. The first field effect transistor is connected between the first connection terminal and the second connection terminal. The second field effect transistor is connected between a connection point of the first field effect transistor and the second connection terminal and an electricity storage device. The drive circuit drives the second field effect transistor. In a non-failure state in which the main power supply has not failed, the control section turns on the first field effect transistor and controls the drive circuit to turn the second field effect transistor into an active region. to charge the storage device through the charging path. The charging path is a path from the main power supply through the first field effect transistor and the second field effect transistor. In a failure state in which the main power supply fails, the control unit controls the first field effect transistor to be off and controls the drive circuit to turn on the second field effect transistor. to supply power to the load via the backup path. The backup path is a path from the storage device through the second field effect transistor. The drive circuit has a push-pull circuit of a first transistor and a second transistor, a first drive circuit, a second drive circuit, and a third drive circuit. The push-pull circuit of the first transistor and the second transistor is connected in series between the source of the second field effect transistor and a reference potential. The emitters of the first transistor and the second transistor are connected to the gate of the second field effect transistor. The second drive circuit turns on the second field effect transistor. The third drive circuit turns off the second field effect transistor. The first drive circuit outputs a drive signal based on a current command value input from the control unit and a current value of a current flowing through the second field effect transistor to the bases of the first transistor and the second transistor. to operate the second field effect transistor in the active region. The second drive circuit has a first switching element connected between the collector and base of the second transistor and turned on by an ON signal input from the control section.

According to the present disclosure, it is possible to provide a backup power supply system in which circuit size is reduced.

FIG. 1 is a circuit diagram showing an overview of a backup power supply system according to Embodiment 1 of the present disclosure. FIG. 2 is a schematic circuit diagram of the same backup power supply system. FIG. 3 is a specific circuit diagram of the backup power supply system of the same. FIG. 4 is an explanatory diagram for explaining the operation of the backup power supply system of the same. FIG. 5 is an explanatory diagram for explaining the operation of the backup power supply system of the same. FIG. 6 is a specific circuit diagram of a backup power supply system according to Embodiment 2 of the present disclosure.

Embodiments of the backup power supply system are described below. Each drawing described in the following embodiments is a schematic drawing, and the ratio of the size and thickness of each component in each drawing does not necessarily reflect the actual dimensional ratio. .

(Embodiment 1)
(1) Overview As shown in FIG. 1, the backup power supply system 1 of the present embodiment includes a first connection terminal T1, a second connection terminal T2, a first field effect transistor SW1, a field effect transistor SW2, A second field effect transistor SW3 and a control unit 10 are provided. The backup power supply system 1 further includes a drive circuit 20 that drives the second field effect transistor SW3. The drive circuit 20 will be described in detail in "(2.1) Configuration". Further, hereinafter, the first field effect transistor SW1 may be abbreviated as the field effect transistor SW1, and the second field effect transistor SW3 may be abbreviated as the field effect transistor SW3.

A main power supply 2 is connected to the first connection terminal T1. A load 4 is connected to the second connection terminal T2. The first field effect transistor SW1 is connected between the first connection terminal T1 and the second connection terminal T2. A series circuit of the field effect transistor SW2 and the P-channel second field effect transistor SW3 is connected between the power storage device 3 and a connection point P1 between the first field effect transistor SW1 and the second connection terminal T2. The body diode D2 provided in the field effect transistor SW2 is connected in the direction in which current flows from the connection point P1 to the power storage device 3, and the body diode D3 provided in the second field effect transistor SW3 allows current to flow from the power storage device 3 to the connection point P1. connected in the direction of flow.

In a non-failure state in which the main power supply 2 has not failed, the control unit 10 turns on the first field effect transistor SW1 and controls the drive circuit 20 to turn the second field effect transistor SW3 into the active region. , the power storage device 3 is charged via the charging path RT1. Charging path RT1 is a path through which current flows from main power supply 2 to storage device 3 through first field effect transistor SW1, field effect transistor SW2, and second field effect transistor SW3. In addition, in a failed state in which the main power supply 2 fails, the control unit 10 turns off the first field effect transistor SW1 and turns on the field effect transistor SW2, and controls the drive circuit 20 to turn on the second field effect transistor SW1. By turning on the field effect transistor SW3, power is supplied from the storage device 3 to the load 4 via the backup path RT2. In a failure state, the path through which the discharge current from power storage device 3 flows to load 4 may include backup path RT2. Backup route RT2 is a route through which current flows from power storage device 3 to load 4 through second field effect transistor SW3 and field effect transistor SW2.

In the non-failure state, power is supplied from the main power supply 2 to the load 4 via the first field effect transistor SW1, and a charging current flows from the main power supply 2 to the storage device 3 to charge the storage device 3. The backup power supply system 1 of this embodiment is used to supply power from the power storage device 3 to the load 4 in a failure state.

Here, the failure state in which the main power supply 2 fails is a state in which power supply from the main power supply 2 to the load 4 is stopped due to failure, deterioration, disconnection, or the like of the main power supply 2 . A non-failure state in which the main power supply 2 does not fail is a state in which power is supplied from the main power supply 2 to the load 4 and the load 4 can operate with the power supplied from the main power supply 2 . The fact that the control unit 10 turns on the field effect transistors SW1 to SW3 means that the field effect transistors SW1 to SW3 are operated in the saturation region. Further, the fact that the control unit 10 turns off the field effect transistors SW1 to SW3 means that the field effect transistors SW1 to SW3 are operated in the blocking region. Note that even when the field effect transistors SW1 to SW3 are controlled to be in the cutoff region, since the field effect transistors SW1 to SW3 are provided with the body diodes D1 to D3, forward current flows through the body diodes D1 to D3. can flow.

In addition, the control unit 10 operates the second field effect transistor SW3 in the active region in order to control the charging current flowing through the electricity storage device 3 . For example, the control unit 10 executes current control until the charging voltage of the power storage device 3 reaches a predetermined target value (target voltage value). In addition, for example, after the charging voltage of the electricity storage device 3 reaches the target value, the control unit 10 performs constant voltage control so that the voltage does not drop due to the discharge due to the internal resistance component of the cell, thereby keeping the charging voltage constant. control (eg, trickle charge) to maintain In order to perform current control or constant voltage control, the control unit 10 operates the second field effect transistor SW3 in a saturation region or an active region (linear region) to control the magnitude of the current flowing through the second field effect transistor SW3. to control

As described above, in the backup power supply system 1 of the present embodiment, the field effect transistor SW2 and the second field effect transistor SW3 are shared by the charging path RT1 and the backup path RT2. can be reduced. Therefore, there is an advantage that the mounting space for mounting the field effect transistor on the circuit board can be reduced and the size of the circuit board can be reduced.

Also, the charging path RT1 is a path through which current flows from the main power supply 2 to the storage device 3 through the first field effect transistor SW1, the field effect transistor SW2, and the second field effect transistor SW3. If the first field effect transistor SW1 and the field effect transistor SW2 are turned on, no voltage drop occurs due to the forward voltage of the diode. Further, since the control unit 10 operates the second field effect transistor SW3 in the active region, the on-resistance of the second field effect transistor SW3 is small, and the voltage drop generated in the second field effect transistor SW3 is in the order of the diode. smaller than the directional voltage. Therefore, when the power storage device 3 is charged via the charging path RT1, a voltage drop due to the forward voltage of the diode does not occur.

Backup path RT2 is a path through which current flows from power storage device 3 to load 4 through second field effect transistor SW3 and field effect transistor SW2. If the second field effect transistor SW3 and the field effect transistor SW2 are turned on, no voltage drop occurs due to the forward voltage of the diode, so that the drop in the voltage supplied to the load 4 can be suppressed.

In this way, since a voltage drop due to the forward voltage of the diode does not occur in each of the charging path RT1 and the backup path RT2, there is an advantage that a decrease in the voltage supplied to the load 4 can be suppressed when backup power supply is performed.

(2) Details Hereinafter, the backup power supply system 1 according to the present embodiment will be described in detail with reference to the drawings.

(2.1) Configuration FIG. 2 is a specific circuit diagram of the backup power supply system 1 (see FIG. 1) described above. As described above, the backup power supply system 1 includes the first connection terminal T1, the second connection terminal T2, the first field effect transistor SW1, the second field effect transistor SW2, the second field effect transistor SW3, and the control It includes a unit 10 , an electricity storage device 3 , and a drive circuit 20 . The backup power supply system 1 further includes a current detection resistor R1, a failure detection section 11, and a charging voltage detection section 14.

The electrical storage device 3 is, for example, an electrical double layer capacitor (EDLC) capable of rapid charging and discharging. The power storage device 3 may be composed of two or more power storage devices (for example, electric double layer capacitors) electrically connected in parallel or in series, or may be composed of a plurality of power storage devices electrically connected in parallel and in series. may be composed of a power storage device (for example, an electric double layer capacitor). That is, the power storage device 3 may be realized by a parallel circuit or a series circuit of two or more power storage devices, or a combination thereof.

A main power source 2 such as a vehicle battery is connected to the first connection terminal T1 via a main switch MS1 provided in the vehicle. When the main switch MS1 is turned on, the power supply voltage V1 is input from the main power supply 2 to the first connection terminal T1 through the main switch MS1.

A load 4 is connected to the second connection terminal T2. The load 4 is, for example, an electric brake system mounted on a vehicle. Note that the load 4 is not limited to the electric brake system, and may be a control system or drive system device related to ADAS (Advanced Driver-Assistance Systems).

The field effect transistors SW1 to SW3 are, for example, P-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

A drain of the first field effect transistor SW1 is connected to the first connection terminal T1, and a source of the first field effect transistor SW1 is connected to the second connection terminal T2. The body diode D1 of the first field effect transistor SW1 is connected in a direction in which current flows from the first connection terminal T1 to the second connection terminal T2.

The drain of the field effect transistor SW2 is connected to the connection point P1, and the source of the field effect transistor SW2 is connected to the source of the second field effect transistor SW3 via the current detection resistor R1. The drain of the second field effect transistor SW3 is connected to the positive terminal of the storage device 3 . A negative terminal of the storage device 3 is connected to the reference potential of the backup power supply system 1 . Here, when the field effect transistor SW2 is turned off, the body diode D2 of the field effect transistor SW2 prevents current from flowing from the storage device 3 to the connection point P1. Also, when the second field effect transistor SW3 is off, the body diode D3 of the second field effect transistor SW3 prevents current from flowing from the connection point P1 toward the storage device 3 .

The failure detection section 11 includes a detection section 12 and a comparison section 13 .

The detection unit 12 detects the voltage value of the power supply voltage V1 input to the first connection terminal T1.

The comparison unit 13 compares the voltage value of the power supply voltage V1 detected by the detection unit 12 with a threshold to determine whether the main power supply 2 is in a failed state or not. It is detected whether it is in a non-failed state. The comparison unit 13 outputs the detection result of the failure state or non-failure state to the control unit 10 .

The threshold is the lower limit of the voltage range that can be regarded as a failure-free state, and is set to a value lower than the rated voltage of the main power supply 2, for example. The thresholds may include a first threshold for detecting occurrence of the failure state and a second threshold for detecting that the failure state has returned to the non-failure state. The first threshold and the second threshold may be the same value or different values.

The charging voltage detector 14 includes a detector 15 and a comparator 16 .

The detection unit 15 detects the voltage value at the connection point between the second field effect transistor SW3 and the power storage device 3 , that is, the voltage value of the charging voltage V2 that is the voltage across the power storage device 3 .

The comparison unit 16 compares the voltage value of the charging voltage V<b>2 detected by the detection unit 15 with the target voltage value, and outputs the comparison result to the control unit 10 .

The control unit 10 controls the first field effect transistor SW1, the field effect transistor SW2, and the second field effect transistor SW3. By controlling the operation of the drive circuit 20, the control unit 10 controls the second field effect transistor SW3.

A specific circuit of the drive circuit 20 will now be described with reference to FIG. 3 and the like. 3, illustration of the main switch MS1, the failure detection unit 11, and the charging voltage detection unit 14 is omitted.

The drive circuit 20 includes a push-pull circuit 24 , a first drive circuit 21 , a second drive circuit 22 and a third drive circuit 23 .

The push-pull circuit 24 has a first transistor Tr13 and a second transistor Tr14 connected in series between the source of the second field effect transistor SW3 and the reference potential. The first transistor Tr13 is, for example, an npn-type bipolar transistor, and the second transistor Tr14 is a pnp-type bipolar transistor. The bases of the first transistor Tr13 and the second transistor Tr14 are connected to each other, and the emitters of the first transistor Tr13 and the second transistor Tr14 are connected to each other. ing. Each emitter of the first transistor Tr13 and the second transistor Tr14 is connected to the gate of the second field effect transistor SW3.

The first drive circuit 21 operates the second field effect transistor SW3 in the active region. The first drive circuit 21 includes, for example, a current detection amplifier A11, a differential amplifier A12, and a reference voltage source V10.

The current detection amplifier A11 amplifies the voltage across the current detection resistor R1 and is proportional to the magnitude of the current flowing through the second field effect transistor SW3 (the charging current flowing through the power storage device 3 or the discharging current flowing from the power storage device 3). output voltage.

The reference voltage source V10 is a voltage source with a variable output voltage. The reference voltage source V10 outputs a DC voltage proportional to the current command value S11 input from the control unit 10 according to the current command value S11.

The differential amplifier A12 outputs a drive signal S12, which is a voltage signal proportional to the voltage difference between the output voltage of the current detection amplifier A11 and the output voltage of the reference voltage source V10. The output terminal of the differential amplifier A12 is connected to the bases of the first transistor Tr13 and the second transistor Tr14 via the resistor R13.

Thus, the first drive circuit 21 outputs the drive signal S12 based on the current command value S11 input from the control unit 10 and the current value of the current flowing through the second field effect transistor SW3 to the first transistor Tr13 and the first transistor Tr13. The output to the base of the second transistor Tr14 causes the second field effect transistor SW3 to operate in the active region.

Here, if the current value of the current flowing through the second field effect transistor SW3 is higher than the current value corresponding to the current command value S11, the output voltage of the current detection amplifier A11 is higher than the output voltage of the reference voltage source V10. Become. In this case, the voltage value of the drive signal S12 output from the differential amplifier A12 increases, and the output voltage of the push-pull circuit 24 increases, so that the gate-source voltage of the second field effect transistor SW3 decreases. , the current flowing through the second field effect transistor SW3 decreases.

Further, when the current value of the current flowing through the second field effect transistor SW3 becomes lower than the current value corresponding to the current command value S11, the output voltage of the current detection amplifier A11 becomes lower than the output voltage of the reference voltage source V10. . In this case, the voltage value of the drive signal S12 output from the differential amplifier A12 decreases, and the output voltage of the push-pull circuit 24 decreases, so that the gate-source voltage of the second field effect transistor SW3 increases. , the current flowing through the second field effect transistor SW3 increases.

That is, the first drive circuit 21 controls the second field effect transistor SW3 in the active region (linear region) so that the current flowing through the second field effect transistor SW3 has a current value corresponding to the current command value S11. do.

The second drive circuit 22 turns on the second field effect transistor SW3. The second drive circuit 22 has a first switching element Q14 connected between the collector and the base of the second transistor Tr14 and turned on by an on-signal Son input from the control section 10 . The first switching element Q14 is composed of, for example, an N-channel MOSFET.

The first switching element Q<b>14 is turned on by an on-signal Son input from the control section 10 . When the first switching element Q14 is turned on, the base potentials of the first transistor Tr13 and the second transistor Tr14 become the reference potential, and the output voltage of the push-pull circuit 24 becomes equal to the reference potential. As a result, a voltage exceeding the pinch-off voltage is applied between the gate and source of the second field effect transistor SW3, and the second field effect transistor SW3 is operated in a saturated state, that is, turned on. Since the first switching element Q14 is provided after the second transistor Tr14, the first switching element Q14 can be made smaller than when the switching element is connected between the electrodes of the second field effect transistor SW3. It can be realized by switching elements of capacitance, and the size of the circuit can be reduced.

The third drive circuit 23 turns off the second field effect transistor SW3.

The third drive circuit 23 includes an impedance element (for example, a resistor R14) connected between the collector and base of the first transistor Tr13, and a second switching element Q13 connected between the collector and base of the first transistor Tr13. and have When the second switching element Q13 is turned on by the off signal Soff input from the control section 10, the second field effect transistor SW3 is turned off. The second switching element Q13 is composed of, for example, an N-channel MOSFET. The impedance element is, for example, the resistor R14, but any circuit element other than the resistor may be used as long as it has an impedance component.

The second switching element Q13 is turned on by an off signal Soff input from the control section 10 . When the second switching element Q13 is turned on, the base potentials of the first transistor Tr13 and the second transistor Tr14 become equal to the source potential of the second field effect transistor SW3, and the output voltage of the push-pull circuit 24 also becomes the second 2 equal to the potential of the source of the field effect transistor SW3. As a result, the gate-source voltage of the second field effect transistor SW3 becomes substantially zero, and the second field effect transistor SW3 operates in the blocking region, that is, is turned off.

Since the second switching element Q13 is provided in the subsequent stage of the first transistor Tr13, the second switching element Q13 can be used more efficiently than in the case where the switching element is connected between the electrodes of the second field effect transistor SW3. It can be realized with a small-capacity switching element, and miniaturization of the circuit can be achieved.

(2.2) Description of Operation The operation of the backup power supply system 1 of Embodiment 1 will be described with reference to FIGS. 1 to 5 and the like.

(2.2.1) Operation When Failure Occurs During Charging The operation of the backup power supply system 1 when the main power supply 2 fails during charging of the power storage device 3 will be described with reference to FIG. 4 and the like.

When the main switch MS1 is turned on at time t101, the power supply voltage V1 is supplied from the main power supply 2 to the backup power supply system 1. FIG. Since the voltage value of the power supply voltage V1 exceeds the predetermined threshold value Lv1 from time t101 to time t103, the failure detection unit 11 detects that the main power supply 2 is in the non-failure state. The control unit 10 turns on the first field effect transistor SW1 while the failure detection unit 11 is detecting the non-failure state (from time t101 to time t103). Further, in the first period from time t101 to time t102, the voltage value of charging voltage V2 of power storage device 3 is equal to or lower than target voltage value Lv2, so control unit 10 turns on field effect transistor SW2. In addition, based on the detection result of the charging voltage detection unit 14, the control unit 10 controls the voltage value of the charging voltage V2 of the electric storage device 3 to the target voltage value Lv2, so that the second field effect transistor SW3 is in the active region. Control. As a result, charging current flows from the main power supply 2 to the storage device 3 via the charging path RT1, and the charging voltage V2 of the storage device 3 gradually increases.

When charging voltage V2 of power storage device 3 reaches target voltage value Lv2 at time t102, control unit 10 turns on first field effect transistor SW1 and field effect transistor SW2 based on the detection result of charging voltage detection unit . control off. In the second period from time t102 to time t103 when the charging voltage V2 reaches the target voltage value Lv2, the control unit 10 prevents the charging voltage from dropping due to the internal resistance component of the cells of the electricity storage device 3. 2 field effect transistor SW3 is controlled in the active region.

That is, in the non-failure state, the control unit 10 activates the second field effect transistor SW3 so as to maintain the charging voltage V2 of the electricity storage device 3 at the target voltage value Lv2 in the second period after the first period. Constant voltage control is performed by controlling in the area. Here, since the current flowing through the second field effect transistor SW3 in the second period is smaller than that in the first period, the drain-source resistance of the second field effect transistor SW3 is lower than that in the first period. get higher A period LA (first period and second period) in FIG. 4 indicates a period during which the second field effect transistor SW3 operates in the active region.

After that, when a failure of the main power supply 2 occurs and the power supply voltage V1 falls below the threshold Lv1 at time t103, the failure detection unit 11 detects the failure state of the main power supply 2 and notifies the control unit 10 of the detection result. Output. The control unit 10 keeps the first field effect transistor SW1 on, the field effect transistor SW2 off, and the second field effect transistor SW3 active until the predetermined mask period DT1 elapses from time t103. Control by area. Then, when the failure state continues for the mask period DT1 from time t103, at time t104, the control unit 10 turns off the first field effect transistor SW1 and turns off the field effect transistor SW2 and the second field effect transistor SW3. control on. At this time, the controller 10 outputs the ON signal Son to the second drive circuit 22 to turn on the second field effect transistor SW3. As a result, power is supplied from the power storage device 3 to the load 4 via the backup path RT2, so that the load 4 can receive power from the power storage device 3 and operate even if a failure occurs.

Here, the mask period DT1 is set to a time of, for example, several tens of microseconds to several hundred microseconds. For example, even if dust or the like adheres to the main power supply 2 and a short-circuit state occurs temporarily, if the detection of the failure state by the failure detection unit 11 does not continue for the mask period DT1 or longer, the backup power supply from the power storage device 3 is stopped. Since it is not performed, malfunction of the backup power supply system 1 can be suppressed.

It should be noted that when the control unit 10 determines that the charging voltage V2 of the storage device 3 has fallen below the predetermined stop voltage based on the detection result of the charging voltage detection unit 14 while power is being supplied from the storage device 3 to the load 4, , the field effect transistor SW2 and the second field effect transistor SW3 are preferably turned off. Thereby, the control unit 10 can suppress overdischarge of the power storage device 3 and suppress deterioration of the power storage device 3 . Here, the control unit 10 outputs an off signal Soff to the third drive circuit 23 to turn off the second field effect transistor SW3.

When the backup power supply system 1 is used in a vehicle, for example, when the ignition switch is turned off, the control unit 10 turns on the field effect transistor SW2 and the second field effect transistor SW3 to turn on the electric storage device. It is preferable to discharge a charging voltage of 3. Here, the control unit 10 may lower the charging voltage of the power storage device 3 compared to when the ignition switch is on, and may lower the charging voltage of the power storage device 3 to 0V. When the ignition switch is off, the vehicle is stopped and there is no need to supply backup power to the load 4. Therefore, the life of the storage device 3 can be extended by discharging the storage device 3.

(2.2.2) Operation when a failure occurs after charging is completed and then the main power supply is restored Next, after charging of the storage device 3 is completed, the main power supply 2 fails and backup power supply is performed. After that, the operation of the backup power supply system 1 when the main power supply 2 is restored will be described with reference to FIG. 5 and the like.

When the main switch MS1 is turned on at time t111, the power supply voltage V1 is supplied from the main power supply 2 to the backup power supply system 1. FIG. Since the voltage value of the power supply voltage V1 exceeds the threshold value Lv1 from time t111 to time t113, the failure detection unit 11 detects that the main power supply 2 is in the non-failure state. The control unit 10 turns on the first field effect transistor SW1 while the failure detection unit 11 is detecting the non-failure state (from time t111 to time t113). In addition, in the first period from time t111 to time t112, the voltage value of charging voltage V2 of power storage device 3 is equal to or lower than target voltage value Lv2, so control unit 10 turns on field effect transistor SW2.

Further, in the first period from time t111 to time t112, the voltage value of the charging voltage V2 of the power storage device 3 is equal to or lower than the target voltage value Lv2. , the second field effect transistor SW3 is controlled in the active region so that the voltage value of the charging voltage V2 of the electric storage device 3 is controlled to the target voltage value Lv2. As a result, charging current flows from the main power supply 2 to the storage device 3 via the charging path RT1, and the charging voltage V2 of the storage device 3 gradually increases.

When charging voltage V2 of power storage device 3 reaches target voltage value Lv2 at time t112, control unit 10 turns on first field effect transistor SW1 and field effect transistor SW2 based on the detection result of charging voltage detection unit . control off. In the second period from time t112 to time t113 when the charging voltage V2 reaches the target voltage value Lv2, the control unit 10 prevents the charging voltage from dropping due to the internal resistance component of the cells of the electricity storage device 3. 2 field effect transistor SW3 is controlled in the active region, and constant voltage control is performed so that the charging voltage V2 is maintained at the target voltage value Lv2. That is, in the non-failure state, the control unit 10 activates the second field effect transistor SW3 so as to maintain the charging voltage V2 of the electricity storage device 3 at the target voltage value Lv2 in the second period after the first period. The voltage is controlled by area control. Here, since the current flowing through the second field effect transistor SW3 in the second period is smaller than that in the first period, the drain-source resistance of the second field effect transistor SW3 is lower than that in the first period. get higher A period LA (first period and second period) in FIG. 5 indicates a period in which the second field effect transistor SW3 is controlled in the active region.

After that, when a failure of the main power supply 2 occurs and the power supply voltage V1 falls below the threshold Lv1 at time t113, the failure detection unit 11 detects the failure state of the main power supply 2 and sends the detection result to the control unit 10. Output. The control unit 10 keeps the first field effect transistor SW1 on, the field effect transistor SW2 off, and the second field effect transistor SW3 active until the predetermined mask period DT1 elapses from time t113. Control by area. Then, when the failure state continues for the mask period DT1 from time t113, at time t114, the control unit 10 turns off the first field effect transistor SW1 and turns off the field effect transistor SW2 and the second field effect transistor SW3. control on. At this time, the controller 10 outputs the ON signal Son to the second drive circuit 22 to turn on the second field effect transistor SW3. As a result, power is supplied from the power storage device 3 to the load 4 via the backup path RT2, so that the load 4 can receive power from the power storage device 3 and operate even if a failure occurs.

After that, at time t115, when the failure state of the main power supply 2 is resolved and the power supply voltage V1 exceeds the threshold value Lv1, the failure detection unit 11 detects that the main power supply 2 is in the non-failure state, and the detection result is is output to the control unit 10 . Based on the detection result of the failure detection unit 11, the control unit 10 controls to turn on the field effect transistor SW2 and turn off the second field effect transistor SW3. The control unit 10 stops outputting the ON signal Son and outputs an OFF signal Soff to the third drive circuit 23 to turn off the second field effect transistor SW3. Further, when a failure of the main power supply 2 occurs, the control unit 10 controls the first field effect transistor SW1 to be off even if the failure state of the main power supply 2 is subsequently resolved.

At this time, if the power supply voltage V1 is higher than the charging voltage V2, power is supplied from the main power supply 2 to the load 4 via the body diode D1 of the first field effect transistor SW1. On the other hand, if power supply voltage V1 is lower than charging voltage V2, power is supplied from power storage device 3 to load 4 via backup path RT2. Since the second field effect transistor SW3 is off, when the power supply voltage V1 of the main power supply 2 is higher than the charging voltage V2 of the power storage device 3, a large current flows from the main power supply 2 to the power storage device 3. can be blocked by the second field effect transistor SW3. Moreover, since the first field effect transistor SW1 is controlled to be off, the possibility of current flowing from the power storage device 3 to the main power supply 2 side can be reduced.

Further, when the control unit 10 determines that the charging voltage V2 of the power storage device 3 has fallen below the predetermined stop voltage based on the detection result of the charging voltage detection unit 14 while the power storage device 3 is supplying power to the load 4, , the field effect transistor SW2 and the second field effect transistor SW3 are preferably turned off. Thereby, the control unit 10 can suppress overdischarge of the power storage device 3 and suppress deterioration of the power storage device 3 . Here, the control unit 10 outputs an off signal Soff to the third drive circuit 23 to turn off the second field effect transistor SW3.

In this embodiment, the third drive circuit 23 has an impedance element (for example, a resistor R14) and the second switching element Q13. It is not essential to have both Q13.

The third drive circuit 23 may have only the second switching element Q13. That is, the third drive circuit 23 only needs to have the second switching element Q13 connected between the collector and base of the first transistor Tr13. Also in this case, the second field effect transistor SW3 is turned off by turning on the second switching element Q13 by the off signal Soff input from the control unit 10 . Since the second switching element Q13 is provided after the first transistor Tr13, a switching element for turning off the second field effect transistor SW3 is connected between the electrodes of the second field effect transistor SW3. The second switching element Q13 can be realized with a small-capacity switching element as compared with the case of using the second switching element Q13, and the size of the circuit can be reduced.

Note that in the circuit shown in FIG. 3, the resistor R14, which is an impedance element for extracting the charge of the bases of the first and second transistors Tr13 and Tr14 when switching the second field effect transistor SW3 from on to off, is It is connected between the collector and base of the first transistor Tr13. Therefore, when the second field effect transistor SW3 is switched from on to off, if the control unit 10 stops outputting the on signal Son and turns off the first switching element Q14, the first and second transistors The charge on the bases of Tr13 and Tr14 can be gradually withdrawn through the impedance elements. Therefore, when the control unit 10 subsequently outputs the off signal Soff to turn on the second switching element Q13, the electric charges of the bases of the first and second transistors Tr13 and Tr14 turn on the second switching element Q13. , and the second field effect transistor SW3 can be switched from on to off in a short time.

The third drive circuit 23 may have only an impedance element (for example, resistor R14) connected between the collector and base of the first transistor Tr13. When the second field effect transistor SW3 is switched from on to off, if the control unit 10 stops outputting the on signal Son and turns off the first switching element Q14, the first and second transistors Tr13, The charge on the base of Tr14 can be gradually withdrawn through the impedance element to turn off the second field effect transistor SW3. Therefore, compared to the case where the second switching element Q13 for turning off the second field effect transistor SW3 is provided, the size of the circuit can be reduced.

In the present embodiment, the first switching element Q14 and the second switching element Q13 are configured by field effect transistors, but the first switching element Q14 and the second switching element Q13 are limited to field effect transistors. not. The first switching element Q14 and the second switching element Q13 may be composed of bipolar transistors or the like.

(Embodiment 2)
A backup power supply system 1 of Embodiment 2 will be described with reference to FIG. 6, illustration of the main switch MS1, the failure detection unit 11, and the charging voltage detection unit 14 is omitted.

The backup power supply system 1 of Embodiment 2 has a circuit configuration in which the second field effect transistor SW3 is an N-channel field effect transistor, and the drive circuit 20 drives the N-channel field effect transistor. It is different from the first embodiment in that In addition, the same code|symbol is attached|subjected to the component which is common in Embodiment 1, and the description is abbreviate|omitted.

The drive circuit 20 includes a push-pull circuit 24 , a first drive circuit 21 , a second drive circuit 22 and a third drive circuit 23 .

The push-pull circuit 24 has a first transistor Tr11 and a second transistor Tr12 connected in series between the positive and negative electrodes of the control power supply VC. The first transistor Tr11 is, for example, an npn-type bipolar transistor, and the second transistor Tr12 is a pnp-type bipolar transistor. The bases of the first transistor Tr11 and the second transistor Tr12 are connected to each other, and the emitters of the first transistor Tr11 and the second transistor Tr12 are connected to each other. ing. Each emitter of the first transistor Tr11 and the second transistor Tr12 is connected to the gate of the second field effect transistor SW3.

The first drive circuit 21 operates the second field effect transistor SW3 in the active region. The first drive circuit 21 outputs a drive signal S12 based on the current command value S11 input from the control unit 10 and the current value of the current flowing through the second field effect transistor SW3 to the first transistor Tr11 and the second transistor. The output to the base of Tr12 causes the second field effect transistor SW3 to operate in the active region. Since the first drive circuit 21 has the same configuration as that of the first embodiment, its description is omitted.

The second drive circuit 22 turns on the second field effect transistor SW3.

The second drive circuit 22 has a first switching element Q11 connected between the collector and the base of the first transistor Tr11 and turned on by an ON signal Son input from the control section 10 . The first switching element Q11 is composed of, for example, an N-channel MOSFET.

The first switching element Q<b>11 is turned on by an on-signal Son input from the control section 10 . When the first switching element Q11 is turned on, the base potential of the first transistor Tr11 and the second transistor Tr12 becomes equal to the potential on the positive side of the control power supply VC, and the output voltage of the push-pull circuit 24 becomes equal to that of the control power supply VC. equal to the potential on the positive electrode side. As a result, a voltage exceeding the pinch-off voltage is applied between the gate and source of the second field effect transistor SW3, and the second field effect transistor SW3 is operated in a saturated state, that is, turned on. Since the first switching element Q11 is provided after the first transistor Tr11, the first switching element Q14 can be made smaller than when the switching element is connected between the electrodes of the second field effect transistor SW3. It can be realized by switching elements of capacitance, and the size of the circuit can be reduced.

The third drive circuit 23 turns off the second field effect transistor SW3.

The third drive circuit 23 includes an impedance element (for example, a resistor R12) connected between the collector and base of the second transistor Tr12, and a second switching element Q12 connected between the collector and base of the second transistor Tr12. and have When the second switching element Q12 is turned on by the off signal Soff input from the control section 10, the second field effect transistor SW3 is turned off. The second switching element Q12 is composed of, for example, an N-channel MOSFET. The impedance element is, for example, the resistor R12, but any circuit element other than the resistor may be used as long as it has an impedance component.

The second switching element Q<b>12 is turned on by an off signal Soff input from the control section 10 . When the second switching element Q12 is turned on, the base potentials of the first transistor Tr11 and the second transistor Tr12 become equal to the source potential of the second field effect transistor SW3, and the output voltage of the push-pull circuit 24 also becomes the second 2 equal to the potential of the source of the field effect transistor SW3. As a result, the gate-source voltage of the second field effect transistor SW3 becomes substantially zero, and the second field effect transistor SW3 operates in the blocking region, that is, is turned off.

Since the second switching element Q12 is provided in the subsequent stage of the second transistor Tr12, the second switching element Q12 can be used more efficiently than in the case where the switching element is connected between the electrodes of the second field effect transistor SW3. It can be realized with a small-capacity switching element, and miniaturization of the circuit can be achieved.

In this embodiment, the third drive circuit 23 has the impedance element (resistor R12) and the second switching element Q12, but the third drive circuit 23 has the impedance element and the second switching element Q12. It is not essential to have both

The third drive circuit 23 may have only the second switching element Q12. That is, the third drive circuit 23 only needs to have the second switching element Q12 connected between the collector and base of the second transistor Tr12. When the second switching element Q12 is turned on by the off signal Soff input from the control section 10, the second field effect transistor SW3 is turned off. Since the second switching element Q12 is provided after the second transistor Tr12, a switching element for turning off the second field effect transistor SW3 is connected between the electrodes of the second field effect transistor SW3. The second switching element Q12 can be realized by a switching element with a small capacity, and the circuit can be miniaturized.

Note that in this embodiment, when the second field effect transistor SW3 is switched from on to off, the resistor R12, which is an impedance element for extracting the charge of the bases of the first and second transistors Tr11 and Tr12, is the second resistor. is connected between the collector and the base of the transistor Tr12. Therefore, when the second field effect transistor SW3 is switched from on to off, when the control unit 10 stops outputting the on signal Son and turns off the first switching element Q11, the first and second transistors Tr11 , Tr12 can be withdrawn through the impedance element. Therefore, when the control unit 10 subsequently outputs the off signal Soff to turn on the second switching element Q12, the charges of the bases of the first and second transistors Tr11 and Tr12 turn on the second switching element Q12. , and the second field effect transistor SW3 can be switched from on to off in a short time.

The third drive circuit 23 may have only an impedance element (for example, resistor R12) connected between the collector and base of the second transistor Tr12. When the second field effect transistor SW3 is switched from on to off, when the on signal Son stops and the first switching element Q11 is turned off, the base charges of the first and second transistors Tr11 and Tr12 are discharged. , can be pulled through the impedance element, turning off the second field effect transistor SW3. Therefore, compared to the case where the second switching element Q12 for turning off the second field effect transistor SW3 is provided, the size of the circuit can be reduced.

In this embodiment, the first switching element Q11 and the second switching element Q12 are configured by field effect transistors, but the first switching element Q11 and the second switching element Q12 are limited to field effect transistors. not. The first switching element Q11 and the second switching element Q12 may be composed of bipolar transistors or the like.

(3) Modification The backup power supply system 1 is installed in a moving object such as a vehicle. That is, the mobile includes a backup power supply system 1 and a mobile main body (for example, a vehicle body). A mobile main body is equipped with a backup power supply system 1 , a main power supply 2 , and a load 4 . A backup power supply system 1 supplies electric power from a power storage device 3 to a load 4 (for example, an electric brake system, etc.) when a vehicle main power supply 2 (for example, a vehicle battery) fails. As a result, even if the main power supply 2 fails, the load 4 can continue to operate by power supply from the power storage device 3 .

It should be noted that the mobile object on which the backup power supply system 1 is mounted is not limited to a vehicle, and may be an airplane, a ship, a train, or the like. Moreover, the backup power supply system 1 is not limited to being mounted on a moving object, and may be installed and used in a facility or the like.

(summary)
As described above, the backup power supply system (1) of the first aspect includes a first connection terminal (T1), a second connection terminal (T2), a first field effect transistor (SW1), an N-channel type second field effect transistor (SW3), a control section (10) and a drive circuit (20). A main power supply (2) is connected to the first connection terminal (T1). A load (4) is connected to the second connection terminal (T2). A first field effect transistor (SW1) is connected between the first connection terminal (T1) and the second connection terminal (T2). A second field effect transistor (SW3) is connected between the connection point of the first field effect transistor (SW1) and the second connection terminal (T2) and the storage device (3). A drive circuit (20) drives a second field effect transistor (SW3). In a non-failure state in which the main power supply (2) has not failed, the control unit (10) turns on the first field effect transistor (SW1), controls the drive circuit (20), and controls the second power supply (2). The storage device (3) is charged through the charging path (RT1) by operating the field effect transistor (SW3) in the active region. The charging path (RT1) is the path from the main power supply (2) through the first field effect transistor (SW1) and the second field effect transistor (SW3). In a failed state in which the main power supply (2) fails, the control unit (10) turns off the first field effect transistor (SW1) and controls the drive circuit (20) to turn on the second power supply. Power is supplied to the load (4) via the backup path (RT2) by turning on the field effect transistor (SW3). The backup path (RT2) is the path from the storage device (3) through the second field effect transistor (SW3). The drive circuit (20) includes a push-pull circuit (24) comprising a first transistor (Tr11) and a second transistor (Tr12), a first drive circuit (21), a second drive circuit (22), and a third drive circuit (23). A push-pull circuit (24) consisting of a first transistor (Tr11) and a second transistor (Tr12) is connected in series between the positive and negative terminals of the control power supply (VC). The emitters of the first transistor (Tr11) and the second transistor (Tr12) are connected to the gate of the second field effect transistor (SW3). A second drive circuit (22) turns on a second field effect transistor (SW3). A third drive circuit (23) turns off the second field effect transistor (SW3). A first drive circuit (21) outputs a drive signal (S12) based on a current command value (S11) input from a control section (10) and a current value of a current flowing through a second field effect transistor (SW3). The second field effect transistor (SW3) is operated in the active region by outputting to the bases of the first transistor (Tr11) and the second transistor (Tr12). The second drive circuit (22) is connected between the collector and base of the first transistor (Tr11), and is turned on by an ON signal (Son) input from the control section (10). ).

According to this aspect, it is possible to reduce the size of the circuit.

In the backup power supply system (1) of the second aspect, in the first aspect, the third drive circuit (23) has the impedance element (R12) connected between the collector and base of the second transistor (Tr12) as have.

According to this aspect, it is possible to reduce the size of the circuit.

In the backup power supply system (1) of the third aspect, in the first aspect, the third drive circuit (23) includes a second switching element ( Q12). The second field effect transistor (SW3) is turned off when the second switching element (Q12) is turned on by the off signal (Soff) input from the control section (10).

According to this aspect, it is possible to reduce the size of the circuit.

In the backup power supply system (1) of the fourth aspect, in the first aspect, the third drive circuit (23) has an impedance element (R12) and a second switching element (Q12). An impedance element (R12) is connected between the collector and base of the second transistor (Tr12). The second switching element (Q12) is connected between the collector and base of the second transistor (Tr12). The second field effect transistor (SW3) is turned off when the second switching element (Q12) is turned on by the off signal (Soff) input from the control section (10).

According to this aspect, it is possible to reduce the size of the circuit. Also, the time for the second field effect transistor (SW3) to switch from on to off can be shortened.

A backup power supply system (1) of a fifth aspect includes a first connection terminal (T1), a second connection terminal (T2), a first field effect transistor (SW1), a P-channel second electric field It comprises an effect transistor (SW3), a control section (10) and a drive circuit (20). A main power supply (2) is connected to the first connection terminal (T1). A load (4) is connected to the second connection terminal (T2). A first field effect transistor (SW1) is connected between the first connection terminal (T1) and the second connection terminal (T2). A second field effect transistor (SW3) is connected between the connection point of the first field effect transistor (SW1) and the second connection terminal (T2) and the storage device (3). A drive circuit (20) drives a second field effect transistor (SW3). In a non-failure state in which the main power supply (2) has not failed, the control unit (10) turns on the first field effect transistor (SW1), controls the drive circuit (20), and controls the second power supply (2). The storage device (3) is charged through the charging path (RT1) by operating the field effect transistor (SW3) in the active region. The charging path (RT1) is the path from the main power supply (2) through the first field effect transistor (SW1) and the second field effect transistor (SW3). In a failed state in which the main power supply (2) fails, the control unit (10) turns off the first field effect transistor (SW1) and controls the drive circuit (20) to turn on the second power supply. Power is supplied to the load (4) via the backup path (RT2) by turning on the field effect transistor (SW3). The backup path (RT2) is the path from the storage device (3) through the second field effect transistor (SW3). The drive circuit (20) includes a push-pull circuit (24) comprising a first transistor (Tr13) and a second transistor (Tr14), a first drive circuit (21), a second drive circuit (22), and a third drive circuit (23). A push-pull circuit (24) consisting of a first transistor (Tr13) and a second transistor (Tr14) is connected in series between the source of the second field effect transistor (SW3) and the reference potential. The emitters of the first transistor (Tr13) and the second transistor (Tr14) are connected to the gate of the second field effect transistor (SW3). A second drive circuit (22) turns on a second field effect transistor (SW3). A third drive circuit (23) turns off the second field effect transistor (SW3). A first drive circuit (21) outputs a drive signal (S12) based on a current command value (S11) input from a control section (10) and a current value of a current flowing through a second field effect transistor (SW3). The second field effect transistor (SW3) is operated in the active region by outputting to the bases of the first transistor (Tr13) and the second transistor (Tr14). The second drive circuit (22) is connected between the collector and base of the second transistor (Tr14), and is turned on by the ON signal (Son) input from the control section (10). ).

According to this aspect, it is possible to reduce the size of the circuit.

In the backup power supply system (1) of the sixth aspect, in the fifth aspect, the third drive circuit (23) has an impedance element (R14) connected between the collector and base of the first transistor (Tr13) as have.

According to this aspect, it is possible to reduce the size of the circuit.

In the backup power supply system (1) of the seventh aspect, in the fifth aspect, the third drive circuit (23) includes a second switching element ( Q13). The second field effect transistor (SW3) is turned off by turning on the second switching element (Q13) by the off signal (Soff) input from the control section (10).

According to this aspect, it is possible to reduce the size of the circuit.

In the backup power supply system (1) of the eighth aspect, in the fifth aspect, the third drive circuit (23) has an impedance element (R14) and a second switching element (Q13). The impedance element (R14) is connected between the collector and base of the first transistor (Tr13). The second switching element (Q13) is connected between the collector and base of the first transistor (Tr13). The second field effect transistor (SW3) is turned off by turning on the second switching element (Q13) by the off signal (Soff) input from the control section (10).

According to this aspect, it is possible to reduce the size of the circuit. Also, the time for the second field effect transistor (SW3) to switch from on to off can be shortened.

The configurations according to the second to fourth aspects are not essential to the backup power supply system (1) according to the first aspect, and can be omitted as appropriate. The configurations according to the sixth to eighth aspects are not essential configurations for the backup power supply system (1) according to the fifth aspect, and can be omitted as appropriate.

1 backup power supply system 2 main power supply 3 power storage device 4 load 10 control unit 20 drive circuit 21 first drive circuit 22 second drive circuit 23 third drive circuit 24 push-pull circuit Q11, Q14 first switching element Q12, Q13 second second switching element R12, R14 resistance (impedance element)
RT1 charging path RT2 backup path S11 current command value S12 drive signal Soff OFF signal Son ON signal SW1 First field effect transistor SW3 Second field effect transistor T1 First connection terminal T2 Second connection terminal Tr11, Tr13 First transistor Tr12, Tr14 second transistor VC control power supply

Claims (8)

a first connection terminal to which a main power supply is connected;
a second connection terminal to which a load is connected;
a first field effect transistor connected between the first connection terminal and the second connection terminal;
a second N-channel field effect transistor connected between a connection point of the first field effect transistor and the second connection terminal and a storage device;
a control unit;
a drive circuit that drives the second field effect transistor,
In a non-failure state in which the main power supply has not failed, the control section turns on the first field effect transistor and controls the drive circuit to turn the second field effect transistor into an active region. charging the storage device via a charging path from the main power supply through the first field effect transistor and the second field effect transistor by operating at
In a failure state in which the main power supply fails, the control unit controls the first field effect transistor to be off and controls the drive circuit to turn on the second field effect transistor. supplying power from the storage device to the load via a backup path through the second field effect transistor;
The drive circuit is
a push-pull circuit of a first transistor and a second transistor connected in series between the positive and negative electrodes of a control power supply and having respective emitters connected to the gate of the second field effect transistor;
a first drive circuit for operating the second field effect transistor in an active region;
a second drive circuit for turning on the second field effect transistor;
a third drive circuit that turns off the second field effect transistor;
The first drive circuit outputs a drive signal based on a current command value input from the control unit and a current value of a current flowing through the second field effect transistor to the bases of the first transistor and the second transistor. operating the second field effect transistor in the active region by outputting to
The second drive circuit has a first switching element connected between the collector and base of the first transistor and turned on by an ON signal input from the control unit.
Backup power system. the third drive circuit has an impedance element connected between the collector and base of the second transistor;
The backup power system of claim 1. The third drive circuit has a second switching element connected between the collector and base of the second transistor,
When the second switching element is turned on by an off signal input from the control unit, the second field effect transistor is turned off.
The backup power system of claim 1. The third drive circuit is
an impedance element connected between the collector and base of the second transistor;
a second switching element connected between the collector and base of the second transistor;
When the second switching element is turned on by an off signal input from the control unit, the second field effect transistor is turned off.
The backup power system of claim 1. a first connection terminal to which a main power supply is connected;
a second connection terminal to which a load is connected;
a first field effect transistor connected between the first connection terminal and the second connection terminal;
a P-channel second field effect transistor connected between a connection point of the first field effect transistor and the second connection terminal and an electricity storage device;
a control unit;
a drive circuit that drives the second field effect transistor,
In a non-failure state in which the main power supply has not failed, the control section turns on the first field effect transistor and controls the drive circuit to turn the second field effect transistor into an active region. charging the storage device via a charging path from the main power supply through the first field effect transistor and the second field effect transistor by operating at
In a failure state in which the main power supply fails, the control unit controls the first field effect transistor to be off and controls the drive circuit to turn on the second field effect transistor. supplying power from the storage device to the load via a backup path through the second field effect transistor;
The drive circuit is
a first transistor and a second transistor connected in series between the source of the second field effect transistor and a reference potential and having emitters connected to the gate of the second field effect transistor; a push-pull circuit;
a first drive circuit that operates the second field effect transistor in an active region;
a second drive circuit for turning on the second field effect transistor;
a third drive circuit that turns off the second field effect transistor;
The first drive circuit outputs a drive signal based on a current command value input from the control unit and a current value of a current flowing through the second field effect transistor to the bases of the first transistor and the second transistor. operating the second field effect transistor in the active region by outputting to
The second drive circuit has a first switching element connected between the collector and base of the second transistor and turned on by an ON signal input from the control unit.
Backup power system. the third drive circuit has an impedance element connected between the collector and base of the first transistor;
6. The backup power system of claim 5. The third drive circuit has a second switching element connected between the collector and base of the first transistor,
When the second switching element is turned on by an off signal input from the control unit, the second field effect transistor is turned off.
6. The backup power system of claim 5. The third drive circuit is
an impedance element connected between the collector and base of the first transistor;
a second switching element connected between the collector and base of the first transistor;
When the second switching element is turned on by an off signal input from the control unit, the second field effect transistor is turned off.
6. The backup power system of claim 5.

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