JP2022100912A - Semiconductor device - Google Patents

Abstract

To prevent loss of confidentiality and authenticity due to security attacks on the reverse side.SOLUTION: A semiconductor device mounted on a circuit board 1 having a first surface on which electronic circuits 15 are formed and a second surface that is the reverse side of the first surface, with the first surface facing a printed circuit board 2, comprises a wiring board 17 to be attached to the second side of the circuit board 1, and the circuit board 1 has a via conductor 14 connecting the first surface and the second surface, and the electronic circuits 15 are connected through the via conductor 14 to a wiring conductor 13c on the bonding surface of the circuit board 17.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device capable of preventing deterioration of confidentiality and authenticity due to a security attack on the back surface of a circuit board.

Conventionally, with the progress of semiconductor manufacturing technology, various semiconductor devices including integrated electronic circuits have been used for processing signals.

Certain signal processing (eg, encryption and decryption) may require the confidentiality and / or authenticity of the signal being processed. In this case, it is required that the signal containing the confidential information is not transmitted to the signal line that can be directly accessed from the outside. Further, it is required that the circuit for processing the signal containing confidential information does not leak the contents of the signal in the form of unnecessary radio waves or power supply noise.

For example, Patent Document 1 describes a technique of a backside embedded wiring structure that prevents security attacks such as noise observation and fault injection through the backside silicon substrate of an IC chip and detects physical attacks, that is, exposure attacks from the backside. It has been disclosed.

Japanese Unexamined Patent Publication No. 2019-110293

However, the above-mentioned Patent Document 1 has a problem that the back surface of the circuit board is exposed when the flip chip is mounted on the printed circuit board with the electronic circuit side of the IC chip facing down. Therefore, it is possible for an attacker to take a workaround, such as a bypass attack such as providing a bypass circuit for the wiring on the back surface, and there is a possibility that the attacker will be attacked at a high level.

The present invention has been made to solve the above-mentioned problems (problems) caused by the prior art, and is a semiconductor device capable of preventing deterioration of confidentiality and authenticity due to a security attack on the back surface of a circuit board. The purpose is to provide.

In order to solve the above-mentioned problems and achieve the object, the present invention relates to the first surface of a circuit board having a first surface on which an electronic circuit is formed and a second surface behind the first surface. A semiconductor device in which the surface of the circuit board is mounted toward the printed circuit board, the present invention includes a wiring board to be bonded to the second surface of the circuit board, and the circuit board has the first surface and the second surface. The electronic circuit is characterized by being connected to a wiring conductor provided on a joint surface of the wiring board via the via conductor.

Further, the present invention is characterized in that, in the above invention, the circuit board and the wiring board are bonded by an oxide film bond.

Further, the present invention is characterized in that, in the above invention, the circuit board is flip-chip mounted on the printed circuit board.

Further, the present invention is characterized in that, in the above invention, the wiring conductor is formed of a strip conductor.

Further, the present invention is characterized in that, in the above invention, the wiring conductor is formed in a meander shape, a stripe shape, or a mesh shape.

Further, the present invention is characterized in that, in the above invention, the wiring board is characterized in that a capacitive wiring conductor made of a strip conductor is formed on the joint surface.

Further, in the present invention, in the above invention, the wiring conductor is connected so as to allow the discharge current of the capacitive wiring conductor to flow, and the electronic circuit detects the approach of an object from the change in the capacitance of the capacitive wiring conductor and discharges. It is characterized by being equipped with a capacitance sensor circuit that detects disconnection from static current.

Further, in the present invention, in the above invention, the wiring board is formed in a meander shape on the entire surface of the joint surface, and the electronic circuit is a capacitance sensor that detects the approach of a cutting place and an object by the capacitance change of the wiring conductor. It is characterized by having a circuit.

Further, according to the present invention, in a semiconductor device including a capacity sensor circuit for detecting a change in wiring capacity, the capacity sensor circuit includes a charge / discharge circuit for performing capacity measurement and a reference capacity for improving the sensitivity of capacity measurement. It is characterized by being equipped with a charge / discharge circuit.

According to the present invention, it is possible to provide a semiconductor device capable of preventing deterioration of confidentiality and authenticity due to a security attack on the back surface of a circuit board.

FIG. 1 is a perspective view showing the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device in line AA of FIG. FIG. 3 is a diagram showing a joint surface of the wiring board of FIG. FIG. 4 is a circuit diagram showing a configuration of a capacitance sensor circuit of the semiconductor device according to the first embodiment. FIG. 5 is a timing chart showing the operation of the capacitance sensor circuit of FIG. FIG. 6 is a circuit diagram showing a configuration of a disconnection detection circuit of the semiconductor device according to the first embodiment. FIG. 7 is a timing chart showing the operation of the disconnection detection circuit of FIG. 6, which is a normal operation and an operation when the semiconductor device is attacked. FIG. 8 is a diagram showing a joint surface of the wiring board of the semiconductor device according to the second embodiment. FIG. 9 is a circuit diagram showing a configuration of a capacitance sensor circuit of the semiconductor device according to the second embodiment. FIG. 10 is a timing chart showing the operation of the capacitance sensor circuit of FIG. FIG. 11 is a diagram showing a joint surface of the wiring board of the semiconductor device according to the third embodiment. FIG. 12 is a circuit diagram showing a configuration of a capacitance sensor circuit of the semiconductor device according to the third embodiment. FIG. 13 is a timing chart showing the operation of the capacitance sensor circuit of FIG. FIG. 14 is a circuit diagram showing a configuration of a high resolution capacitance sensor circuit of the semiconductor device according to the fourth embodiment. FIG. 15 is a timing chart showing the operation of the high resolution capacitance sensor circuit of FIG. FIG. 16 is a diagram showing a principle for realizing high resolution of the high resolution capacitance sensor circuit of FIG. FIG. 17 is a diagram showing a computer simulation result of increasing the resolution of the high-resolution capacitance sensor circuit of FIG.

Hereinafter, each embodiment of the semiconductor device according to the present invention will be described in detail with reference to the drawings.

[Embodiment 1]
First, an outline of the semiconductor device according to the first embodiment will be described. In the first embodiment, a semiconductor device in which a circuit board 1 forming an electronic circuit 15 and a wiring board 17 forming wiring conductors 13a, 13b and 13c for detecting a security attack are bonded by an oxide film bond will be described.

FIG. 1 is a perspective view showing the configuration of the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device includes a circuit board 1, a printed circuit board 2, a wiring conductor 3, an oxide film bonding surface 16, and a wiring board 17. The circuit board 1 has two planes parallel to the XY plane of FIG. Here, the surface on which the electronic circuit 15 is provided is referred to as a "first surface", and the back surface of the first surface is referred to as a "second surface".

The circuit board 1 includes a semiconductor substrate 11 and a plurality of wiring layers 12a formed in parallel to the XY plane in the semiconductor substrate 11. For example, the semiconductor substrate 11 is made of, for example, silicon, and the wiring layer 12a is made of, for example, copper. The materials of the semiconductor substrate 11 and the wiring layer 12a are not limited to this. An electronic circuit 15 is formed on the circuit board 1. Further, the circuit board 1 is formed with a via conductor 14 that connects the wiring layer 12a formed on the first surface of the circuit board 1 and the second surface of the circuit board 1.

The electronic circuit 15 includes a detection circuit that detects a cutting attack, a bypass attack, or the like on a semiconductor device. On the first surface of the circuit board 1, a plurality of pad conductors 12ac for supplying electric power to the electronic circuit 15 and inputting / outputting signals are formed.

Like the circuit board 1, the wiring board 17 has two surfaces parallel to the XY plane of FIG. 1, and includes a plurality of embedded wiring conductors 13 formed on the joint surface with the circuit board 1. For example, the wiring board 17 is made of silicon, and the embedded wiring conductor 13 is made of copper.

An oxide film bonding surface 16 is formed on the second surface of the circuit board 1 except for the via conductor portion described later, and the wiring board 17 is superposed on the oxide film bonding surface 16 to form two substrates (circuit board). 1 and the wiring board 17) are joined. As described above, since the oxide film is an insulating film, the oxide film bonding surface 16 is not formed on the via conductor portion of the second surface. Here, the oxide film bonding is a technique for forming an oxide film on the bonding surface of a silicon wafer by superimposing and heating silicon wafers to bond the wafers to each other. The advantages of the oxide film bond are that the bonding strength is strong and that the substrate potential of the wiring board 17 can be insulated from the substrate potential of the circuit board 1 (usually the ground potential) to form a floating node.

With such a configuration, the embedded wiring conductor 13 of the wiring board 17 is not exposed on the surface opposite to the connecting surface of the wiring board 17, and an attacker's bypass attack can be prevented. Further, since the substrate potential of the wiring board 17 is insulated from the substrate potential of the circuit board 1 (usually the ground potential) and is set to a floating potential, it is necessary to detect an electric field change from the outside by providing a capacitive circuit on the wiring board 17. Can be done.

The semiconductor device in which the circuit board 1 and the wiring board 17 are bonded by an oxide film bond is flip-chip mounted on the printed circuit board 2 on the first surface of the circuit board 1 on which the electronic circuit 15 is formed, for example, by a bump conductor or the like. ing. Such flip-chip mounting is a mounting technique in which a bare chip obtained by cutting out a semiconductor into a chip is flipped (reversed) and mounted.

The printed circuit board 2 is a substrate for connecting between a plurality of semiconductor devices and applying a power supply voltage _VDD from the outside, and is made of resin or ceramic. The wiring conductor 3 is wiring for applying a power supply voltage _VDD to a semiconductor device and transmitting a signal. The description of the embedded wiring conductor 13 will be described later.

Next, the configuration of the semiconductor device according to the first embodiment will be described. FIG. 2 is a cross-sectional view of the semiconductor device in line AA of FIG. As shown in FIG. 2, the circuit board 1 includes a semiconductor substrate 11, a multilayer wiring conductor 12, a via conductor 14, and an electronic circuit 15. Further, the wiring board 17 includes an embedded wiring conductor 13. The circuit board 1 and the wiring board 17 are bonded to each other by the oxide film bonding surface 16.

The circuit board 1 and the wiring board 17 to which the oxide film is bonded are bonded with a strong bonding strength. Further, the substrate potential of the wiring board 17 is insulated from the substrate potential of the circuit board 1 (usually the ground potential) and becomes a floating potential. Therefore, by providing the capacitance circuit on the wiring board 17, it is possible to detect the change in the electric field from the outside.

The semiconductor substrate 11 has a multilayer wiring conductor 12 including a plurality of wiring layers 12a on the first surface of the circuit board 1. In the example of FIG. 2, the multilayer wiring conductor 12 includes six wiring layers 12a. Each wiring layer 12a is patterned by any semiconductor process technique. As a result, the electronic circuit 15 is formed on the multilayer wiring conductor 12. The electronic circuit 15 includes a plurality of circuit elements 15a such as transistors, diodes, capacitors, resistors, and inductors.

The electronic circuit 15 can be formed by CMOS process technology or other process technology. Further, a part of the wiring layer 12a is formed as a pad conductor 12ac. The via conductor 14 is formed so as to penetrate the semiconductor substrate 11 in the Z direction (thickness direction). At least one via conductor 14 is electrically connected to the multilayer wiring conductor 12, and at least one via conductor 14 is formed as an electrode on the second surface of the circuit board 1.

The wiring board 17 has an embedded wiring conductor 13 on the joint surface of the wiring board 17. The embedded wiring conductor 13 is formed by digging a groove in the wiring board 17 by etching and embedding metal in the groove. Since the printed circuit board 2 has already been described, detailed description thereof will be omitted here.

Next, the pattern of the joint surface of the wiring board 17 of the semiconductor device according to the first embodiment will be described. FIG. 3 is a diagram showing a joint surface of the wiring board 17 of FIG. As shown in FIG. 3, the wiring conductor 13a and the wiring conductor 13b are formed in parallel with each other by strip conductors to form a mutual capacitance circuit. The node N31 and the node N32 are connected to the capacitance sensor circuit 20 in the electronic circuit 15 via the via conductor 14 of FIG.

With such a structure, when an attacker attempts to attack by approaching the probe, the capacitance value measured by the capacitance sensor circuit 20 changes, so that the fact that the probe is approached to attack is detected. be able to.

Further, the wiring conductor 13c includes a plurality of linear strip conductors connected to each other, and is formed in a meander shape from the node N33 to the node N34 so as to substantially cover the entire joint surface of the wiring board 17. The node N33 and the node N34 are connected to the disconnection detection circuit 30 in the electronic circuit 15 via the via conductor 14 of the circuit board 1 coupled with the oxide film of FIG.

With such a structure, when an attacker makes a remote attack with a laser, the wiring conductor 13c is cut and the cutting detection circuit 30 can detect the fact that the cutting attack has been received.

Next, the configuration of the capacitance sensor circuit 20 will be described. FIG. 4 is a circuit diagram showing the configuration of the capacitance sensor circuit 20 of the semiconductor device according to the first embodiment. As shown in FIG. 4, the capacitance sensor circuit 20 includes switching elements 21, 22, a constant current source 23, a pulse gate circuit 24, and a pulse counter 25. The capacitance sensor circuit 20 is provided inside the electronic circuit 15 and is connected to the node N31 and the node N32 of FIG. 3 via the via conductor 14 of FIG.

The capacitance sensor circuit 20 repeats charging and discharging by alternately turning on and off the switching element 21 and the switching element 22. The pulse gate circuit 24 compares the voltage of the node _N31 with the reference voltage VC, and outputs a pulse signal when the voltage of the node _N31 becomes lower than the reference voltage VC. The pulse counter 25 counts the number of pulses output by the pulse gate circuit 24 and outputs the number of pulses D _OUT .

Next, the operation of the capacitance sensor circuit 20 will be described. FIG. 5 is a timing chart showing the operation of the capacitance sensor circuit 20 of FIG. As shown in FIG. 4, the voltage of the node N31 is charged to the power supply voltage V _DD with the switching element 21 on and the switching element 22 off. After that, when the switching element 21 is turned off and the switching element 22 is turned on, the charge of the capacitance is discharged by the constant current source 23 with a constant current, so that the voltage of the node N31 drops in a slope shape.

The pulse gate circuit 24 outputs the pulse signal V _PULSE when the voltage of the node N 31 becomes lower than the reference voltage VC ( _{t 1} ). Further, when the capacity is charged, when the voltage of the node N31 becomes higher than the reference voltage VC ( _{t 2} ), the output of the pulse signal V _PULSE is stopped.

In the capacitance sensor circuit 20, when the capacitance value connected to the node N31 is large, the timing at which the voltage of the node N31 becomes lower than the reference voltage VC ( _{t 3} ) is delayed as compared with the case where the capacitance value is low. This is because when a large amount of electric charge is discharged by the constant current source 23, it takes time to discharge, that is, the discharge slope of the voltage of the node N31 becomes gentle. On the other hand, when charging the capacity, the charging speed does not have much influence on the magnitude of the capacity value, so that the timing at which the voltage of the node N31 becomes higher than the reference voltage VC ( _{t 4} ) is the same as when the capacity is small.

Therefore, the time for which the pulse signal V _PULSE is output from the pulse gate circuit 24 is long when the capacitance connected to the capacitance sensor circuit 20 is small, and short when the capacitance is large. The capacitance value can be measured by counting the number of pulses of this Pace signal V _PULSE with the pulse counter 25. That is, the approach of the attacker's hand or probe can be detected by this change in the capacitance value.

Next, the configuration of the disconnection detection circuit 30 will be described. FIG. 6 is a circuit diagram showing the configuration of the disconnection detection circuit 30 of the semiconductor device according to the first embodiment. As shown in FIG. 6, the disconnection detection circuit 30 includes switching elements 26 to 28 and a latch circuit 29. The disconnection detection circuit 30 is provided inside the electronic circuit 15 and is connected to the node N33 and the node N34 in FIG. 3 via the via conductor 14 in FIG. The disconnection detection circuit 30 generates a detection signal by inputting a reset signal and applying a constant voltage from other parts of the electronic circuit 15.

Next, the operation of the disconnection detection circuit 30 will be described. FIG. 7 is a timing chart showing the operation of the disconnection detection circuit 30 of FIG. 6, which is a normal operation and an operation when the semiconductor device is attacked. Normally, the voltage of node N33 is equal to the voltage of node N34 (ground voltage) and the detection signal remains low level. On the other hand, when the semiconductor device receives a remote attack by a laser and the wiring conductor 13c is cut, the voltage of the node N33 becomes a high voltage. Therefore, the detection signal shifts from the low level to the high level.

When the detection signal shifts from the low level to the high level, the signal processed inside the semiconductor device can be protected from an attacker by stopping the operation of the electronic circuit 15.

As described above, in the first embodiment, since the circuit board 1 and the wiring board 17 are bonded by an oxide film bond, the circuit such as the wiring conductor is not exposed on the back surface of the semiconductor device, and a bypass attack from the back surface or the like is performed. Can be prevented. Further, by providing the wiring conductors 13a, 13b and 13c in the semiconductor device and the capacitance sensor circuit 20 and the disconnection detection circuit 30 in the electronic circuit 15, the fact that the attacker's probe approached and the like was detected and the cutting attack was received. Can be detected. The semiconductor device according to the first embodiment stops the operation of the electronic circuit 15 when it detects the approach of an attacker's probe and the fact that it has been subjected to a cutting attack, thereby ensuring confidentiality and authenticity due to a security attack. Can be prevented from decreasing.

[Embodiment 2]
By the way, in the first embodiment, separate circuits are used for detecting the approach of the probe of the attacker and detecting the fact that the cutting attack has been received, but the structure of the electronic circuit 15 becomes complicated. Therefore, in the second embodiment, a semiconductor device that detects the approach of the probe of the attacker and the fact that the attack has been cut by a single circuit will be described.

First, the joint surface of the wiring board 17 of the semiconductor device according to the second embodiment will be described. FIG. 8 is a diagram showing a joint surface of the wiring board 17 of the semiconductor device according to the second embodiment. As shown in FIG. 8, the wiring conductor 13d forms a flat plate self-capacity circuit using a strip conductor. Further, the wiring conductor 13e includes a plurality of linear strip conductors connected to each other, and is formed in a meander shape from the node N36 to the node N37 so as to substantially cover the entire joint surface of the wiring board 17. The node N35, the node N36, and the node N37 are connected to the capacitance sensor circuit 40 in the electronic circuit 15 via the via conductor 14 of the circuit board 1 coupled with the oxide film of FIG.

The wiring conductor 13d is connected to the capacitance sensor circuit 40 in the electronic circuit 15 as a self-capacity circuit. The capacitance value of the wiring conductor 13d increases due to the approach of the probe or the like. Therefore, the capacitance sensor circuit 40 can detect the change in the capacitance value and detect the fact that the probe or the like is approaching.

Further, the wiring conductor 13e is connected to the charge discharge path of the self-capacity circuit formed by the wiring conductor 13d of the capacitance sensor circuit 40 via the node N36 and the node N37. The capacitance sensor circuit 40 can detect the fact that the attacker has made a remote attack with a laser or the like because the wiring conductor 13e is cut and the potential of the node N35 becomes a high potential when the attacker makes a cutting attack or the like.

Next, the configuration of the capacitance sensor circuit 40 will be described. FIG. 9 is a circuit diagram showing the configuration of the capacitance sensor circuit 40 of the semiconductor device according to the second embodiment. As shown in FIG. 9, the capacitance sensor circuit 40 includes switching elements 31, 32, a constant current source 33, a pulse gate circuit 34, and a pulse counter 35. The capacitance sensor circuit 40 is provided inside the electronic circuit 15 and is connected to the node N35, the node N36 and the node N37 of FIG. 8 via the via conductor 14 of FIG.

The capacitance sensor circuit 40 repeatedly charges and discharges the self-capacitating circuit formed by the wiring conductor 13d by alternately turning on and off the switching element 31 and the switching element 32. On the other hand, a meander circuit formed by the wiring conductor 13e is connected to the discharge path of the capacitance sensor circuit 40. The pulse gate circuit 34 compares the voltage of the node _N35 with the reference voltage VC, and outputs a pulse signal when the voltage of the node _N35 becomes lower than the reference voltage VC. The pulse counter 35 counts the number of pulses output by the pulse gate circuit 24 and outputs the number of pulses D _OUT .

Next, the operation of the capacitance sensor circuit 40 will be described. FIG. 10 is a timing chart showing the operation of the capacitance sensor circuit 40 of FIG. As shown in FIG. 10, the voltage of the node N35 is charged to the power supply voltage V _DD with the switching element 31 on and the switching element 32 off. After that, when the switching element 31 is turned off and the switching element 32 is turned on, the constant current source 33 discharges the electric charge of the capacitance through the wiring conductor 13a at a constant current, so that the voltage of the node N35 drops in a slope shape.

The pulse gate circuit 34 outputs the pulse signal V _PULSE when the voltage of the node N35 becomes lower than the reference voltage VC ( _{t 5} ). Further, when the capacity is charged, when the voltage of the node N35 becomes higher than the reference voltage V _c (t ₆ ), the output of the pulse signal V _PULSE is stopped.

In the capacitance sensor circuit 40, when the capacitance value connected to the node N35 is large, the timing at which the voltage of the node N35 becomes lower than the reference voltage VC ( _{t 7} ) is delayed as compared with the case where the capacitance value is low. This is because when a large amount of electric charge is discharged by the constant current source 33, it takes time to discharge. That is, the slope of the voltage discharge of the node N35 becomes gentle. On the other hand, when charging the capacity, the charging speed does not affect the magnitude of the capacity value so much, so the timing when the voltage of the node N35 becomes higher than the reference voltage VC ( _{t 8} ) is the same as when the capacity value is small. ..

Therefore, the time for which the pulse signal V _PULSE is output from the pulse gate circuit 34 is long when the capacitance connected to the capacitance sensor circuit 40 is small, and short when the capacitance is large. The capacitance value can be measured by counting the number of pulses of this Pace signal V _PULSE with the pulse counter 35, that is, the approach of the attacker's hand or probe can be detected by the change of this capacitance value. Further, when the semiconductor device receives a remote attack by a laser from an attacker, the wiring conductor 13e is cut. Therefore, the electric charge is not discharged, and the node N35 is fixed to the power supply potential. As a result, the pulse signal V _PULSE is not output, and the fact that the attacker has received a remote attack by the laser can be detected.

As described above, the semiconductor device according to the second embodiment includes the wiring conductor 13d, the wiring conductor 13e, and the capacitance sensor circuit 40 in the electronic circuit 15, so that the attacker can detect the approach of the probe or the like. , It is possible to detect the fact that a remote attack by a laser has been received. The semiconductor device according to the second embodiment is confidential and authentic due to a security attack by stopping the operation of the electronic circuit 15 when the attacker detects the approach of the probe or the fact that the electronic circuit 15 is remotely attacked by the laser. It is possible to prevent deterioration of sex.

[Embodiment 3]
By the way, in the above-described first and second embodiments, two circuits, a capacitive circuit for detecting the approach of the probe and a meander circuit for detecting the disconnection of the wiring due to the remote attack by the laser, are required. Therefore, in the third embodiment, a semiconductor device that detects the approach of the probe and the disconnection of the wiring due to the remote attack by the laser will be described only by the meander circuit.

First, the joint surface of the wiring board 17 of the semiconductor device according to the third embodiment will be described. FIG. 11 is a diagram showing a joint surface of the wiring board 17 of the semiconductor device according to the third embodiment. As shown in FIG. 11, the wiring conductor 13f includes a plurality of linear strip conductors connected to each other, and is formed in a meander shape from node N38 to node N39 so as to substantially cover the entire joint surface of the wiring board 17. It is formed. The node N38 and the node N39 are connected to the capacitance sensor circuit 50 in the electronic circuit 15 via the via conductor 14 of the circuit board 1 electrically connected by the oxide film coupling of FIG.

The wiring conductor 13f is connected to the capacitance sensor circuit 50 in the electronic circuit 15 as a self-capacity circuit. The capacitance value of the wiring conductor 13f increases due to the approach of the probe or the like. Therefore, the capacitance sensor circuit 50 can detect the change in the capacitance value and detect the fact that the probe or the like is approaching.

Further, the capacitance value of the wiring conductor 13f decreases when the wiring conductor 13f is cut by a remote attack by a laser. Therefore, the capacitance sensor circuit 50 can detect the decrease in the capacitance value and detect the fact that the attacker has received a remote attack by the laser.

Next, the configuration of the capacitance sensor circuit 50 will be described. FIG. 12 is a circuit diagram showing the configuration of the capacitance sensor circuit 50 of the semiconductor device according to the third embodiment. As shown in FIG. 12, the capacitance sensor circuit 50 includes switching elements 41 and 42, a constant current source 43, a pulse gate circuit 44, and a pulse counter 45. The capacitance sensor circuit 50 is provided in the electronic circuit 15 and is connected to the node 38 and the node N39 in FIG. 11 via the via conductor 14 in FIG.

The capacitance sensor circuit 50 repeats charging and discharging by alternately turning on and off the switching element 41 and the switching element 42. The pulse gate circuit 44 compares the voltage of the node _N38 with the reference voltage VC, and outputs a pulse signal when the voltage of the node _N38 becomes lower than the reference voltage VC. The pulse counter 45 counts the number of pulses output by the pulse gate circuit 44, and outputs the number of pulses D _OUT .

Next, the operation of the capacitance sensor circuit 50 will be described. FIG. 13 is a timing chart showing the operation of the capacitance sensor circuit 50 of FIG. As shown in FIG. 12, the voltage of the node N38 is charged to the power supply voltage V _DD with the switching element 41 on and the switching element 42 off. After that, when the switching element 41 is turned off and the switching element 42 is turned on, the charge of the capacitance is discharged by the constant current source 43 with a constant current, so that the voltage of the node N38 drops in a slope shape.

The pulse gate circuit 44 outputs the pulse signal V _PULSE when the voltage of the node N 38 becomes lower than the reference voltage VC ( _{t 9} ). Further, when the capacity is charged, when the voltage of the node _N38 becomes higher than the reference voltage VC (t ₁₀ ), the output of the pulse signal V _PULSE is stopped.

In the capacitance sensor circuit 50, when the capacitance value connected to the node N38 is large, the timing at which the voltage of the node _N38 becomes lower than the reference voltage VC (t ₁₁ ) is delayed as compared with the case where the capacitance value is low. This is because when a large amount of electric charge is discharged by the constant current source 43, it takes a long time to discharge, that is, the discharge slope of the voltage of the node N38 becomes gentle. On the other hand, when charging the capacity, the charging speed does not have much influence on the magnitude of the capacity value, so that the timing at which the voltage of the node _N38 becomes higher than the reference voltage VC (t ₁₂ ) is the same as when the capacity is small.

On the other hand, in the capacitance sensor circuit 50, when the wiring conductor 13f is cut, the self-capacity value of the wiring conductor 13f decreases. As a result, the timing (t ₁₃ ) at which the voltage of the node _N38 becomes lower than the reference voltage VC becomes earlier than the timing before the wiring conductor 13f is cut, for example, t ₉ . With such a configuration, it is possible to detect the approach of the probe by the attacker and the fact that the remote attack by the laser is received only by the wiring conductor 13f. Further, since the capacitance value changes depending on the wiring length from the cutting location of the wiring conductor 13f to the node N38, the cutting location can be specified by measuring the capacitance value with the capacitance sensor circuit 50.

As described above, in the third embodiment, by providing the wiring conductor 13f and the capacitance sensor circuit 50 in the electronic circuit 15 in the semiconductor device, the attacker detects the approach of the probe and the remote attack by the laser is received. Can be detected. The semiconductor of the third embodiment is concealed by a security attack from the back surface of the circuit board 1 by stopping the operation of the electronic circuit 15 when the approach of the probe is detected or the fact that the remote attack is received by the laser is detected. And the deterioration of authenticity can be prevented.

[Embodiment 4]
By the way, in the above-described first to third embodiments, there are cases where the resolution of the capacitive sensor circuit is not sufficient. Therefore, in the fourth embodiment, a semiconductor device having an improved resolution of the capacitance sensor circuit will be described.

First, the configuration of the high-resolution capacitance sensor circuit 60 of the semiconductor device according to the fourth embodiment will be described. FIG. 14 is a circuit diagram showing the configuration of the high resolution capacitance sensor circuit 60 of the semiconductor device according to the fourth embodiment. As shown in FIG. 14, the high-resolution capacitance sensor circuit 60 is composed of a charge / discharge circuit 60a composed of switching elements 51 and 52 and a constant current source 53, and switching elements 54 and 55, a constant current source 56 and a reference capacitance 59. It includes a charge / discharge circuit 60b, a pulse gate circuit 57, and a pulse counter 58. The high-resolution capacitance sensor circuit 60 is provided inside the electronic circuit 15 and is connected to the node N35, the node N36, and the node N37 of FIG. 3 via the via conductor 14 of FIG.

The high-resolution capacitance sensor circuit 60 fills the self-capacity circuit formed by the wiring conductor 13d by alternately turning on / off the switching element 51 and the switching element 52 of the charge / discharge circuit 60a connected to the power supply voltage V _DD . Repeat the discharge. Further, in the high resolution capacitance sensor circuit 60, a meander circuit formed by a wiring conductor 13e is connected to the discharge path. Then, the high-resolution capacitance sensor circuit 60 repeatedly charges and discharges the reference capacitance 59 by alternately turning on and off the switching element 54 and the switching element 55 of the charge / discharge circuit _60b connected to the reference voltage VC, and the node. The voltage of N40 is used as the reference voltage of the pulse gate circuit 57.

The pulse gate circuit 57 outputs a pulse signal V _PULSE when the voltage of the node N35 becomes lower than the voltage of the node N40. Since the voltage of the node N40 changes in a slope shape during the time when the pulse gate circuit 57 outputs the pulse, the time when the pulse signal V _PULSE is output becomes longer with respect to the change in the capacitance value. That is, since the number of pulses D _OUT output increases for a certain capacitance value, the capacitance value per unit pulse becomes small and the resolution becomes high. The pulse counter 58 counts the number of pulses output by the pulse gate circuit 57, and outputs the pulse number D _OUT .

Next, the operation of the high resolution capacitance sensor circuit 60 will be described. FIG. 15 is a timing chart showing the operation of the high resolution capacitance sensor circuit 60 of FIG. As shown in FIG. 14, the voltage of the node N35 is charged to the power supply voltage V _DD with the switching element 51 of the charge / discharge circuit 60a on and the switching element 52 off. After that, when the switching element 51 is turned off and the switching element 52 is turned on, the constant current source 53 discharges the electric charge of the capacitance through the wiring conductor 13e at a constant current, so that the voltage of the node N35 drops in a slope shape.

Further, the voltage of the node N40, which is the reference voltage of the pulse gate circuit 57, is charged to the reference voltage _VC with the switching element 54 of the charge / discharge circuit 60b on and the switching element 55 off. After that, when the switching element 54 is turned off and the switching element 55 is turned on, the charge of the reference capacitance 59 is discharged by the constant current source 56 with a constant current, so that the voltage of the node N40 also drops in a slope shape.

The pulse gate circuit 57 outputs a pulse signal V _PULSE when the voltage of the node N35 becomes lower than the voltage of the node N40 (t ₁₅ ). Further, when the capacity is charged, when the voltage of the node N35 becomes higher than the voltage of the node N40 (t ₁₆ ), the output of the pulse signal V _PULSE is stopped.

In the high-resolution capacitance sensor circuit 60, when the capacitance value connected to the node N35 is large, the timing at which the voltage of the node N35 becomes lower than the voltage of the node N40 (t ₁₇ ) is delayed as compared with the case where the capacitance value is low. .. This is because when a large amount of electric charge is discharged by the constant current source 53, it takes a long time to discharge, that is, the discharge slope of the voltage of the node N35 becomes gentle. On the other hand, when charging the capacity, the charging speed does not have much influence on the magnitude of the capacity value, so that the timing at which the voltage of the node N35 becomes higher than the voltage of the node N45 (t ₁₈ ) is the same as when the capacity value is small.

Therefore, the time for which the pulse signal V _PULSE is output from the pulse gate circuit 57 is long when the capacitance connected to the high resolution capacitance sensor circuit 60 is small, and short when the capacitance is large. Since the high-resolution capacitance sensor circuit 60 changes the voltage of the node N40 that controls the output of the pulse number D _OUT of the pulse gate circuit 57 in a slope shape, the capacitance value connected to the node N35 is the conventional capacitance sensor circuit. Even if it is the same as 20, the time for outputting the pulse of the pulse signal V _PULSE can be lengthened.

Next, the principle for realizing the high resolution of the high resolution capacitance sensor circuit 60 will be described. FIG. 16 is a diagram showing a principle for realizing high resolution of the high resolution capacitance sensor circuit 60 of FIG. As shown in FIG. 16, the slope of the voltage change of the node N35 in the normal state (hereinafter referred to as “slope 5”) is such that the capacitance value connected to the node N35 is C _SENSE and the current value of the constant current source 53 is the current value. Assuming I ₁ , it is expressed by the following equation.
dV / dt = I ₁ / C _SENSE

When an attacker brings a probe or the like close to the node N35, the capacitance value of the node N35 of the high-resolution capacitance sensor circuit 60 increases. Therefore, if the increased capacitance value is ΔC, the slope of the voltage change of the node N35 (hereinafter, “slope 6”). ") Is expressed by the following equation.
dV / dt = I ₁ / C _SENSE + ΔC

Here, assuming that the reference voltage of the pulse gate circuit 24 of the conventional capacitance sensor circuit 20 is V _C ', in the pulse signal V _PULSE of the pulse gate circuit 24 in the normal state, the voltage of the node N35 having a gradient 5 is the reference voltage V _C. 'It is output from the lower timing (t ₁₉ ). Further, when an attacker approaches a probe or the like, the pulse signal V _PULSE of the pulse gate circuit 24 is output from the timing (t ₂₀ ) when the voltage of the node N35 having a slope 6 becomes lower than the reference voltage _VC '. ..

The pulse signal V _PULSE of the pulse gate circuit 24 stops when the voltage of the node N35 becomes higher than the reference voltage _VC ', but in the case of charging, it becomes almost constant regardless of the capacitance value. Therefore, the difference dD _OUT of the number of pulses D _OUT counted by the pulse counter 25 in normal times and when the attacker approaches the probe or the like is expressed by the following equation, where P _t is the number of pulses per unit time. Is done.
dD _OUT = (t ₂₀ -t ₁₉ ) x P _t

On the other hand, the inclination of the node N40 of the pulse gate circuit 57 of the high-resolution capacitance sensor circuit 60 (hereinafter referred to as “inclination 7”) is such that the capacitance value of the reference capacitance 59 is C _REF and the constant current source 56 of the charge / discharge circuit 60b. Assuming that the current value is I ₂ , it is expressed by the following equation.
dV / dt = I ₂ / C _REF

The pulse output V _PULSE of the normal pulse gate circuit 57 of the high resolution capacitance sensor circuit 60 is output from the timing (t ₁₉ ) when the voltage of the node N35 having a slope 5 becomes lower than the voltage of the node N40 having a slope 7. Further, when an attacker approaches a probe or the like, the pulse signal V _PULSE of the pulse gate circuit 57 is output from the timing (t ₂₁ ) when the voltage of the node N35 having a slope 6 becomes lower than the voltage of the node N40 having a slope 7. Will be done.

The pulse signal V _PULSE of the pulse gate circuit 57 stops when the voltage of the node N35 becomes higher than the voltage of the node N40 of the inclination 7, but in the case of charging, it becomes almost constant regardless of the capacitance value. Therefore, the difference dD _OUT2 of the number of pulses D _OUT counted by the pulse counter 58 in normal times and when the attacker even approaches the probe or the like is expressed by the following equation, where P _t is the number of pulses per unit time. Is done.
dD _OUT2 = (t ₂₁ -t ₁₉ ) x P _t

Here, since t ₂₁ is a value larger than t ₂₀ , dD _{OUT 2} is a value larger than dD _OUT . In this way, when the same capacitance difference ΔC is expressed by the number of pulses, the larger the pulse number D _OUT , the smaller the capacitance change per unit pulse, and the higher the resolution. That is, a high-resolution sensor can be realized.

Next, the characteristics of the high-resolution capacitance sensor circuit 60 will be described with simulation results. FIG. 17 is a diagram showing a computer simulation result of increasing the resolution of the high-resolution capacitance sensor circuit 60 of FIG. As shown in FIG. 17, in the computer simulation, the output of the pulse counter 25 of the conventional capacitance sensor circuit 20 and the output of the pulse counter 58 of the high resolution capacitance sensor circuit 60 when the capacitance difference ΔC is changed from 1fF to 1pF. Was calculated.

Comparing the outputs of the pulse counters 25 and 58 with the number of pulses D _OUT , the output of the pulse counter 58 of the high resolution capacitance sensor circuit 60 has a larger change with respect to the same capacitance change, and the high resolution capacitance sensor circuit 60 has a larger change. , High resolution can be realized against changes in capacitance value.

As described above, in the fourth embodiment, the reference capacitance 59 and the charge / discharge circuit 60b are used for the reference signal of the pulse gate circuit 57, and the slope-shaped voltage change is used. The resolution capacity sensor circuit 60 can be realized. The high-resolution capacity sensor circuit 60 can detect the fact that the probe is approaching due to the backside attack of the circuit board 1 and the fact that it is remotely attacked by the laser from a smaller capacity change, and is confidential due to a security attack. It is possible to prevent a decrease in authenticity.

Each configuration shown in each of the above embodiments is a schematic function, and does not necessarily have to be physically shown. That is, the form of distribution / integration of each device is not limited to the one shown in the figure, and all or part of them may be functionally or physically distributed / integrated in any unit according to various loads and usage conditions. Can be configured.

The semiconductor device according to each embodiment of the present invention is suitable for preventing deterioration of confidentiality and authenticity due to a security attack on the back surface.

1 Circuit board 2 Printed circuit board 3 Wiring conductor 11 Semiconductor board 12 Multi-layer wiring conductor 12a Wiring layer 12ac Pad conductor 13 Embedded wiring conductor 13a 13b, 13c, 13d, 13e 13f Wiring conductor 14 Via conductor 15 Electronic circuit 16 Oxidation film coupling surface 17 Wiring board 20, 40, 50 Capacitive sensor circuit 21, 22, 26, 27, 28, 31, 32, 41, 42, 51, 52, 54, 55 Switching element 23, 33, 43, 53, 56 Constant current source 24 , 34, 44, 57 Pulse gate circuit 25, 35, 45, 58 Pulse counter 29 Latch circuit 30 Disconnection detection circuit 59 Reference capacity 60 High resolution capacity sensor circuit 60a, 60b Charge / discharge circuit N31 to N40 node

Claims (9)

A semiconductor device in which the first surface of a circuit board having a first surface on which an electronic circuit is formed and a second surface behind the first surface is mounted toward a printed circuit board.
A wiring board to be bonded to the second surface of the circuit board is provided.
The circuit board comprises a via conductor connecting the first surface and the second surface.
The electronic circuit is a semiconductor device characterized in that it is connected to a wiring conductor provided on a joint surface of the wiring board via the via conductor. The semiconductor device according to claim 1, wherein the circuit board and the wiring board are bonded by an oxide film bond. The semiconductor device according to claim 1, wherein the circuit board is flip-chip mounted on the printed circuit board. The semiconductor device according to claim 1, wherein the wiring conductor is formed of a strip conductor. The semiconductor device according to claim 4, wherein the wiring conductor is formed in a meander shape, a stripe shape, or a mesh shape. The semiconductor device according to any one of claims 1 to 5, wherein the wiring board is a capacitive wiring conductor made of a strip conductor formed on the joint surface. The wiring conductor is
Connect so that the discharge current of the capacitive wiring conductor flows,
The electronic circuit is
The semiconductor device according to claim 6, further comprising a capacitance sensor circuit that detects the approach of an object from a change in the capacitance of the capacitance wiring conductor and detects disconnection from a stationary discharge current. The wiring board is formed in a meander shape on the entire surface of the joint surface, and is formed.
The electronic circuit is
The semiconductor device according to claim 1, further comprising a capacitance sensor circuit that detects a cutting location and an object approaching due to a capacitance change of the wiring conductor. In a semiconductor device including a capacitance sensor circuit that detects a change in wiring capacitance,
The capacitance sensor circuit is
Charge / discharge circuit for capacity measurement and
A semiconductor device characterized by being equipped with a reference capacitance charge / discharge circuit for improving the sensitivity of capacitance measurement.

Images