JP2022010387A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to improve the performance of a semiconductor device. A drift layer DR is formed on a semiconductor substrate SB which is a SiC substrate. The drift layer DR has n-type semiconductor layers NE1 to NE3 and a p-type semiconductor region PT. Here, the impurity concentration of the n-type semiconductor layer NE2 is higher than the impurity concentration of the n-type semiconductor layer NE1 and the impurity concentration of the n-type semiconductor layer NE3. Further, in plan view, the semiconductor layer NE2 located between the p-type impurity regions PT adjacent to each other overlaps with at least part of the gate electrode G formed in the trench TR. [Selection drawing] Fig. 3

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly suitable for a semiconductor device using a silicon carbide (SiC) substrate.

As a semiconductor device having a power transistor, a semiconductor device using a SiC substrate is being studied. When a SiC substrate is used, SiC has a larger bandgap than silicon (Si), so that the dielectric breakdown withstand voltage is large. Further, in the power transistor of the SiC substrate, the trench gate structure used in the power transistor of the Si substrate is applied.

Patent Document 1 discloses a power transistor having a trench gate structure using a SiC substrate, and is on an n-type low-concentration drift layer provided with a p-type impurity region for electric field relaxation and a low-concentration drift layer. The n-type high-concentration drift layer formed in the above is disclosed. Then, it is disclosed that the trench gate is provided in the high concentration drift layer.

Patent Document 2 discloses a planar type power transistor using a SiC substrate, and has a structure in which a low-concentration epitaxial layer, a high-concentration epitaxial layer, and a low-concentration epitaxial layer are laminated on a semiconductor substrate. It has been disclosed.

Patent Document 3 discloses a power transistor having a trench gate structure using a SiC substrate, and has an n-type first low-concentration drift layer provided with a p-type impurity region for electric field relaxation and a first low concentration. The n-type second low-concentration drift layer formed on the concentration drift layer is disclosed. Then, it is disclosed that an n-type high-concentration impurity region is provided between a plurality of p-type impurity regions.

Japanese Unexamined Patent Publication No. 2014-175518 Japanese Unexamined Patent Publication No. 2001-274395 JP-A-2015-26726

In a power transistor having a trench gate structure using a SiC substrate, it is desired to reduce the on-resistance of the power transistor and improve the withstand voltage around the lower part of the trench gate.

Other issues and novel features will become apparent from the description and accompanying drawings herein.

A brief description of typical embodiments disclosed in the present application is as follows.

According to one embodiment, the semiconductor device includes a semiconductor substrate composed of silicon and carbon, a first conductive type first semiconductor layer formed on the upper surface of the semiconductor substrate, and the first semiconductor. The first conductive type third semiconductor layer formed on the layer, the first conductive type second semiconductor layer formed between the first semiconductor layer and the third semiconductor layer, and the first. It is a second conductive type that is formed between the first semiconductor layer and the third semiconductor layer and is a conductive type opposite to the first conductive type, and sandwiches the second semiconductor layer in a plan view. Of the plurality of first impurity regions formed in, the second conductivity type second impurity region formed in the third semiconductor layer, and the first conductive type region formed in the first impurity region. A groove that penetrates the third impurity region, the second impurity region, and the third impurity region and reaches the third semiconductor layer, a gate insulating film formed in the groove, and the gate in the groove. It has a gate electrode embedded via an insulating film. Here, the impurity concentration of the second semiconductor layer is higher than the impurity concentration of the first semiconductor layer and the impurity concentration of the third semiconductor layer, and in a plan view, the groove and the gate electrode are the first. A plurality of the gate electrodes extending in a direction are formed so as to be adjacent to each other in the second direction, and a center line is drawn from the center of the gate electrode in the thickness direction in a cross section perpendicular to the first direction. When the distance connecting the center lines of the two adjacent gate electrodes in the second direction is L6, the plurality of first impurity regions are formed with a period of 1 / integer of L6. ..

According to one embodiment disclosed in the present application, the performance of the semiconductor device can be improved.

It is a top view which shows the layout of the semiconductor chip which is the semiconductor device of Embodiment 1. FIG. It is a main part plan view of the semiconductor device of Embodiment 1. FIG. It is sectional drawing of the semiconductor device of Embodiment 1. FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device of Embodiment 1. FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is a figure which shows the result of the simulation by the inventor of this application. It is a figure which shows the result of the simulation by the inventor of this application. It is a figure which shows the result of the simulation by the inventor of this application. It is a figure which shows the result of the simulation by the inventor of this application. It is a figure which shows the result of the simulation by the inventor of this application. It is a figure which shows the result of the simulation by the inventor of this application. It is a figure which shows the result of the simulation by the inventor of this application. It is sectional drawing of the semiconductor device of the modification of Embodiment 1. FIG. It is a figure which shows the result of the simulation by the inventor of this application. It is a main part plan view of the semiconductor device of Embodiment 2. FIG. It is sectional drawing of the semiconductor device of Embodiment 2. FIG. It is sectional drawing of the semiconductor device of the modification of Embodiment 2. It is sectional drawing of the semiconductor device of Embodiment 3. FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device of Embodiment 3. FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device following FIG. It is sectional drawing of the semiconductor device of the modification of Embodiment 3. FIG. It is a main part plan view of the semiconductor device of Embodiment 4. FIG. It is sectional drawing of the semiconductor device of Embodiment 4. FIG. It is a main part plan view of the semiconductor device of the modification of Embodiment 4. It is sectional drawing of the semiconductor device of the modification of Embodiment 4. It is sectional drawing which shows the semiconductor device of the study example.

In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, one of which is the other. It is related to some or all of the modified examples, details, supplementary explanations, etc. Further, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except for this, the number is not limited to the specific number, and may be more than or less than the specific number. Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered to be essential in principle. Needless to say. Similarly, in the following embodiments, when the shape, positional relationship, etc. of a component or the like is referred to, the shape is substantially the same except when explicitly stated or when it is considered that it is not apparent in principle. It shall include things that are similar to or similar to. This also applies to the above numerical values and ranges.

Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment, the members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. Further, in the following embodiments, the same or similar parts will not be repeated in principle unless it is particularly necessary.

Further, in the cross-sectional view and the plan view, the size of each part does not correspond to the actual device, and a specific part may be displayed relatively large in order to make the drawing easy to understand. Further, even when the cross-sectional view corresponds to the plan view, a specific portion may be displayed in a relatively large size in order to make the drawing easy to understand.

Further, in the drawings used in the embodiment, hatching may be omitted in order to make the drawings easier to see.

(Embodiment 1)
Hereinafter, the structure of the semiconductor device of the present embodiment, the manufacturing method of the semiconductor device, the description of the study example, and the main features of the present embodiment will be described in order.

<Structure of semiconductor device>
FIG. 1 is a plan view of a semiconductor chip C, which is a semiconductor device of the present embodiment. FIG. 1 shows a state in which the insulating film IF5 (see FIG. 3) is transmitted through the insulating film IF5 (see FIG. 3) for easy understanding, and although it is a plan view, the gate potential electrode GE and the source potential electrode SE are hatched. The semiconductor chip C has a plurality of power transistors having a trench gate structure. Such a power transistor may be referred to as a power MOSFET (Metal Oxyde Semiconductor Field Effect Transistor).

As shown in FIG. 1, the surface of the semiconductor chip C is mainly covered with the source potential electrode SE and the gate potential electrode GE. A part of the gate potential electrode GE is formed on the outer periphery of the source potential electrode SE in the pad region PA, which is a region near the central portion of the semiconductor chip C, and one of the source potential electrodes SE is further formed on the outer periphery thereof. The part is formed. In the pad region PA, a part of the insulating film IF5 is removed, and a part of the source potential electrode SE and a part of the gate potential electrode GE are exposed. By connecting external connection terminals such as wire bonding or clips (copper plates) on these exposed source potential electrodes SE and gate potential electrodes GE, respectively, the semiconductor chip C can be connected to other chips or wiring boards. It is electrically connected.

FIG. 2 is a plan view of a main part of the semiconductor chip C, and corresponds to a plan view of a part under the source potential electrode SE in the pad region PA shown in FIG. FIG. 3 is a cross-sectional view taken along the line AA of FIG.

FIG. 2 shows only the gate electrode G, the n-type semiconductor layer NE2, and the p-type impurity region PT formed in the groove TR, which are configurations closely related to the main features of the present embodiment, and others. The configuration of is omitted from the illustration. Further, the gate electrode G formed in the groove TR is shown by a broken line, and FIG. 2 is a plan view, but in order to make the drawing easier to see, the gate electrode G formed in the groove TR is hatched. ing.

As shown in FIG. 2, the groove TR, the gate electrode G, the n-type semiconductor layer NE2, and the p-type impurity region PT each extend in the Y direction. That is, the planar shapes of the groove TR, the gate electrode G, the n-type semiconductor layer NE2, and the p-type impurity region PT are rectangular with long sides in the Y direction, and the lengths in the Y direction are different. Greater than these lengths in the X direction. Further, the groove TR, the gate electrode G, the n-type semiconductor layer NE2, and the p-type impurity region PT are repeatedly arranged in the X direction. Further, in the present embodiment, when the center line is drawn from the center of the gate electrode G in the thickness direction (Z direction) in the cross section perpendicular to the Y direction, the two p-type impurity regions PT adjacent to each other in the X direction are PT. Are arranged so as to be symmetrical with respect to the center line.

As will be described in detail later, as one of the features of the present embodiment, at least a part of the gate electrode G formed in the groove TR is arranged at a position overlapping with the n-type semiconductor layer NE2 in a plan view. ing.

Next, with reference to FIG. 3, a cross-sectional structure of a power transistor having a trench gate structure according to the present embodiment will be described.

The semiconductor substrate SB used in the present embodiment is a substrate composed of silicon and carbon, and specifically, is a silicon carbide (SiC) substrate into which an n-type impurity is introduced. A drift layer DR is formed on the upper surface (first surface) of the semiconductor substrate SB, and a drain potential electrode DE made of a metal film is formed on the back surface (second surface) of the semiconductor substrate SB. The semiconductor substrate SB and the drift layer DR each form a part of the drain region of the power transistor, are electrically connected to the drain potential electrode DE, and the drain potential is measured during the operation of the power transistor via the drain potential electrode DE. Applied.

The drift layer DR has n-type semiconductor layers NE1 to NE3 and a p-type impurity region PT. The n-type semiconductor layer NE1 is formed on the semiconductor substrate SB, the n-type semiconductor layer NE3 is formed on the n-type semiconductor layer NE1, and the n-type semiconductor layer NE2 is the n-type semiconductor layers NE1 and n. It is formed between the type semiconductor layer NE3 and the type semiconductor layer NE3. Each of these n-type semiconductor layers NE1 to NE3 is a semiconductor layer formed by an epitaxial method on a semiconductor substrate SB which is a SiC substrate. Therefore, the n-type semiconductor layers NE1 to NE3 are each composed of SiC. Further, the impurity concentration of the n-type semiconductor layer NE2 is higher than the impurity concentration of the n-type semiconductor layer NE1 and the impurity concentration of the n-type semiconductor layer NE3. The impurity concentration of the n-type semiconductor layer NE1 is about the same as the impurity concentration of the n-type semiconductor layer NE3.

A plurality of p-type impurity region PTs are formed between the n-type semiconductor layer NE3 and the n-type semiconductor layer NE1. An n-type semiconductor layer NE2 is formed between the p-type impurity regions PT adjacent to each other. That is, in a plan view, the p-type impurity regions PT adjacent to each other are formed so as to sandwich the n-type semiconductor layer NE2. As will be described in detail later, the thickness of the p-type impurity region PT may be the same as the thickness of the n-type semiconductor layer NE2, or may be thicker or thinner than the thickness of the n-type semiconductor layer NE2. In the present embodiment, the thickness of the p-type impurity region PT is thinner than the thickness of the n-type semiconductor layer NE2, and the case where the p-type impurity region PT is formed in the n-type semiconductor layer NE2 is exemplified. There is. Therefore, in FIG. 3, the n-type semiconductor layer NE2 is formed between the p-type impurity region PT and the n-type semiconductor layer NE1.

A p-type channel region (impurity region) PC is formed on the surface side of the n-type semiconductor layer NE3, which is the upper layer of the drift layer DR, and an n-type source region (impurity region) is formed on the surface side of the channel region PC. Region) NS and p-type body region (impurity region) PB are formed. The source region NS and the body region PB are each electrically connected to the source potential electrode SE, and the source potential is applied during the operation of the power transistor via the source potential electrode SE. The body region PB is a region provided for the purpose of reducing contact resistance when the source potential electrode SE is connected to the channel region PC. Therefore, the impurity concentration of the body region PB is higher than the impurity concentration of the channel region PC.

Further, a silicide layer may be formed on the surfaces of the source region NS and the body region PB for the purpose of further reducing the contact resistance with the source potential electrode SE. The silicide layer is made of, for example, titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ) or nickel silicide (NiSi). In this embodiment, the illustration of this silicide layer is omitted.

A groove TR is formed on the surface side of the semiconductor substrate SB. The groove TR is formed so as to penetrate the source region NS and the channel region PC and reach the n-type semiconductor layer NE3. That is, the bottom of the groove TR is located in the n-type semiconductor layer NE3. Further, the groove TR is formed so as to be located between the two source regions NS.

A gate electrode G is embedded in the groove TR via a gate insulating film GI. The gate electrode G is electrically connected to the gate potential electrode GE, and the gate potential is applied during the operation of the power transistor. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrode G is, for example, a polycrystalline silicon film into which an n-type impurity is introduced. Further, as the gate insulating film GI, a high dielectric constant film having a higher dielectric constant than the silicon oxide film, such as an aluminum oxide film or a hafnium oxide film, may be used instead of the silicon oxide film.

Here, the relationship between the p-type impurity region PT and the gate electrode G in the groove TR will be described. The vicinity of the bottom of the gate electrode G (the bottom of the groove TR) in the groove TR, particularly the vicinity of the corner of the groove TR, is a region where a strong electric field is generated during the operation of the power transistor, and the gate insulating film GI is easily destroyed. It is an area. The p-type impurity region PT is mainly provided to relax this electric field. By providing the p-type impurity region PT in the drift layer DR below the groove TR, the electric field is relaxed, so that the destruction of the gate insulating film GI can be suppressed and the withstand voltage of the entire drift layer DR can be improved.

Further, in the present embodiment, when the center line is drawn from the center of the gate electrode G in the thickness direction in the cross section perpendicular to the Y direction, the two p-type impurity region PTs adjacent to each other in the X direction are in the center. They are arranged so as to be symmetrical with respect to the line.

Further, as described above, in a plan view, at least a part of the gate electrode G formed in the groove TR is arranged at a position overlapping with the n-type semiconductor layer NE2. In other words, in the cross-sectional view, the n-type semiconductor layer NE2 is formed immediately below at least a part of the gate electrode G formed in the groove TR. In the present embodiment, the n-type semiconductor layer NE2 is formed directly below the entire bottom portion connecting the two corner portions of the gate electrode G formed in the groove TR.

The term "directly below" expressed in the present embodiment means the lower part of one object, and includes a state in which one object and the other object are not in direct physical contact with each other. In other words, "directly below" means a state in which one object and the other object overlap in a plan view. For example, in FIG. 3, the n-type semiconductor layer NE2 is formed below the groove TR and the gate electrode G, and is not physically in contact with the groove TR and the gate electrode G.

A part of the gate insulating film GI is formed on the source region NS, and an interlayer insulating film IL made of, for example, silicon oxide is formed on the upper surface of each of the part of the gate insulating film GI and the gate electrode G. There is. A contact hole CH is formed in the interlayer insulating film IL. The contact hole CH is formed so as to penetrate the interlayer insulating film IL and the gate insulating film GI and reach the source region NS and the body region PB.

A source potential electrode SE is formed on the interlayer insulating film IL, and the source potential electrode SE is embedded in the contact hole CH. That is, the source potential electrode SE is electrically connected to the source region NS and the body region PB. The source potential electrode SE is made of, for example, a conductive film mainly made of aluminum. Further, the source potential electrode SE may be a laminated film of, for example, a barrier metal film made of titanium nitride and a conductive film mainly made of aluminum. Although not shown in FIG. 3, the gate potential electrode GE shown in FIG. 1 is also formed in the same manner as the source potential electrode SE, and the gate potential electrode GE is electrically connected to the gate electrode G. ing.

An insulating film IF5 made of a resin such as polyimide is formed on the source potential electrode SE. Although not shown in FIG. 3, in the pad region PA shown in FIG. 1, an opening is provided in the insulating film IF5 so as to expose a part of the source potential electrode SE and a part of the gate potential electrode GE. Is provided.

Further, in FIG. 3, the area surrounded by the broken line indicates the unit cell UC. In the present embodiment, the unit cell UC is a source region NS, a body region PB, a channel region PC, a drift layer DR, and a semiconductor formed on both sides of one gate electrode G and one gate electrode G, respectively. Includes substrate SB. In the present embodiment, the unit cell UC is a region from the center of the body region PB formed on one side surface side of the gate electrode G to the center of the body region PB formed on the other side surface side of the gate electrode G. Is defined as. A plurality of unit cells UC are repeatedly arranged on the semiconductor chip C.

Further, in FIG. 3, the width of the unit cell UC is shown as a distance L6. The distances L1 to L5 will be used later when the main features of the present embodiment are explained.

In the present embodiment, the distance L6, which is the width of the unit cell UC, is represented as the distance connecting the centers of the two body regions PB described above. For example, in a cross section perpendicular to the Y direction, the gate is formed. When the center line is drawn from the center of the electrode G in the thickness direction, the distance connecting the center lines of the two gate electrodes adjacent to each other in the X direction can be expressed as the distance L6.

<Manufacturing method of semiconductor devices>
Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 4 to 14. 4 to 14 show only the area corresponding to the unit cell UC of FIG. 3 for the sake of brevity.

First, as shown in FIG. 4, a semiconductor substrate SB made of SiC on which an epitaxial layer is formed is prepared. The epitaxial layer is a semiconductor layer made of SiC, and has a single-layer structure of an n-type semiconductor layer NE1 into which an n-type impurity is introduced, or an n-type semiconductor layer NE1 and an n-type semiconductor into which an n-type impurity is introduced. It has a laminated structure with layer NE2. Here, the impurity concentration of the n-type semiconductor layer NE2 is higher than the impurity concentration of the n-type semiconductor layer NE1. The n-type semiconductor layer NE1 has, for example, an impurity concentration of about 1 × 10 ¹⁶ / cm ³ and a thickness of about 8.6 μm. The n-type semiconductor layer NE2 has, for example, an impurity concentration of about 4 × 10 ¹⁶ / cm ³ and a thickness of about 0.4 μm.

The n-type semiconductor layer NE1 is formed by epitaxially growing on the upper surface of the semiconductor substrate SB while introducing n-type impurities. The n-type semiconductor layer NE2 is formed by epitaxial growth while introducing n-type impurities onto the n-type semiconductor layer NE1, or by ion-injecting n-type impurities onto the surface of the n-type semiconductor layer NE1. To.

FIG. 5 shows a step of forming a p-type impurity region PT.

First, an insulating film IF1 made of, for example, silicon oxide is formed on the n-type semiconductor layer NE2 by, for example, a CVD (Chemical Vapor Deposition) method. Next, the insulating film IF1 is patterned by a photolithography method and an etching process. Next, by performing ion implantation using the patterned insulating film IF1 as a mask, a p-type impurity region PT is formed in the n-type semiconductor layer NE2. This ion implantation is performed under the conditions that aluminum (Al) ions are used, for example, the implantation energy is about 150 KeV and the dose amount is about 5 × 10 ¹³ / cm ² .

Further, the thickness of the p-type impurity region PT may be the same as the thickness of the n-type semiconductor layer NE2, or may be thicker or thinner than the thickness of the n-type semiconductor layer NE2. In the present embodiment, the thickness of the p-type impurity region PT is thinner than the thickness of the n-type semiconductor layer NE2, and the case where the p-type impurity region PT is formed in the n-type semiconductor layer NE2 is exemplified. There is.

Then, the insulating film IF1 is removed by, for example, a wet etching treatment using a solution containing hydrofluoric acid.

FIG. 6 shows a process of forming the n-type semiconductor layer NE3.

The n-type semiconductor layer NE3 is formed by epitaxial growth while introducing n-type impurities on the n-type semiconductor layer NE2 and the p-type impurity region PT. The impurity concentration of the n-type semiconductor layer NE3 is lower than the impurity concentration of the n-type semiconductor layer NE2, and is about the same as the impurity concentration of the n-type semiconductor layer NE1. The n-type semiconductor layer NE3 has, for example, an impurity concentration of about 1 × 10 ¹⁶ / cm ³ and a thickness of about 3.0 μm.

FIG. 7 shows a process of forming a p-type channel region PC.

The p-type channel region PC is formed in the n-type semiconductor layer NE3 by ion implantation using, for example, aluminum (Al) ions.

FIG. 8 shows a process of forming an n-type source region NS.

First, an insulating film IF2 made of, for example, silicon oxide is formed on the p-type impurity region PT by, for example, a CVD method. Next, the insulating film IF2 is patterned by a photolithography method and an etching process. Next, by performing ion implantation using nitrogen (N) ions using the patterned insulating film IF2 as a mask, an n-type source region NS is selectively formed in the p-type impurity region PT.

Then, the insulating film IF2 is removed by, for example, a wet etching treatment using a solution containing hydrofluoric acid.

FIG. 9 shows a step of forming a p-shaped body region PB.

First, an insulating film IF3 made of, for example, silicon oxide is formed on the source region NS by, for example, a CVD method. Next, the insulating film IF3 is patterned by a photolithography method and an etching process. Next, by performing ion implantation using aluminum (Al) ions using the patterned insulating film IF3 as a mask, a p-type body region PB adjacent to the source region NS and reaching the channel region PC is formed.

Then, the insulating film IF3 is removed by, for example, a wet etching treatment using a solution containing hydrofluoric acid.

FIG. 10 shows a process of forming the groove TR.

First, an insulating film IF4 made of, for example, silicon oxide is formed on the source region NS and the body region PB by, for example, a CVD method. Next, the insulating film IF4 is patterned by a photolithography method and an etching process. Next, by performing a dry etching process using the patterned insulating film IF4 as a mask, a groove TR that penetrates the source region NS and the channel region PC and reaches the n-type semiconductor layer NE3 is formed. The width of the groove TR is about 0.8 μm, and the depth of the groove TR is about 1.2 μm. This dry etching process is performed using a gas composed of fluorine-containing molecules such as CF ₄ or SF ₆ .

Then, the insulating film IF4 is removed by, for example, a wet etching treatment using a solution containing hydrofluoric acid.

FIG. 11 shows a process of forming the gate insulating film GI and the gate electrode G.

First, a gate insulating film GI made of, for example, silicon oxide is formed in the groove TR, on the source region NS, and on the body region PB, for example, by a CVD method. As the gate insulating film GI, a high dielectric constant film having a higher dielectric constant than the silicon oxide film, such as aluminum oxide or hafnium oxide film, may be used instead of the silicon oxide film.

Next, a conductive film made of, for example, polycrystalline silicon is formed on the gate insulating film GI so as to be embedded in the groove TR by, for example, a CVD method. Next, a resist pattern RP1 covering a part of the conductive film is formed on the conductive film. Next, the conductive film exposed from the resist pattern RP1 is removed by performing a dry etching process using the resist pattern RP1 as a mask. As a result, the gate electrode G made of the remaining conductive film is formed.

After that, the resist pattern RP1 is removed by an ashing process or the like.

FIG. 12 shows a process of forming the interlayer insulating film IL.

An interlayer insulating film IL made of, for example, silicon oxide is formed on the gate insulating film GI, for example, by a CVD method so as to cover the side surface and the upper surface of the gate electrode G formed outside the groove TR. The interlayer insulating film IL is not limited to the silicon oxide film, and may be formed of another insulating film such as a silicon nitride film or a silicon oxynitride film.

FIG. 13 shows a process of forming a contact hole CH.

First, a resist pattern RP2 that covers a part of the interlayer insulating film IL and has a width wider than the width of the gate electrode G outside the groove TR is formed on the interlayer insulating film IL. Next, the interlayer insulating film IL and the gate insulating film GI are removed by performing a dry etching process using the resist pattern RP2 as a mask. As a result, a part of the source region NS and a contact hole CH reaching the body region PB are formed in the interlayer insulating film IL and the gate insulating film GI.

After that, the resist pattern RP2 is removed by an ashing process or the like.

Further, although not shown in the present embodiment, after the contact hole CH forming step, a silicide layer may be formed on a part of the source region NS and the upper surface of each of the body region PB. In that case, the silicide layer can be specifically formed as follows. First, a metal film for forming a silicide layer made of, for example, titanium (Ti), cobalt (Co) or nickel (Ni) is formed on a part of the source region NS and the upper surface of each of the body region PB. Next, by heat-treating the metal film, a part of the source region NS and the material constituting the body region PB are reacted with the metal film, for example, titanium silicide (TiSi ₂ ) and cobalt silicide. A silicide layer made of (CoSi ₂ ) or nickel silicide (NiSi) is formed. Then, the unreacted metal film is removed.

FIG. 14 shows a process of forming the source potential electrode SE, the insulating film IF5, and the drain potential electrode DE.

First, a conductive film mainly made of aluminum is formed on the interlayer insulating film IL so as to be embedded in the contact hole CH, for example, by a sputtering method. Next, by patterning the conductive film by a photolithography method and an etching process, a source potential electrode SE that is electrically connected to the source region NS and the body region PB is formed. Further, before forming the conductive film, for example, a barrier metal film made of titanium nitride may be formed, and the source potential electrode SE may be a laminated film of the barrier metal film and the conductive film. Although not shown here, the gate potential electrode GE shown in FIG. 1 is also formed in the same manner as the source potential electrode SE, and the gate potential electrode GE is electrically connected to the gate electrode G. There is.

Next, an insulating film IF5 made of a resin such as polyimide is formed on the source potential electrode SE by using, for example, a coating method. After that, although not shown here, in the pad region PA shown in FIG. 1, an opening is provided so as to expose a part of the source potential electrode SE and a part of the gate potential electrode GE to the insulating film IF5. To form.

Next, the back surface of the semiconductor substrate SB is subjected to a polishing treatment to thin the semiconductor substrate SB to a desired thickness. Next, a drain potential electrode DE made of a metal film such as a titanium nitride film is formed on the back surface of the semiconductor substrate SB by, for example, a sputtering method or a CVD method.

As a result, the semiconductor device shown in FIG. 3 is manufactured.

<Explanation of study examples>
With reference to FIG. 36, the semiconductor device of the study example examined by the inventor of the present application will be described.

The semiconductor device of the study example is a power transistor having a trench gate structure using a semiconductor substrate SB made of SiC, as in the present embodiment. FIG. 36 is a cross-sectional view corresponding to the unit cell UC of the present embodiment. As shown in FIG. 36, in the study example, the n-type semiconductor layer NE1, the n-type semiconductor layer NE3, and the p-type impurity region PT are formed in the region to be the drift layer DR, as in the present embodiment. However, unlike the present embodiment, the n-type semiconductor layer NE2 is not formed.

The issues of the study example will be described below.

As described above, the p-type impurity region PT is provided to alleviate the electric field generated near the bottom of the gate electrode G (bottom of the groove TR) in the groove TR, particularly near the corner of the groove TR. When the width of the p-type impurity region PT is widened, the electric field relaxation effect becomes stronger, and the withstand voltage of the entire drift layer DR can be improved. However, when the distance between the p-type impurity regions PT adjacent to each other becomes narrow, the current path becomes narrow, and as a result, there is a problem that the on-resistance increases.

In order to suppress the increase in on-resistance, for example, the impurity concentration of the n-type semiconductor layer NE3 may be increased, but this causes the withstand voltage to deteriorate at the corner of the groove TR where the electric field concentration is the strongest. It causes. Similarly, the on-resistance can be lowered by increasing the impurity concentration of the n-type semiconductor layer NE1, but the withstand voltage of the entire drift layer DR is lowered. In particular, when the concentration of the n-type semiconductor layer NE1 which is the thickest layer in the drift layer DR is increased, the influence of the decrease in withstand voltage becomes large. As described above, there is a trade-off relationship between the improvement of the withstand voltage of the power transistor and the reduction of the on-resistance, and there is a problem that it is difficult to improve the performance of both of them at the same time.

<Main features of the semiconductor device of this embodiment>
Hereinafter, the main features and effects of the semiconductor device of the present embodiment will be described with reference to FIGS. 15 to 21. 15 to 21 are diagrams showing the results of a simulation carried out by the inventor of the present application. FIG. 15 shows not only the results of the present embodiment but also the results of the above-mentioned study example and the results of the second embodiment described later as comparison targets.

The distance L1 shown in FIG. 15 corresponds to the distance L1 shown in FIG. 3 and is the distance between the p-type impurity regions PT adjacent to each other. That is, the distance L1 is the distance between each p-type impurity region PT in the X direction in a plan view.

The vertical axis of FIG. 15 shows the on-resistance of the power transistor as a relative value, and shows that the on-resistance decreases and the on-resistance improves as the distance L1 increases. The horizontal axis of FIG. 15 indicates the withstand voltage of the power transistor as a relative value, and the smaller the distance L1, the higher the withstand voltage and the better the withstand voltage.

As shown in FIG. 15, it can be seen that the semiconductor device of the present embodiment is superior to the semiconductor device of the study example in both the on-resistance and the withstand voltage of the power transistor.

Here, widening the distance L1 narrows the width of the p-type impurity region PT itself, or widens the width of the n-type semiconductor layer NE2 formed between the p-type impurity region PTs adjacent to each other. Means to do. On the contrary, narrowing the distance L1 means widening the width of the p-type impurity region PT itself or narrowing the width of the n-type semiconductor layer NE2.

In the present embodiment, unlike the study example, the n-type semiconductor layer NE2, which is a high-concentration impurity region, is formed between the p-type impurity regions PT adjacent to each other. That is, since the n-type semiconductor layer NE2 having a low resistance is formed in the region serving as the current path, the on-resistance of the power transistor can be reduced. Further, the bottom portion of the groove TR is located in the n-type semiconductor layer NE3 having a lower concentration than that of the n-type semiconductor layer NE2. Therefore, the withstand voltage near the bottom of the groove TR can be improved.

Further, an n-type semiconductor layer NE2 is formed immediately below at least a part of the gate electrode G formed in the groove TR. Therefore, a low-resistance n-type semiconductor layer NE2 is formed in the shortest path of the current path via the drain potential electrode DE, the channel region PC on the side surface of the groove TR (side surface of the gate electrode G), and the source potential electrode SE. It will be done. In other words, the low resistance n-type semiconductor layer NE2 is formed in the region where the current density is high. Therefore, the on-resistance of the power transistor can be efficiently reduced.

As shown in FIG. 15, the width of the n-type semiconductor layer NE2 varies depending on the value of the distance L1, but the n-type semiconductor layer NE2 is directly below at least a part of the gate electrode G formed in the groove TR. It is important that is formed. In other words, in a plan view, at least a part of the gate electrode G formed in the groove TR overlaps with the n-type semiconductor layer NE2. In particular, it is preferable that the n-type semiconductor layer NE2 is formed immediately below at least one of the two corner portions of the gate electrode G formed in the groove TR.

As described above, in the present embodiment, the on-resistance of the power transistor can be reduced and the withstand voltage can be improved. Therefore, the performance of the semiconductor device can be improved, and the reliability of the semiconductor device can be improved.

16 to 21 are the results of repeated studies by the inventor of the present application regarding the relationship between the configurations of the semiconductor device of the present embodiment.

FIG. 16 shows the relationship between the ratio of the impurity concentration of the n-type semiconductor layer NE2 to the impurity concentration of the n-type semiconductor layer NE1 and the on-resistance. Here, the distance L1 is adjusted so that the withstand voltage is constant at 1500 V at each measurement point. The leftmost point (the point where the value on the horizontal axis is 1) corresponds to the study example.

As shown in FIG. 16, when the concentration of the n-type semiconductor layer NE2 is increased, the on-resistance decreases, but when the concentration of the n-type semiconductor layer NE2 is increased too much, the on-resistance increases. That is, if the concentration of the n-type semiconductor layer NE2 is increased too much, the withstand voltage decreases. Therefore, in order to maintain the withstand voltage at 1500 V as described above, it is necessary to narrow the distance L1. Therefore, the current path, which is a region between the p-type impurity regions PT adjacent to each other, becomes too narrow, and as a result, the on-resistance increases.

In the present embodiment, a range in which the value on the horizontal axis is 2 to 10 can be used as an appropriate range. Further, the value on the horizontal axis is more preferably in the range of 3 to 7. For example, when the impurity concentration of the n-type semiconductor layer NE1 is about 1 × 10 ¹⁶ / cm ³ , the impurity concentration of the n-type semiconductor layer NE2 is 2 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁶ / cm ³ . The range is preferably 3 × 10 ¹⁶ / cm ³ to 7 × 10 ¹⁶ / cm ³ .

FIG. 17 shows the relationship between the ratio of the impurity concentration of the n-type semiconductor layer NE2 to the impurity concentration of the n-type semiconductor layer NE3 and the withstand voltage. Here, the distance L1 is adjusted so that the on-resistance is constant at each measurement point, and the impurity concentration of the n-type semiconductor layer NE1 and the impurity concentration of the n-type semiconductor layer NE3 are about the same. It is measured under the conditions.

As shown in FIG. 17, it can be seen that a sufficient withstand voltage of around 1500 V can be secured in the range where the value on the horizontal axis is 2.0 to 5.0.

FIG. 18 shows the relationship between the ratio of the impurity concentration of the n-type semiconductor layer NE3 to the impurity concentration of the n-type semiconductor layer NE1 and the withstand voltage. Here, the distance L1 is adjusted so that the on-resistance is constant at each measurement point, and the ratio of the impurity concentration of the n-type semiconductor layer NE2 to the impurity concentration of the n-type semiconductor layer NE1 is 4. It is measured under the conditions.

As shown in FIG. 18, it can be seen that a sufficient withstand voltage of around 1500 V can be secured in the range where the value on the horizontal axis is 0.8 to 2.0.

FIG. 19 shows the relationship between the distance L2 from the bottom of the groove TR to the upper surface of the n-type semiconductor layer NE2 and the on-resistance. Further, the distance L2 shown in FIG. 19 corresponds to the distance L2 shown in FIG. Here, the distance L1 is adjusted so that the withstand voltage is constant at 1500 V at each measurement point.

As shown in FIG. 19, when the distance L2 is 4 μm or more, the on-resistance is almost constant, but when the distance L2 is 4 μm or less, the on-resistance decreases. When the distance L2 is 0.5 μm or less, the groove TR and the p-type impurity region PT are too close to each other, and the current path becomes too narrow, resulting in an increase in on-resistance.

In the present embodiment, a range in which the distance L2 is 0.3 μm to 4.0 μm can be used as an appropriate range. In particular, the distance L2 is preferably in the range of 0.3 μm to 2.0 μm, and most preferably in the range of 0.5 μm to 1.0 μm.

FIG. 20 shows the relationship between the ratio of the thickness of the n-type semiconductor layer NE2 (distance L4) to the thickness of the drift layer DR (distance L3) and the on-resistance. Here, the thickness of the drift layer DR (distance L3) is the sum of the thicknesses of the n-type semiconductor layers NE1 to NE3. Further, the distance L3 and the distance L4 shown in FIG. 20 correspond to the distance L3 and the distance L4 shown in FIG. Here, the distance L1 is adjusted so that the withstand voltage is constant at 1500 V at each measurement point. The leftmost point (the point where the value on the horizontal axis is 0.00) corresponds to the study example.

As shown in FIG. 20, the value of the distance L4 / distance L3 is in the range of 0.02 to 0.13, and the on-resistance is reduced. Therefore, for example, when the thickness of the drift layer DR (distance L3) is 12 μm, the thickness of the n-type semiconductor layer NE2 (distance L4) is preferably 0.24 μm to 1.56 μm.

FIG. 21 shows the relationship between the ratio of the thickness of the n-type semiconductor layer NE2 (distance L4) to the thickness of the p-type impurity region PT (distance L5) and the on-resistance. Further, the distance L4 and the distance L5 shown in FIG. 21 correspond to the distance L4 and the distance L5 shown in FIG. Here, the distance L1 is adjusted so that the withstand voltage is constant at 1500 V at each measurement point. The leftmost point (the point where the value on the horizontal axis is 0.0) corresponds to the study example.

As shown in FIG. 21, the value of the distance L4 / distance L5 is in the range of 0.5 to 2.2, and the on-resistance is reduced. Then, a high effect is obtained when the value of the distance L4 / distance L5 is in the range of 1.0 to 2.0, and a higher effect is obtained in the range of 1.4 to 1.9. For example, when the thickness of the p-type impurity region PT (distance L5) is 0.4 μm, the thickness of the n-type semiconductor layer NE2 (distance L4) is preferably 0.2 μm to 0.88 μm. It is more preferably 0.4 μm to 0.8 μm, and even more preferably 0.56 μm to 0.76 μm.

As described above, in the present embodiment, not only the n-type semiconductor layer NE2 is formed directly under the groove TR, but also the relationship between the above configurations is set within an appropriate range to further improve the performance of the semiconductor device. It can be improved, and the reliability of the semiconductor device can be further improved.

(Modified Example of Embodiment 1)
FIG. 22 shows a semiconductor device of a modification of the first embodiment. In the following description, the differences from the first embodiment will be mainly described.

In the first embodiment, when the center line is drawn from the center of the gate electrode G in the thickness direction in the cross section perpendicular to the Y direction, the two p-type impurity region PTs adjacent to each other are relative to the center line. It was arranged so as to be symmetrical.

On the other hand, in this modification, the two p-type impurity regions PT adjacent to each other are arranged so as to be asymmetric with respect to the center line.

In FIG. 22, the distance between the center line and the midpoint between the two p-type impurity regions PT adjacent to each other is shown as the distance L7. In other words, the center line and the center of the n-type semiconductor layer NE2 are separated from each other within a distance L7.

Further, the width of the unit cell UC in this modification is the same as the width of the unit cell UC in the first embodiment. Therefore, in the unit cell UC, the flat area and volume of the p-type impurity region PT and the flat area and volume of the n-type semiconductor layer NE2 are the same in the first embodiment and the present modification.

FIG. 23 is a diagram showing the results of the simulation carried out by the inventor of the present application, and for comparison, not only the present modification but also the results of the modification of the second embodiment described later are shown.

FIG. 23 shows the relationship between the ratio of the distance L7 to the width of the unit cell UC (distance L6) and the on-resistance by a solid line. Further, the point where the value on the horizontal axis is 0.0 corresponds to the first embodiment, and the center line coincides with the midpoint between the two p-type impurity regions PT adjacent to each other. It is a point.

As shown in FIG. 23, the on-resistance increases as the absolute value of the distance L7 / distance L6 increases. According to the study of the inventor of the present application, if the absolute value of the distance L7 / distance L6 is within 1/8 (0.125), the on-resistance value required in the market can be maintained. That is, ideally, as in the first embodiment described above, it is most preferable that the two p-type impurity regions PTs adjacent to each other are arranged so as to be symmetrical with respect to the center line. As in this modification, the performance of the semiconductor device can be maintained even if the absolute value of the distance L7 / distance L6 is within 1/8 (0.125).

In FIG. 23, the distance L1 is adjusted so that the withstand voltage is constant at 1500 V at each measurement point. The broken line in FIG. 23 is the ratio of the distance L7 to the width of the unit cell UC (distance L6) and the ratio of the distance (distance L1) between the p-type impurity region PT to the width of the unit cell UC (distance L6). Shows the relationship. As shown in FIG. 23, when the absolute value of the distance L7 / the distance L6 is increased, the value of the distance L1 / the distance L6 is slightly decreased. That is, the width of the p-type impurity region PT itself is slightly increased. As a result, the withstand voltage can be kept constant even when the center line and the midpoint between the two p-type impurity regions PT adjacent to each other are deviated from each other.

(Embodiment 2)
Hereinafter, the semiconductor device of the second embodiment will be described with reference to FIGS. 24 and 25. FIG. 24 is a plan view of a main part showing a portion similar to that of FIG. 2 of the first embodiment, and FIG. 25 is a cross-sectional view taken along the line AA of FIG. 24. In the following description, the differences from the first embodiment will be mainly described.

In the first embodiment, the period of arrangement of the p-type impurity region PT was the same as the width of the unit cell UC (distance L6).

On the other hand, in the second embodiment, the period of arrangement of the p-type impurity region PT is one integral fraction of the width (distance L6) of the unit cell UC. In FIGS. 24 and 25, as an example of the cycle, the case where the cycle is one half of the distance L6 is illustrated. Therefore, two p-type impurity region PTs are arranged in the unit cell UC.

FIG. 24 illustrates a semiconductor device in which the p-type impurity region PT is arranged at a position overlapping the gate electrode G formed in the groove TR in a plan view. In other words, as shown in FIG. 25, a p-type impurity region PT is formed immediately below a part of the gate electrode G formed in the groove TR. Further, the plurality of p-type impurity regions PTs are arranged so as to be separated from each other. Therefore, in the second embodiment, the withstand voltage of the power transistor can be further improved as compared with the first embodiment.

Further, also in the second embodiment, as in the first embodiment, the n-type semiconductor layer NE2 may be formed directly under at least a part of the gate electrode G formed in the groove TR. In particular, the n-type semiconductor layer NE2 may be formed immediately below at least one of the two corner portions of the gate electrode G formed in the groove TR. However, in the second embodiment, these features are not essential, and for example, the p-type impurity region PT may be formed directly under the entire gate electrode G formed in the groove TR.

Further, as described above, simply forming the p-type impurity region PT directly under the gate electrode G formed in the groove TR improves the withstand voltage of the power transistor, but increases the on-resistance. Therefore, in the second embodiment, the width of each p-type impurity region PT itself is reduced and the area and volume of the n-type semiconductor layer NE2 occupied in the unit cell UC are increased as compared with the first embodiment.

Further, as in the first embodiment, when the center line is drawn in the thickness direction from the center of the gate electrode G in the cross section perpendicular to the Y direction, these p-type impurity region PTs are relative to the center line. Most preferably, they are arranged so as to be symmetrical.

FIG. 15 is a graph showing the relationship between the on-resistance of the power transistor and the withstand voltage when the distance L1 between the p-type impurity regions PT adjacent to each other is changed. As shown in FIG. 15, the semiconductor device of the second embodiment has not only the semiconductor device of the study example but also the semiconductor device of the first embodiment in terms of both on-resistance and withstand voltage of the power transistor. It turns out to be excellent.

The manufacturing method of the second embodiment is the same as that of the first embodiment except that the pattern of the insulating film IF1 which is the mask for forming the p-type impurity region PT described in FIG. 5 is different.

Further, in the second embodiment, the case where the cycle of the arrangement of the p-type impurity region PT is half of the width (distance L6) of the unit cell UC is exemplified, but the cycle of the arrangement of the p-type impurity region PT is illustrated. May be another value, such as one-third of the distance L6.

(Modified Example of Embodiment 2)
FIG. 26 shows a semiconductor device of a modification of the second embodiment. In the following description, the differences from the second embodiment will be mainly described.

In this modification, as in the modification of the first embodiment, when the center line is drawn from the center of the gate electrode G in the thickness direction in the cross section perpendicular to the Y direction, each p-type impurity region PT is described above. It is arranged so as to be asymmetric with respect to the center line. Further, in this modification, the distance between the center line and the center of the p-type impurity region PT located directly below the groove TR is shown as the distance L7. In other words, the center line and the center of the p-type impurity region PT located directly below the groove TR are separated from each other within a distance L7.

In FIG. 23, the relationship between the ratio of the distance L7 to the width (distance L6) of the unit cell UC and the on-resistance in this modification is shown by a solid line. Further, the point where the value on the horizontal axis is 0.0 corresponds to the second embodiment, and the center line coincides with the center of the p-type impurity region PT located directly below the groove TR. It is a point.

As shown by the solid line in FIG. 23, the on-resistance increases as the absolute value of the distance L7 / distance L6 increases. However, as compared with the first embodiment, in the second embodiment, the on-resistance is increased. The increase is suppressed.

Further, in the second embodiment and the present modification, the case where the period of arrangement of the p-type impurity region PT is one half of the width (distance L6) of the unit cell UC is exemplified. Therefore, the broken line in FIG. 23 indicates the ratio of the distance L7 to the width of the unit cell UC (distance L6) and the distance (distance L1) between the p-type impurity region PT with respect to the width of the unit cell UC (distance L6). It shows the relationship with the ratio of double values. When increasing the absolute value of the distance L7 / distance L6, it is necessary to make the width of the p-type impurity region PT itself smaller than that of the first embodiment. As a result, the withstand voltage can be kept constant even when the center line is deviated from the center of the p-type impurity region PT located directly below the groove TR.

(Embodiment 3)
Hereinafter, the semiconductor device of the third embodiment will be described with reference to FIGS. 27 to 30. In the following description, the differences from the first embodiment will be mainly described. 27 to 30 show only the unit cell UC.

In the first embodiment, the n-type semiconductor layer NE2 is formed on the entire upper surface of the n-type semiconductor layer NE1 by the epitaxial growth method, and the p-type impurity region PT is selectively formed in the n-type semiconductor layer NE2 by the ion implantation method. Was. Therefore, the n-type semiconductor layer NE2 was in contact with the p-type impurity region PT.

In the third embodiment, as shown in FIG. 27, the n-type semiconductor layer NE2a does not necessarily have to be in contact with the p-type impurity region PT, and may be arranged separately from the p-type impurity region PT. .. When both are separated, a part of the n-type semiconductor layer NE1 is present between the p-type impurity region PT and the n-type semiconductor layer NE2a. That is, the n-type semiconductor layer NE2a is selectively formed in a part of the region between the p-type impurity regions PT adjacent to each other.

Also in the third embodiment, as in the first embodiment, an n-type semiconductor layer NE2a is provided as a high-concentration n-type impurity region immediately below at least a part of the gate electrode G formed in the groove TR. It is formed. In particular, an n-type semiconductor layer NE2a is formed immediately below at least one of the two corners of the groove TR. Therefore, the on-resistance of the power transistor can be reduced. However, in a region away from directly below the gate electrode G, there is an n-type semiconductor layer NE1 having a lower impurity concentration than the n-type semiconductor layer NE2a. That is, the n-type semiconductor layer NE2a is selectively formed only in the region where the current density is high and which is the main path of the current path, and the n-type semiconductor layer NE1 exists in the region where the current density is low. Therefore, it is possible to improve the withstand voltage while effectively reducing the on-resistance.

28 to 30 show a method of manufacturing the semiconductor device according to the third embodiment.

First, as shown in FIG. 28, an insulating film IF6 made of, for example, silicon oxide is formed on the n-type semiconductor layer NE1 by, for example, a CVD method. Next, the insulating film IF6 is patterned by a photolithography method and an etching process. Next, by performing ion implantation using the patterned insulating film IF6 as a mask, the n-type semiconductor layer NE2a is formed as a high-concentration n-type impurity region in the n-type semiconductor layer NE1. This ion implantation may be performed not only once but also in a plurality of times. Further, in the case of a plurality of ion implantations, each implantation energy may be changed to adjust the peak position of each impurity concentration. Then, the insulating film IF6 is removed by a wet etching treatment using a solution containing hydrofluoric acid or the like.

Next, as shown in FIG. 29, an insulating film IF7 made of, for example, silicon oxide is formed on the n-type semiconductor layer NE1 and the n-type semiconductor layer NE2a by, for example, a CVD method. Next, the insulating film IF7 is patterned by a photolithography method and an etching process. Next, by performing ion implantation using the patterned insulating film IF7 as a mask, a p-type impurity region PT is formed in the n-type semiconductor layer NE1. Then, the insulating film IF7 is removed by a wet etching treatment using a solution containing hydrofluoric acid or the like.

Although the third embodiment shows an example in which the n-type semiconductor layer NE2a is formed first and the p-type impurity region PT is formed later, the order thereof may be reversed.

Next, as shown in FIG. 30, the n-type semiconductor layer NE3 is formed on the n-type semiconductor layer NE1, the n-type semiconductor layer NE2a, and the p-type impurity region PT by the epitaxial growth method. As a result, a drift layer DR having an n-type semiconductor layer NE1, an n-type semiconductor layer NE2a, an n-type semiconductor layer NE3, and a p-type impurity region PT is formed.

After that, the semiconductor device of FIG. 27 is manufactured by going through the same manufacturing process as in the first embodiment.

As described above, in the third embodiment, the n-type semiconductor layer NE2a and the p-type impurity region PT are formed by ion injection, but the impurity concentration of the n-type semiconductor layer NE2a and the p-type impurities are formed. The impurity concentration of the region PT is the same as the impurity concentration of the n-type semiconductor layer NE2 of the first embodiment and the impurity concentration of the p-type impurity region PT, respectively.

Further, in the third embodiment, by using ion implantation instead of the epitaxial growth method, the effect that the thickness (distance L4) of the n-type semiconductor layer NE2a can be easily adjusted, and the impurities in the n-type semiconductor layer NE2a are easily adjusted. It has the effect of facilitating adjustment of the profile. That is, the n-type semiconductor layer NE2a is a layer having a higher impurity concentration than the n-type semiconductor layers NE1 and the n-type semiconductor layer NE3. For example, when the epitaxial growth method is used, the n-type semiconductor layers NE2a and n At the interface with the type semiconductor layer NE3, the gradient of the impurity concentration becomes steep. Therefore, the electric field in the vicinity of this interface changes abruptly, which may cause a decrease in withstand voltage. The interface between the n-type semiconductor layer NE2a and the n-type semiconductor layer NE1 has the same problem. In the third embodiment, the above-mentioned ion implantation can be used to adjust so that the gradient of the impurity concentration near these interfaces becomes gentle. Therefore, the reliability of the semiconductor device can be further improved.

Further, the technique described in the third embodiment may be applied to the modified example of the first embodiment, the second embodiment, and the modified example of the second embodiment described above.

(Modified Example of Embodiment 3)
FIG. 31 shows a semiconductor device of a modification of the third embodiment. In the following description, the differences from the third embodiment will be mainly described.

Also in this modification, the n-type semiconductor layer NE2b is formed by ion implantation as in the third embodiment.

In the third embodiment, the n-type semiconductor layer NE2a formed between the p-type impurity regions PT adjacent to each other is separated into two places. Therefore, in this modification, as shown in FIG. 31, two n-type semiconductor layers NE2b are formed as two separated portions. Therefore, a low-concentration n-type semiconductor layer NE1 exists in the region between the two n-type semiconductor layers NE2b.

Further, the two n-type semiconductor layers NE2b are formed immediately below the two corners of the gate electrode G formed in the groove TR, respectively. That is, the two n-type semiconductor layers NE2b are arranged in the region where the current density is the highest. As a result, the withstand voltage can be further improved, although the on-resistance is slightly higher than that of the third embodiment.

Further, in this modification, two n-type semiconductor layers NE2b are exemplified, but three or more n-type semiconductor layers NE2b may be arranged. That is, a plurality of n-type semiconductor layers NE2b may be formed in a region between the p-type semiconductor layers PT adjacent to each other as a structure in which the n-type semiconductor layer NE2a is separated into a plurality of locations.

The method for manufacturing the n-type semiconductor layer NE2b is the same as that of the third embodiment except that the pattern of the insulating film IF6 described with reference to FIG. 28 is different.

(Embodiment 4)
Hereinafter, the semiconductor device of the fourth embodiment will be described with reference to FIGS. 32 and 33. FIG. 32 is a plan view of a main part showing a portion similar to that of FIG. 2 of the first embodiment, and FIG. 33 is a cross-sectional view taken along the line BB of FIG. 32. The cross-sectional view taken along the line AA of FIG. 32 is the same as that of FIG. In the following description, the differences from the first embodiment will be mainly described.

In the first embodiment, in the plan view, the p-type impurity region PT is continuously formed so as to extend in the Y direction, similarly to the groove TR and the gate electrode G. That is, in a plan view, the p-type impurity region PT was formed in a striped shape.

In the fourth embodiment, as shown in FIG. 32, the p-type impurity region PT is divided in the Y direction in a plan view, and a plurality of p-type impurity region PTs are formed so as to be separated from each other. There is. That is, in a plan view, the plurality of p-type impurity regions PTs are separated in the Y direction and the X direction, respectively, and are formed as a plurality of islands.

Further, as shown in FIG. 33, in the BB cross section, the p-type impurity region PT is not formed in the n-type semiconductor layer NE2. In other words, the n-type semiconductor layer NE2 is formed between the p-type impurity regions PTs adjacent to each other in the Y direction.

As described above, the p-type impurity region PT may be formed discontinuously in the Y direction, but has a structure in which the withstand voltage is likely to be slightly lowered as compared with the first embodiment.

However, in embodiments 1 and 2 described above, as described with reference to FIG. 15, the on-resistance and withstand voltage of the power transistor can be adjusted by the distance L1 between the p-type impurity regions PT in the X direction. can. Therefore, for example, the p-type impurity region PT is discontinuously formed in the Y direction in a state where the distance L1 between each p-type impurity region PT in the X direction is narrowed to improve the withstand voltage. It is also possible to adjust to a desired withstand voltage. As described above, by using the technique disclosed in the fourth embodiment, the degree of freedom in design for pressure resistance adjustment can be increased.

The manufacturing method of the fourth embodiment is the same as that of the first embodiment except that the pattern of the insulating film IF1 which is the mask for forming the p-type impurity region PT described in FIG. 5 is different.

(Modified Example of Embodiment 4)
Hereinafter, the semiconductor device of the fourth embodiment will be described with reference to FIGS. 34 and 35. FIG. 34 is a plan view of a main part showing a portion similar to that of FIG. 32 of the fourth embodiment, and FIG. 35 is a cross-sectional view taken along the line BB of FIG. 34. The cross-sectional view taken along the line AA of FIG. 34 is the same as that of FIG. In the following description, the differences from the fourth embodiment will be mainly described.

As shown in FIG. 34, in this modification as well, the p-type impurity region PT is formed discontinuously in the Y direction, as in the fourth embodiment.

However, as shown in FIG. 33, in the BB cross section, the p-type impurity region PT is also formed immediately below a part of the gate electrode G formed in the groove TR. Therefore, in this modification, the structure of the AA cross section of FIG. 3 and the structure of the BB cross section of FIG. 35 are alternately formed in the Y direction. Therefore, as shown in FIG. 34, the plurality of p-type impurity regions PTs are arranged in a staggered manner in a plan view. In other words, the plurality of p-type impurity regions PTs located immediately below a part of the groove TR are formed so as to be separated from each other in regions not adjacent to other p-type impurity regions PTs in the X direction.

As described above, by adopting a structure in which the p-type impurity region PT is arranged directly under a part of the gate electrode G formed in the groove TR, the withstand voltage is improved as compared with the fourth embodiment. The structure can be made easy to make.

Although the invention made by the inventors of the present application has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. ..

For example, in the above-described embodiments 1 to 4, the trench gate type power transistor has been described as an n-type MOSFET, but the techniques of the above-described embodiments 1 to 4 can also be applied to a p-type MOSFET. Specifically, the p-type MOSFET can be manufactured by reversing the conductive type of each configuration described in the above-described first to fourth embodiments.

Further, in the above-described first to fourth embodiments, the trench gate type power transistor has been described as a MOSFET, but the trench gate type power transistor can also be applied to an IGBT (Insulated Gate Bipolar Transistor).

In addition, a part of the contents described in the above embodiment is described below.

[Appendix 1]
A semiconductor substrate composed of silicon and carbon,
A first conductive type first semiconductor layer formed on the upper surface of the semiconductor substrate,
The first conductive type third semiconductor layer formed on the first semiconductor layer and
The first conductive type second semiconductor layer formed between the first semiconductor layer and the third semiconductor layer, and
The second semiconductor layer is a second conductive type formed between the first semiconductor layer and the third semiconductor layer and is a conductive type opposite to the first conductive type, and the second semiconductor layer is viewed in a plan view. A plurality of first impurity regions formed so as to be sandwiched, and
The second impurity region of the second conductive type formed in the third semiconductor layer and
The first conductive type third impurity region formed in the first impurity region and
A groove that penetrates the second impurity region and the third impurity region and reaches the third semiconductor layer.
The gate insulating film formed in the groove and
A gate electrode embedded in the groove via the gate insulating film,
Have,
The impurity concentration of the second semiconductor layer is higher than the impurity concentration of the first semiconductor layer and the impurity concentration of the third semiconductor layer.
In plan view, the groove and the gate electrode extend in the first direction.
A plurality of the gate electrodes are formed so as to be adjacent to each other in the second direction.
In the cross section perpendicular to the first direction, a center line is drawn from the center of the gate electrode in the thickness direction, and the distance connecting the center lines of each of the two adjacent gate electrodes in the second direction is defined as L6. At that time, the plurality of first impurity regions are formed in a period of 1 / integer of L6, which is a semiconductor device.

[Appendix 2]
In the semiconductor device described in Appendix 1,
A semiconductor device whose period is one half of L6.

[Appendix 3]
In the semiconductor device described in Appendix 1,
A semiconductor device in which the second semiconductor layer located between the first impurity regions adjacent to each other overlaps at least a part of the gate electrode embedded in the groove in a plan view.

[Appendix 4]
In the semiconductor device described in Appendix 1,
A semiconductor device in which one of the plurality of first impurity regions is formed immediately below the entire gate electrode embedded in the groove.

C Semiconductor chip CH Contact hole DE Drain potential electrode DR Drift layer G Gate electrode GE Gate potential electrode GI Gate insulating film IF1 to IF7 Insulating film IL Interlayer insulating film L1 to L7 Distance NE1, NE2, NE2a, NE2b, NE3 n-type semiconductor layer NS source region (impurity region)
PB body area (impurity area)
PC channel area (impurity area)
PT p-type impurity region RP1, RP2 resist pattern SB semiconductor substrate SE source potential electrode TR groove UC unit cell

Claims (4)

A semiconductor substrate composed of silicon and carbon,
A first conductive type first semiconductor layer formed on the upper surface of the semiconductor substrate,
The first conductive type third semiconductor layer formed on the first semiconductor layer and
The first conductive type second semiconductor layer formed between the first semiconductor layer and the third semiconductor layer, and
The second semiconductor layer is a second conductive type formed between the first semiconductor layer and the third semiconductor layer and is a conductive type opposite to the first conductive type, and the second semiconductor layer is viewed in a plan view. A plurality of first impurity regions formed so as to be sandwiched, and
The second impurity region of the second conductive type formed in the third semiconductor layer and
The first conductive type third impurity region formed in the second impurity region and
A groove that penetrates the second impurity region and the third impurity region and reaches the third semiconductor layer.
The gate insulating film formed in the groove and
A gate electrode embedded in the groove via the gate insulating film,
Have,
The impurity concentration of the second semiconductor layer is higher than the impurity concentration of the first semiconductor layer and the impurity concentration of the third semiconductor layer.
In plan view, the groove and the gate electrode extend in the first direction in plan view.
A plurality of the gate electrodes are formed so as to be adjacent to each other in a second direction orthogonal to the first direction in a plan view.
In the cross section perpendicular to the first direction, a center line is drawn in the thickness direction from the center of the gate electrode, and the distance connecting the center lines of each of the two adjacent gate electrodes in the second direction is defined as L6. At times, the plurality of first impurity regions are formed in a period of 1 / integer of L6, that is, a semiconductor device. In the semiconductor device according to claim 1,
A semiconductor device whose period is one half of L6. In the semiconductor device according to claim 1,
A semiconductor device in which the second semiconductor layer located between the first impurity regions adjacent to each other overlaps at least a part of the gate electrode embedded in the groove in a plan view. In the semiconductor device according to claim 1,
A semiconductor device in which one of the plurality of first impurity regions is formed immediately below the entire gate electrode embedded in the groove.

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