JP2022009279A - Semiconductor device and continuous reading method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to perform continuous reading while reducing a scale of a page buffer/sensing circuit.

SOLUTION: A continuous reading method of a NAND flash memory includes a step in which, after outputting data of a cache C0 held in a latch L1 of a page buffer/sensing circuit, data of the cache C0 of a next page is read from a memory cell array, and the read data of the cache C0 is held in the latch L1; after outputting data of a cache C1 held in the latch L1, data of the same next page of the cache C1 is read from the memory cell array, and the read data of the cache C1 is held in the latch L1.

SELECTED DRAWING: Figure 7

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a semiconductor device, and more particularly to continuous reading of a NAND flash memory or the like.

The NAND flash memory is equipped with a continuous read function (burst read function) that continuously reads a plurality of pages in response to an external command. The page buffer / sense circuit contains, for example, two latches, and when a continuous read operation is performed, the output of the data held in the other latch while holding the data read from the array in one latch. It is possible (for example, Patent Documents 1, 2, 3, etc.).

Japanese Patent No. 5323170 Japanese Patent No. 5667143 U.S. Patent Application US2014 / 01049447A1

FIG. 1 shows a schematic configuration of a NAND flash memory equipped with an on-chip ECC function. The flash memory includes a memory cell array 10 including a NAND string, a page buffer / sense circuit 20, data transfer circuits 30 and 32, an error detection and correction circuit (hereinafter referred to as an ECC circuit) 40, and an input / output circuit 50. The page buffer / sense circuit 20 includes two latches L1 and L2 (one latch is, for example, 4 KB) that holds read data and input data to be programmed, and the latches L1 and L2 are cache C0 and cache C1 (one latch is, for example, 4 KB), respectively. One cache contains, for example, 2KB). The caches C0 and C1 can operate independently of each other. In addition, the ECC circuit 40 can be enabled or disabled by a user option.

FIG. 2 shows a timing chart when performing conventional continuous reading. Continuous reading is to read data continuously from a plurality of pages, and this operation can be executed by a command. First, the array reading of page P0 is performed. The read time tRD1 at this time is about 24 μs. The read data of the page P0 is held in the caches C0 and C1 of the latch L1 (P0C0 and P0C1), and then the data of the caches C0 and C1 of the latch L1 are transferred to the caches C0 and C1 of the latch L2. While one of the caches C0 and C1 is outputting data, the other is ECC-processed, and while the other is data-output, one is ECC-processed. Further, after the data is transferred from the latch L1 to the latch L2, the array read on the next page P1 is performed, and this is held by the latch L1.

In continuous reading, the row address is automatically incremented, and continuous reading of a plurality of pages is started from page P1. The array read time tR during continuous read is about 18 μS. The array read is performed in synchronization with the internal clock signal, and the data output by the input / output circuit 50 is performed in synchronization with the external clock signal ExCLK that is asynchronous with the internal clock signal. The time tDOUT for outputting the data of one page depends on the frequency of the external clock signal ExCLK. For example, when the external clock signal ExCLK is 104 MHz, the tDOUT is about 39.4 μs. In continuous read, the array read time tR must be smaller than the data output time tDOUT of one page.

The memory cell array 10 includes a main area for storing data and a spare area for storing error detection codes by ECC processing, user information, and the like. FIG. 1B shows the configuration of the main area and the spare area of the memory cell array 10. The main area includes the main portion C0_M corresponding to the cache C0 and the main portion C1_M corresponding to the cache C1, the column address of the main portion C0_M is 000F to 3FFh, and the column address of the main portion C1_M is 400h to 7FFh. Is. The spare area includes the spare portion C0_S corresponding to the cache C0 and the spare portion C1_S corresponding to the cache C1, the column address of the spare portion C0_S is 800h to 83Fh, and the column address of the spare portion C1_S is 840h to 87Fh. Is.

The caches C0 and C1 used by the user are defined by C0 = main part C0_M + spare part C0_S, C1 = main part C1_M + spare part C1_S. This user definition is the same as the definition when the flash memory operates internally. The column address of the memory cell array and the column addresses of the latches L1 and L2 of the page buffer 20 have a one-to-one correspondence and are the same. Then, in the continuous reading operation, the data is sequentially output in the order of the column addresses 000h to 87Fh.

As the size of one page increases due to high integration, the area occupied by the page buffer / sense circuit increases proportionally. If the latch L2 can be removed, the occupied area of the page buffer / sense circuit can be significantly reduced. FIG. 3 is a timing chart assuming continuous reading with a single latch L1 (without latch L2). In this case, since there is no place to save the data of the latch L1, the array cannot be read unless the data of the latch L1 becomes empty. That is, it is virtually impossible to perform seamless reading.

Therefore, it is considered to read the data of one page separately into 1/2 page of the cache C0 and the cache C1. In this case, since the same page is read twice, there is a concern about disturb due to the reading operation. That is, in the read operation, all the bit lines are precharged / decharged, so that an undesired voltage due to capacitive coupling between the bit lines may affect the bit lines and memory cells.

FIG. 4 is a timing chart when reading 1/2 page of caches C0 and C1 (reading an array twice) in a continuous reading operation. When reading the cache C0 on the selection page of the memory cell array, as shown in FIG. 1B, when the main portion C0_M and the spare portion C0_S are read, these data are transferred to the latch L1 and the cache C1 is read. The main portion C1_M and the spare portion C1_S are read out, and these data are transferred to the latch L1.

Therefore, the data transfer of the cache C0 of the next page P1 must be performed after the cache C0 of the page P0 of the latch L1 is output. If the data transfer of the cache C0 of the page P1 is performed before that, the cache C0 of the page P0 will be overwritten. The data output of the cache C0 is completed when the spare portion C0_S of the cache C0 is output. In other words, the data transfer of the cache C0 of the page P1 is performed during the data output of the spare portion C1_S of the cache C1. Otherwise, the data on page P1 cannot be output seamlessly. However, the data output time tDOUT_C1Sp of the spare portion C1_S of the cache C1 is about 1.2 μs, and severe timing adjustment is required to transfer the data of the cache C0 on the next page during this short period. It is very difficult to achieve this.

The present invention has been made to solve such a conventional problem, and provides a semiconductor device and a continuous readout method capable of performing continuous readout while reducing the scale of a page buffer / sense circuit. The purpose is.

In the method for continuously reading a NAND flash memory according to the present invention, after the output of the first page data held in the first holding area of the data holding portion of the page buffer / sense circuit, the first page of the next page is output from the memory cell array. The page data of 1 is read, the read first page data is held in the first holding area, and after the output of the second page data held in the second holding area of the data holding unit, the memory cell array is used. The step includes reading the second page data of the next page and holding the read second page data in the second holding area.

In one embodiment, after outputting the first page data held in the first holding area, the second page data held in the second holding area is continuously output. In one embodiment, the first and second page data are 1/2 pages of data that are continuous in the column address direction of the selected page of the memory cell array, respectively. In one embodiment, the first page data includes data in the main area used to store the data, and the second page data includes data in the main area and data in the spare area. In one embodiment, when reading the first page data, m first group bit lines are selected, and when reading the second page data, m second group bit lines are selected. , The bit lines of the first group and the bit lines of the second group are arranged alternately. In one embodiment, the first and second page data held in the first and second holding regions are output to the outside in synchronization with the clock signal.

The semiconductor device according to the present invention includes a NAND type memory cell array, a page buffer / sense circuit connected to each bit line of the memory cell array, a read-out means for reading a selection page of the memory cell array, and the read-out means. The reading means includes an output means for outputting the data read by the above, and the reading means is held in the first holding area of the data holding portion of the page buffer / sense circuit when continuously reading a plurality of pages. After the page data of 1 is output by the output means, the first page data of the next page is read from the memory cell array, the read first page data is held in the first holding area, and the data holding unit is used. After the second page data held in the second holding area of the above is output by the output means, the second page data of the next page is read from the memory cell array, and the read second page data is used as the second page data. Hold in the holding area of 2.

In one embodiment, the output means outputs the first page data held in the first holding area and then continuously outputs the second page data held in the second holding area. In one embodiment, the first and second page data are 1/2 pages of data that are continuous in the column address direction of the selected page of the memory cell array, respectively. In one embodiment, the first page data includes data in the main area used to store the data, and the second page data includes data in the main area and data in the spare area. In one embodiment, the reading means selects m first group of bit lines when reading the first page data and of m second groups when reading the second page data. A bit line is selected, and the bit line of the first group and the bit line of the second group are arranged alternately. In one embodiment, the output means outputs the first and second page data held in the first and second holding regions to the outside in synchronization with the clock signal.

According to the present invention, after the output of the first page data, the first page data of the next page is read from the memory cell array, the read first page data is held in the first holding area, and the second page is held. After the data is output, the second page data of the next page is read from the memory cell array, and the read second page data is held in the second holding area. Therefore, the circuit scale of the page buffer / sense circuit can be adjusted. Continuous reading becomes possible while reducing.

It is a figure which shows the schematic structure of the conventional NAND type flash memory. It is a timing chart at the time of the conventional continuous reading using latches L1 and L2. It is a timing chart at the time of the conventional continuous reading using the latch L1. It is a timing chart at the time of another conventional continuous reading using the latch L1. It is a figure which shows the structure of the flash memory which concerns on embodiment of this invention. It is a figure explaining the definition of the cache C0, C1 which concerns on embodiment of this invention. It is a timing chart at the time of continuous reading operation which concerns on embodiment of this invention. It is a figure which shows the layout of the page buffer / sense circuit which concerns on embodiment of this invention. It is a figure explaining the selection of the row direction of the page buffer / sense circuit at the time of reading the cache C0, C1 of this embodiment. It is a figure explaining the selection of the column direction of the page buffer / sense circuit at the time of reading the cache C0, C1 of this embodiment. It is a table which shows the page buffer / sense circuit selected at the time of reading the cache C0, C1 of this embodiment.

Next, embodiments of the present invention will be described in detail with reference to the drawings. The semiconductor device according to the present invention is, for example, a NAND flash memory or a microprocessor in which such a flash memory is embedded, a microcontroller, a logic, an ASIC, a processor that processes images and sounds, a processor that processes signals such as wireless signals, and the like. Is.

FIG. 5 is a diagram showing a configuration of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 according to this embodiment has a memory array 110 in which a plurality of memory cells are arranged in a matrix, outputs data to the outside in response to an external clock signal ExCLK, and captures data input from the outside. An input / output circuit 120 that can enable data, an ECC circuit 130 that detects and corrects data errors, an address register 140 that receives address data via the input / output circuit 120, and commands received via the input / output circuit 120. It receives row address information Ax from the controller 150 that controls each part based on the control signal applied to the external terminal and the address register 140, decodes the row address information Ax, and selects blocks and word lines based on the decoding results. The word line selection circuit 160, the page buffer / sense circuit 170, which holds the data read from the page selected by the word line selection circuit 160, and the data to be programmed to the selected page, and the address register 140. A column selection circuit 180 that receives column address information Ay from, decodes column address information Ay, and selects columns in the page buffer / sense circuit 170 based on the decoding result, and data reading, programming, erasing, etc. It is configured to include an internal voltage generation circuit 190 that generates various voltages (write voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, etc.) required for the purpose.

The memory array 110 has, for example, m memory blocks BLK (0), BLK (1), ..., BLK (m-1) arranged in the column direction. A plurality of NAND strings in which a plurality of memory cells are connected in series are formed in one memory block. The NAND string may be formed two-dimensionally on the surface of the substrate or may be formed three-dimensionally on the surface of the substrate. Further, the memory cell may be an SLC type that stores one bit (binary data) or an MLC type that stores multiple bits. One NAND string is configured by connecting a plurality of memory cells (for example, 64), a bit line side selection transistor (selection gate line SGD), and a source line side selection transistor (selection gate line SGS) in series. Will be done. The drain of the bit line side selection transistor is connected to one corresponding bit line GBL, and the source of the source line side selection transistor is connected to the common source line SL.

In the read operation of the flash memory 100, a certain positive voltage is applied to the bit line, a certain voltage (for example, 0V) is applied to the selected word line, and a pass voltage Vpass (for example, 4.5V) is applied to the non-selected word line. ) Is applied, a positive voltage (for example, 4.5V) is applied to the selection gate lines SGD and SGS, the bit line side selection transistor and source line side selection transistor of the NAND string are turned on, and 0V is applied to the common source line. do. In the program (write) operation, a high voltage program voltage Vpgm (15 to 20V) is applied to the selected word line, an intermediate potential (for example, 10V) is applied to the non-selected word line, and the bit line side selection transistor is applied. It is turned on, the source line side selection transistor is turned off, and the potential corresponding to the data of "0" or "1" is supplied to the bit line. In the erasing operation, 0V is applied to the selected word line in the block, a high voltage (for example, 20V) is applied to the P well, and the electrons of the floating gate are drawn out to the substrate to erase the data in block units.

The page buffer / sense circuit 170 is configured to include a single latch L1 rather than having two latches L1 and L2 as shown in FIG. Further, it should be noted that in the internal operation of the flash memory 100, the caches C0 and C1 are defined by 1/2 page in which the column addresses are continuous. FIG. 6A shows the configuration of the main area and the spare area on the memory cell array, and FIG. 6B shows the internal definitions of the caches C0 and C1.

The main area includes the main portion C0_M corresponding to the cache C0 and the main portion C1_M corresponding to the cache C1, the column address of the main portion C0_M is 000h to 3FFh, and the column address of the main portion C1_M is 400h to 7FFh. Is. The spare area includes the spare portion C0_S corresponding to the cache C0 and the spare portion C1_S corresponding to the cache C1, the column address of the spare portion C0_S is 800h to 83Fh, and the column address of the spare portion C1_S is 840h to 87Fh. Is.

In the internal operation of the flash memory 100, the cache C0 is defined as the column addresses 000h to 43Fh, and the cache C1 is defined as the column addresses 440h to 87Fh. Therefore, the cache C0 includes a main portion C0_M and a portion of the main portion C1_M, and the cache C1 includes a portion of the main portion C1_M and the spare portions C0_S and C1_S. On the other hand, by the definition from the user's point of view, the cache C0 includes the main portion C0_M and the spare portion C0_S, and the cache C1 includes the main portion C0_M and the spare portion C0_S.

The data read from the selection page of the memory cell array is sensed by the sense node of the page buffer / sense circuit 170, and the sensed data is transferred to the latch L1 and held there. In the continuous read operation, the same page is read twice, first the data in the cache C0 is read, this is transferred to the column addresses 000h to 43Fh of the latch L1, and then the data in the cache C1 is read. This is transferred to the column addresses 440h to 87Fh of the latch L1. The caches C0 and C1 of the latch L1 can operate independently of each other. That is, in the continuous read operation, reading from the array and output of data are performed independently in units of 1/2 page. Array reading is performed based on the internal clock signal, and data transfer between the latch L1 and the input / output circuit 120 and data output from the input / output circuit 120 are performed based on the external clock signal ExCLK.

The column selection circuit 180 selects the reading start position of the data in the page according to the input column address Ay, or automatically reads the data from the top position of the page without using the column address. Further, the column selection circuit 180 may include a column address counter that increments the column address in response to a clock signal.

Next, the continuous reading operation of the flash memory 100 of this embodiment will be described. The continuous read operation is performed, for example, in a flash memory equipped with an SPI (Serial peripheral Interface) function. FIG. 7 is a timing chart of the continuous reading operation of this embodiment. As shown in the figure, after the data of the cache C0 of the page P0 is output, the array of the cache C0 of the next page P1 is read out during the data output of the cache C1 of the page P0, and the read cache is read. The data of C0 is transferred to the latch L1. The controller 150 starts the array reading of the cache C0 when the output of the data held in the latch L1 reaches the column address 43F.

Next, after the data of the cache C1 of the page P0 is output, the page P1 is selected again during the data output of the cache C0 of the page P1, and the data of the cache C1 of the page P1 is transferred to the latch L1. The controller 150 starts the array reading of the cache C1 when the output of the data held in the latch L1 reaches the column address 87F.

As described above, in this embodiment, the cache C1 of the latch L1 reads the data of the cache C0 of the next page into the latch L1 while the cache C0 is outputting, and the cache C0 reads the data of the cache C1 of the next page into the latch L1 while the cache C0 is outputting. Therefore, even if a high-speed frequency external clock signal ExCLK is used, the data output time tDOUT of the cache on page 1/2> the array read time tR on page 1/2 can be easily satisfied, and seamless data on multiple pages. Can output.

Next, a schematic layout of the page buffer / sense circuit 170 of this embodiment is shown in FIG. 8 (A). FIG. 8B is a table showing the connection relationship between the page buffer / sense circuits <0> to <7>, the sub-bit lines SBL <0> to <7>, and the global bit lines <0> to <15>. As shown in the figure, the page buffer sense circuit 170 is arranged so as to have 2 columns × 4 stages in one pitch in the row direction. One page buffer / sense circuit is configured to include one sense circuit and one latch circuit. One sub-bit line SBL connected to the sense node of one page buffer / sense circuit is connected to the even global bit line GBL_e and the odd global bit line GBL_o via the bit line selection circuit 172. The even-numbered global bit line GBL_e and the odd-numbered global bit line GBL_o extend in the column direction on a plurality of blocks of the memory cell array 110. Therefore, in one pitch, eight sub-bit lines connected to the 16 even-numbered global bit lines GBL_e and the odd-numbered global bit lines GBL_o via the bit line selection circuit 172 are laid out, and the eight sub-bit lines are laid out. Eight connected page buffers / sense circuits 170 are arranged. By laying out the page buffer / sense circuit in 2 rows × 4 stages, the number of stages in the column direction of the page buffer / sense circuit 170 is reduced, and the area efficiency is improved. Further, in this embodiment, since the page buffer / sense circuit 170 does not include the plurality of latches L1 and L2, the size in the height direction can be reduced. In the continuous read operation, when the cache C0 is read, the even global bit line GBL_e corresponding to the sub bit lines SBL <0, 2, 4, 6> connected to the page buffer / sense circuits <0> to <3> Alternatively, when reading any of the odd-numbered global bit lines GBL_o and reading the cache C1, it corresponds to the sub-bit lines SBL <1, 3, 5, 7> connected to the page buffer / sense circuits <4> to <7>. Either the even-numbered global bit line GBL_e or the odd-numbered global bit line GBL_o is read, at which time the non-selected even-numbered global bit line or the odd-numbered global bit line is electrically connected to the GND and shield reading is performed.

9, 10, and 11 show the connection relationship between the caches C0 and C1 and the page buffer / sense circuit (subbit line) shown in FIG. In these figures, Y1_PB_SA × 8 <0> and Y1_PB_SA × 8 <1> represent the layout of eight page buffers / sense circuits. The YAEb <*> signal, the YAOb <*> signal, and the YBC <*> signal are selection signals generated by decoding the column address by the column selection circuit 180, and FIG. 10 (A) shows the column address CA. The decoding table is shown.

When the caches C0 and C1 are read, the corresponding sense amplifier / sense circuit 170 is selected by YBC <*>. In FIG. 10B, YBC <0> to <67> select the page buffer / sense circuits <0> to <3> when reading the cache C0, and YBC <68> to <135> indicate. When reading the cache C1, the page buffer / sense circuits <4> to <7> are selected. YBC [0,68], YBC [1,69], ... YBC [67,135] are a pair of caches C0, C1 in the page buffer / sense circuit of Y1_PB_SA × 8. In this way, in reading the caches C0 and C1, by alternately arranging the activated page buffer / sense circuit in the column direction and the deactivated page buffer / sense circuit in the column direction, FIG. 6 ( The page buffer / sense circuit that is connected to the physically separated caches C0 and C1 as shown in B) and further activated is physically separated (the page buffer that is deactivated in between). (Because the sense circuit is intervened), it is possible to separate the bit lines selected at the same time by cache C0 or C1, and the page buffer / sense circuit or bit line when the same page is read repeatedly. The effect of capacity coupling is suppressed.

Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and variations are made within the scope of the gist of the present invention described in the claims. It can be changed.

100: Flash memory 110: Memory cell array 120: Input / output circuit 130: ECC circuit 140: Address register 150: Controller 160: Word line selection circuit 170: Page buffer / sense circuit 180: Column selection circuit

Claims (12)

It is a continuous reading method for NAND flash memory.
After outputting the first page data held in the first holding area of the data holding part of the page buffer / sense circuit, the first page data of the next page is read from the memory cell array, and the read first page data is read. In the first holding area,
After outputting the second page data held in the second holding area of the data holding unit, the second page data of the next page is read from the memory cell array, and the read second page data is used as the second page data. A method that involves holding in a holding area. The method according to claim 1, wherein the second page data held in the second holding area is continuously output after the first page data held in the first holding area is output. The method according to claim 1 or 2, wherein the first and second page data are 1/2 page data continuous in the column address direction of the selected page of the memory cell array, respectively. The method according to claim 3, wherein the first page data includes data in a main area used for storing data, and the second page data includes data in a main area and data in a spare area. When reading the first page data, the bit lines of the first group of m are selected, and when reading the second page data, the bit lines of the second group of m are selected and the first group. The method according to any one of claims 1 to 4, wherein the bit lines of the above and the bit lines of the second group are alternately arranged. The method according to any one of claims 1 to 5, wherein the first and second page data held in the first and second holding regions are output to the outside in synchronization with a clock signal. NAND type memory cell array and
A page buffer / sense circuit connected to each bit line of the memory cell array,
A reading means for reading the selection page of the memory cell array and
Including an output means for outputting the data read by the reading means.
When the reading means continuously reads a plurality of pages, the first page data held in the first holding area of the data holding portion of the page buffer / sense circuit is output by the output means, and then the memory. The first page data of the next page is read from the cell array, the read first page data is held in the first holding area, and the second page data held in the second holding area of the data holding unit. Is output by the output means, the second page data of the next page is read from the memory cell array, and the read second page data is held in the second holding area. The semiconductor according to claim 7, wherein the output means outputs the first page data held in the first holding region and then continuously outputs the second page data held in the second holding region. Device. The semiconductor device according to claim 7 or 8, wherein the first and second page data are 1/2 page data continuous in the column address direction of the selection page of the memory cell array, respectively. The semiconductor device according to claim 9, wherein the first page data includes data in a main area used for storing data, and the second page data includes data in a main area and data in a spare area. The reading means selects m first group bit lines when reading the first page data, and selects m second group bit lines when reading the second page data. The semiconductor device according to any one of claims 7 to 10, wherein the bit wires of the first group and the bit wires of the second group are alternately arranged. The output means according to any one of claims 7 to 11, wherein the output means outputs the first and second page data held in the first and second holding regions to the outside in synchronization with the clock signal. Semiconductor device.

Images