JP2022061674A - Memory control device and control method - Google Patents

Abstract

[Problem] When data transfer is performed by the DMA method, memory reads and writes by methods other than the DMA method are reduced. [Solution] A transfer device (230) receives a tag number from a first firmware (112), reads out a plurality of transmission descriptors included in a transmission descriptor table corresponding to the tag number in an order specified by the transmission descriptor table, and sequentially transfers a plurality of transfer target data according to the descriptions of the plurality of transmission descriptors read out in sequence. [Selected Figure] Figure 1

Description

The present invention relates to a memory control device and a control method.

When transferring data between CPU (Central Processing Unit) units or between CPU units and device units, data may be transferred by the DMA (Direct Memory Access) method. For example, Patent Document 1 below discloses a DMA circuit that confirms whether or not a descriptor is correct when reading a descriptor and determines whether or not DMA transfer of memory data is possible.

When transferring data by the DMA method, prepare a descriptor that describes the data to be transferred and the transfer amount in the memory of the unit on the transmitting side and / or the receiving side, and read the descriptor into the DMAC (DMA Controller). I need to let you. One descriptor is required for each DMAC that transfers a chunk of data (eg, one packet).

Japanese Unexamined Patent Publication No. 2006-178795

However, when a plurality of transfer target data are collectively transferred to a packet or the like, a memory copy associated with packet creation may frequently occur in a control unit (for example, CPU, MPU, etc.) that controls the transmitting side unit. Further, even in the control unit that controls the receiving side unit, there is a possibility that memory copying due to packet decompression occurs frequently.

FIG. 6 is a diagram schematically showing a process when data is packetized in a conventional data transfer method using a DMA method. The memory in the figure is the memory of the unit on the side of transmitting data (that is, the unit on the transmitting side).

When a plurality of data A to E exist at non-consecutive addresses on the memory, the control unit of the transmitting unit first sorts the data A to E in the order in which they are desired to be tags. For example, as shown in FIG. 6, the control unit copies the data A to E to any area in the memory so that the data A to E are stored at consecutive addresses (STEP: 1). .. Next, the CPU generates the tag X from the sorted and stored data A to E, and copies the tag X to any area in the memory (STEP: 2). For example, if there is another tag Y to be packetized together, the tag X is copied to an address contiguous with the tag Y. Finally, the tags stored in the consecutive addresses (tag X and tag Y in the example of FIG. 6) are put together to generate a packet (STEP: 3).

In this way, when the storage destination addresses of the data to be transferred are not contiguous, those data are stored in contiguous addresses in the memory in order to tag and / or packetize the data. So you need to organize the data and copy it back to memory. Therefore, there is a problem that memory copying frequently occurs in the CPU of the transmitting side unit, and the processing load is applied to the CPU of the transmitting side unit instead.

Further, the CPU or MPU of the receiving unit that has received the packet or tag needs to decompress the packet and / or the tag and copy the data contained therein to an appropriate area on the memory. Specifically, the control unit of the receiving unit needs to copy each data to an area on the memory that can be used by the application of the receiving unit.

One aspect of the present invention has been made in view of the above problems, and an object thereof is to reduce reading and writing of a memory by a method other than the DMA method when data is transferred by the DMA method.

In order to solve the above problems, the memory control device according to one aspect of the present invention accesses the transmission side memory and the reception side memory by a DMA (Direct Memory Access) method, and transmits a plurality of transfer target data to the transmission side. A memory control device that transfers data from a memory to the receiving memory, and the transmitting memory stores at least the plurality of transfer target data and a transmitting descriptor table including a plurality of transmitting descriptors. From the sender control unit to the identifier receiver that receives the identifier that specifies the transmit descriptor table, and from the transmit descriptor table that the identifier specifies, to the transmit descriptor table in the order specified by the transmit descriptor table. A transmission descriptor reading unit that reads out a plurality of included transmission descriptors, and a data reading unit that sequentially reads the plurality of transfer target data from the transmitting side memory according to the description of the plurality of transmitting descriptors that are sequentially read from the transmitting side memory. , Equipped with.

In order to solve the above problems, the control method of the memory control device according to one aspect of the present invention accesses the transmission side memory and the reception side memory by the DMA (Direct Memory Access) method, and transfers a plurality of data to be transferred. A method of controlling a memory control device for transferring data from a transmitting side memory to the receiving side memory, wherein the transmitting side memory includes at least the plurality of transfer target data and a plurality of transmitting descriptors. Is stored, and the identifier receiving step for receiving the identifier specifying the transmission descriptor table from the transmitting side control unit and the transmission descriptor table specified by the identifier are in the order specified by the transmission descriptor table. According to the description of the transmission descriptor read step for reading a plurality of transmission descriptors included in the transmission descriptor table and the plurality of transmission descriptors sequentially read from the transmission side memory, the plurality of transfer target data are transferred from the transmission side memory. Includes a data read step to read sequentially.

According to the above configuration, the memory controller reads the transmit descriptors in the order specified by the transmit descriptor table. Then, the memory control device can sequentially read the transfer target data from the transmission side memory according to the description of those transmission descriptors. Therefore, the memory control device can read out a plurality of transfer target data only by receiving the identifier from the transmission side control unit. In other words, the transmitting side control unit does not have to access the transmitting side memory after first transmitting the identifier to the memory control device. Therefore, according to the above configuration, it is possible to reduce the frequency with which the transmitting side control unit accesses the transmitting side memory.

Further, the memory control device can read out the transfer target data separately even when a plurality of transfer target data are stored at non-consecutive addresses in the transmission side memory, for example. Therefore, the transmitting side control unit does not need to combine a plurality of transfer target data into one packet or the like in advance. That is, the transmitting side control unit does not need to access the transmitting side memory and copy data or the like in order to generate packets and / or tags. Therefore, according to the above configuration, it is possible to reduce the frequency with which the transmitting side control unit accesses the transmitting side memory, as compared with the case where a plurality of transfer target data are collectively transferred as a packet and / or a tag or the like.

In order to solve the above problems, the memory control device according to one aspect of the present invention accesses the transmission side memory and the reception side memory by a DMA (Direct Memory Access) method, and transmits a plurality of transfer target data to the transmission side. It is a memory control device that transfers data from a memory to the receiving side memory, and the receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors, and the receiving side control unit gives the receiving side control unit. The identifier receiving unit that receives the identifier that specifies the descriptor table and the receiving descriptor table that corresponds to the identifier determined by the transmitting side control unit are included in the receiving descriptor table in the order specified by the receiving descriptor table. According to the description of the receiving descriptor reading unit that reads a plurality of receiving descriptors and the plurality of receiving descriptors that are sequentially read from the receiving side memory, the plurality of transfer target data read from the transmitting side memory is stored in the receiving side memory. A data writing unit for sequentially writing to the data is provided.

In order to solve the above problems, the control method of the memory control device according to one aspect of the present invention accesses the transmission side memory and the reception side memory by the DMA (Direct Memory Access) method, and transfers a plurality of transfer target data. A control method for a memory control device for transferring data from a transmitting side memory to the receiving side memory, wherein a receiving descriptor table including at least a plurality of receiving descriptors is stored in the receiving side memory, and the transmitting side has a storage side. From the identifier receiving step of receiving the identifier specifying the receiving descriptor table from the control unit and the receiving descriptor table corresponding to the identifier determined by the transmitting side control unit, the order specified by the receiving descriptor table is specified. The plurality of transfer targets read from the transmitting side memory according to the description of the receiving descriptor reading step of reading a plurality of receiving descriptors included in the receiving descriptor table and the plurality of receiving descriptors sequentially read from the receiving side memory. A data writing step of sequentially writing data to the receiving side memory is included.

According to the above configuration, the memory controller reads the receive descriptors in the order specified by the receive descriptor table. Then, the memory control device can sequentially write the transfer target data to the receiving side memory according to the description of those receiving descriptors. As a result, the receiving side control unit can write the data to be transferred without accessing the receiving side memory. Therefore, according to the above configuration, it is possible to reduce the frequency with which the receiving side control unit accesses the receiving side memory.

In addition, the memory control device writes a plurality of transfer target data separately. Therefore, for example, it is not necessary for the receiving side control unit to decompress a packet and / or a tag that summarizes a plurality of transfer target data and copy each transfer target data back to an appropriate area. Therefore, according to the above configuration, it is possible to reduce the frequency with which the receiving side control unit accesses the receiving side memory as compared with the case where a plurality of transfer target data are collectively transferred as a packet and / or a tag or the like.

The receiving side memory may store at least a receiving descriptor table including a plurality of receiving descriptors, and the identifier includes the transmitting descriptor table and the receiving descriptor table corresponding to the transmitting descriptor table. It may be a designated identifier. Then, the memory control device includes a receive descriptor reading unit that reads a plurality of receive descriptors included in the receive descriptor table in the order specified by the receive descriptor table from the receive descriptor table designated by the identifier. A data writing unit for sequentially writing the plurality of transfer target data read from the transmitting side memory to the receiving side memory according to the description of the plurality of receiving descriptors sequentially read from the receiving side memory. May be good.

According to the above configuration, the memory control device receives an identifier for designating the transmission descriptor table and the reception descriptor table from the transmission side control unit. As a result, the memory control device can read the receive descriptor paired with the transmit descriptor from the receive descriptor table designated by the identifier in the order specified by the receive descriptor table. Then, the memory control device can sequentially write the transfer target data to the receiving side memory according to the description of those receiving descriptors. As a result, the receiving side control unit can write the data to be transferred without accessing the receiving side memory. Therefore, according to the above configuration, it is possible to reduce both the frequency with which the transmitting side control unit accesses the transmitting side memory and the frequency with which the receiving side control unit accesses the receiving side memory.

Further, the memory control device separately reads a plurality of transfer target data from the transmission side memory and writes them separately. Therefore, the sender control unit does not need to access the sender memory for packet and / or tag generation, and the receiver control unit decompresses the packet and / or tag that summarizes a plurality of transfer target data. , It is not necessary to copy each transfer target data to an appropriate area again. Therefore, according to the above configuration, the frequency with which the transmitting side control unit accesses the transmitting side memory and the frequency with which the receiving side control unit accesses the storage side memory, as compared with the case where a plurality of transfer target data are collectively transferred to a packet and / or a tag or the like. Both the frequency of accessing the receiving memory can be reduced.

In the memory control device, the transmitting side memory may be provided in the first device, and the receiving side memory is a device different from the first device and communicates with the first device by a DMA method. It may be provided in two devices.

According to the above configuration, in the data transfer between the transmitting side memory and the receiving side memory mounted on different devices, it is possible to reduce the frequency of accessing the memory by a method other than the DMA method.

In the memory control device, the transmitting side memory and the receiving side memory may be the same. According to the above configuration, in data transfer within a certain memory, it is possible to reduce the frequency of access to the memory by a method other than the DMA method.

According to one aspect of the present invention, when data is transferred by the DMA method, the frequency of accessing the memory by a method other than the DMA method can be reduced.

It is a block diagram which shows an example of the main part structure of the data transfer system which concerns on Embodiment 1. FIG. It is a figure which shows the data structure of a tag table and a descriptor table. It is a figure which shows the data structure of the transmit descriptor and the receive descriptor. It is a sequence diagram which shows the flow of the process of downlink data transfer in the said data transfer system. It is a block diagram which shows an example of the main part structure of the data transfer system which concerns on Embodiment 2. It is a figure which schematically showed the process in the case of packetizing data in the conventional data transfer method using the DMA (Direct Memory Access) method.

[Embodiment 1]
§1. Application example In this embodiment, as an example, the first processing device 110 included in the first unit (first device, second device) 100 and the second processing device 110 included in the second unit (first device, second device) 200 are included. A data transfer system capable of bidirectional data transfer to and from the processing device 210 will be described.

In the following description, transferring data from the first processing device 110 to the second processing device 210 may be referred to as "downlink transfer". Further, transferring data from the second processing device 210 to the first processing device 110 may be referred to as "uplink transfer".

FIG. 1 is a block diagram showing an example of a main part configuration of the data transfer system 500 according to the present embodiment. The data transfer system 500 includes a first unit 100 and a second unit 200. The first unit 100 includes a first processing device 110 and a first memory 120, and the second unit 200 includes a second processing device 210, a second memory 220, and a transfer device 230.

(1st unit 100)
The first unit 100 is, for example, a unit that controls industrial equipment. The first unit 100 can be realized by a PLC (Programmable Logic Controller) or the like. The first processing device 110 is a processor in the first unit 100. The first processing device 110 may be, for example, a CPU (Central Processing Unit). The first memory 120 is a volatile storage device in the first unit 100. The first memory 120 may be, for example, a DRAM (Dynamic Random Access Memory).

(2nd unit 200)
The second unit 200 is, for example, a unit for complementing or expanding the function of the first unit 100. More specifically, the second unit 200 may be a unit having a function such as a data statistical function, a router function, or a database function.

The second processing device 210 is a processor of the second unit 200. The second processing unit 210 may be, for example, an MPU (Micro Processing Unit). The second memory 220 is a volatile storage device in the second unit 200. The second memory 220 may be, for example, a DRAM.

The transfer device 230 is a device for realizing data transfer by the DMA method between the first processing device 110 and the second processing device 210. The transfer device 230 can be realized by, for example, an FPGA (Field-Programmable gate array). In the present embodiment, the transfer device 230 is provided in the second unit 200, but in the data transfer system 500, the transfer device 230 may be provided in the first unit 100.

In either case, the first processing device 110 and the transfer device 230, and the second processing device 210 and the transfer device 230 are each connected by a bus conforming to the PCIe (Peripheral Component Interconnect Express) standard. As a result, the first processing device 110 and the second processing device 210 can communicate with each other by PCIe via the transfer device 230.

(Data transfer)
Although the details will be described later, in the data transfer system 500, the transmitting side unit transmits a certain identifier to the receiving side unit. The identifier is information for specifying the transmit descriptor table used by the transmitting unit, and is also information for specifying the receiving descriptor table used by the receiving unit.

The transmit descriptor table contains a plurality of transmit descriptors. The receive descriptor table contains a plurality of receive descriptors. Therefore, it can be said that the above-mentioned identifier specifies a transmission descriptor group and a reception descriptor group used when transferring a plurality of transfer target data.

The transfer device 230 reads a transmission descriptor from the transmission descriptor table of the transmission side memory. Further, the transfer device 230 reads the receive descriptor from the receive descriptor table of the receiving side memory. Then, the transfer device 230 transfers the transfer target data from the transmission side memory to the reception side memory according to the description of one set of transmission descriptor and reception descriptor. The transfer device 230 repeats reading such a transmission descriptor and a reception descriptor and transferring data to be transferred by the number of sets of transmission descriptors and reception descriptors.

According to the process shown in FIG. 4, in the data transfer system 500, the transmitting unit need only determine an identifier and transmit the identifier to the transfer device 230. Therefore, even when there are a plurality of transfer target data, it is not necessary to tag and / or packetize the transfer target data. Furthermore, it is not necessary to rearrange the data on the memory for tagging and / or packetizing the data to be transferred. Therefore, according to the data transfer system 500, it is possible to reduce the frequency of memory access by the control unit of the transmitting side unit.

Further, in the data transfer system 500, the receiving unit receives the transfer target data as it is, not the packet or the tag. Therefore, the process of writing the packet or tag to the memory and then decompressing it does not occur. Further, it is not necessary to relocate each of the decompressed transfer target data to an appropriate area on the memory. Therefore, according to the data transfer system 500, it is possible to reduce the frequency of memory access by the control unit of the receiving side unit.

§2. Configuration example (1st unit 100)
Next, the main components of the first unit 100 and the second unit 200 shown in FIG. 1 will be described. In the example of FIG. 1, the first unit 100 includes a first processing device 110 and a first memory 120. The first unit 100 may also include an input device, an output device, a non-volatile storage device such as a ROM (Read Only Memory), and the like.

(First processing device 110)
The first processing device 110 (transmitting side control unit) is a processor that collectively controls the first unit 100. The first processing device 110 is realized by, for example, a CPU. The first processing device 110 expands the control program of the first unit 100 stored in the non-volatile storage device (not shown) into the first memory 120. Then, the first processing apparatus 110 interprets and executes the control program expanded in the first memory 120, and controls each component. As a result, as shown in FIG. 1, the first processing apparatus 110 according to the present embodiment functions as the first control unit 111, the first firmware (FW) 112, and the first PCIe interface 113.

The first control unit 111 controls a device (for example, an industrial device) connected to the first unit 100. Further, the first control unit 111 may communicate with the connected device at a fixed cycle and acquire data processed in a downstream process from various devices. Further, for example, the data acquired by the first control unit 111 may be transferred to the second unit 200 and then processed by the second unit 200.

The first firmware 112 executes various processes related to data transfer between the first unit 100 and the second unit 200. For example, the first firmware 112 determines the tag number at the time of downlink data transfer and notifies the transfer device 230. The tag number will be described in detail later. Further, the first firmware 112 performs a process of creating or downloading a tag table, a transmission descriptor table, and a reception descriptor table in advance before starting data transfer between the first unit 100 and the second unit 200, and the creation or download thereof. It also performs a process of writing the downloaded tag table, transmission descriptor table, and receive descriptor table to the first memory 120. That is, the first firmware 112 prepares the tag table, the transmit descriptor table, and the receive descriptor table in advance and stores them in the first memory 120.

The first PCIe interface 113 is an interface for the first processing device 110 to connect to the transfer device 230 via PCIe via PCIe bus.

(First memory 120)
The first memory 120 is a volatile storage area (RAM; Random Access Memory). The first memory 120 is executed by the transmission data generated by the first processing device 110, the received data generated by the second processing device 210 to be processed by the first processing device 110, and the first processing device 110. Stores various programs to be used. Further, the first memory 120 may be used as a working memory when executing various programs by the first processing device 110. As the first memory 120, a DRAM (Dynamic Random Access Memory) can be typically used.

The transmission tag table, the transmission descriptor table, the reception tag table, the reception descriptor table, and the data to be transferred (data 1 to m in FIG. 1) are stored in the first memory 120.

The transmission descriptor of the first memory 120 is a descriptor that defines a part of the operation for the DMAC233 (described later) of the transfer device 230 to realize downlink transfer. As a result, the first firmware 112 of the first processing device 110 can transmit data to the second firmware 212 of the second processing device 210.

The receive descriptor of the first memory 120 defines a part of the operation for the DMAC233 to realize the uplink transfer. As a result, the first firmware 112 of the first processing device 110 can receive the data transmitted from the second firmware 212 of the second processing device 210.

(Tag table and descriptor table)
FIG. 2 is a diagram showing the data structures of the tag table and the descriptor table. If it is a tag table, the basic data structure is the same whether it is a transmission tag table or a reception tag table. Further, if it is a descriptor table, the basic data structure is the same whether it is a transmit descriptor table or a receive descriptor table.

The "tag table" is a list of start addresses of storage destinations in the memory of each of a plurality of descriptor tables. The transmission tag table is a table used when transmitting data, and is a list of start addresses of the transmission descriptor table. The receive tag table is a table used when receiving data, and is a list of start addresses of the receive descriptor table.

In FIG. 2, for convenience, the descriptors specified by the start address of a certain descriptor table (descriptor table 1) of the tag table are shown side by side in association with the tag table. However, the tag table and the descriptor table corresponding to the tag table may be stored at non-consecutive addresses in the memory. Further, the tag table in FIG. 2 specifies the start address of the descriptor table, and does not have to include the descriptor table itself.

Further, the order of the start addresses of each descriptor table in the tag table of FIG. 2 is not particularly limited. For example, in the example of the figure, the start addresses of the X descriptor tables are specified in reverse order from the descriptor table X to the descriptor table 1, but the descriptor table 1 to the descriptor table X are specified in order. It may be arranged in such an order.

The "descriptor table" is a data table that stores a plurality of descriptors in the order of being used for data transfer. In the example of FIG. 2, the descriptor table includes descriptors 1 to descriptor i. The transmission descriptor table is a data table that stores a plurality of transmission descriptors in the order of being used for data transfer. The receive descriptor table is a data table that stores a plurality of receive descriptors in the order of being used for data transfer. For example, when the descriptor in FIG. 2 is a transmission descriptor, the transmission descriptor is used in order from the descriptor 1 when reading data from the transmission side memory. Further, for example, when the descriptor in FIG. 2 is a receiving descriptor, the receiving descriptor is used in order from the descriptor 1 when writing data to the receiving side memory.

(Send descriptor and receive descriptor)
FIG. 3 is a diagram showing the data structures of the transmit descriptor and the receive descriptor. As shown in FIG. 2, the transmission descriptor includes the following (1) to (3).

(1) Storage address of the data specified as the transmission target in the memory (2) Size of the data specified as the transmission target (3) Other data Of these, the "other data" shown in (3) For example, a transfer completion flag set when the transfer is completed successfully is included.

The receive descriptor includes the following (4) and (5) as shown in FIG.

(4) Storage destination address of the data to be received in the memory (5) Other data Of these, the "other data" shown in (5) is, for example, a transfer to be set when the transfer is completed successfully. Includes completion flags and more.

(2nd unit 200)
In the example of FIG. 1, the second unit 200 includes a second processing device 210, a second memory 220, and a transfer device 230.

(Second processing device 210)
The second processing device (transmitting side control unit) 210 collectively controls the second unit 200. The second processing device 210 is realized by, for example, an MPU. The second processing device 210 expands the control program of the second unit 200 stored in the non-volatile storage device (not shown) into the second memory 220. Then, the second processing apparatus 210 interprets and executes the control program expanded in the second memory 220 to control each component. As a result, as shown in FIG. 1, the second processing apparatus 210 according to the present embodiment functions as the second control unit 211, the second firmware 212, and the second PCIe interface 213.

The second control unit 211 executes processing related to various functions carried out by the second unit 200 itself. For example, the second control unit 211 may aggregate the data acquired from the first unit 100.

The second firmware 212 executes various processes related to data transfer between the second unit 200 and the first unit 100. For example, the second firmware 212 determines the tag number at the time of uplink data transfer and notifies the transfer device 230. Further, the second firmware 212 performs a process of creating or downloading a tag table, a transmission descriptor table, and a receive descriptor table in advance before the start of data transfer between the second unit 200 and the first unit 100, and the creation or download thereof. It also performs a process of writing the downloaded transmit descriptor table and receive descriptor table to the second memory 220. That is, the second firmware 212 prepares the tag table, the transmission descriptor table, and the receive descriptor table in advance and stores them in the second memory 220.

The second PCIe interface 213 is an interface for the second processing device 210 to connect to the transfer device 230 via PCIe bus.

(Second memory 220)
The second memory 220 is a volatile storage area (RAM). The second memory 220 is executed by the transmission data generated by the second processing device 210, the received data generated by the first processing device 110 to be processed by the second processing device 210, and the second processing device 210. Stores various programs to be used. Further, the second memory 220 may be used as a working memory when executing various programs by the second processing device 210. As the second memory 220, a DRAM or the like can be typically used.

Like the first memory 120, the second memory 220 stores a transmission tag table, a transmission descriptor table, a reception tag table, a reception descriptor table, and data to be transferred. The data structures of the tag table and the descriptor table are the same as the data of the same name described in the first memory 120.

The transmission descriptor of the second memory 220 is a descriptor that defines a part of the operation for the DMAC233 of the transfer device 230 to realize the uplink transfer. As a result, the second firmware 212 of the second processing device 210 can transmit data to the first firmware 112 of the first processing device 110.

The receive descriptor of the second memory 220 defines a part of the operation for the DMAC 233 to realize the downlink transfer. As a result, the second firmware 212 of the second memory 220 can receive the data transmitted from the first firmware 112 of the first processing device 110.

(Transporter 230)
The transfer device (memory control device) 230 is a device for communicating with the first processing device 110 and the second processing device 210 by PCIe. The transfer device 230 controls the downlink transfer between the first processing device 110 and the second processing device 210, and the uplink transfer as needed.

In order to realize downlink transfer, the transfer device 230 has at least a DMAC (Direct Memory Access Controller) 233, a downlink transmission descriptor controller (identifier receiving unit, transmitting descriptor reading unit) 235, and a downlink receiving descriptor controller (receiving descriptor reading unit). Part) 234 and.

The DMAC233 (data reading unit, data writing unit) controls data transfer from the first memory 120 of the first processing device 110 to the second memory 220 of the second processing device 210. The DMAC233 reads out the data to be sequentially transferred according to the description of the transmission descriptor. The DMAC 233 writes the read data to the second memory 220 according to the description of the receiving descriptor.

The downlink transmission descriptor controller 235 receives from the first firmware 112 a tag number that specifies a transmission and reception descriptor table used for transferring data to be transferred.

Here, the "tag number" is an identifier that specifies the descriptor table in the tag table. Since the descriptor table contains descriptors, it can be said that the "tag number" is an identifier that specifies the descriptor group used for transferring the data to be transferred. That is, the "tag number" in the unit on the transmitting side is an identifier that specifies a group of transmission descriptors to be used when receiving data from now on. The "tag number" in the unit on the receiving side is an identifier that specifies a group of receiving descriptors to be used when receiving data from now on.

The format of the tag number is not particularly limited. For example, the tag number may be an identifier including at least one of a numerical value, a character string, a code, and the like. In the present embodiment, the tag number is a value that specifies a specific address in the memory.

The downlink transmission descriptor controller 235 specifies the transmission descriptor table specified by the tag number from the transmission descriptor tables stored in the first memory 120. The downlink transmit descriptor controller 235 refers to the specified transmit descriptor table and reads out the transmit descriptors in the order stored in the table (that is, specified in the table). This transmission descriptor is a transmission descriptor related to an address in which transfer target data (that is, data read from the first memory 120) in the first memory 120 is stored.

The downlink receive descriptor controller 234 specifies the receive descriptor table specified by the tag number from the receive descriptor tables stored in the second memory 220. The downlink receive descriptor controller 234 refers to the specified receive descriptor table and reads the receive descriptor in the order stored in the table (that is, specified in the table). This receive descriptor is a receive descriptor relating to an address for storing transfer target data in the second memory 220 (that is, data to be written in the second memory 220).

The transfer device 230 may further include an uplink transmission descriptor controller (identifier reception unit, transmission descriptor reading unit) 237 and an uplink reception descriptor controller (reception descriptor reading unit) 236 in order to realize uplink transfer.

When the uplink transfer is realized, the DMAC (data reading unit, data writing unit) 233 controls the data transfer from the second memory 220 of the second processing device 210 to the first memory 120 of the first processing device 110. The DMAC233 reads out the data to be sequentially transferred according to the description of the transmission descriptor. The DMAC233 writes the read data to the first memory 120 according to the description of the receiving descriptor.

The uplink transmission descriptor controller 237 receives from the second firmware 212 a tag number that specifies a transmission and reception descriptor table used for transferring data to be transferred.

The uplink transmission descriptor controller 237 specifies the transmission descriptor table specified by the tag number from the transmission descriptor tables stored in the second memory 220. The uplink transmit descriptor controller 237 refers to the identified transmit descriptor table and reads out the transmit descriptors in the order stored in the table (that is, specified in the table). This transmission descriptor is a transmission descriptor related to an address in which transfer target data (that is, data read from the second memory 220) in the second memory 220 is stored.

The uplink receive descriptor controller 236 specifies the receive descriptor table specified by the tag number from the receive descriptor tables stored in the first memory 120. The uplink receive descriptor controller 236 refers to the specified receive descriptor table and reads the receive descriptor in the order stored in the table (that is, specified in the table). This receive descriptor is a receive descriptor relating to an address for storing transfer target data in the first memory 120 (that is, data to be written in the first memory 120).

The first PCIe interface 231 is an interface for the transfer device 230 to connect to the first processing device 110 via PCIe via PCIe bus.

The second PCIe interface 232 is an interface for the transfer device 230 to connect to the second memory 220 by PCIe via via PCIe bus.

§3. Process flow FIG. 4 is a sequence diagram showing a flow of downlink data transfer in the data transfer system 500. Before the series of processes shown in FIG. 4, as an initial process, the first firmware 112 of the first processing device 110 prepares at least a transmission tag table and a transmission descriptor table in the first memory 120. Further, the second firmware 212 of the second processing device 210 prepares at least a receive tag table and a receive descriptor table in the second memory 220. Further, it is assumed that a plurality of transfer target data are stored in the first memory 120.

When the preparations of the various tag tables and the descriptor tables are completed, the first firmware 112 of the first processing device 110 transmits the tag number to the downlink transmission descriptor controller 235 of the transfer device 230. The downlink transmission descriptor controller 235 receives the tag number (S100. Identifier reception step), and outputs the tag number to the downlink reception descriptor controller 234 (S101). The downlink receive descriptor controller 234 accepts the input tag number (S201).

When the notification of the tag number of S101 to S201 is completed, the downlink transmission descriptor controller 235 identifies the transmission descriptor table (transmission DescT) corresponding to the tag number from the transmission tag table of the first memory 120 (S102). The downlink transmission descriptor controller 235 reads the transmission descriptor (transmission Desc) stored in the first (that is, the head) of the specified transmission descriptor table from the first memory 120 (S103, transmission descriptor read step).

On the other hand, after receiving the tag number (S201), the downlink receive descriptor controller 234 identifies the receive descriptor table (reception DeskT) corresponding to the tag number from the receive tag table of the second memory 220 (S202). The downlink receive descriptor controller 234 reads the receive descriptor (reception Desk) stored in the first (that is, the head) of the specified receive descriptor table from the second memory 220 (S203, receive descriptor read step).

The DMAC 233 reads data (that is, the first data) from the first memory 120 according to the information described in the transmission descriptor read by the downlink transmission descriptor controller 235 (S301, data read step). The DMAC 233 writes the read data to the second memory 220 according to the information described in the receive descriptor read by the downlink reception descriptor controller 234 (S302, data writing step).

When the writing of the first data to the second memory 220 (S302) is completed, the downlink transmit descriptor controller 235 subsequently stores the transmit descriptor (that is, the second) of the transmit descriptor table specified in S102. Read the transmit descriptor) (S104, transmit descriptor read step). The downlink receive descriptor controller 234 also reads the next stored receive descriptor (that is, the second receive descriptor) of the receive descriptor table specified in S202 after the processing of S302 is completed (S204, receive descriptor read step). ..

The DMAC233 executes the same processing as in S301 to S302 based on the second transmit descriptor and the second receive descriptor. That is, the DMAC233 reads the second data according to the information described in the second transmit descriptor (S303, data read step), and writes the second data to the second memory 220 based on the second receive descriptor. (S304, data writing step).

After that, the downlink transmission descriptor controller 235, the downlink reception descriptor controller 234, and the DMAC233 repeat the same processing until all the transfer target data is transferred. That is, the downlink transmission descriptor controller 235 reads the transmission descriptor (mth transmission descriptor) stored next in the transmission descriptor table specified in S102 (S105, transmission descriptor read step). The downlink receive descriptor controller 234 reads the next stored receive descriptor (that is, the m-th receive descriptor) of the receive descriptor table specified in S202 (S205, receive descriptor read step).

The DMAC233 executes the same processing as in S301 to S302 based on the m-th transmit descriptor and the m-th receive descriptor. That is, the DMAC233 reads the mth data according to the information described in the mth transmission descriptor (S305, data read step), and writes the mth data to the second memory 220 based on the mth receive descriptor. (S306, data writing step).

According to the process shown in FIG. 4, the transfer device 230 transfers data between the first memory 120 and the second memory 220 mounted on different devices from the first processing device 110 to the first memory 120. Access frequency can be reduced. Further, according to the process shown in FIG. 4, the transfer device 230 has the second memory 210 to the second memory in the data transfer between the first memory 120 and the second memory 220 mounted on different devices. The frequency of access to 220 can be reduced. That is, the transfer device 230 can reduce the frequency of access to the memory by a method other than the DMA method.

According to the process shown in FIG. 4, the transfer device 230 reads out the transmission descriptors in the order specified by the transmission descriptor table. Then, the transfer device 230 can sequentially read the transfer target data from the first memory 120 according to the description of those transmission descriptors. Therefore, the transfer device 230 can read out a plurality of transfer target data only by receiving the tag number from the first processing device 110. In other words, the first processing device 110 does not have to access the first memory 120 after first transmitting the tag number to the transfer device 230. Therefore, according to the process shown in FIG. 4, the frequency with which the first processing device 110 accesses the first memory 120 can be reduced.

Further, the transfer device 230 can read the transfer target data separately even when a plurality of transfer target data are stored at non-consecutive addresses in the first memory 120, for example. Therefore, the first processing device 110 does not need to combine a plurality of transfer target data into one packet or the like in advance. That is, the first processing device 110 does not need to access the first memory 120 to copy data or the like in order to generate packets and / or tags. Therefore, according to the process shown in FIG. 4, the frequency with which the first processing device 110 accesses the first memory 120 is reduced as compared with the case where a plurality of transfer target data are collectively transferred to a packet and / or a tag or the like. be able to.

According to the process shown in FIG. 4, the transfer device 230 reads the receive descriptors in the order specified by the receive descriptor table. Then, the transfer device 230 can sequentially write the transfer target data to the second memory 220 according to the description of those receive descriptors. As a result, the second processing device 210 can write the data to be transferred without accessing the second memory 220. Therefore, according to the process shown in FIG. 4, the frequency with which the second processing device 210 accesses the second memory 220 can be reduced.

Further, the transfer device 230 writes a plurality of transfer target data separately. Therefore, for example, specifically, it is not necessary for the second processing device 210 to decompress the packet and / or tag that summarizes the plurality of transfer target data and copy each transfer target data back to an appropriate area. Therefore, according to the process shown in FIG. 4, the frequency with which the second processing device 210 accesses the second memory 220 is reduced as compared with the case where a plurality of transfer target data are collectively transferred to a packet and / or a tag or the like. be able to.

The flow of uplink data transfer in the data transfer system 500 is the same as that of downlink data transfer except for the main body of various processes. Specifically, in the case of uplink data transfer, the control device and memory on the transmitting side are changed to the second processing device 210 and the second memory 220, and the control device on the receiving side is changed to the first processing device 110 and the first memory 120. Further, in the case of uplink data transfer, the uplink transmission descriptor controller 237 and the uplink reception descriptor controller 236 may execute the processes performed by the downlink transmit descriptor controller 235 and the downlink receive descriptor controller 234, respectively. Further, the DMAC 233 may write the data read from the second memory 220 to the first memory 120.

[Embodiment 2]
In the present invention, the transmitting side memory and the receiving side memory may be the same. That is, the data transfer system according to the present invention not only transfers data between two independent devices, but also transfers data in one memory of one device (that is, data transfer in one memory). It may be applied to read / write).

Hereinafter, a second embodiment of the present invention will be described. For convenience of explanation, the same reference numerals are given to the members having the same functions as the members described in the above-described embodiment, and the description thereof will not be repeated. Further, in the present embodiment, as an example, a case where data transfer is performed in the device of the third unit 300 will be described.

FIG. 5 is a block diagram showing an example of the configuration of a main part of the data transfer system 600 according to the present embodiment. The third unit 300 according to the data transfer system 600 includes a first processing device (transmitter control unit) 110, a first memory 120, and a transfer device (memory control device) 330.

The transfer device 330 includes a DMAC (data reading unit, data writing unit) 331, a receiving descriptor controller (receiving descriptor reading unit) 332, a transmitting descriptor controller (identifier receiving unit, transmitting descriptor reading unit) 333, and a PCIe interface 334. And prepare. The transmission descriptor controller 333 executes the same processing as the downlink transmission descriptor controller 235 and the uplink transmission descriptor controller 237. The receive descriptor controller 332 executes the same processing as the downlink receive descriptor controller 234 and the uplink receive descriptor controller 236.

The basic flow of uplink and downlink data transfer in the data transfer system 600 is the same as the flow of uplink and downlink data transfer in the data transfer system 500 according to the first embodiment. Specifically, in the case of the present embodiment, both the transmitting side memory and the receiving side memory are the first memory 120. That is, where the information in the second memory 220 was read / written in the process shown in FIG. 4, the same information may be read / written to / from the first memory 120. Further, in the case of the present embodiment, the first firmware 112 of the first processing device 110 determines the tag number for designating the transmit descriptor table and the receive descriptor table used for transferring the transfer target data, and determines the tag number to be used in the downlink transmission descriptor controller 333. Send.

Further, the process executed by the downlink transmission descriptor controller 235 in FIG. 4 is executed by the transmission descriptor controller 333. Further, the process executed by the downlink receive descriptor controller 234 in FIG. 4 is executed by the receive descriptor controller 332. Further, the process executed by the DMAC 233 in FIG. 4 is executed by the DMAC 331.

According to the above configuration, when data is transferred by the DMA method, the frequency of access by the first processing device 110 to the first memory 120 can be reduced.

[Modification example]
Although the embodiments of the present invention have been described in detail above, the above description is merely an example of the present invention in all respects. Needless to say, various improvements and modifications can be made without departing from the scope of the present invention. For example, the following changes can be made. In the following, the same reference numerals will be used for the same components as those in the above embodiment, and the same points as in the above embodiment will be omitted as appropriate. The following modifications can be combined as appropriate.

The data transfer system 500 according to the first embodiment may include one first unit 100 and a plurality of second units 200. In this case, one transfer device 230 may be provided in the first unit 100, or each of the plurality of second units 200 may be provided. As a result, the plurality of second units 200 can transmit and receive data to and from the first unit 100 via the transfer device 230, respectively.

[Example of implementation by software]
The control blocks of the first processing device 110, the second processing device 210, the transfer device 230, and the transfer device 330 may be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like. It may be realized by software.

In the latter case, the first processing device 110, the second processing device 210, the transfer device 230, and the transfer device 330 include a computer that executes instructions of a program that is software that realizes each function. The computer includes, for example, one or more processors and a computer-readable recording medium that stores the program. Then, in the computer, the processor reads the program from the recording medium and executes the program, thereby achieving the object of the present invention. As the processor, for example, a CPU (Central Processing Unit) can be used. As the recording medium, a "non-temporary tangible medium", for example, a ROM (Read Only Memory) or the like, a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. Further, a RAM (Random Access Memory) for expanding the above program may be further provided. Further, the program may be supplied to the computer via any transmission medium (communication network, broadcast wave, etc.) capable of transmitting the program. It should be noted that one aspect of the present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the above program is embodied by electronic transmission.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention.

100 1st unit (1st device, 2nd device)
110 First processing device (transmitter control unit)
111 1st control unit 112 1st firmware 113, 213, 231, 232, 334 Interface 120 1st memory (sending side memory, receiving side memory)
200 2nd unit (1st device, 2nd device)
210 Second processing device (transmitter control unit)
211 2nd control unit 212 2nd firmware 220 2nd memory (sending side memory, receiving side memory)
230, 330 Transfer device (memory control device)
233,331 DMAC (data reading unit, data writing unit)
234 Downstream receive descriptor controller 235 Downstream transmission descriptor controller (identifier receiver, transmit descriptor read section)
236 Uplink receive descriptor controller (receive descriptor read unit)
237 Uplink transmission descriptor controller (identifier receiver, transmit descriptor reader)
332 Receive descriptor controller (Receive descriptor reader)
333 Transmit descriptor controller (identifier receiver, transmit descriptor reader)
300 3rd unit 500, 600 Data transfer system

Claims (7)

A memory control device that accesses a transmission side memory and a reception side memory by a DMA (Direct Memory Access) method and transfers a plurality of transfer target data from the transmission side memory to the reception side memory.
At least the plurality of transfer target data and the transmission descriptor table including the plurality of transmission descriptors are stored in the transmission side memory.
An identifier receiving unit that receives an identifier that specifies the transmit descriptor table from the transmitting side control unit, and
A transmission descriptor reading unit that reads a plurality of transmission descriptors included in the transmission descriptor table in the order specified by the transmission descriptor table from the transmission descriptor table designated by the identifier.
A memory control device comprising: a data reading unit for sequentially reading the plurality of transfer target data from the transmitting side memory according to the description of the plurality of transmitting descriptors sequentially read from the transmitting side memory. A memory control device that accesses a transmission side memory and a reception side memory by a DMA (Direct Memory Access) method and transfers a plurality of transfer target data from the transmission side memory to the reception side memory.
The receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors.
An identifier receiving unit that receives an identifier that specifies the receiving descriptor table from the transmitting side control unit, and
A receive descriptor reading unit that reads a plurality of receiving descriptors included in the receiving descriptor table in the order specified by the receiving descriptor table from the receiving descriptor table according to the identifier determined by the transmitting side control unit.
It is characterized by comprising a data writing unit for sequentially writing the plurality of transfer target data read from the transmitting side memory to the receiving side memory according to the description of the plurality of receiving descriptors sequentially read from the receiving side memory. A memory control device. The receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors.
The identifier is an identifier that specifies the transmit descriptor table and the receive descriptor table corresponding to the transmit descriptor table.
A receive descriptor reading unit that reads a plurality of receive descriptors included in the receive descriptor table in the order specified by the receive descriptor table from the receive descriptor table designated by the identifier.
It is characterized by comprising a data writing unit for sequentially writing the plurality of transfer target data read from the transmitting side memory to the receiving side memory according to the description of the plurality of receiving descriptors sequentially read from the receiving side memory. The memory control device according to claim 1. The transmitting side memory is provided in the first device, and is provided in the first device.
The memory control device according to claim 3, wherein the receiving side memory is a device different from the first device and is provided in a second device that communicates with the first device by a DMA method. .. The memory control device according to claim 3, wherein the transmission side memory and the reception side memory are the same. It is a control method of a memory control device that accesses a transmission side memory and a reception side memory by a DMA (Direct Memory Access) method and transfers a plurality of transfer target data from the transmission side memory to the reception side memory.
At least the plurality of transfer target data and the transmission descriptor table including the plurality of transmission descriptors are stored in the transmission side memory.
An identifier receiving step that receives an identifier that specifies the transmit descriptor table from the transmitting side control unit, and
A transmission descriptor read step for reading a plurality of transmission descriptors included in the transmission descriptor table in the order specified by the transmission descriptor table from the transmission descriptor table designated by the identifier.
A control method comprising: a data reading step of sequentially reading the plurality of transfer target data from the transmitting side memory according to the description of the plurality of transmitting descriptors sequentially read from the transmitting side memory. It is a control method of a memory control device that accesses a transmission side memory and a reception side memory by a DMA (Direct Memory Access) method and transfers a plurality of transfer target data from the transmission side memory to the reception side memory.
The receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors.
An identifier receiving step for receiving an identifier specifying the receiving descriptor table from the transmitting side control unit, and
A receive descriptor read step for reading a plurality of receive descriptors included in the receive descriptor table in the order specified by the receive descriptor table from the receive descriptor table according to the identifier determined by the transmission side control unit.
It is characterized by including a data writing step of sequentially writing the plurality of transfer target data read from the transmitting side memory to the receiving side memory according to the description of the plurality of receiving descriptors sequentially read from the receiving side memory. The control method.

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