JP2021090089A - Image processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing apparatus using a data capture function by a FIFA memory, even when an overflow occurs in the FIFA memory, as compared with a case where image processing is not continued using the image data stored in a line buffer. , Provide an image processing apparatus in which the waiting time for image processing in the subsequent stage is suppressed. An image processing device includes a processor and a control unit. The control unit executes image processing by the image processing unit using the image data sent from the FIFA memory that temporarily stores the image data obtained by reading the image in pixel units, and when an overflow in the FIFA memory is detected, the image processing is performed. The input of the image data to the unit is stopped, and the image processing is executed using the image data stored in the line buffer that stores the image data in a predetermined unit. [Selection diagram] Fig. 4

Description

The present invention relates to an image processing apparatus.

Patent Document 1 describes a first-in / first-out memory provided between an image input means or an image recording means and an image compression / decompression means, and an access to the memory immediately before an overflow or underflow of the memory occurs. It is provided with an error detecting means for stopping the error detection means, and a control means for disabling the process from the middle of the line in response to the output of the error detecting means and returning to the normal processing with the end of the one line as a delimiter after the error is cleared. An image compression / decompression device characterized by the above is disclosed.

In Patent Document 2, an image in which input image data is temporarily stored and the read image data is sequentially transferred via a buffer means for outputting the stored image data only when an output request is made. The reading device has an overflow detecting means for detecting the overflow of the buffer means and an interpolation means for interpolating the target image data from the image data in the vicinity thereof, and the image lost due to the overflow of the buffer means. An image reading device is disclosed, which comprises creating and supplementing image data corresponding to the data by an interpolation means.

In Patent Document 3, a film image of a photographic film is scanned by a CCD line sensor, image data read from the CCD line sensor is transferred to an external image receiving device via a line buffer, the data receiving side becomes busy, and data is obtained. If the state where the data cannot be transferred continues, the line buffer will overflow. Therefore, the overflow detector detects the overflow, and when the overflow is detected, the writing of the image data to the line buffer is interrupted and the rescan is executed. Disclosed is an image reading device in which a communication control unit detects image data that matches the image data at the time of detection of overflow at the time of rescanning, and restarts writing of the image data to the line buffer from the detection time.

Japanese Unexamined Patent Publication No. 06-054202 Japanese Unexamined Patent Publication No. 2001-024886 Japanese Unexamined Patent Publication No. 09-252391

According to the present invention, in an image processing apparatus using a data capture function using a FIFO memory, when an overflow occurs in the FIFO memory as compared with a case where image processing is not continued using the image data stored in the line buffer. However, it is an object of the present invention to provide an image processing apparatus in which the waiting time for image processing in the subsequent stage is suppressed.

The image processing apparatus according to the first aspect includes a processor and a control unit, and the control unit uses the image data sent from the FIFA memory that temporarily stores the image data obtained by reading the image in pixel units. When an overflow in the FIFA memory is detected, the input of the image data to the image processing unit is stopped, and the image data is stored in a line buffer that stores the image data in a predetermined unit. The image processing is executed using the image data.

The image processing device according to the second aspect is the image processing device according to the first aspect, in which the control unit stops the temporary storage of the image data in the FIFA memory when the control unit detects an overflow in the FIFA memory. , The input of the image data to the image processing unit is stopped.

In the image processing device according to the third aspect, in the image processing device according to the second aspect, the image is read in line units, the predetermined unit is the line unit, and the control unit is the FIFO memory. The temporary storage of the image data in the above is stopped for one line, and after the stop for one line is completed, the image data in the predetermined unit input to the image processing unit and the line buffer are displayed. The image processing is executed using the stored image data.

The image processing apparatus according to the fourth aspect is the image processing apparatus according to the third aspect, in which the processor processes the image data stored in the line buffer within the stop period of the FIFO memory for one line. If it does not complete, error processing is executed.

In the image processing device according to any one of the first to fourth aspects, the image processing device according to the fifth aspect stores the image data for a plurality of lines in the line buffer, and the control unit is a subordinate. The image processing is executed using the pixel values of each of the plurality of lines continuous in the scanning direction.

The image processing device according to the sixth aspect transfers the image data processed by the image processing unit directly to the storage device by the memory access method in the image processing device according to any one of the first to fifth aspects. The transfer method further includes a transfer unit, and the transfer method between the FIFA memory and the image processing unit and between the image processing unit and the transfer unit is a handshake method.

According to the first aspect, in the image processing apparatus using the data capture function by the FIFO memory, the overflow occurs in the FIFO memory as compared with the case where the image processing is not continued using the image data stored in the line buffer. Even if it occurs, it is possible to provide an image processing device in which the waiting time for image processing in the subsequent stage is suppressed.

According to the second aspect, when an overflow in the FIFA memory is detected, image processing is performed by temporarily stopping the temporary storage of the image data in the FIFA memory, as compared with the case where the input of the image data to the image processing unit is directly stopped. It has the effect that the input of image data to the unit can also be stopped.

According to the third aspect, after the temporary storage of image data for two or more lines is stopped in the FIFA memory, the image data is stored in the image data of a predetermined unit input to the image processing unit and the line buffer. Compared with the case where the image processing is executed using the existing image data, it is possible to suppress a decrease in the accuracy of the image processing in the image processing unit.

According to the fourth aspect, as compared with the case where the error processing is executed when the processing of the image data stored in the line buffer is not completed within the period exceeding the stop period of the FIFO memory for one line, It has the effect of being able to quickly shift to error handling.

According to the fifth aspect, as compared with the case where the image processing unit executes image processing other than image processing using the pixel values of the plurality of lines continuous in the sub-scanning direction, the present configuration is changed to, for example, fringe processing. It has the effect of being applicable.

According to the sixth aspect, even when the communication between the respective parts connected to the subsequent stage of the FIFO memory is performed by the communication method in which the procedure is established and takes longer, the waiting time for the image processing in the subsequent stage is set. It has the effect of being able to be suppressed.

It is a block diagram which shows an example of the structure of the image processing apparatus which concerns on embodiment. It is a block diagram explaining the overflow mode of the image processing apparatus which concerns on embodiment. It is a time chart explaining the operation of each mode of the image processing apparatus which concerns on embodiment. It is a flowchart which shows the flow of overflow processing of the image processing apparatus which concerns on embodiment.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the present embodiment, the image reading unit (scanner unit) reads and acquires an image of the image processing device according to the present invention, and performs predetermined image processing on the image data transmitted to the image processing device. The form applied to the processing apparatus will be described as an example.

FIG. 1 is a block diagram showing an image processing device 10 according to the present embodiment together with a scanner unit 30 connected to the outside of the image processing device 10. As shown in FIG. 1, the image processing apparatus 10 includes an image processing unit 11, a line buffer 12, a register 13, and FIFO (First In First Out) memories 14-1, 14-2, 14-3 (in FIG. 1). , "CAP FIFO". Hereinafter, when collectively referred to, "FIFA memory 14"), LSYNC pattern detection unit 15, separation unit 16 (denoted as "MUX" in FIG. 1), input interface 17 (in FIG. 1 Includes an analog-digital conversion circuit 18 (denoted as "A / D" in FIG. 1), a tagger unit 19, a DMA (Direct Memory Access: direct memory access) unit 21, and a control unit 20 (denoted as "INF"). It is configured.

The input interface 17 is an interface for receiving image data as analog data DA sent from the scanner unit 30. The details of the input interface 17 will be described later.

The analog-digital conversion circuit 18 is a circuit that converts analog data DA into digital data DD. The analog image data from the scanner unit 30 is converted into digital image data and sent to the separation unit 16 in the subsequent stage.

The separation unit 16 separates the pixel data to be sent to the FIFO memory 14 and the LSYNC pattern data to be sent to the LSYNC pattern detection unit 15 from the digital data DD.

The FIFO memory 14 is a memory that temporarily stores (captures) pixel data sent from the separation unit 16 in pixel units. Each of the FIFO memories 14-1 and 14-2.14-3 has a capacity of several pixels. In the present embodiment, a mode using three FIFO memories 14 will be described as an example, but the number of FIFO memories 14 is not particularly limited, and for example, a mode using four or more FIFO memories may be used.

The LSYNC pattern detection unit 15 is a portion that detects a line synchronization pattern (LSYNC pattern) included in the digital data DD. The scanner unit 30 according to the present embodiment reads an image in line (line) units, and inserts a synchronization signal for identifying each line between the image data of each line as an LSYNC pattern. When the LSYNC pattern detection unit 15 detects the LSYNC pattern, it notifies the image processing unit 11 that the LSYNC pattern has been detected. The detection of the LSYNC pattern may be notified via the control unit 20.

The tagger unit 19 is a portion for assigning a tag (identifier) of 0 to 8 to the input pixel.

The image processing unit 11 is a portion that executes predetermined image processing on the image data sent from the scanner unit 30. The content of the image processing executed by the image processing unit 11 is not particularly limited, but in the present embodiment, the fringe processing is executed as an example. The “fringe process” refers to a process for correcting the deviation of the scanning positions of R, G, and B caused by scanning the image, which occurs in the scanning of the image by the scanner unit 30. The correction is performed by setting the coefficients for each of R, G, and B for the pixel values of the pixels of three lines continuous in the sub-scanning direction. A register for storing this coefficient may be provided. The image processing unit 11 usually executes the fringe processing using the image data of three lines.

The register 13 is a storage unit for parameters such as the above-mentioned coefficients that are generated in image processing in the image processing unit 11.

The line buffer 12 is a memory that stores a plurality of lines of image data transmitted from the scanner unit 30 in line units. In the present embodiment, the capacity of the line buffer 12 is set to two lines. However, the capacity of the line buffer 12 is not limited to this, and the capacity of the line buffer 12 may be a capacity of 3 lines or more.

The DMA unit 21 is a control unit for directly outputting the image data processed by the image processing device 10 to an external storage device or the like by a memory access method, and is composed of, for example, a DMA. The direct memory access method refers to transferring data directly between a memory and a memory or between a memory and an I / O (Input / Output) device without using a CPU.
The "DMA unit 21" is an example of the "transfer unit" according to the present invention.

The control unit 20 is a portion that collectively controls the entire image processing device 10, and includes a CPU, a ROM, a RAM, and the like (not shown). The control unit 20 also controls the overflow process executed in the image processing device 10. The details of overflow processing will be described later. The above "CPU" is an example of the "processor" according to the present invention.

The DDR (Double Data Rate) device 22 shown in FIG. 1 is provided outside the image processing device 10, is processed by the image processing unit 11, and is output-controlled by the DMA unit 21. This is, for example, a DDR type memory that relays data for transmission to an image processing circuit 23 or the like. The DDR method is a method in which the processing speed is increased by using both the rising and falling edges of the clock signal that controls the operation. The DDR device 22 may be accessed not only by the image processing device 10 but also by other devices, in which case a waiting list occurs.

On the other hand, the scanner unit 30 includes a CIS (Contact Image Sensor) 31 and an output interface 32 (denoted as “INF” in FIG. 1).

The CIS 31 is a close contact type image reading device, which reads an image of a document or the like arranged in the scanner unit 30, and outputs the image data obtained by reading the image data as analog data DA. The output interface 32 is an interface for transmitting the analog data DA sent from the CIS 31 to the input interface 17 of the image processing device 10 paired with the output interface 32. The method of the output interface 32 and the input interface 17 is not particularly limited, but for example, an LVDS (Low Voltage Differential Signaling) interface or the like can be used.

Next, the overall operation of the image processing device 10 will be described. First, the clock system is divided into a CLK1 system from the scanner unit 30 to the FIFO memory 14 and a CLK2 system from the FIFO memory 14 to the DMA unit 21. The CLK1 system is a clock system operated by the clock signal CLK1 generated by the scanner unit 30, and the image data acquired by the scanner unit 30 is transmitted to the image processing device 10 at a constant speed by the clock signal CLK1. There are no restrictions on data transmission at this time, so to speak, the data is transmitted in a drooling state.

On the other hand, the CLK2 system is a clock system operated by the clock signal CLK2 generated by the image processing device 10, and the image data transmitted by the CLK1 system is captured by the FIFA memory 14, and the image processing unit in the subsequent stage. It is sent to 11, and the image data processed by the image processing unit 11 is further DMA-transferred to the DDR device 22. While the CLK1 system is a drooling method, the CLK2 system transmits image data by a handshake method. The "handshake method" is a method of processing data after establishing a transmission procedure between circuits and synchronizing them. While the handshake method is a method that enables more reliable transmission of data, a standby state may occur when the transmitted data is congested. In the present embodiment, a mode in which the transfer from the FIFO memory 14 or later is performed by the handshake method will be described as an example, but the present invention is not limited to this, and other transfer methods may be used.

As described above, the CLK2 system of the image processing device 10 may be a handshake transfer, and the transfer by the DMA unit 21 may be clogged depending on the usage state of the band of the DDR device 22. If the transfer by the DMA unit 21 is clogged, the clog may propagate to the FIFA memory 14. In this case, the overflow of the FIFO memory 14 may cause an error in the image processing device 10 to stop, and restart processing may be required. When such a state occurs, for example, the start of processing of the image processing circuit 23 in the subsequent stage may be delayed, and the waiting time may increase.

Therefore, in the present embodiment, when an overflow occurs in the FIFA memory 14, the input of the image data to the image processing unit 11 is stopped, and the image processing is performed using the image data stored in the line buffer 12. I decided to continue. As a result, the occurrence of the interruption period is suppressed, so that even if an overflow occurs in the FIFO memory 14 in an image processing device using the data capture function by the FIFO memory 14, the waiting time for image processing in the subsequent stage is suppressed. The image processing device to be used is provided.

Next, the contents of the image processing executed in the image processing apparatus 10 will be described in more detail with reference to FIGS. 2 to 4. As described above, in the image processing apparatus 10 according to the present embodiment, when an overflow occurs in the FIFO memory 14, a predetermined process different from the normal image process, that is, an overflow process is performed, and the image process is performed. Avoiding interruptions.

Hereinafter, a mode in which normal image processing is executed in the image processing apparatus 10 is referred to as a “normal mode”, and a mode in which overflow processing is executed when an overflow occurs is referred to as an “overflow mode”. The detection of overflow in the FIFO memory 14 and the transition from the normal mode to the overflow mode are executed by the selector in the control unit 20.
In the normal mode, the image processing in the image processing unit 11 is executed using three lines, whereas in the overflow mode, it is executed using two lines.

When the control unit 20 detects an overflow of the FIFO memory 14 during operation in the normal mode, the control unit 20 executes the overflow process according to the following procedure.
(Procedure 1) As shown in FIG. 2, the input of the image processing unit 11 is stopped, and the capture by the FIFO memory 14 is stopped until the next line.
(Procedure 2) Clear the FIFO memory 14 so that the input is not accepted until the next line start timing. The start timing of the next line is determined by detecting the LSYNC pattern in the LSYNC pattern detection unit 15.
(Procedure 3) The fringe processing executed on 3 lines (the current 1 line input to the image processing unit 11 and the 2 lines stored in the line buffer 12) in the normal mode is saved in the line buffer 12. Execute with only 2 lines. At this time, it is necessary when shifting from fringe processing using 3 lines (hereinafter, may be referred to as "3 line processing") to fringe processing using 2 lines (hereinafter, may be referred to as "2 line processing"). The parameter of the fringe processing for the two-line processing to be used may be stored in the register 13. The parameter in this case is a coefficient for each R, G, B in the fringe processing and the like.

By the above procedure, the image processing in the image processing unit 11 can be extended to the inactive period between the lines of the image data sent from the scanner unit 30, so that the output from the image processing device 10 can be continued. .. At this time, if the processing of (Procedure 3) is not completed by the start of the next line, the conventional error processing is executed.
(Procedure 4) Return to the normal mode at the start timing of the next line. The start timing of the next line is determined by detecting the LSYNC pattern in the LSYNC pattern detection unit 15.

The operation in each mode will be described in more detail with reference to FIG. 3A and 3B are time charts showing the operation of each mode. FIG. 3A shows a time chart in a normal mode, and FIG. 3B shows a time chart in an overflow mode in the case of normal termination. FIG. 3C shows time charts of overflow modes when an error ends.

In the normal mode shown in FIG. 3A, LSYNC is detected by the LSYNC pattern detection unit 15 at time t1, and the processing of one line is completed at time t2 (the set number of pixels is completed). The period T2 from the time t1 to t2 is the valid period during which the nth line is processed, and the FIFO memory 14 is operating normally. The fringe processing at this time is a three-line processing, and the n, (n-1), and (n-2) th pixels are used. The period from time t2 to time t3 when the next LSYNC is detected (period T3) is an invalid period for waiting for the image data of the next line to be input. In the invalid period, the image processing unit 11 does not process anything in principle. Incidentally, the period until LSYNC is detected at time t1 is also an invalid period of period T1. When LSYNC is detected at time t3, the valid period (period T4) of the (n + 1) th line is started, and the image processing unit 11 uses the (n + 1), n, and (n-1) th pixels. Perform fringe processing.

Next, with reference to FIG. 3B, overflow processing in the case of normal termination will be described. This process corresponds to the case where the process of (Procedure 3) is completed by the start of the next line in the above procedure. In FIG. 3B, after the invalid period of the period T5, LSYNC was detected at time t4, and the valid period of the nth line was started, but the FIFA memory 14 overflowed at time t5. Therefore, the 3-line processing ends in the period T6 from the time t4 to t5, and the overflow processing starts from the time t5. That is, from time t5, the two-line processing is executed using the (n-1) and (n-2) th pixels without using the nth pixel. Since this two-line processing ends at time t6, the period T7 from time t5 to time t6 is the period of two-line processing. That is, in the period T7, the processing of one line is completed, and the set number of pixels is completed.

Here, the valid period in the normal mode ends at time t * (corresponding to time t2 in FIG. 3A). That is, in the overflow process, the valid period is extended to the invalid period in the normal mode as necessary. Therefore, the invalid period of the period T8 from the time t6 to t7 in the overflow mode is shorter than the invalid period in the normal mode (corresponding to the period T3 in FIG. 3A). After that, 3-line processing is started from time t7 (period T9). Originally, the (n + 1), n, and (n-1) th pixels are used for the three-line processing in the period T9 (see FIG. 3 (a)), but in this mode, the nth pixel is overflowed due to the overflow of the FIFO memory 14. Pixels have not been captured. Therefore, as shown in FIG. 3B, the nth pixel is substituted (interpolated) with the (n-1) th pixel.

Subsequently, with reference to FIG. 3C, overflow processing when an error ends will be described. This process corresponds to the case where the process of (Procedure 3) is not completed by the start of the next line in the above procedure. In FIG. 3C, LSYNC is detected at time t8 after the invalid period T10 has passed, and FIFA 14 overflows at time t9. That is, the period T11 from the time t8 to t9 is the valid period for executing the three-line processing. From time t9, the process shifts to overflow processing of two-line processing using the (n-1) and (n-2) th pixels (period T12), and LSYNC is detected at time t10. However, in this example, the two-line processing could not be completed between the times t9 and t10, that is, until the next LSYNC was detected, and the output for one line was not in time (the set number of pixels was not completed). Met). In this case, the error stop processing is started when LSYNC is detected at time t10 (period T13). In the error stop processing, for example, the image processing in the image processing unit 11 is stopped. Further, for example, a restart process may be executed.

Next, the flow of overflow processing executed in the image processing apparatus 10 according to the present embodiment will be described with reference to the flowchart shown in FIG. FIG. 4 is a flowchart showing a processing flow of an overflow processing program executed by the image processing apparatus 10. The overflow processing program is stored in a storage means such as a ROM (not shown) of the control unit 20 of the image processing device 10, and the CPU reads the overflow processing program from the storage means such as the ROM, expands it into a RAM or the like, and executes the program. .. Further, in the present embodiment, it is assumed that the scanner unit 30 has already started scanning and has started transmitting image data to the image processing device 10.

First, in step S100, reception of image data transmitted from the scanner unit 30 is started.

In step S101, it is determined whether or not the LSYNC pattern detection unit 15 has detected the LSYNC (whether or not the detection signal has been transmitted from the LSYNC pattern detection unit 15). In step S101, the process waits until LSYNC is detected, and when LSYNC is detected, the process proceeds to step S102.

In step S102, the capture by the FIFA memory 14 is started.

In step S103, it is determined whether or not an overflow has occurred in the FIFA memory 14. If the determination is affirmative, the process proceeds to step S106, and if the determination is negative, the process proceeds to step S104.

In step S104, it is determined whether or not the processing of the image data for one line is completed. If the determination is negative, the process returns to step S103 and continues to detect the overflow of the FIFO memory 14. On the other hand, if a positive determination is made, the process proceeds to step S105.

In step S105, it is determined whether or not the processing of all lines is completed. If the determination is negative, the process returns to step S101 to continue the detection of LSYNC. On the other hand, if the determination is affirmative, the overflow processing program is terminated. Here, in the present embodiment, since the overflow process is executed on a page-by-page basis as an example, the entire line means the entire line within one page. In the present embodiment, a mode in which the overflow processing is executed on a page-by-page basis will be described as an example, but the present embodiment is not limited to this, and may be, for example, a mode in which the overflow processing is executed on a job (processing) unit.

In step S106, in response to the overflow of the FIFO memory 14, the mode shifts to the overflow mode. That is, the input to the image processing unit 11 is stopped, and the capture operation of the FIFO memory 14 is stopped.

In step S107, the processing parameters of the image processing in the image processing unit 11 are changed.
That is, the parameters such as the coefficient are changed according to the change from the 3-line processing to the 2-line processing. At this time, the parameters in the two-line processing may be stored in the register 13.

In step S108, the input of the image processing unit 11 is changed to the image data stored in the line buffer.

In step S109, it is determined whether or not LSYNC has been detected. If the determination is affirmative, the process proceeds to step S112, while if the determination is negative, the process proceeds to step S110.

In step S110, it is determined whether or not one line has been completed, and if the determination is negative, the process returns to step S109 to continue the detection of LSYNC, and if the determination is positive, the process proceeds to step S111. If the determination is affirmative in step S110, it corresponds to the overflow mode of normal termination shown in FIG. 3B, and if the determination is negative, it corresponds to the overflow mode of error termination shown in FIG. 3C.

In step S111, the processing in the image processing unit 11 is returned to the normal processing. That is, it is changed to return to the normal mode and execute the 3-line processing. After that, the process proceeds to step S105.

In step S112, in response to the failure to complete the two-line processing during one line, error processing is executed, and in subsequent step S113, restart processing is executed to end the overflow processing program. The restart processing in step S113 may be performed as needed, and the overflow processing program may be terminated only by executing the error processing in step S112.

In the above embodiment, a mode in which the capacity of the line buffer 12 is provided with a capacity of two lines has been described as an example. It may be in the form of having a capacity for one line, or generally N (integer of ≧ 3) lines. When the line buffer 12 has a capacity of N lines, overflow processing can be performed in the period of (N-1) lines.

Further, in the above embodiment, the fringe processing has been described as an example of the image processing in the image processing apparatus 10, but the present invention is not limited to this, and may be applied to other image processing using the line buffer 12. At this time, if the image processing is performed on a plurality of lines continuous in the sub-scanning direction, the effect of the present embodiment is more exhibited.

Further, in the above embodiment, the line buffer 12 has been described as an example as a storage unit connected to the image processing unit 11, but the present invention is not limited to this, and generally, image data in a predetermined unit (for example, a page unit) is described. It may be used as a storage unit for storing.

In the above embodiment, the processor refers to a processor in a broad sense, such as a general-purpose processor (for example, CPU: Central Processing Unit, etc.) or a dedicated processor (for example, GPU: Graphics Processing Unit, ASIC: Application Specific Integrated Circuit, etc.). FPGA: Includes Field Programmable Gate Array, programmable logic device, etc.). Further, the operation of the processor in the above embodiment may be performed not only by one processor but also by a plurality of processors existing at physically separated positions in cooperation with each other. Further, the order of each operation of the processor is not limited to the order described in the above-described embodiment, and may be changed as appropriate.

10 Image processing device 11 Image processing unit 12 Line buffer 13 Register 14, 14-1, 14-2, 14-3 FIFO memory 15 LSYNC pattern detection unit 16 Separation unit 17 Input interface 18 Analog-digital conversion circuit 19 Tagger unit 20 Control unit 21 DMA section 22 DDR device 23 Image processing circuit 30 Scanner section 31 CIS
32 Output interface CLK1, CLK2 Clock signal DA Analog data DD Digital data T1 to T13 Period t1 to t11 Time

Claims (6)

Equipped with a processor and a control unit
When the control unit executes image processing by the image processing unit using the image data sent from the FIFA memory that temporarily stores the image data obtained by reading the image in pixel units, and detects an overflow in the FIFA memory. An image processing apparatus that stops the input of the image data to the image processing unit and executes the image processing using the image data stored in the line buffer that stores the image data in a predetermined unit. .. The first aspect of claim 1, wherein when the control unit detects an overflow in the FIFO memory, the temporary storage of the image data in the FIFO memory is stopped and the input of the image data to the image processing unit is stopped. Image processing equipment. The image is read line by line
The predetermined unit is the line unit.
The control unit temporarily stops the temporary storage of the image data in the FIFO memory for one line, and at the same time,
After the stop for one line is completed, the image processing is executed using the image data of the predetermined unit input to the image processing unit and the image data stored in the line buffer. The image processing apparatus according to claim 2. The image processing apparatus according to claim 3, wherein the processor executes error processing when the processing of the image data stored in the line buffer is not completed within the stop period of the FIFA memory for one line. .. The line buffer stores the image data for a plurality of lines and stores the image data.
The image processing apparatus according to any one of claims 1 to 4, wherein the control unit executes the image processing using the pixel values of the plurality of lines continuous in the sub-scanning direction. Further including a transfer unit that directly transfers the image data processed by the image processing unit to the storage device by the memory access method.
The image processing according to any one of claims 1 to 5, wherein the transfer method between the FIFO memory and the image processing unit and between the image processing unit and the transfer unit is a handshake method. apparatus.

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