JP2021082199A - Storage control device, method for controlling the same, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage control device capable of maintaining the performance of a write process according to a write request received during execution of a rebuild process.
A bridge IC 105 performs a rebuild process of replicating one or more data stored in one of a storage 111 and a storage 115 connected to the bridge IC 105 to the other. The bridge IC 105 converts the write command received during the execution of the rebuild process into a command that does not retain data in the cache memory.
[Selection diagram] Fig. 5

Description

The present invention relates to a storage control device, a control method thereof, and a program.

An image forming apparatus having a plurality of storages is known. The image forming apparatus performs mirroring (RAID1) for storing the same data in two storages connected to the storage control device of the image forming apparatus in order to improve the fault tolerance. When data identity is broken between two storages in mirroring, the storage controller performs a rebuild process that replicates one or more data stored in the normally operating storage to the other storage (eg,). , Patent Document 1). In the rebuild process, the data read from the copy source storage is first temporarily held in the volatile cache memory in the copy destination storage, and then at an arbitrary timing, the non-volatile recording medium in the copy destination storage. Written in. On the other hand, the storage control device can accept a write request not related to the rebuild process (hereinafter, referred to as “rebuild-unrelated write request”) while the rebuild process is being executed. At this time, in the storage of the duplication destination, the data corresponding to the write request unrelated to rebuild is held in the cache memory together with the data read from the storage of the duplication source.

The storage controller sends a write command corresponding to the rebuild unrelated write request to the storage, and then sends a cache flush command to record the data corresponding to the rebuild unrelated write request held in the cache memory. Instruct to write to the medium. The storage writes all the data held in the cache memory to the recording medium according to the received cache flush command. When the storage control device confirms that the cache flush is completed, it instructs the storage to execute the next write process.

Japanese Unexamined Patent Publication No. 2016-139251

However, if the write process is executed according to the rebuild unrelated write request received while the rebuild process is being executed, in the copy destination storage, in addition to the data corresponding to the rebuild unrelated write request, the rebuild process is performed. Data is held in the cache memory. In such a case, the storage control device executes the next write process unless it completes writing not only the data corresponding to the rebuild unrelated write request but also all the data held in the cache memory to the recording medium. I can't tell. That is, conventionally, the performance of the write process according to the rebuild unrelated write request received during the execution of the rebuild process is deteriorated.

An object of the present invention is to provide a storage control device, a control method thereof, and a program capable of maintaining the performance of write processing according to a write request received while executing rebuild processing.

In order to achieve the above object, the storage control device of the present invention is a storage control device that controls storage of data in a plurality of storages including holding means and a non-volatile recording medium, and is one of the plurality of storages. A control means for controlling the execution of a rebuild process for replicating the data stored in the storage to another storage, and a receiving means for receiving a write command including an instruction to write the data held in the holding means to the recording medium. A conversion means for converting a write command received during execution of the rebuild process into a write command without holding the data in the holding means, and a plurality of storages for the converted write command. It is characterized by including a transmission means for transmitting to.

According to the present invention, it is possible to maintain the performance of the write process according to the write request received during the execution of the rebuild process.

It is a block diagram which shows typically the structure of the image forming apparatus which includes the bridge IC as the storage control apparatus which concerns on embodiment of this invention. It is a state transition diagram of the bridge IC of FIG. It is a flowchart which shows the procedure of the rebuild control processing executed by the bridge IC of FIG. It is a flowchart which shows the procedure of the conventional access control processing. It is a flowchart which shows the procedure of access control processing in this embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram schematically showing a configuration of an image forming apparatus 100 including a bridge IC 105 as a storage control apparatus according to an embodiment of the present invention. In FIG. 1, the image forming apparatus 100 includes a controller 101, a reader unit 119, and a printer unit 120. The controller 101 is connected to the reader unit 119 and the printer unit 120. Further, the controller 101 includes a host CPU 102, a host ROM 103, a host RAM 104, a bridge IC 105, a storage 111, and a storage 115.

The host CPU 102 is a central processing unit that controls the entire controller 101. The host CPU 102 is connected to the host ROM 103 and the host RAM 104 via a memory bus (not shown). Further, the host CPU 102 is connected to the bridge IC 105 via a SATA communication line (not shown). The host ROM 103 is a non-volatile storage device and stores setting data, programs, and the like. The host ROM 103 stores, for example, a firmware module for operating the host CPU 102. The data stored in the host ROM 103 is expanded in the host RAM 104 as a temporary storage area.

The bridge IC 105 includes a bridge CPU 106, a bridge ROM 107, a bridge RAM 108, and a bridge buffer 110. The host CPU 102 is connected to the connector D of the bridge IC 105, the storage 111 is connected to the connector H1 of the bridge IC 105, and the storage 115 is connected to the connector H2 of the bridge IC 105. In the present embodiment, as an example, a configuration including two connectors for connecting the storage will be described, but the present invention is not limited to this configuration, and a configuration including three or more connectors may be used.

The bridge IC 105 controls to read data from the connected storage 111 or 115 according to a read command received from the host CPU 102. Further, the bridge IC 105 controls to write data to the storage 111 or the storage 115 according to the write command received from the host CPU 102. The bridge IC 105 includes a mirroring control function that controls storage of the same data in a plurality of connected storages. The bridge CPU 106 is a central processing unit that controls the entire bridge IC 105. The bridge CPU 106 can operate independently of other devices in the controller 101. The bridge CPU 106 is connected to the bridge ROM 107 and the bridge RAM 108 via an internal bus (not shown). The bridge ROM 107 is a non-volatile storage device. The data stored in the bridge ROM 107 is expanded in the bridge RAM 108 as a temporary storage area. The bridge ROM 107 stores, for example, a firmware module for operating the bridge CPU 106 and a rebuild table 109.

The rebuild table 109 is data for managing the execution status of the rebuild process for replicating one or more data stored in one of the storage 111 and the storage 115 connected to the bridge IC 105 to the other. In the rebuild table 109, the implementation status setting values for each sector of the storage of the replication source are set in the rebuild process. Here, the storage of the duplication source is called a master storage, and the storage of the duplication destination is called a slave storage. For example, in the rebuild table 109, "1" indicating that the data duplication is completed is set as the implementation status setting value for the LBA indicating the sector that has completed the data duplication. Further, "0" indicating that the data duplication is not completed is set as the implementation status setting value for the LBA indicating the sector that has not completed the data duplication. LBA is a value indicating the number of sectors based on the first sector in the master storage. For example, when the implementation status setting value corresponding to the maximum LBA in the rebuild table 109 is "1", it means that all the data stored in the master storage has been duplicated in the slave storage, that is, the rebuild process has been completed. .. In the following, the LBA value is referred to as “a” and the implementation status setting value is referred to as TABLE (a). The bridge buffer 110 is used to temporarily hold the data when the bridge CPU 106 transmits / receives data to / from the host CPU 102, the storage 111, and the storage 115.

The storage 111 is a non-volatile storage device, and includes a CPU A112, a cache memory A113, and a recording medium A114. The CPUA 112 is an arithmetic unit that controls the entire storage 111, and is operated by a unique firmware stored in a non-volatile storage device (not shown). The cache memory A113 is a volatile memory. The cache memory A113 is a temporary storage area used for efficiently performing these processes when the CPU A112 writes data to the recording medium A114 or when the CPU A112 reads data from the recording medium A114. The recording medium A114 is a non-volatile recording medium. In the storage 111, for example, the data received from the bridge IC 105 is held in the cache memory A113, and the held data is written to the recording medium A114 at a predetermined timing. As a result, even if the supply of electric power to the storage 111 is stopped, the data received from the bridge IC 105 can be retained.

The storage 115 has the same function and configuration as the storage 111, and includes a CPU B116, a cache memory B117, and a recording medium B118. CPUB116 has the same function and configuration as CPUA112. The cache memory B117 has the same function and configuration as the cache memory A113. The recording medium B118 has the same function and configuration as the recording medium A114. In the storage 115 as well, for example, the data received from the bridge IC 105 is held in the cache memory B117, and the held data is written to the recording medium B118 at a predetermined timing, as in the storage 111.

The reader unit 119 reads the arranged document, generates the image data of the scanned document, and transmits the image data to the controller 101 according to the instruction from the controller 101. The printer unit 120 prints the image data on the paper according to the instruction from the controller 101.

FIG. 2 is a state transition diagram of the bridge IC 105 of FIG. The bridge IC 105 has two modes of operation, specifically a single mode and a mirroring mode.

The single mode is an operation mode in which only one of the storage 111 and the storage 115 operates. The mirroring mode is an operation mode in which the bridge IC 105 operates in a state of being connected to two storages, such as the storage 111 and the storage 115. There are four states in the mirroring mode: mirror state, degraded state, rebuild state, and held state.

The mirror state is a state in which the two storages are operating normally. In the mirror state, when reading data, the bridge IC 105 accesses the storage set as the master storage of the two storages. On the other hand, when writing data, the bridge IC 105 accesses both of the two storages and causes the two storages to write the same data. If one of the two storages fails in the mirror state, the bridge IC 105 transitions to the degraded state. Further, the bridge IC 105 transitions from the mirror state to the rebuild state according to the instruction from the bridge CPU 106.

The degraded state is a state in which the non-failed storage of the two storages is operating. In the degraded state, the bridge IC 105 does not access the failed storage. The image forming apparatus 100 of the present embodiment includes an automatic rebuild function that executes a rebuild process when a predetermined condition is satisfied. When the automatic rebuild function is set to ON, when a new storage alternative to the failed storage is connected to the bridge IC 105 that has transitioned to the degraded state, the bridge IC 105 transitions to the rebuild state. On the other hand, when the automatic rebuild function is set to OFF, the bridge IC 105 does not transition to the rebuild state even if a new storage alternative to the failed storage is connected to the bridge IC 105 that has transitioned to the degraded state. In this case, the bridge IC 105 transitions from the degraded state to the rebuild state according to the instruction from the bridge CPU 106. In the degraded state, when the storage that has not failed also fails, the bridge IC 105 transitions to the held state.

The rebuild state is a state in which the non-failed storage of the two storages is operating. In the rebuild state, the bridge IC 105 executes a rebuild process and replicates data from the non-failed storage to the connected new storage in place of the failed storage. In the rebuild state, when the slave storage, which is the storage of the replication destination, fails, the bridge IC 105 transitions to the degraded state. Further, in the rebuild state, if the master storage fails, the bridge IC 105 transitions to the held state. When the rebuild process is completed, the bridge IC 105 transitions from the rebuild state to the mirror state. The halt state is a state in which mirroring cannot be continued because both of the two storages have failed.

The image forming apparatus 100 of the present embodiment has an initial rebuild function that executes a rebuild process when the mirroring mode is entered. When the user instructs the user to shift from the single mode to the mirroring mode while the initial rebuild function is set to ON, the bridge IC 105 transitions to the rebuild state and executes the rebuild process. On the other hand, when the user instructs the transition from the single mode to the mirroring mode with the initial rebuild function set to OFF, the bridge IC 105 transitions to the mirror state. In the present embodiment, the bridge IC 105 shifts to the single mode when the user receives an instruction to shift to the single mode in any of the above-described states in the mirroring mode.

FIG. 3 is a flowchart showing the procedure of the rebuild control process executed by the bridge IC 105 of FIG. The process of FIG. 3 is realized by the bridge CPU 106 executing the program stored in the bridge ROM 107. The process of FIG. 3 is executed when the bridge IC 105 transitions to the rebuild state. In the process of FIG. 3, as an example, one of the storage 111 and the storage 115 functions as the master storage, and the other functions as the slave storage.

In FIG. 3, the bridge CPU 106 acquires the minimum LBA and the maximum LBA in each of the storage 111 and the storage 115 by using the intelligent-device command or the like in order to specify the storage area to be executed by the rebuild control process. Next, the bridge CPU 106 substitutes the acquired minimum LBA into the variable a (step S301) and substitutes the maximum LBA into the variable e (step S302). Next, the bridge CPU 106 reads the TABLE (a), which is the implementation status setting value of the minimum LBA, from the rebuild table 109 (step S303), and determines whether or not the TABLE (a) is "0" (step S304). ..

As a result of the determination in step S304, when TABLE (a) is "1", the process of replicating the data stored in the sector indicated by the minimum LBA in the master storage to the slave storage is completed. At this time, the bridge CPU 106 performs the process of step S308 described later. As a result of the determination in step S304, when TABLE (a) is "0", the duplication of the minimum LBA data has not been completed. At this time, the bridge CPU 106 instructs the master storage to read the data stored in the sector indicated by the LBA (a), and saves the read data in the bridge buffer 110 (step S305). Next, the bridge CPU 106 reads the data stored in the bridge buffer 110, and instructs the slave storage to write the read data to the sector indicated by the LBA (a) of the slave storage (step S306). When the writing to the sector indicated by the LBA (a) of the slave storage is completed, the bridge CPU 106 substitutes “1” indicating that fact into the TABLE (a) of the rebuild table 109 (step S307). The bridge CPU 106 then adds "1" to the variable a to process the next LBA (step S308). Next, the bridge CPU 106 determines whether the variable a to which "1" is added (hereinafter, referred to as "added variable a") is the variable e, that is, whether or not the maximum LBA has been reached (step). S309).

As a result of the determination in step S309, when the added variable a has not reached the variable e, the duplication of some LBA data has not been completed, that is, the rebuild process has not been completed, so that the bridge CPU 106 has not completed. The process returns to step S303. As a result of the determination in step S309, when the added variable a reaches the variable e, the duplication of all LBA data has been completed, that is, the rebuild process has been completed. End the process.

Next, processing when the bridge IC 105 in the rebuild state receives a read command or a write command from the host CPU 102 will be described.

FIG. 4 is a flowchart showing a conventional access control processing procedure. The process of FIG. 4 is realized by the bridge CPU 106 executing the program stored in the bridge ROM 107. The process of FIG. 4 is executed when the bridge IC 105 transitions to the rebuild state. In the rebuild state, the rebuild process is executed, and for example, the data sequentially read from the master storage is written and held in the cache memory of the slave storage. In the process of FIG. 4, as in the process of FIG. 3, as an example, one of the storage 111 and the storage 115 functions as the master storage, and the other functions as the slave storage.

In FIG. 4, when the bridge CPU 106 receives a command from the host CPU 102 (YES in step S401), the bridge CPU 106 determines whether the received command is a read command or a write command (step S402).

As a result of the determination in step S402, when the received command is a read command, the bridge CPU 106 transfers the received command to the master storage (step S403). The master storage interrupts the process related to data duplication in the rebuild process being executed, and performs the read process according to the received command. The master storage outputs the data corresponding to the received command to the bridge CPU 106. The bridge CPU 106 transfers the data received from the master storage to the host CPU 102 (step S404), and performs the process of step S406 described later.

As a result of the determination in step S402, when the received command is a write command, the bridge CPU 106 transfers the data to be written and the received command to the master storage and the slave storage (step S405). The master storage and the slave storage interrupt the process related to data duplication in the rebuild process being executed, and perform the write process according to the received command. For example, when the received command is a cache flush command, each storage holds the data to be written in the cache memory, and then writes all the data held in the cache memory to the recording medium according to the received cache flush command. When the writing process is completed, each storage sends a notification to that effect to the bridge CPU 106. Upon receiving this notification, the bridge CPU 106 notifies the host CPU 102 of the completion of the process according to the received command (step S406), resumes the interrupted process related to the duplication of the data, and returns to the process of step S401. ..

As described above, in the rebuild state, the rebuild process is executed, and the data sequentially read from the master storage is written and held in the cache memory of the slave storage. When the write process is executed according to the write command received during the rebuild state, the slave storage holds the data related to the rebuild process in the cache memory in addition to the data to be written. In such a case, the bridge IC 105 cannot instruct the execution of the next writing process unless the writing of not only the data to be written but also all the data held in the cache memory of the slave storage to the recording medium is completed. That is, the performance of the write process according to the write command received during the rebuild state deteriorates.

On the other hand, in the present embodiment, the write command received during the execution of the rebuild process is converted into a command that does not retain the data in the cache memory.

FIG. 5 is a flowchart showing the procedure of access control processing in the present embodiment. The process of FIG. 5 is also realized by the bridge CPU 106 executing the program stored in the bridge ROM 107. The process of FIG. 5 is also executed when the bridge IC 105 transitions to the rebuild state. In the process of FIG. 5, as in the process of FIG. 3, as an example, one of the storage 111 and the storage 115 functions as the master storage, and the other functions as the slave storage.

In FIG. 5, the bridge CPU 106 performs the processes of steps S401 and S402. As a result of the determination in step S402, when the received command is a read command, the bridge CPU 106 performs the processes after step S403. As a result of the determination in step S402, when the received command is a write command, the bridge CPU 106 temporarily stores the received command, the write target data, and the LBA indicating the sector for storing the write target data in the bridge buffer 110. (Step S501). Next, the bridge CPU 106 selects a write command that does not involve holding data in the cache memory from the known SATA specifications (step S502). For example, when the command received in step S401 is Write_DMA, Write_DMA_FUA is selected. Write_DMA_FUA is a command that gives an instruction to write directly to a recording medium without holding data in a cache memory. Next, the bridge CPU 106 converts the command stored in the bridge buffer 110 into the command selected in step S502 (step S503). In step S503, only the command is converted, and the write target data and the LBA indicating the sector storing the write target data are maintained as the contents received in step S401 without being converted. Next, the bridge CPU 106 transfers the command converted in step S503 to the master storage and the slave storage (step S504). Each storage interrupts the process related to data duplication in the rebuild process being executed, and performs the write process according to the received command. For example, each storage writes directly to the recording medium according to the received Write_DMA_FUA without holding the data to be written in the cache memory. When the writing process is completed, each storage sends a notification to that effect to the bridge CPU 106. Next, the bridge CPU 106 performs the process of step S406.

According to the above-described embodiment, the write command received during the execution of the rebuild process is converted into a command that does not retain data in the cache memory. As a result, when the write process according to the write command received during the rebuild process is executed, the next step is performed without waiting for all the data held in the cache memory to be written to the recording medium. It is possible to instruct the execution of the writing process of. As a result, the performance of the write process according to the write command received during the rebuild process can be maintained.

Further, in the above-described embodiment, the bridge IC 105 includes a mirroring control function that controls storage of the same data in two connected storages. As a result, it is possible to maintain the performance of the write process accompanied by mirroring according to the write command received while the rebuild process is being executed.

Further, in the above-described embodiment, the write command that does not involve holding the data in the cache memory is a command that gives an instruction to write directly to the recording medium without holding the data in the cache memory. As a result, it is possible to maintain the performance of the write process according to the write command received during the rebuild process, and retain the data even if the power supply to the storage is stopped.

Although the present invention has been described above with reference to the above-described embodiments, the present invention is not limited to the above-described embodiments. For example, three or more storages may be connected to the bridge IC 105, and the present invention may be applied to a configuration in which mirroring is performed with the three or more connected storages.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device read the program. It can also be realized by the processing to be executed. The present invention can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

105 Bridge IC
106 bridge CPU
111, 115 Storage 113 Cache memory A
114 Recording medium A
117 cache memory B
118 Recording medium B

Claims (5)

A storage control device that controls storage of data in a plurality of storages including a holding means and a non-volatile recording medium.
A control means for controlling the execution of a rebuild process that replicates the data stored in one storage in the plurality of storages to another storage,
A receiving means for receiving a write command including an instruction to write the data held by the holding means to the recording medium, and a receiving means.
A conversion means for converting a write command received during execution of the rebuild process into a write command that does not involve holding the data in the holding means, and a conversion means.
A storage control device including a transmission means for transmitting the converted write command to the plurality of storages. The storage control device according to claim 1, further comprising a mirroring control function that controls storage of the same data in the plurality of storages. Claim 1 or 2 is characterized in that the write command without holding the data in the holding means is a command for instructing the holding means to directly write the data without holding the data in the holding means. The storage controller described. A control method for a storage control device that controls storage of data in a plurality of storages including a holding means and a non-volatile recording medium.
A control step that controls execution of a rebuild process that replicates data stored in one storage in the plurality of storages to another storage, and
A receiving step of receiving a write command including an instruction to write the data held by the holding means to the recording medium, and
A conversion step of converting a write command received while executing the rebuild process into a write command that does not involve holding the data in the holding means, and a conversion step.
A control method of a storage control device, which comprises a transmission step of transmitting the converted write command to the plurality of storages. A program that causes a computer to execute a control method of a storage control device that controls storage of data in a plurality of storages including a holding means and a non-volatile recording medium.
The control method of the storage control device is
A control step that controls execution of a rebuild process that replicates data stored in one storage in the plurality of storages to another storage, and
A receiving step of receiving a write command including an instruction to write the data held by the holding means to the recording medium, and
A conversion step of converting a write command received while executing the rebuild process into a write command that does not involve holding the data in the holding means, and a conversion step.
A program comprising a transmission step of transmitting the converted write command to the plurality of storages.

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