JP2021064761A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of optimizing a joint portion and improving the adhesion of a sealing resin. SOLUTION: A semiconductor device is a sealing resin that covers a semiconductor element and covers at least a part of a base material and a lead, and on a bonding surface of the surface of the base material that is bonded by the semiconductor element and the bonding portion. The first roughening plating is arranged on the surface of at least a part of the surface along the sealing resin of the base material, and the second roughening plating is provided. The first roughened plating has a larger surface roughness than the second roughened plating. [Selection diagram] Fig. 1

Description

The present invention relates to a semiconductor device for joining a semiconductor element to a base material, and a method for manufacturing the same.

Conventionally, in semiconductor devices used at high frequencies, it has been common to mount semiconductor elements directly on a circuit board or a housing by screwing or the like. However, in order to improve productivity and eliminate damage caused by stress during screwing, there is an increasing need for automatic mounting using reflow.

In reflow mounting, for example, semiconductor devices are soldered to circuit boards and enclosures with Pb-free solder. At this time, since not only the Pb-free solder but also the sealing resin is melted at 300 ° C. or higher, there is a concern that the mechanical properties may be deteriorated due to the decomposition of the sealing resin. In addition, since the adhesive strength tends to decrease at high temperatures, there is a concern that the sealing resin may peel off from the lead or heat sink.

As one of the countermeasures against such a problem, it has been proposed to apply a primer resin having a high glass transition temperature between the sealing resin and the semiconductor element, the wire, the lead, and the heat sink (for example, a patent). Document 1). According to such a configuration, deterioration of adhesive force and mechanical properties can be suppressed even at the temperature at the time of reflow mounting, so that reliability at a high temperature can be ensured.

Japanese Unexamined Patent Publication No. 2015-164165

However, according to the configuration using a primer resin having a high glass transition temperature, although heat resistance higher than the reflow temperature can be obtained, the water absorption rate is higher than that of a general sealing resin, so that it is transported or stored during production. Occasionally, the absorbed water may volatilize when the reflow is mounted. Due to the volatile expansion stress, the primer resin and the sealing resin covering the primer resin may be peeled off from the reed or the heat sink. Further, there is a problem that a relatively large number of cracks are present at the joint portion that joins the semiconductor element and the heat sink.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of optimizing the joint portion and improving the adhesion of the sealing resin.

The semiconductor device according to the present invention includes a semiconductor element, a base material to be bonded to the semiconductor element, a joint portion containing a metal sintered material for bonding the semiconductor element and the base material, and the semiconductor element and electricity. By a lead that is specifically connected, a sealing resin that covers the semiconductor element and at least a part of the base material and the lead, and a joint portion between the semiconductor element and the joint portion of the surface of the base material. A first roughening plating disposed on the bonding surface to be bonded and a second roughening plating disposed on at least a part of the surface of the base material along the sealing resin are provided. The surface roughness of the first roughened plating is larger than that of the second roughened plating.

According to the present invention, the first roughened plating having a surface roughness larger than that of the second roughened plating is arranged on the joint surface of the base material which is joined by the semiconductor element and the joint portion. 2 Roughening plating is disposed on at least a part of the surface along the sealing resin of the base material. According to such a configuration, the joint portion can be made appropriate, and the adhesion of the sealing resin can be improved.

It is a top view which shows the schematic structure of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the schematic structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a top view which shows the schematic structure which removed the sealing resin from the semiconductor device which concerns on Embodiment 1. FIG. It is a top view which shows the roughened plating which concerns on Embodiment 1. FIG. It is a cross-sectional view which expanded the part B of FIG. It is a cross-sectional view which expanded the part C of FIG. It is a cross-sectional view which expanded the part D of FIG. It is an enlarged view which shows the joint part of the contrast semiconductor device. It is an enlarged view which shows the joint part of the semiconductor device which concerns on Embodiment 1. FIG. It is a top view which shows the roughened plating which concerns on Embodiment 2. It is a top view which shows the roughened plating which concerns on Embodiment 2. It is a top view which shows the roughened plating which concerns on Embodiment 2. It is a top view which shows the roughened plating which concerns on Embodiment 2. It is a flowchart which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3. It is a top view which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3. FIG. It is a top view which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3. FIG.

Hereinafter, embodiments will be described with reference to the attached drawings. The features described in each of the following embodiments are exemplary, and not all features are required. Further, in the description shown below, similar components are designated by the same or similar reference numerals in a plurality of embodiments, and different components will be mainly described. In addition, in the description described below, specific positions and directions such as "top", "bottom", "left", "right", "front" or "back" are directions when they are actually carried out. Does not have to match.

<Embodiment 1>
FIG. 1 is a plan view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the schematic configuration along the line AA of FIG. As shown in FIGS. 1 and 2, the semiconductor device according to the first embodiment includes a sealing resin 5. FIG. 3 is a plan view showing a schematic configuration of the semiconductor device from which the sealing resin 5 has been removed.

As shown in FIG. 2, in the semiconductor device according to the first embodiment, in addition to the sealing resin 5, the semiconductor element 1, the circuit board 2, the bonding wire 3, the lead 4, the bonding portion 12, and the metal The sintered material coating 13, the heat sink 21, and the roughened plating 22 are provided.

The semiconductor element 1 contains, for example, Si (silicon), and is at least one of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), SBD (Schottky Barrier Diode), and PND (PN junction diode). Includes one or one. The semiconductor element 1 is, for example, a semiconductor element for high-frequency communication used for mobile communication and disaster prevention radio. An Au (gold) electrode may be provided on the back surface of the semiconductor element 1 (the lower surface of FIG. 2).

The circuit board 2 is electrically connected to the semiconductor element 1 by, for example, a bonding wire 3. The circuit board 2 includes, for example, a MIC (Microwave Integrated Circuit) substrate for matching high frequency characteristics in a semiconductor device for high frequency communication.

The Cu heat sink 21, which is the base material, is joined to the semiconductor element 1 and the circuit board 2. The joining portion 12 joins the semiconductor element 1 and the circuit board 2 to the heat sink 21. The joint portion 12 includes, for example, a metal sintered material such as an Ag sintered material obtained by sintering a metal sintered material paste of Ag (silver).

The metal sintered material coating 13 contains the same metal sintered material as the joint portion 12, and is continuous with the joint portion 12. The thickness of the metal sintered material coating 13 is thinner than the thickness of the joint portion 12.

The reed 4 is electrically connected to the electrode pattern of the semiconductor element 1 and the circuit board 2 by, for example, a bonding wire 3. The portion of the lead 4 that is not covered by the sealing resin 5 is connected to an external substrate (not shown), and the external substrate is electrically connected to the semiconductor element 1 and the circuit board 2.

The sealing resin 5 covers the semiconductor element 1 and the circuit board 2, and covers at least a part of the heat sink 21 and the reed 4. As a result, the semiconductor element 1 and the circuit board 2 are isolated from the influences of external moisture, pollution, heat, electromagnetic field, etc., and their insulating properties are ensured. The sealing resin 5 is formed by, for example, transfer molding an epoxy resin, and the water absorption rate of the sealing resin 5 thus formed is 0.5% or less. By making the water absorption rate of the sealing resin 5 relatively low in this way, it is possible to suppress mold peeling during substrate mounting.

The first roughening plating 22L and the second roughening plating 22S are arranged as the roughening plating 22 on the surfaces of at least a part of the heat sink 21 and the lead 4. FIG. 4 is a plan view showing the roughened plating 22 (first roughened plating 22L and second roughened plating 22S) in the configuration of FIG. FIG. 5 is an enlarged view of a portion B of FIG. 2, FIG. 6 is an enlarged view of a portion C of FIG. 2, and FIG. 7 is an enlarged view of a portion D of FIG.

The surface roughness of the first roughened plating 22L shown in FIGS. 5 and 6 is larger than that of the second roughened plating 22S shown in FIG. 7.

As shown in FIGS. 2, 4 to 6, the first roughened plating 22L is arranged on the bonding surface of the surface of the heat sink 21 which is bonded by the semiconductor element 1 and the bonding portion 12. In the first embodiment, the first roughened plating 22L is mounted on the semiconductor element 1 not only on the bonding surface but also on the surface of the heat sink 21 in a plan view, adjacent to the bonding surface and outside the semiconductor element 1. It is also arranged on an adjacent surface adjacent to the outer peripheral portion of the. However, it is not essential that the first roughened plating 22L is arranged on the adjacent surface. Further, in the first embodiment, the first roughened plating 22L is arranged on the circuit board 2 in the same manner as the above-mentioned arrangement for the semiconductor element 1, but as will be described in a modified example described later. This is not mandatory.

As shown in FIGS. 2, 4 and 7, the second roughened plating 22S has at least one of a surface of the heat sink 21 along the sealing resin 5 and a surface of the reed 4 along the sealing resin 5. It is arranged on the surface of the portion. In FIG. 2, the second roughening plating 22S is not arranged on the portion of the heat sink 21 exposed from the sealing resin 5, but the second roughening plating 22S may be arranged on the portion. Good. Further, in FIG. 2, the second roughened plating 22S is disposed on the portion of the reed 4 exposed from the sealing resin 5, but the second roughened plating 22S is not disposed on the portion. Alternatively, the second roughening plating 22S may not be arranged on all the leads 4.

According to such roughening plating 22 (first roughening plating 22L and second roughening plating 22S), it is possible to increase the density of the joint portion 12 of the B portion of FIG. 2 and the C portion of FIG. The metal sintered material coating 13 of the above can be formed. This will be described in detail in the third embodiment, which is the method for manufacturing the semiconductor device according to the first embodiment, and will be briefly described here.

A metal sintered material paste containing metal particles as a raw material for the joint portion 12 and a solvent for increasing the fluidity of the metal particles is applied onto the first roughened plating 22L. A part of the applied metal sintered material paste seeps out in a plan view due to the surface tension of the unevenness of the first roughened plating 22L. At this time, since the metal particles have a lower fluidity than the solvent, the solvent is mainly leached as the leaching of the metal sintered material paste, and a small amount of metal particles are leached with the leaching of the solvent.

As a result, in the portion where the metal sintered material paste is first applied, the gap between the remaining metal particles is reduced and the viscosity of the remaining metal particles is increased by reducing the solvent. On the other hand, in the portion where the metal sintered material paste has leached, a small amount of metal particles will be present.

When the metal sintered material paste is heated in such a state, the metal particles in the portion where the metal sintered material paste is first applied are subjected to a high density and relatively thick joint portion 12 as shown in FIG. Is formed. On the other hand, as shown in FIGS. 5 and 6, a relatively thin metal sintered material coating 13 is formed from the metal particles in the portion where the metal sintered material paste has leached. Although the joint portion 12 and the metal sintered material coating 13 are shown separately in FIG. 5, they are actually integrated.

As shown in FIG. 6, the metal sintered material coating 13 formed as described above covers the first roughened plating 22L. The metal sintered material coating 13 does not cover the second roughening plating 22S at the portion D in FIG. 7 sufficiently separated from the joint portion 12, but the second roughening plating 22S around the first roughening plating 22L. May be covered a little.

When the metal sintered material coating 13 contains, for example, Ag, hydrogen bonds can be formed with OH groups generated by sulfurization. Therefore, the roughened plating 22 can obtain better adhesion to the sealing resin 5 by hydrogen bonding in addition to the anchor effect. As a result, the adhesiveness can be enhanced, and sufficient moisture absorption / reflow resistance can be ensured.

The RMS of the first roughened plating 22L is preferably 250 nm or more in order to enhance the leaching of the metal sintered material paste described above. RMS is a parameter indicating surface roughness that can be measured by an atomic force microscope (AFM), and is a square root of a value obtained by averaging the square of the deviation from the average line of the surface to the measurement curve.

The RMS of the second roughened plating 22S is 100 nm or more and 250 nm in order to increase the adhesion strength between the second roughened plating 22S and the sealing resin 5 and suppress unnecessary leaching of the metal sintered material paste. It is preferably smaller. If the RMS of the second roughened plating 22S is smaller than 100 nm, the adhesion strength of the sealing resin 5 is insufficient, and peeling may occur during reflow mounting. However, even if the sealing resin 5 is peeled off, the RMS of the second roughened plating 22S may be smaller than 100 nm if the effect on the joint portion 12 is small and does not lead to an increase in thermal resistance. Further, if the surface roughness of the second roughened plating 22S is not a problem even with the surface roughness of general flat plating, the second roughened plating 22S may be flat plating.

Next, among the surfaces of the heat sink 21, the upper surface (joint surface and adjacent surface) on which the first roughening plating 22L is arranged will be described.

The bonding surface may be provided corresponding to the entire lower surface of the semiconductor element 1, and if the solvent and a small amount of metal particles can be efficiently leached, the four corners (four corners) of the lower surface of the semiconductor element 1 may be provided. Only the part) may be provided corresponding to only the long side of the lower surface of the semiconductor element 1 or only the short side. In this case, since the area of the joint surface and eventually the first roughened plating 22L can be reduced, the cost of forming the first roughened plating 22L can be suppressed.

It is desirable that the adjacent surface adjacent to the bonding surface is provided within 0.5 mm outside the bonding surface (the end of the semiconductor element 1 in a plan view). According to such a configuration, it is possible to suppress excessive leaching of metal particles, so that it is possible to suppress an extremely decrease in the density and thickness of the joint portion 12 after sintering. When it is necessary to prioritize the adhesion of the sealing resin 5 over the density and thickness of the joint portion 12, the adjacent surface may be in a range larger than 0.5 mm outside the joint surface. According to such a configuration, since the area of the metal sintered material coating 13 can be increased, the adhesion between the roughened plating 22 and the sealing resin 5 can be improved, and sufficient moisture absorption and reflow resistance can be ensured. can do.

Next, regarding the results of confirming that the density of the joint portion 12 can be increased and that the thickness of the joint portion 12 can be made sufficient for joining (for example, 30 μm or more) according to the first embodiment. explain.

FIG. 8 is an enlarged view of the joint portion 12 below the center of the semiconductor element 1 when the first roughened plating 22L is not formed. FIG. 9 is an enlarged view of the joint portion 12 below the center of the semiconductor element 1 when the first roughened plating 22L is formed, and corresponds to an enlarged view of the joint portion 12 of FIG.

As shown in FIG. 8, in the contrasting semiconductor device in which the first roughened plating 22L was not formed, horizontal cracks 51 existing near the interface of the semiconductor element 1 of the joint portion 12 and vertical cracks 52 cracked in the vertical direction were formed. It has occurred. On the other hand, as shown in FIG. 9, in the semiconductor device of the first embodiment in which the first roughened plating 22L is formed, the occurrence of horizontal cracks and vertical cracks is suppressed, and a good bonding state is obtained. Was done. Further, the density of the joint 12 in FIG. 8 was 71.3%, whereas the density of the joint 12 in FIG. 9 was 79.1%, which was improved by about 10%. Further, the thickness of the joint portion 12 in FIG. 8 was 12 μm, whereas the thickness of the joint portion 12 in FIG. 9 was 45 μm, which was a sufficient thickness.

When the thickness of the joint portion 12 is, for example, 30 μm or more, the life for the temperature cycle test can be extended, but the life is not limited to this. If the joint portion 12 is made thicker, the thermal resistance increases. Therefore, the thickness of the joint portion 12 may be determined in consideration of the thermal design of the semiconductor device.

Next, an example of the material of the roughened plating 22 will be described. The roughened plating 22 includes, for example, a lamination of Ni (nickel) plating / Pd (palladium) plating / Au plating, in which case the resurface is an Au layer. The thicknesses of the Ni layer, the Pd layer, and the Au layer are preferably 1 to 3 μm, 0.01 to 0.03 μm, and 0.1 to 3 μm, respectively, but are not limited to these, and are bonded to the metal sintered material paste. The thickness of each layer may be determined depending on the state.

According to the roughened plating 22 as described above, the underlying Ni layer grows in a needle shape and a Pd layer and an Au layer are formed on the surface thereof, so that the surface of the roughened plating 22 can be roughened in a needle shape. it can. Therefore, since the anchor effect can be enhanced, the adhesion with the sealing resin 5 can be enhanced. The size of the surface roughness of the roughened plating 22 can be appropriately adjusted depending on the material of the roughened plating 22 and its ratio. Further, if the Ni layer is not substantially deformed at the time of sintering, or if the roughened plating 22 and the metal sintered material paste are sufficiently bonded, the Pd layer is unnecessary.

<Summary of Embodiment 1>
According to the semiconductor device according to the first embodiment as described above, the first roughened plating 22L having a surface roughness larger than that of the second roughened plating 22S is bonded to the semiconductor element 1 on the surface of the heat sink 21. It is arranged on the joint surface joined by the portion 12. According to such a configuration, it is possible to obtain a joint portion 12 having a sufficient thickness in which initial cracks are suppressed. Further, even if a primer resin having a high water absorption rate is not used, the adhesion between the roughened plating and the sealing resin 5 can be improved by the metal sintered material coating 13. Thereby, for example, the moisture absorption reflow resistance and the life for the temperature cycle test can be improved.

<Modification example>
In the first embodiment, the heat sink 21 is composed of Cu, but it may not be composed of Cu as long as it has a function of dissipating heat due to the operation of the semiconductor element 1. For example, the heat sink 21 may be composed of iron, tungsten, molybdenum, nickel, cobalt, alloys thereof, or a composite material thereof. As described above, if a heat sink material having a high thermal conductivity (for example, 200 W / mk or more) is used, the heat generated from the semiconductor element 1 can be efficiently dissipated to the outside, so that the strain applied to the joint portion 12 can be reduced. .. Further, the shape of the heat sink 21 is not limited to a square pillar, but may be a polygonal pillar, a cylinder, an elliptical pillar, or a shape in which a step is provided in a part thereof. Further, in the first embodiment, the base material is the heat sink 21, but the base material is not limited to this, and may be, for example, a substrate.

Further, in the first embodiment, the semiconductor element 1 is composed of Si, but the present invention is not limited to this. For example, the semiconductor element 1 may be composed of GaAs (gallium arsenide) or a wide bandgap semiconductor such as SiC (silicon carbide), GaN (gallium nitride), or diamond. When the semiconductor element 1 is composed of a wide bandgap semiconductor, the electron speed is improved, the durability of the breakdown voltage due to the wide bandgap is improved, the operating power is increased, the operating bandwidth is expanded, and so on. Various merits such as high temperature operation, miniaturization, and cost reduction can be obtained. In particular, when the semiconductor element 1 is composed of GaN, it can operate at a higher temperature than when it is composed of Si or GaAs, and the junction temperature of the semiconductor element 1 can be increased (for example, about 250 ° C.). it can.

Further, in the first embodiment, the semiconductor element 1 is a semiconductor element having a long side and a short side in a plan view, but the present invention is not limited to this, and for example, the semiconductor element 1 is a semiconductor element having the same sides. May be good. Further, the semiconductor element 1 is not limited to the semiconductor element for high frequency communication, and may be, for example, a semiconductor element for electric power.

Further, the semiconductor device according to the first embodiment includes a semiconductor element 1 and a circuit board 2. However, the circuit board 2 is not indispensable, and the semiconductor device may include at least the semiconductor element 1. Further, the joint portion 12 of the circuit board 2 does not have to be made of a metal sintered material, and for example, an AuSn (Sn is tin) alloy or PbSn that can withstand the reflow temperature (for example, around 250 ° C.) at the time of mounting the substrate. It may be a solder material such as an alloy.

Further, the metal sintered material of the joint portion 12 is not limited to the Ag sintered material, and is classified into, for example, noble metals such as Cu sintered material, Au sintered material, Pd sintered material, and Pt sintered material. It may be a sintered material based on pure metal, or based on an alloy such as Ag-Pd sintered material, Au-Si sintered material, Au-Ge sintered material, Au-Cu sintered material, etc. It may be a sintered material. Further, the metal sintered material of the joint portion 12 may be 100% metal fine particles, or a metal fine particle and a resin material (for example, about 10% epoxy-based, silicon-based, acrylic-based resin, etc.) are mixed. It may be a metal sintered material.

<Embodiment 2>
10 to 13 are plan views showing the roughened plating 22 (first roughened plating 22L and second roughened plating 22S) according to the second embodiment of the present invention.

In the first embodiment, as shown in FIG. 4, the first roughened plating 22L is adjacent to the bonding surface of the surface of the heat sink 21 in a plan view, and the semiconductor element 1 is located outside the semiconductor element 1. It was also arranged on the adjacent surface adjacent to the outer peripheral portion of the. However, if it is possible to efficiently leach a part of each of the solvent and the metal particles of the metal sintered material paste, the adjacent surface on which the first roughened plating 22L is arranged is as described below. For example, it may be provided only in the vicinity of the four corners (four corners) of the semiconductor element 1, only in the vicinity of the long side of the semiconductor element 1, or only in the vicinity of the short side. In this case, since the area of the first roughened plating 22L can be reduced, the cost of forming the first roughened plating 22L can be suppressed.

In the configuration shown in FIG. 10, the shape of the semiconductor element 1 in a plan view has corners. The first roughened plating 22L is also arranged on the surface of the heat sink 21 in a plan view, which is adjacent to the bonding surface and on the outer surface of the semiconductor element 1 which is adjacent to the corner portion. .. According to such a configuration, since the first roughened plating 22L is arranged only at the four corners where a relatively large thermal stress is generated, it is possible to secure the moisture absorption reflow resistance and the life for the temperature cycle test at low cost. .. In FIG. 10, the first roughened plating 22L is arranged adjacent to the four corners of the semiconductor element 1, but is arranged adjacent only to the pair of diagonally located corners. You may.

In the configuration shown in FIG. 11, the shape of the semiconductor element 1 in a plan view has a short side and a long side. The first roughened plating 22L is also arranged on the surface of the heat sink 21 in a plan view, which is adjacent to the bonding surface and on the outer surface of the semiconductor element 1 which is adjacent to the short side. .. According to such a configuration, the area of the metal sintered material coating 13 can be made larger than the configuration of FIG. 10, so that the moisture absorption reflow resistance and the temperature cycle test can be performed while suppressing the cost of the first roughened plating 22L. The lifespan of the bicycle can be further extended.

In the configuration shown in FIG. 12, similarly to the configuration shown in FIG. 11, the shape of the semiconductor element 1 in a plan view has a short side and a long side. The first roughened plating 22L is also arranged on the surface of the heat sink 21 in a plan view, which is adjacent to the bonding surface and on the outer surface of the semiconductor element 1 which is adjacent to the long side. .. According to such a configuration, the area of the metal sintered material coating 13 can be made larger than the configuration of FIG. 11, so that the moisture absorption reflow resistance and the temperature cycle test can be performed while suppressing the cost of the first roughened plating 22L. The lifespan of the bicycle can be further extended.

In the configuration shown in FIG. 13, the shape of the semiconductor element 1 in a plan view has a pair of long sides (a pair of sides). The first roughened plating 22L is formed on one or more adjacent surfaces of the surface of the heat sink 21 in a plan view, which are adjacent to the bonding surface and adjacent to the pair of long sides on the outside of the semiconductor element 1. It is also arranged in. Adjacent surfaces of each set face each other via the semiconductor element 1 in a plan view. According to such a configuration, the region where the first roughened plating 22L is arranged has an uneven shape in the vertical direction and the horizontal direction in a plan view, so that the surface area of the first roughened plating 22L becomes large. Therefore, the solvent of the metal sintered material paste 11 can be efficiently leached. Further, not only the anchor effect in the height direction by the first roughened plating 22L but also the anchor effect in the vertical direction and the horizontal direction in a plan view can be obtained, so that the moisture absorption reflow resistance and the life for the temperature cycle test can be further enhanced. Can be done.

<Embodiment 3>
FIG. 14 is a flowchart showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention. Hereinafter, as the manufacturing method, a method of manufacturing the semiconductor device according to the first embodiment and the second embodiment will be described.

First, a heat sink 21 on which the first roughening plating 22L and the second roughening plating 22S are arranged is prepared. Then, in step S1, the metal sintered material paste is applied onto the first roughened plating 22L, which is roughened plating (coating step). For the application of the metal sintered material paste, dispense may be used, or screen printing, stamping, or the like may be used.

The metal sintered material paste generally contains metal particles having a submicron size, nano size, or both sizes, a protective film covering the surface of the metal particles, and a solvent for dispersing the metal particles. The metal particles are not limited to a sphere shape, and may have various shapes such as a flake shape and a shape in which a sphere is covered with a needle shape.

In step S2, by waiting for a certain period of time, a part of each of the solvent and the metal particles of the metal sintered material paste is leached to the outside in a plan view (waiting step). FIG. 15 is a plan view showing a state after the weighting process. In the following, the range in which the metal particles are sloppy may be referred to as the metal particles 14a or the metal particles 14b.

As shown in FIG. 15, a large amount of solvent 15 (some solvents) and a small amount of metal particles 14a (some metal particles) of the metal sintered material paste 11 are leached to the outside by the weighting process. The leaching solvent 15 exceeds the first roughening plating 22L and reaches the second roughening plating 22S. On the other hand, the leached metal particles 14a expand with the leaching of the solvent 15, but do not expand more than the solvent 15, and are in a range of about 0.1 mm from the portion to which the metal sintered material paste 11 is applied in step S1. Stay in. Further, since the metal particles have lower fluidity than the solvent, many metal particles 14b (remaining metal particles) are present in the portion where the metal sintered material paste 11 is applied in step S1.

It takes about 1 minute for the metal particles 14a to leach 0.5 mm outside the region on which the semiconductor element 1 is placed. Since the leaching time and the leaching distance are generally in a proportional relationship, the standby time may be controlled by the area of the metal particles 14a to be the metal sintered material coating 13. By this weighting step, the solvent and metal particles of the metal sintered material paste 11 may be provided on the entire surface of the first roughened plating 22L, or may be provided on a part of the surface of the first roughened plating 22L. It may be provided.

In step S3, the semiconductor element 1 is mounted on the remaining metal particles 14b of the metal sintered material paste 11 (element mounting step). For example, a mounter is used for this placement. The remaining metal particles 14b on which the semiconductor element 1 is placed expand to some extent by being pushed from the semiconductor element 1.

In step S4, for example, the metal sintered material paste 11 is heated without pressure to sinter the remaining metal particles 14b to form a joint portion 12 for joining the semiconductor element 1 and the heat sink 21 (. Joining process). When the metal sintered material paste 11 is heated at about 200 ° C., the volatilization of the protective film and the solvent is enhanced, and the joint portion 12 containing the neck-sintered metal particles 14b is formed. The necking-sintered joint 12 is expected to have substantially the same thermal conductivity and heat resistance as bulk metal.

FIG. 16 is a plan view showing a state after the joining process. After sintering, the solvent 15 becomes a solvent discharge mark 17, the remaining metal particles 14b become a joint portion 12 having a hem-spreading shape (fillet) in a cross-sectional view, and some metal particles 14b are metal sintered materials. It becomes coating 13. Since the metal sintered material coating 13 has substantially the same region as the first roughened plating 22L, the position and area of the metal sintered material coating 13 can be controlled by controlling the position and area of the first roughened plating 22L. Can be controlled.

In step S5, the surface electrodes of the semiconductor element 1 and the circuit board 2 and the leads 4 are electrically connected by connecting them with the bonding wire 3 (connection step).

In step S6, the sealing resin 5 that covers the semiconductor element 1 and the circuit board 2 and covers at least a part of the heat sink 21 and the reed 4 is formed (sealing step). As described above, the semiconductor device according to the first embodiment and the second embodiment is completed.

<Summary of Embodiment 3>
According to the method for manufacturing a semiconductor device according to the third embodiment as described above, the semiconductor device according to the first and second embodiments, that is, the semiconductor device including the joint portion 12 in which the initial crack is suppressed is provided. Can be formed. Further, according to the third embodiment, since the metal sintered material coating 13 can be formed, the complexity of the manufacturing process can be suppressed.

In the present invention, each embodiment and each modification can be freely combined, and each embodiment and each modification can be appropriately modified or omitted within the scope of the invention.

1 Semiconductor element, 4 leads, 5 sealing resin, 11 metal sintered material paste, 12 joints, 14a, 14b metal particles, 15 solvent, 21 heat sink, 22L 1st roughened plating, 22S 2nd roughened plating.

Claims (9)

With semiconductor elements
The base material bonded to the semiconductor element and
A joint portion containing a metal sintered material that joins the semiconductor element and the base material,
A reed electrically connected to the semiconductor element,
A sealing resin that covers the semiconductor element and at least a part of the base material and the lead.
Of the surface of the base material, the first roughened plating disposed on the bonding surface to be bonded by the semiconductor element and the bonding portion,
It comprises a second roughened plating disposed on at least a part of the surface of the base material along the sealing resin.
The first roughened plating is a semiconductor device having a surface roughness larger than that of the second roughened plating. The semiconductor device according to claim 1.
The RMS of the first roughened plating is 250 nm or more, and is
The RMS of the second roughened plating is 100 nm or more and smaller than 250 nm.
The first roughened plating is also disposed on an adjacent surface of the surface of the base material adjacent to the joint surface in a plan view.
A semiconductor device in which the adjacent surface is provided within a range of 0.5 mm from the bonded surface. The semiconductor device according to claim 1 or 2.
The shape of the semiconductor element in a plan view has corners and has corners.
The first roughened plating is also arranged on the surface of the base material, which is adjacent to the bonding surface in a plan view and is adjacent to the corner portion on the outside of the semiconductor element. , Semiconductor device. The semiconductor device according to claim 1 or 2.
The shape of the semiconductor element in a plan view has a short side and a long side, and has a short side and a long side.
The first roughened plating is adjacent to the bonding surface of the surface of the base material in a plan view, and is adjacent to at least one of the short side and the long side on the outside of the semiconductor element. A semiconductor device that is also arranged on an adjacent surface. The semiconductor device according to claim 1 or 2.
The shape of the semiconductor element in a plan view has a pair of sides and has a pair of sides.
The first roughened plating is performed on one or more adjacent surfaces of the surface of the base material in a plan view, which are adjacent to the bonding surface and adjacent to the pair of sides on the outside of the semiconductor element. Is also arranged,
A semiconductor device in which the adjacent surfaces of each set face each other via the semiconductor element in a plan view. The semiconductor device according to any one of claims 1 to 5.
The second roughening plating is a semiconductor device that is also disposed on at least a part of the surface of the lead along the sealing resin. A step of applying a metal sintered material paste on the roughened plating provided on the surface of the base material and leaching a part of each of the solvent and the metal particles of the metal sintered material paste to the outside in a plan view.
The step of placing the semiconductor element on the metal particles remaining in the metal sintered material paste, and
A step of forming a joint portion for joining the semiconductor element and the base material by heating the metal sintering material paste and sintering the remaining metal particles.
The process of electrically connecting the reed to the semiconductor element and
A method for manufacturing a semiconductor device, comprising a step of forming a sealing resin that covers the semiconductor element and covers at least a part of the base material and the lead. The method for manufacturing a semiconductor device according to claim 7.
By the step of leaching the solvent of the metal sintered material paste and a part of each of the metal particles, the solvent and the metal particles of the metal sintered material paste are brought to the surface of the roughened plating. A method for manufacturing semiconductor devices, which is provided for all. The method for manufacturing a semiconductor device according to claim 7.
By the step of leaching the solvent of the metal sintered material paste and a part of each of the metal particles, the solvent and the metal particles of the metal sintered material paste are brought to the surface of the roughened plating. A method for manufacturing a semiconductor device provided in a part.

Images