JP2021043495A - Information processing program and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute training of a neural network by designating an arbitrary batch size. An information processing program is a processor from a plurality of processing instructions having different batch sizes to be processed based on the size of training data used for training the layer to be trained in a neural network and the input batch size. Selects the processing instruction to be executed, calculates the memory size used for training the layer to be trained based on the size of the training data and the batch size specified by the selected processing instruction, and holds the training data. If the memory size of the first memory area does not match the calculated memory size, a second memory area having the calculated memory size is secured in the memory, the training data is transferred, and the data is transferred to the second memory area. Using the learned data, the processor is made to execute the selected processing instruction, and the information processing device is made to execute the processing. [Selection diagram] FIG. 9

Description

The present invention relates to an information processing program and an information processing method.

In deep learning, hundreds of thousands to millions or more of training data are used to change the parameters of each layer of the deep neural network to appropriate values. Since the product-sum calculation is often used in the deep learning calculation, the calculation time of the deep learning is shortened by improving the execution efficiency of the product-sum calculation.

For this reason, GPUs (Graphics Processing Units), which have higher execution efficiency of multiply-accumulate operations than CPUs (Central Processing Units), are widely used for deep learning. In addition, as the industrial use of deep learning has become widespread, dedicated processors for deep learning have been developed that specialize in deep learning calculations.

For example, a processor used for deep learning includes a plurality of arithmetic cores including an arithmetic unit, a unique memory used by each arithmetic core, a shared memory shared by a predetermined number of arithmetic cores, and an arithmetic core. It has a control unit that controls execution and is connected to the main memory. Then, each arithmetic core executes an arithmetic of data transferred from the main memory to the private memory or the shared memory based on the control by the control unit.

For example, the data block processed by the processor has an allocation attribute related to the division of the data block, a margin attribute indicating the peripheral data to be transferred together with the divided subblocks of the data block, and a dependency attribute indicating the dependency between the subblocks. Set. Then, when the allocation attributes of the first and second kernels, which are programs executed sequentially in the arithmetic core, match, the control unit does not transfer the execution result of the first kernel from the local memory to the global memory. By using it in the kernel of 2, the processing efficiency is improved. At this time, the control unit logically adds the margin attributes and the dependency attributes set in the data block used in the second kernel to the margin attributes and the dependency attributes of the data block used in the first kernel (for example). , Patent Document 1).

In addition, by providing a data transfer function between shared memories in the memory control circuit provided corresponding to the unique memory, the image data commonly used in the arithmetic core can be read without accessing the main memory. , Processing efficiency is improved (see, for example, Patent Document 2).

Japanese Unexamined Patent Publication No. 2015-149038 International Publication No. 2008/139265

For example, the layers included in the deep neural network include a convolution layer, a pooling layer, a fully connected layer, an output layer, and the like, and the types of layers are limited, and the processing contents of each layer are limited. Therefore, a processing instruction that combines arithmetic instructions executed by the arithmetic unit may be prepared according to the processing content of each layer.

Further, in deep learning, learning data included in a batch is often divided into a plurality of parts to create a mini-batch, and learning is executed in units of mini-batch. Therefore, the calculation efficiency of deep learning is improved by preparing a plurality of processing instructions that specify the batch size, which is the number of times that training data is given to the deep neural network.

However, in this case, if the user specifies a batch size other than the batch size specified by the processing instruction, an error occurs and the processing instruction is not executed. When the batch size specified by the processing instruction is disclosed to the user, the occurrence of an error can be suppressed, but since the user cannot select an arbitrary batch size, the degree of freedom in learning is narrowed. On the other hand, it is not realistic to prepare a large number of processing instructions corresponding to all batch sizes that can be specified by the user.

In one aspect, the present invention aims to perform neural network learning by specifying an arbitrary batch size.

According to one aspect, the information processing program learns a neural network including multiple layers executed by a processor having one or more arithmetic units including an arithmetic unit and a memory for holding data used in the arithmetic unit. An information processing program to be controlled, which is executed by the processor from a plurality of processing instructions having different batch sizes to be processed based on the size of training data used for learning the layer to be learned and the input batch size. The processing instruction to be processed is selected, the memory size used for learning the layer to be learned is calculated based on the size of the training data and the batch size specified by the selected processing instruction, and the training data is held. When the memory size of the first memory area of the memory does not match the calculated memory size, a second memory area having the calculated memory size is secured in the memory, the learning data is transferred, and the second memory area is transferred. Using the learning data transferred to the memory area of the above, the processor is made to execute the selected processing instruction, and the information processing apparatus is made to execute the processing.

In one aspect, the present invention allows the training of neural networks to be performed by specifying any batch size.

It is a block diagram which shows an example of the information processing apparatus in one Embodiment. It is a flow diagram which shows an example of the operation when the information processing apparatus of FIG. 1 executes the learning of a neural network. It is a block diagram which shows an example of the information processing apparatus in another embodiment. It is explanatory drawing which shows the outline of a deep neural network. It is explanatory drawing which shows an example of the specification information of the processing instruction which can be executed by the arithmetic core of FIG. FIG. 5 is an explanatory diagram showing an example of a data structure of input / output data used for learning each layer of a neural network and a data structure related to a processing instruction in the information processing apparatus of FIG. It is explanatory drawing which shows an example of the arrangement pattern of FIG. It is a flow diagram which shows an example of the operation when the information processing apparatus of FIG. 3 executes the learning of a neural network. It is explanatory drawing which shows an example of the operation at the time of learning in the layer to be learned of the neural network in the information processing apparatus of FIG. It is explanatory drawing which shows another example of the operation at the time of learning in the layer to be learned of the neural network in the information processing apparatus of FIG. It is a block diagram which shows an example of the information processing apparatus in another embodiment. It is explanatory drawing which shows an example of the function realized by the host CPU of FIG. 11 executing a host program. It is explanatory drawing which shows the relationship between the memory size and arrangement pattern of the memory area reserved in memory, and the memory size and arrangement pattern corresponding to the processing instruction used for learning of the layer to be learned. It is a flow chart which shows an example of the operation when the information processing apparatus of FIG. 11 executes the learning of a neural network. It is explanatory drawing which shows an example which executes the processing instruction in the information processing apparatus in another embodiment. It is explanatory drawing which shows an example which executes the processing instruction in the information processing apparatus in still another Embodiment.

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 shows an example of an information processing device according to an embodiment. The information processing device 100 shown in FIG. 1 is, for example, a server, and includes a host CPU 200, a host memory 300, an I / O (Input / Output) controller 220, and a processor 500 for deep learning (DL). The host CPU 200 is connected to the host memory 300 via the bus and is connected to the processor 500 via the I / O controller 220. For example, the host CPU 200, the host memory 300, the I / O controller 220, and the processor 500 are mounted on the system board. For example, the host memory 300 is a memory module mounted on a system board.

The host CPU 200 controls the overall operation of the information processing apparatus 100 by executing various programs stored in the host memory 300, controls the operation of the processor 500, and learns the neural network using the learning data. Execute. The various programs also include the operating system.

The information processing device 100 includes an input device (keyboard and mouse), an output device (monitor and printer) and an external storage device (HDD (Hard Disk Drive) and SDD (Solid State Drive)) connected to the system board. May have. Further, the information processing device 100A may be connected to a network such as an intranet or the Internet, or a plurality of information processing devices 100A may be connected to each other via the network.

The host memory 300 stores a user-defined file 310 and a host program 400 for causing a neural network (NN) to execute an operation. The user-defined file 310 includes a file 311 containing the configuration information defining the neural network and a file 312 of training data. Files 311 and 312 are prepared by the user. Hereinafter, the configuration information of the neural network included in the file 311 is also referred to as a neural network 311, and the learning data included in the file 312 is also referred to as a learning data 312. Unless otherwise specified, the learning data 312 indicates the learning data used for learning the layer to be learned among the plurality of layers included in the neural network.

When executed by the host CPU 200, the host program 400 functions as a selection unit 401, a calculation unit 402, a determination unit 403, a transfer unit 404, and a processing instruction execution unit 405. The processing instruction file 406 included in the host program 400 includes a plurality of processing instructions executed by the processor 500, is transferred to the processor 500 when the training of the neural network 311 is executed, and is executed by the processor 500. For example, the processing instruction includes a processing instruction for a convolution operation that executes an operation of a convolutional layer included in a neural network, a processing instruction for a pooling operation that executes an operation of a pooling layer, an addition instruction, a matrix product operation instruction, and the like.

The processor 500 has a plurality of arithmetic cores 510 including a plurality of arithmetic units 520 and a memory 530, respectively. The memory 530 is used only for the arithmetic unit 520 mounted on the arithmetic core 510 together with the memory 530. The calculation core 510 is an example of a calculation unit. The arithmetic core 510 executes processing instructions in parallel based on an instruction from the host CPU 200. It should be noted that each memory 530 may be provided outside each arithmetic core 510 as a memory exclusively used for each arithmetic core 510. The plurality of arithmetic units 520 are a product-sum arithmetic unit, an adder, a matrix product arithmetic unit, and the like.

When the host CPU 200 executes the host program 400 to execute the learning of the neural network, the selection unit 401, the calculation unit 402, the determination unit 403, the transfer unit 404, and the processing instruction execution unit 405 function as follows. Hereinafter, learning for each layer of the neural network will be described, but learning of the neural network can be executed by sequentially executing learning of each layer. In addition, forward propagation processing can be executed by sequentially executing learning from the input side layer of the neural network, and backpropagation processing is executed by sequentially executing learning from the output side layer of the neural network. be able to.

The selection unit 401 acquires the size of the training data used for learning the layer to be learned from the user-defined file 310 in the neural network. The selection unit 401 selects a processing instruction to be executed by the processor 500 from a plurality of processing instructions in the file 406 based on the size of the acquired learning data and the batch size input to the information processing apparatus 100. As described with reference to FIG. 5, a plurality of processing instructions having different batch sizes are prepared for each type of operation (convolution operation, pooling operation, etc.) and stored in file 406 in advance. For example, the batch size input to the information processing device 100 is an arbitrary batch size specified by the user.

The calculation unit 402 is used for learning the layer to be learned based on the size of the learning data of the layer to be learned acquired by the selection unit 401 and the batch size specified by the processing instruction selected by the selection unit 401. Calculate the memory size of memory 530. Here, the batch size specified by the processing instruction is a fixed batch size to be processed for each processing instruction, and the batch size specified by the user input to the information processing apparatus 100 is the batch size specified by the processing instruction. It does not always match.

Before starting the learning of the layer to be learned, the memory 530 of the arithmetic core 510 is allocated a memory area (first memory area) for storing the input data to the layer and the output data from the layer. In addition, the input data (learning day) used for learning is stored in the memory area for input data. In the second and subsequent layers, the output data output by the calculation of the previous layer is held in the memory area (first memory area) as the input data of the layer to be learned.

The determination unit 403 determines whether or not the memory size of the first memory area of the memory 530 that holds the learning data matches the memory size calculated by the calculation unit 402. That is, the determination unit 403 determines whether or not the memory size obtained from the size of the learning data and the batch size specified by the user matches / does not match the memory size obtained from the size of the learning data and the batch size depending on the processing instruction. ..

If the memory sizes match, learning can be executed using the learning data (input data) held in the first memory area, but if the memory sizes do not match, an error will occur during calculation execution, so learning will be performed. Cannot be executed. The determination unit 403 determines whether the memory size matches or does not match for each tensor data input or output for each layer of the neural network.

When the determination unit 403 determines that the memory sizes do not match, the transfer unit 404 sets the memory area (second memory area) of the memory size calculated by the calculation unit 402 in response to the tensor data that determines the mismatch to the memory 530. Secure a new one. The transfer unit 404 transfers the learning data (input data) to be learned in the layer to be learned to the newly secured second memory area. When the learning data is transferred to the newly secured second memory area, the learning data held in the first memory area is prohibited from use, invalidated, or destroyed.

Then, the processing instruction execution unit 405 executes the processing instruction selected by the selection unit 401 to the processor 500 using the learning data held in the effective memory area (first memory area or second memory area). By letting it, the learning of the neural network is executed.

In this embodiment, even when the batch size input to the information processing apparatus 100 is different from the batch size specified by the processing instruction for executing learning, the memory area is set according to the memory size used for executing the processing instruction. Can be secured. As a result, even when an arbitrary batch size is input to the information processing apparatus 100, learning can be executed without causing an error.

FIG. 2 shows an example of the operation when the information processing apparatus 100 of FIG. 1 executes the learning of the neural network. The operation shown in FIG. 2 is realized by the host CPU 200 executing the host program 400. That is, FIG. 2 shows an example of an information processing program and an information processing method.

For example, the operation shown in FIG. 2 is started based on the fact that the information processing apparatus 100 receives an instruction to execute the learning of the neural network. The operation shown in FIG. 2 is executed in the forward propagation process and the back propagation process corresponding to each of the plurality of layers included in the neural network.

First, in step S1, the selection unit 401 selects a processing instruction to be executed by the processor 500 from a plurality of processing instructions based on the size of the learning data and the batch size input to the information processing device 100.

Next, in step S2, the calculation unit 402 calculates the memory size of the memory 530 used for learning based on the size of the learning data and the batch size specified by the processing instruction selected by the selection unit 401.

Next, in step S3, the determination unit 403 determines whether or not the memory size of the first memory area of the memory 530 holding the learning data matches the memory size calculated by the calculation unit 402. If the memory sizes match, the process proceeds to step S5, and if the memory sizes do not match, the process proceeds to step S4.

In step S4, the transfer unit 404 newly secures a memory area (second memory area) of the memory size calculated by the calculation unit 402 in the memory 530, and transfers the learning data to the secured second memory area. , The process proceeds to step S5.

In step S5, the processing instruction execution unit 405 uses the learning data held in the effective memory area (first memory area or second memory area) to transmit the processing instruction selected by the selection unit 401 to the processor 500. To execute. Then, when the processor 500 executes the operation instructed by the processing instruction, the learning of the layer to be learned in the neural network is executed.

As described above, in the embodiment shown in FIGS. 1 and 2, even when the batch size input to the information processing apparatus 100 is different from the batch size specified by the processing instruction for executing learning, it is used for executing the processing instruction. A memory area can be secured according to the memory size. As a result, even if an arbitrary batch size is specified, learning can be executed without causing an error.

FIG. 3 shows an example of an information processing device according to another embodiment. The same elements as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The information processing device 100A shown in FIG. 3 is, for example, a server and has the same configuration as the information processing device 100 of FIG.

The host memory 300 stores a user-defined file 310 and a host program 400A for causing a neural network (NN) to execute an operation. Similar to FIG. 1, the user-defined file 310 includes a file 311 containing configuration information defining a neural network and a file 312 of training data.

When executed by the host CPU 200, the host program 400A functions as a calculation type determination unit 411, a data size change unit 412, a conversion / transfer instruction unit 414, an information management unit 421, and a processing instruction execution unit 432. The functions of the calculation type determination unit 411, the data size change unit 412, the conversion / transfer instruction unit 414, the information management unit 421, and the processing instruction execution unit 432 will be described with reference to the operation flow shown in FIG.

For example, the processing instruction file 423 included in the host program 400A includes a plurality of processing instructions executed by the processor 500, is transferred to the processor 500 when the training of the neural network 311 is executed, and is executed by the processor 500. Each processing instruction includes a sequence of arithmetic instructions executed by the arithmetic unit 520 of the processor 500. The types of processing instructions will be described with reference to FIG.

FIG. 4 shows an outline of a deep neural network. The deep neural network shown in FIG. 4 includes a plurality of sets of convolution layers / pooling layers and a fully connected layer as hidden layers, but may include other layers.

The information processing device 100A, for example, inputs each of a plurality of learning data (input data) included in the mini-batch to the input layer, and sequentially executes operations such as a convolution layer and a pooling layer to obtain information obtained by the operations. Executes forward propagation processing that sequentially transmits from the input side to the output side. For example, in the convolution layer, the data (output data) from the previous layer and the weight data prepared in advance as training data are convolved, and the output data obtained by the calculation is used as the input data of the next layer. It is output.

After executing the forward propagation process by the mini-batch, the back propagation process for reducing the difference between the output data and the correct answer data (for example, the sum of squares of the errors) is executed. Then, parameters such as weights are updated based on the execution of the back propagation process. By executing forward propagation processing, back propagation processing, and parameter update processing in a plurality of mini-batch, the correct answer rate is gradually increased, and the deep neural network is optimized. The operations of each layer in the forward propagation process and the back propagation process are performed by the arithmetic core 510 executing a processing instruction.

FIG. 5 shows an example of specification information of a processing instruction that can be executed by the arithmetic core 510 of FIG. In this embodiment, one or a plurality of processing instructions are prepared in advance for each type of operation, and are held in the file 423 of the host memory 300 as the processing instructions. In FIG. 5, it is assumed that there are two input data (input 1 and input 2) and one output data (output 1), but the number of input data and output data is limited to the example shown in FIG. Not done. Further, the types of processing that can be executed by the processor 500 and the number of processing instructions are not limited to FIG.

In the forward propagation process, input data is given from the input layer side in each layer, and the calculation result is output from the output layer side. In the back propagation process, an input is given from the output layer side (output side in the forward propagation process), and the calculation result is output from the input layer side (input side in the forward propagation process).

For example, in the convolution operation, four types of processing instructions Conv1, Conv2, Conv3, and Conv4 can be used. The processing instructions Conv1-Conv4 are used properly according to the number of corresponding batches and the arrangement pattern (distributed type or copy type) of the input 1, the input 2, and the output 1.

One type of processing instruction Add1 can be used for element-by-element addition. The processing instruction Add1 can be used in any number of batches, and the data arrangements of the input 1, the input 2, and the output 1 are all distributed.

In matrix multiplication, two types of processing instructions Gemm1 and Gemm2 can be used. The processing instructions Gemm1 and Gemm2 can be used in any number of batches, one of the inputs 1 / input 2 is a distributed type, the other of the inputs 1 / input 2 is a copy type, and the output 1 is a distributed type.

FIG. 6 is an explanatory diagram showing an example of a data structure of input / output data used for learning each layer of the neural network and a data structure related to a processing instruction in the information processing apparatus of FIG. FIG. 6 shows a data structure of input / output data in a layer having two input tensor data and one output tensor data.

The data structure of the input / output data is determined for each tensor data input or output for each layer of the neural network. Each tensor data has information on the number of elements in each dimension, the memory size, and the arrangement pattern, in addition to the input / output data input or output to each layer. For example, in learning a neural network for image recognition, there are four dimensions of input image data: batch size N, color C, number of horizontal pixels W, and number of vertical pixels H, and the number of elements is set for each dimension. Will be done. As an example, the number of elements in each dimension is batch size N = 32, color C = 3 (color image), number of pixels W = 10, number of pixels H = 10, and the data is single precision (4 bytes) floating point. Suppose it is a number.

In this case, the tensor data size is 38,400 bytes, and the memory size of the memory area of the memory 530 for storing the tensor data is set to 38,400 bytes or more. Each tensor data size is calculated by multiplying the product of the number of elements in each dimension by the number of bytes per data. The arrangement pattern is either a distributed type in which each tensor data is distributed and stored in a plurality of memories 530, or a copy type in which each tensor data is stored in a plurality of memories 530. An example of the arrangement pattern will be described with reference to FIG.

The number of input tensor data and the number of output tensor data are determined by the type of operation. The data structure related to the processing instruction has a memory size used in the processing instruction and an arrangement pattern used in the processing instruction. The memory size used in the processing instruction is set based on the batch size specified in the processing instruction and the size of the data used for learning the layer to be learned. In the processing by the processing instruction, when one or more tensor data is input, one or more tensor data is output.

FIG. 7 shows an example of the arrangement pattern of FIG. In the example shown in FIG. 7, it is assumed that the tensor data includes the data D1, D2, D3, and D4 for the sake of clarity. When the arrangement pattern is a distributed type, the data D1-D4 are distributed and arranged in the memory 530 of each calculation core 510. On the other hand, when the arrangement pattern is a copy type, the data D1-D4 are arranged in the memory 530 of each calculation core 510. The copy type is an example of a duplicate type.

FIG. 8 shows an example of the operation when the information processing apparatus 100A of FIG. 3 executes the learning of the neural network. The operation shown in FIG. 6 is realized by the host CPU 200 of FIG. 3 executing the host program 400A. That is, FIG. 6 shows an example of an information processing program and an information processing method.

For example, the operation shown in FIG. 8 is started based on the fact that the information processing apparatus 100A receives an instruction to execute the learning of the neural network. The operation shown in FIG. 8 is executed in the forward propagation process and the back propagation process corresponding to each of the plurality of layers included in the neural network.

First, in step S10, the calculation type determination unit 411 of FIG. 3 determines the calculation type based on the specifications such as the configuration information of the layer to be learned in the neural network in the user-defined file 310. For example, when the layer to be learned is a convolution layer, "convolution" is determined as the operation type. The calculation type is an example of a calculation method used for learning the layer to be learned.

Next, in step S12, the conversion / transfer instruction unit 414 is used for calculation in each memory 530 based on the batch size specified by the user, the specifications of the layer to be learned in the neural network, and the learning data. Allocate a memory area to be used. Here, as the specifications of the layer to be learned and the learning data, the input / output data arrangement pattern (distributed / copy type) and the data size used for the calculation are used, and the memory area (first memory area) is set. Secured. Then, the conversion / transfer instruction unit 414 transfers the learning data (data for the batch size specified by the user) to be used for the calculation to the memory area secured in each memory 530 according to the arrangement pattern.

In the learning of the neural network (either forward propagation processing or back propagation processing), in the processing of the second and subsequent layers, the output data obtained by the calculation of the previous layer is used as the input data. Further, the arrangement pattern of the output data obtained by the calculation of the previous layer is used as the arrangement pattern of the input data of the layer to be calculated. Therefore, in the learning of each layer after the second layer, it is not necessary to secure the memory area and transfer the data in step S12.

Next, in step S14, the information management unit 421 executes the calculation target layer based on the calculation type determined in step S10, the batch size specified by the user, and the size of the learning data used for the calculation. Select the processing instruction to do. Here, in the processing of each layer after the second layer, the processing instruction is selected based on the memory size including the size of the output data obtained by the calculation of the previous layer.

Next, in step S16, the information management unit 421 obtains a data arrangement pattern corresponding to the processing instruction selected in step S14, for example, based on the information shown in FIG. Further, the information management unit 421 determines the batch size and arrangement pattern peculiar to the processing instruction specified in the processing instruction selected in step S14, and the memory size used in the selected processing instruction based on the size of the learning data. calculate.

Next, in step S20, the data size changing unit 412 determines the memory size calculated in step S16 (depending on the batch size specified by the selected processing instruction) and the memory size of the memory area secured in step S12. Determine match / mismatch. In the processing of the second and subsequent layers, the memory size including the size of the output data obtained by the calculation of the previous layer is compared with the memory size calculated in step S16. If the memory sizes match, the process proceeds to step S24, and if the memory sizes do not match, the process proceeds to step S22.

In step S22, the data size changing unit 412 replaces the memory area (first memory area) secured in step S12 with a memory area (second memory area) corresponding to the memory size calculated in step S16. It is newly secured in the memory 530. That is, the data size changing unit 412 changes the memory size of the input / output data secured in step S12 to the memory size specified in the processing instruction. The data size changing unit 412 transfers the learning data (data for the batch size specified by the user) used for the calculation to the newly secured memory area, and shifts the process to step S24.

When the size of the newly secured memory area is larger than the size of the learning data used for the calculation, the data size changing unit 412 applies dummy data to the free memory area so as not to affect the execution of the calculation by the processing instruction. May be stored. The data held in the memory area secured in step S12 is prohibited from use, invalidated, or destroyed.

In step S24, the conversion / transfer instruction unit 414 determines a match / mismatch between the data arrangement pattern used in step S12 and the data arrangement pattern obtained in step S16. Here, the match / mismatch of the arrangement pattern is determined for each type of data (input 1, input 2, output 1 in FIG. 5). That is, steps S24 and S26 are determined for each type of data. If the arrangement patterns match, the process proceeds to step S28, and if the arrangement patterns do not match, the process proceeds to step S26. In the processing of the second and subsequent layers, the arrangement pattern including the arrangement pattern of the output data obtained by the calculation of the previous layer is compared with the arrangement pattern of the data obtained in step S16.

In step S26, the conversion / transfer instruction unit 414 replaces the memory area (first memory area) secured in step S12 with a memory area (third memory area) corresponding to the memory size calculated in step S16. A new memory is allocated to each memory 530. That is, the conversion / transfer instruction unit 414 changes the arrangement pattern corresponding to the memory area secured in step S12 to the arrangement pattern which is the specification of the processing instruction. The conversion / transfer instruction unit 414 transfers the learning data (data for the batch size specified by the user) used for the calculation to the newly secured memory area according to the data arrangement pattern obtained in step S16. The process proceeds to step S28.

The processes of steps S22 and S26 may be executed at the same time. That is, when the memory sizes do not match and the arrangement patterns do not match, the memory area is secured and the data is transferred at the same time.

In step S28, the processing instruction execution unit 432 transfers the processing instruction selected in step S14 to each arithmetic core 510, causes each arithmetic core 510 to execute the processing instruction, and ends the processing shown in FIG. As a result, the learning process of one layer of the neural network is executed.

FIG. 9 shows an example of the operation during learning in the layer to be learned of the neural network in the information processing apparatus of FIG. For example, FIG. 9 shows an example of an operation during learning of a neural network that recognizes an image, and the number of elements in each dimension is batch size N = 32, color C = 3, number of pixels W = 10, number of pixels H =. 10. Assume that the data is a single precision floating point number (4 bytes). It is assumed that the size of the input data (input tensor data) input to the layer to be learned is 38,400 bytes. Further, it is assumed that the data arrangement pattern is distributed in the layer to be learned and the layer immediately before the layer to be learned. Hereinafter, the layer to be learned is also referred to as a target layer, and the layer immediately preceding the layer to be learned is also referred to as a front layer.

In FIG. 9A, since the output data (output tensor data) of the previous layer is 38400 bytes (9600 × 4), the processor 500 displays the output data which is the calculation result by 9600 bytes each in four memories 530. Store in a distributed manner.

In the target layer, the memory size calculated in step S16 of FIG. 8 is 38,400 bytes, and the arrangement pattern is distributed. Therefore, in the determination in steps S20 and S24 of FIG. 8, the memory size and the arrangement pattern also match, and the memory size and the arrangement pattern are not changed.

Then, the processor 500 executes learning of the target layer using the calculation result of the previous layer stored in the memory 530 as input data. In this way, when the memory size of the memory area that holds the data used for learning the target layer matches the memory size calculated based on the batch size specified by the processing instruction used for learning the target layer, Processing instructions can be executed using the memory area as it is. Since there is no preprocessing such as securing a memory area after the operation of the previous layer and before the operation of the target layer is executed, it is possible to execute the operation of the processing instruction in the learning of the target layer without lowering the learning efficiency. it can.

In FIG. 9B, the memory size of the memory area for the output data (output tensor data) of the previous layer is 8400 bytes for each memory 530, and the processor 500 displays the output data which is the calculation result of 8400 bytes. Each is distributed and stored in four memories 530. On the other hand, in the target layer, the memory size calculated in step S16 of FIG. 8 is 38400 bytes (9600 × 4), and the arrangement pattern is distributed. The memory size for each memory 530 used in the processing instruction for executing the calculation of the target layer is 9600 bytes, and in the determinations in steps S20 and S24 of FIG. 8, the arrangement patterns match, but the memory sizes do not match.

Therefore, in step S22 of FIG. 8, the data size changing unit 412 replaces the first memory area holding the output data of the previous layer with the second memory corresponding to the memory size specified in the processing instruction. An area is newly secured in each memory 530. Then, the data size changing unit 412 transfers the output data of the previous layer to the newly secured second memory area.

As a result, in the learning in the target layer, the memory size of the memory area in which the input data is stored can be matched with the memory size corresponding to the processing instruction, and the learning of the target layer by the processor 500 is normally executed. can do.

Note that the same as in FIG. 9B even when the data arrangement pattern is a copy type and the memory size of the memory area of each memory 530 for storing the output data which is the calculation result of the previous layer is smaller than 38400 bytes. Processing is done. That is, the data size changing unit 412 newly secures a memory area corresponding to the memory size (38400 bytes), which is the specification of the processing instruction, in each memory 530 instead of the memory area holding the output data of the previous layer. To do. Then, the data size changing unit 412 transfers the output data (copy type) of the previous layer to the newly secured memory area.

As a result, in the learning in the target layer, the memory size of the memory area in which the input data is stored can be matched with the memory size which is the specification of the processing instruction, and the learning of the target layer by the processor 500 can be performed normally. Can be executed.

If the memory size of the memory area that holds the input data does not match the memory size that is the specification of the processing instruction that executes the operation of the target layer, and if a new memory area is not secured, the target layer An error occurs when executing an operation. Therefore, it becomes difficult to execute the learning of the neural network.

FIG. 10 shows another example of the operation during learning in the layer to be learned of the neural network in the information processing apparatus of FIG. A detailed description of the same operation as in FIG. 9 will be omitted. FIG. 10 shows an example of the operation during learning of the neural network that recognizes the image as in FIG. 9, and the number of elements in each dimension is batch size N = 32, color C = 3, number of pixels W = 10, and so on. It is assumed that the number of pixels H = 10 and the data is a single precision floating point number.

It is assumed that the data arrangement pattern of the target layer is a copy type, and the size of the input data (tensor data) input to the target layer is 38400 bytes (9600 × 4). Further, in FIG. 10A, it is assumed that the data arrangement pattern of the front layer is a copy type, and in FIG. 10B, the data arrangement pattern of the front layer is a distributed type.

In FIG. 10A, since the output data (tensor data) of the front layer is 38400 bytes (9600 × 4), the processor 500 transfers the 38400 bytes of output data, which is the calculation result, to each of the four memories 530. Store. In the target layer, the memory size calculated in step S16 of FIG. 8 is 38,400 bytes, and the arrangement pattern is a copy type. Therefore, in the determination in steps S20 and S24 of FIG. 8, the memory size and the arrangement pattern also match, and the memory size and the arrangement pattern are not changed.

Then, the processor 500 executes learning of the target layer using the calculation result of the previous layer stored in the memory 530 as input data. In this way, if the arrangement pattern of the data used for learning the target layer matches the arrangement pattern specified by the processing instruction used for learning the target layer, and the memory size matches, the memory area is used as it is. Can execute processing instructions. Similar to FIG. 9A, since there is no preprocessing such as securing a memory area after the calculation of the previous layer and before the calculation of the target layer is executed, the learning of the target layer is performed without lowering the learning efficiency. It is possible to execute the operation of the processing instruction.

In FIG. 10B, the memory area for the output data (tensor data) of the previous layer is secured as a distributed type, and the memory size is 9600 bytes for each memory 530. The processor 500 distributes and stores the output data (9,600 bytes) of the previous layer in each memory 530. Therefore, in the determination in steps S20 and S24 of FIG. 8, the memory size and the arrangement pattern do not match.

Therefore, in steps S22 and S26 of FIG. 8, a memory area (third memory area) corresponding to the memory size and the arrangement pattern (copy type), which are the specifications of the processing instruction, is newly secured in each memory 530. Then, the output data of the previous layer is transferred to the newly secured third memory area in a copy type.

As a result, the memory size / allocation pattern of the memory area in which the input data is stored can be matched with the memory size / allocation pattern corresponding to the processing instruction by learning in the target layer, and the target by the processor 500 can be matched. Layer learning can be performed normally. Even when the output data of the previous layer is a copy type and the processing instruction specifications are distributed type, a third memory area having a memory size corresponding to the distributed type is newly secured and the data is transferred as the distributed type. By doing so, the same processing as in FIG. 10B can be performed.

For example, when the arrangement pattern of the output data of the previous layer is a distributed type and the arrangement pattern of the input data of the target layer is a copy type, the data used for the calculation in each calculation core 510 is insufficient, so that the target An error occurs when performing a layer operation. Therefore, it becomes difficult to execute the learning of the neural network.

As described above, even in the embodiments shown in FIGS. 3 to 10, the same effects as those in the embodiments shown in FIGS. 1 and 2 can be obtained. For example, if the memory size of the memory area that holds the training data and the memory size calculated based on the batch size specified by the processing instruction do not match, a new memory area of the memory size corresponding to the processing instruction is secured. And transfer the training data. As a result, the memory size of the memory area where the input data is stored can be matched with the memory size corresponding to the processing instruction, and even if an arbitrary batch size is specified, an error does not occur. You can perform learning.

Further, in the embodiment shown in FIGS. 3 to 10, when the arrangement patterns of the learning data and the processing instruction do not match, a new memory area is secured and the learning data is matched with the arrangement pattern specified by the processing instruction. Transfer to a new memory area. As a result, the memory size / allocation pattern of the memory area in which the input data is stored can be matched with the memory size / allocation pattern which is the specification of the processing instruction, and the learning of the target layer by the processor 500 can be performed normally. Can be executed.

If the memory size of the memory area that holds the data used for learning the target layer matches the memory size calculated based on the batch size specified by the processing instruction used for learning the target layer, the memory area is selected. The processing instruction can be executed by using it as it is. If the data used for learning the target layer matches the placement pattern specified by the processing instruction used for learning the target layer and the memory size matches, the memory area is used as it is for processing. Instructions can be executed. In these cases, since there is no preprocessing such as securing a memory area after the operation of the previous layer and before the operation of the target layer is executed, the operation of the processing instruction is performed in the learning of the target layer without lowering the learning efficiency. Can be executed.

As a result, even if an arbitrary batch size is specified, learning can be executed without causing an error.

FIG. 11 shows an example of an information processing apparatus according to another embodiment. Detailed description of the same elements as those in FIGS. 1 and 3 will be omitted. The information processing device 100B shown in FIG. 11 is, for example, a server, and has a host CPU 200, a host memory 300, an I / O controller 220, and a processor 500, as in FIG. 1. The host CPU 200 controls the overall operation of the information processing device 100B by executing various programs stored in the host memory 300, controls the operation of the processor 500, and learns the neural network using the learning data. Execute. The host memory 300 of FIG. 11 stores the host program 400B instead of the host program 400A of FIG.

The host program 400B for causing the neural network to execute an operation has a framework 410 for deep learning (DL), a library 420 for a deep neural network (DNN), and a runtime library 430.

The DL framework 410 includes a calculation type determination unit 411, a data size change unit 412, an inquiry unit 413, a conversion / transfer instruction unit 414, and an execution instruction unit 415. The functions of the calculation type determination unit 411, the data size change unit 412, and the conversion / transfer instruction unit 414 are the same as the functions of the calculation type determination unit 411, the data size change unit 412, and the conversion / transfer instruction unit 414 shown in FIG. Is. The functions of the inquiry unit 413 and the execution instruction unit 415 will be described with reference to FIG.

The DNN library 420 has an information management unit 421, an arithmetic processing prediction unit 422, and a file 423 in which processing instructions are stored. The function of the information management unit 421 is the same as the function of the information management unit 421 shown in FIG. The functions of the arithmetic processing prediction unit 422 will be described with reference to FIGS. 12 and 13.

The runtime library 430 has a conversion / transfer execution unit 431 and a processing instruction execution unit 432. The runtime library 430 is an interface for causing the processor 500 to execute an operation, and is designed according to the specifications of the processor 500. For example, the runtime library 430 executes a control for causing a plurality of arithmetic cores 510 to execute an operation in parallel. The functions of the conversion / transfer execution unit 431 and the processing instruction execution unit 432 will be described with reference to FIG.

FIG. 12 shows an example of the function realized by the host CPU 200 of FIG. 11 executing the host program 400B. In the following, in a deep neural network having a plurality of layers, the operation when learning the target layer, which is the layer to be learned, is described. A detailed description of the same functions and operations as those described in the above-described embodiment will be omitted.

When the DL framework 410 receives an instruction to execute learning of the target layer, the DL framework 410 causes the calculation type determination unit 411 to determine the calculation type. After that, the conversion / transfer instruction unit 414 gives an instruction to secure a memory area used for the calculation in each memory 530 based on the batch size specified by the user, the size of the input / output data, the arrangement pattern, and the like. Issued at 430. The size and arrangement pattern of the input / output data are obtained based on the specifications of the neural network stored in the user-defined file 310 and the learning data.

Further, the conversion / transfer instruction unit 414 issues an instruction to transfer the learning data used for the calculation to the run-time library 430 to the memory area secured in each memory 530. As in the above-described embodiment, when the output data of the previous layer, which is the layer before the target layer, is held in the memory 530 as the input data of the target layer, the conversion / transfer instruction unit 414 is in the memory area. Do not issue secure and learn data transfer instructions, and do not issue data transfer instructions.

The conversion / transfer execution unit 431 of the runtime library 430 allocates the memory area of the memory 530 based on the instruction of the conversion / transfer instruction unit 414 to secure the memory area, and issues a completion notification to the DL framework 410. Further, the conversion / transfer execution unit 431 transfers the learning data to the reserved memory area based on the data transfer instruction from the conversion / transfer instruction unit 414, and issues a completion notification to the DL framework 410.

The inquiry unit 413 notifies the information management unit 421 of the DNN library 420 of the calculation type and the batch size specified by the user, and inquires about the processing instruction used for learning the target layer. Further, the inquiry unit 413 notifies the information management unit 421 of the number of elements in each dimension, and inquires about the memory size used in the processing instruction used for learning the target layer. Further, the inquiry unit 413 notifies the arithmetic processing prediction unit 422 of the memory size and the arrangement pattern of the memory area secured in the runtime library 430, and inquires about the arithmetic method capable of executing the arithmetic at a higher speed.

The information management unit 421 holds the specification information of each processing instruction shown in FIG. 5, searches for a processing instruction suitable for learning of the target layer, and responds to the inquiry unit 413. At this time, the information management unit 421 notifies the inquiry unit 413 of the number of corresponding batches of the processing instructions found by the search and the data arrangement pattern for each tensor data. Further, the information management unit 421 determines the memory size used for executing the learning (calculation) of the target layer by the processing instruction found by the search, based on the batch size notified from the inquiry unit 413 and the number of elements in each dimension. calculate. Then, the information management unit 421 notifies the inquiry unit 413 of the calculated memory size.

The arithmetic processing prediction unit 422 notifies the inquiry unit 413 of an arithmetic method capable of executing the arithmetic at a higher speed based on the inquiry from the inquiry unit 413. The arithmetic processing prediction unit 422 calculates whether the processing instruction is executed without changing the memory size and the allocation pattern, or the processing instruction is executed by changing one or both of the memory size and the allocation pattern. Notify the inquiry unit 413 whether the efficiency is high. The function of the arithmetic processing prediction unit 422 will be described with reference to FIG.

The inquiry unit 413 holds the processing instruction notified from the information management unit 421. Further, when the calculation processing prediction unit 422 notifies that the calculation efficiency is higher when the memory size or the arrangement pattern is changed, the inquiry unit 413 changes the memory size or the arrangement pattern. That is, the match / mismatch between the memory size corresponding to the processing instruction and the memory size of the memory area is determined, and the match / mismatch between the arrangement pattern specified by the processing instruction and the arrangement pattern of the data held in the memory area is determined. Judgment is made and processing is executed according to the judgment result.

On the other hand, when the calculation processing prediction unit 422 notifies that the calculation efficiency is higher when the memory size or the arrangement pattern is not changed, the inquiry unit 413 determines the memory size match / mismatch and the arrangement pattern match / mismatch. Do not execute the judgment. In this case, the DL framework 410 causes the arithmetic core 510 to execute the arithmetic of the processing instruction by using the data held in the current memory area.

The inquiry unit 413 determines whether or not the memory size notified from the information management unit 421 matches the memory size of the memory area reserved for each memory 530 in consideration of the arrangement pattern. When the memory sizes do not match, the inquiry unit 413 instructs the data size change unit 412 to change the memory size.

Further, the inquiry unit 413 determines whether or not the arrangement pattern notified from the information management unit 421 matches the arrangement pattern used when transferring the learning data to the memory area. When the arrangement patterns do not match, the inquiry unit 413 issues an instruction to the data size change unit 412 to newly secure the memory area with the arrangement pattern notified from the information management unit 421. Further, when the memory size does not match or the arrangement pattern does not match, the inquiry unit 413 converts an instruction to transfer the learning data used for learning the target layer to the newly secured memory area 414. Issued to.

Based on the instruction from the inquiry unit 413, the data size change unit 412 issues an instruction to the runtime library 430 to secure a memory area of the memory size notified from the information management unit 421 in each memory 530. The runtime library 430 allocates a new memory area in each memory 530 based on the instruction from the data size change unit 412, and issues a completion notification to the data size change unit 412.

Based on the instruction from the inquiry unit 413, the conversion / transfer instruction unit 414 sends an instruction to transfer the learning data used for learning the target layer to the newly secured memory area to the conversion / transfer execution unit 431 of the runtime library 430. Issue. The conversion / transfer execution unit 431 transfers the learning data from the user-defined file 310 to the newly secured memory area based on the instruction from the conversion / transfer instruction unit 414, and issues a completion notification to the conversion / transfer instruction unit 414. To do.

When the learning data used for learning the target layer is held in the memory 530 according to the arrangement pattern, the execution instruction unit 415 of the DL framework 410 specifies a processing instruction and executes the processing instruction in the DNN library 420. Instruct. The DNN library 420 instructs the processing instruction execution unit 432 of the runtime library 430 to execute the processing instruction based on the instruction from the execution instruction unit 415. Then, the processing instruction execution unit 432 transfers the processing instruction to the memory 530 of the arithmetic core 510 that executes the learning operation of the target layer, and causes the arithmetic core 510 to execute the processing instruction. As a result, learning of the target layer is executed.

FIG. 13 shows the relationship between the memory size and the allocation pattern of the memory area secured in the memory 530 and the memory size and the allocation pattern corresponding to the processing instructions used in the learning of the layer to be learned. Based on the relationship shown in FIG. 13, the arithmetic processing prediction unit 422 of FIGS. 11 and 12 determines whether the processing instruction can be executed without changing the memory size and the arrangement pattern, and determines the arithmetic method having higher arithmetic efficiency. To do.

The processing instruction used in the learning of the target layer is a processing instruction selected by the information management unit 421 of the DNN library 420 based on the inquiry from the DL framework 410. The memory area secured in the memory 530 has a memory size calculated in consideration of the arrangement pattern based on the specifications of the neural network and the learning data stored in the user-defined file 310. When the target layer is the second layer or later, the memory size and arrangement pattern of the memory area may be the memory size and arrangement pattern of the memory area that holds the output data obtained by learning the previous layer.

If both the memory size and the allocation pattern match the already allocated memory area and the memory size and allocation pattern corresponding to the processing instruction, the operation can be performed without changing the memory size and the allocation pattern (). Computable patterns 1, 2).

When the memory size of the memory area is larger than the memory size corresponding to the processing instruction, the operation can be executed without changing the memory size of the secured memory area by executing the processing instruction multiple times (calculation is possible). Patterns 4, 5, 6). However, since the processing instruction is executed a plurality of times, the calculation time increases depending on the number of times the processing instruction is executed. At this time, since the data in the memory area that does not hold the valid data used for learning is meaningless data, the output data that is the calculation result is not used for the next learning.

If the memory size of the memory area is larger than the memory size corresponding to the processing instruction, the memory size of the memory area is re-allocated according to the memory size corresponding to the processing instruction, and the data is transferred to the re-allocated memory area. , The operation may be performed. However, in this case, the time for reallocating the memory area and the time for transferring the data to the re-allocated memory area are different from the execution time of the processing instruction.

When the memory area allocation pattern is copy type and the allocation pattern specified by the processing instruction is distributed, the operation can be executed without changing the allocation pattern by executing the operation of the distributed processing instruction multiple times. Is possible (calculable patterns 3 and 6). For example, as shown in FIG. 7, when the four data D1-D4 are calculated by the four calculation cores 510, the calculation time is four times longer when the data arranged in the copy type is executed by the distributed processing instruction. ..

If the already allocated memory area and the allocation pattern specified by the processing instruction are different from each other, the memory area of the memory size corresponding to the allocation pattern specified by the processing instruction is re-allocated and the re-allocated memory area is used. After transferring the data, the operation may be performed. However, in this case, the time for reallocating the memory area and the time for transferring the data to the re-allocated memory area are different from the execution time of the processing instruction.

If the memory size of the memory area already reserved is smaller than the memory size corresponding to the processing instruction, an error occurs due to the execution of the processing instruction, so the memory area corresponding to the memory size corresponding to the processing instruction is re-allocated. Will be done. Also, if the placement pattern of the learning data held by the memory area already secured is distributed and the placement pattern specified by the processing instruction is copy type, the operation will not be executed correctly, so the placement pattern specified by the processing instruction will not be executed correctly. The memory area of the memory size according to is re-allocated.

From the above, in order to improve the calculation efficiency, for the pattern 3-6 that can be calculated, the calculation time when the processing instruction is executed multiple times and the processing instruction are executed after reallocating the memory area and transferring the data. It is determined which is faster than the calculation time when the operation is performed. For example, the condition shown in the equation (1) is used for the determination.
(Calculation time when the memory size is not changed) <(Time required for changing the memory size and transferring data) + (Calculation time) ‥ (1)
For example, when the arithmetic processing prediction unit 422 satisfies the condition shown in the equation (1), it is better to execute the arithmetic without changing the memory size and the allocation pattern, and to execute the arithmetic by changing the memory size and the allocation pattern. It is judged that the calculation efficiency is higher than that. Further, when the arithmetic processing prediction unit 422 does not satisfy the condition shown in the equation (1), it is better to change the memory size and the allocation pattern to execute the arithmetic, and to execute the arithmetic without changing the memory size and the allocation pattern. It is judged that the calculation efficiency is higher than that.

FIG. 14 shows an example of the operation when the information processing apparatus 100B of FIG. 11 executes the learning of the neural network. The operation shown in FIG. 14 is realized by the host CPU 200 executing the host program 400B. That is, FIG. 14 shows an example of an information processing program and an information processing method. Detailed description of the same operation as in FIG. 8 and the operation described in FIG. 12 will be omitted.

In FIG. 14, steps S17 and S18 are inserted between steps S16 and S20 of FIG. The operations of steps S10, S12, S14, S16, S20, S22, S24, S26, and S28 are the same as those in FIG.

In step S17, the arithmetic processing prediction unit 422 compares the memory size and allocation pattern corresponding to the processing instruction selected in step S16 with the memory size and allocation pattern secured in step S12. Then, the arithmetic processing prediction unit 422 determines whether or not the memory size and the arrangement pattern are the arithmetically operable patterns shown in FIG. If the calculation can be performed without changing the memory size and the arrangement pattern, the process proceeds to step S18. When the calculation cannot be performed without changing the memory size and the arrangement pattern, the calculation processing prediction unit 422 re-allocates the memory area and transfers the learning data to the re-allocated memory area, so that the calculation efficiency is higher. Notify 413. Then, the process proceeds to step S20.

In step S18, the arithmetic processing prediction unit 422 compares the arithmetic efficiency of the case where the memory size of the memory area and the arrangement pattern are changed and the case where the arrangement pattern is not changed, for example, using the condition of the equation (1). When the condition of the equation (1) is satisfied, the arithmetic processing prediction unit 422 determines that the arithmetic efficiency is higher if the memory size (arrangement pattern) is not changed, and shifts the processing to step S28. When the calculation processing prediction unit 422 does not satisfy the condition of the equation (1), the calculation processing prediction unit 422 determines that changing the memory size (arrangement pattern) has higher calculation efficiency, and shifts the processing to step S20.

In this way, even if the memory size or arrangement pattern does not match, if the calculation can be executed without changing the memory size and the calculation efficiency is higher than changing the memory size, the memory size is not changed. By executing the calculation, the learning time can be shortened. Moreover, the calculation method having high calculation efficiency can be easily determined by using the equation (1).

As described above, even in the embodiments shown in FIGS. 11 to 14, the same effects as those in the embodiments shown in FIGS. 1 to 10 can be obtained. For example, when the memory size of the memory area for holding the training data and the memory size calculated in response to the processing instruction do not match, the processor 500 targets by securing a new memory area according to the processing instruction. Layer learning can be performed normally. Further, when the arrangement patterns of the learning data and the processing instructions do not match, the learning of the target layer by the processor 500 can be normally executed by allocating a new memory area according to the arrangement pattern of the processing instructions. As a result, even if an arbitrary batch size is specified, learning can be executed without causing an error.

Further, in the embodiment shown in FIGS. 11 to 14, when the memory size of the memory area secured in advance and the memory size corresponding to the processing instruction are different, it is determined that the calculation is possible without changing the memory size. Then, when the calculation can be performed without changing the memory size, the calculation method having high calculation efficiency is determined, and the calculation is executed based on the determination result. Further, when the arrangement pattern of the learning data held in the memory area secured in advance and the arrangement pattern specified by the processing instruction are different, it is determined that the calculation is possible without changing the memory size and the arrangement pattern. Then, when the calculation can be performed without changing the memory size and the arrangement pattern, the calculation method having high calculation efficiency is determined, and the calculation is executed based on the determination result. As a result, learning can be executed by a calculation method with high calculation efficiency, and the learning time of the neural network can be shortened.

FIG. 15 shows an example of executing a processing instruction in the information processing apparatus according to another embodiment. The configuration of the information processing device 100C shown in FIG. 15 is the same as the configuration of the information processing device 100B shown in FIG.

In FIG. 15, the scale of the neural network and the amount of training data stored in the user-defined file 310 are both smaller than the scale of the neural network and the amount of training data learned by the information processing apparatus 100B shown in FIG. Therefore, the learning of the neural network can be executed by one arithmetic core 510. In this case, by not executing the parallel calculation by the plurality of calculation cores 510, the power consumption of the processor 500 can be reduced as compared with the case where the plurality of calculation cores 510 are operated.

The learning of the neural network by the information processing apparatus 100C is executed in the same manner as in FIG. However, when learning is executed by one arithmetic core 510, all the data used for learning is stored in one memory 530, so it is not necessary to consider the arrangement pattern. Therefore, in the information processing apparatus 100C, the processes of steps S24 and S26 of FIG. 14 are omitted, and in step S17 of FIG. 14, if the memory size of the memory area is equal to or larger than the memory size corresponding to the processing instruction, it is determined that the calculation is possible. To.

In the information processing device 100 shown in FIG. 1 or the information processing device 100A shown in FIG. 3, the neural network learning may be executed by one arithmetic core 510 in the same manner as in the information processing device 100C. In this case, the information processing devices 100 and 100A execute the operation shown in FIG. 2 or the operation shown in FIG. 8 with one calculation core 510 as the calculation target. However, when learning is executed by one arithmetic core 510, the processing of steps S24 and S26 in FIG. 8 is omitted because it is not necessary to consider the arrangement pattern.

As described above, also in this embodiment, the same effect as that of the embodiment shown in FIGS. 1 to 14 can be obtained.

FIG. 16 shows an example of executing a processing instruction in the information processing apparatus according to still another embodiment. The configuration of the information processing device 100D shown in FIG. 15 is the same as the configuration of the information processing device 100B shown in FIG.

In FIG. 16, learning of a plurality of neural networks in which configuration information is stored in a plurality of user-defined files 310 (1, 2, 3) is executed in parallel. That is, the scale of the neural network and the amount of training data stored in each user-defined file 310 are both smaller than the scale of the neural network and the amount of training data learned by the information processing apparatus 100B shown in FIG.

The learning of the neural network of the user-defined file 1 is executed by the two arithmetic cores 510 in the same manner as in FIG. The learning of each of the neural networks of the user-defined files 2 and 3 is executed by one arithmetic core 510 in the same manner as in the embodiment shown in FIG. For example, a 400B (FIG. 11) including the DL framework 410, the DNN library 420, and the runtime library 430 is provided for each user.

In the information processing device 100 shown in FIG. 1 or the information processing device 100A shown in FIG. 3, the learning of the neural networks of a plurality of users may be executed in parallel in the same manner as in the information processing device 100D. In this case, the information processing devices 100 and 100A execute the operation shown in FIG. 2 or the operation shown in FIG. 8 for each user. However, when learning is executed by one arithmetic core 510, the processing of steps S24 and S26 in FIG. 8 is omitted because it is not necessary to consider the arrangement pattern.

As described above, in this embodiment, the same effect as that of the embodiment shown in FIGS. 1 to 14 can be obtained.

The following additional notes will be further disclosed with respect to the embodiments shown in FIGS. 1 to 16 described above.
(Appendix 1)
An information processing program that controls learning of a neural network including a plurality of layers executed by a processor having one or more arithmetic units including an arithmetic unit and a memory for holding data used in the arithmetic unit.
Based on the size of the training data used for learning the layer to be learned and the input batch size, a processing instruction to be executed by the processor is selected from a plurality of processing instructions having different batch sizes to be processed.
Based on the size of the training data and the batch size specified by the selected processing instruction, the memory size used for training the layer to be trained is calculated.
When the memory size of the first memory area of the memory that holds the training data does not match the calculated memory size, a second memory area having the calculated memory size is secured in the memory and the training data. An information processing program that causes an information processing apparatus to execute processing by causing the processor to execute the selected processing instruction using the learning data transferred to the second memory area.
(Appendix 2)
As an arrangement pattern for arranging the learning data in the memory, a distributed type in which the learning data is distributed and arranged in the memories of a plurality of the calculation units, and a distribution type in which the learning data is distributed and arranged in the memories of the plurality of calculation units are duplicated. Has a duplicate type to be placed
When the arrangement pattern of the training data held in the first memory area does not match the arrangement pattern used in the selected processing instruction, a third memory area is secured in the memory and the selected processing instruction is used. Information processing that transfers the training data to the third memory area in the arrangement pattern used in the above-mentioned third memory area, and causes the processor to execute the selected processing instruction using the learning data transferred to the third memory area. The information processing program according to Appendix 1, which is executed by a processing device.
(Appendix 3)
When the memory size of the first memory area matches the calculated memory size, a process of causing the processor to execute the selected processing instruction using the learning data held in the first memory area. The information processing program according to Appendix 1 or Appendix 2, which causes the information processing apparatus to execute the above.
(Appendix 4)
The arrangement pattern of the training data held in the first memory area matches the arrangement pattern used in the selected processing instruction, and the memory size of the first memory area is the calculated memory size. If the information matches, the information according to Appendix 1 or Appendix 2, which causes the information processing apparatus to execute a process of causing the processor to execute the selected processing instruction using the learning data held in the first memory area. Processing program.
(Appendix 5)
When the memory size of the first memory area is larger than the calculated memory size, the learning data held in the first memory area is used to execute the selected processing instruction, and the first. The calculation efficiency of the case where the memory area of 2 is secured, the learning data is transferred, and the selected processing instruction is executed is calculated.
The information processing program according to any one of Supplementary note 1 to Supplementary note 4, wherein the information processing apparatus is made to execute a process of causing the processor to execute the selected processing instruction, whichever has higher calculation efficiency.
(Appendix 6)
When the learning data is held in the first memory area in the duplicate type and the data arrangement pattern of the selected processing instruction is the distributed type, the learning data held in the first memory area is stored. Calculates the calculation efficiency between the case where the selected processing instruction is executed by using the third memory area and the case where the learning data is transferred in the distributed type and the selected processing instruction is executed. And
The information processing program according to Appendix 2, wherein the information processing apparatus is made to execute a process of causing the processor to execute the selected processing instruction with higher calculation efficiency.
(Appendix 7)
The calculation efficiency is the calculation time when the selected processing instruction is executed using the learning data held in the first memory area, or the learning data is transferred by securing a new memory area. The information processing according to Appendix 5 or Appendix 6, which is indicated by the sum of the time to be processed and the calculation time when the selected processing instruction is executed using the learning data held in the newly secured memory area. program.
(Appendix 8)
The information according to any one of Appendix 1 to Appendix 7, which determines the match / mismatch of the memory size for each of the input tensor data input to the learning target layer and the output tensor data output from the learning target layer. Processing program.
(Appendix 9)
The information according to any one of Supplementary note 2 to Appendix 8 that determines the match / mismatch of the arrangement pattern for each of the input tensor data input to the learning target layer and the output tensor data output from the learning target layer. Processing program.
(Appendix 10)
Based on the configuration information of the neural network, the calculation method used for learning the layer to be learned is selected.
The information processing program according to any one of Supplementary note 1 to Supplementary note 9, wherein a processing instruction to be executed by the processor is selected from the plurality of processing instructions corresponding to the determined calculation method.
(Appendix 11)
An information processing method that controls learning of a neural network including a plurality of layers executed by a processor having one or more arithmetic units including an arithmetic unit and a memory for holding data used in the arithmetic unit.
Based on the size of the training data used for learning the layer to be learned and the input batch size, a processing instruction to be executed by the processor is selected from a plurality of processing instructions having different batch sizes to be processed.
Based on the size of the training data and the batch size specified by the selected processing instruction, the memory size used for training the layer to be trained is calculated.
When the memory size of the first memory area of the memory that holds the training data does not match the calculated memory size, a second memory area having the calculated memory size is secured in the memory and the training data. An information processing method for causing an information processing apparatus to execute processing by causing the processor to execute the selected processing instruction by using the learning data transferred to the second memory area.

The above detailed description will clarify the features and advantages of the embodiments. It is intended that the claims extend to the features and advantages of the embodiments as described above, without departing from their spirit and scope of rights. Also, anyone with ordinary knowledge in the art should be able to easily come up with any improvements or changes. Therefore, there is no intention to limit the scope of the embodiments having invention to those described above, and it is possible to rely on suitable improvements and equivalents included in the scope disclosed in the embodiments.

100, 100A, 100B, 100C, 100D Information processing device 200 Host CPU
220 I / O controller 300 Host memory 310 User-defined file 311 Neural network 312 Learning data 400, 400A, 400B Host program 410 DL framework 411 Calculation type determination unit 412 Data size change unit 413 Inquiry unit 414 Conversion / transfer instruction unit 415 Execution Instructor 420 DNN library 421 Information management unit 422 Arithmetic processing prediction unit 423 Processing instruction 430 Runtime library 431 Conversion / transfer execution unit 432 Processing instruction execution unit 500 Processor 510 Arithmetic core 520 Arithmetic core 530 Memory

Claims (8)

An information processing program that controls learning of a neural network including a plurality of layers executed by a processor having one or more arithmetic units including an arithmetic unit and a memory for holding data used in the arithmetic unit.
Based on the size of the training data used for learning the layer to be learned and the input batch size, a processing instruction to be executed by the processor is selected from a plurality of processing instructions having different batch sizes to be processed.
Based on the size of the training data and the batch size specified by the selected processing instruction, the memory size used for training the layer to be trained is calculated.
When the memory size of the first memory area of the memory that holds the training data does not match the calculated memory size, a second memory area having the calculated memory size is secured in the memory and the training data. An information processing program that causes an information processing apparatus to execute processing by causing the processor to execute the selected processing instruction using the learning data transferred to the second memory area. As an arrangement pattern for arranging the learning data in the memory, a distributed type in which the learning data is distributed and arranged in the memories of a plurality of the calculation units and a distribution type in which the learning data is distributed and arranged in the memories of the plurality of calculation units are duplicated. Has a duplicate type to be placed
When the arrangement pattern of the training data held in the first memory area does not match the arrangement pattern used in the selected processing instruction, a third memory area is secured in the memory and the selected processing instruction is used. Information processing that transfers the training data to the third memory area in the arrangement pattern used in the above-mentioned third memory area, and causes the processor to execute the selected processing instruction using the learning data transferred to the third memory area. The information processing program according to claim 1, which is executed by a processing device. When the memory size of the first memory area matches the calculated memory size, a process of causing the processor to execute the selected processing instruction using the learning data held in the first memory area. The information processing program according to claim 1 or 2, wherein the information processing apparatus is executed. The arrangement pattern of the training data held in the first memory area matches the arrangement pattern used in the selected processing instruction, and the memory size of the first memory area is the calculated memory size. 1 or 2 according to claim 1 or 2, wherein the information processing apparatus is made to execute the process of causing the processor to execute the selected processing instruction by using the learning data held in the first memory area. Information processing program. When the memory size of the first memory area is larger than the calculated memory size, the learning data held in the first memory area is used to execute the selected processing instruction, and the first. The calculation efficiency of the case where the memory area of 2 is secured, the learning data is transferred, and the selected processing instruction is executed is calculated.
The information processing program according to any one of claims 1 to 4, wherein the information processing apparatus is made to execute a process of causing the processor to execute the selected processing instruction with higher calculation efficiency. When the learning data is held in the first memory area in the duplicate type and the data arrangement pattern of the selected processing instruction is the distributed type, the learning data held in the first memory area is stored. Calculates the calculation efficiency between the case where the selected processing instruction is executed by using the third memory area and the case where the learning data is transferred in the distributed type and the selected processing instruction is executed. And
The information processing program according to claim 2, wherein the information processing apparatus causes the information processing apparatus to execute a process of causing the processor to execute the selected processing instruction with higher calculation efficiency. The calculation efficiency is the calculation time when the selected processing instruction is executed using the learning data held in the first memory area, or the learning data is transferred by securing a new memory area. The fifth or sixth aspect of the present invention, which is represented by the sum of the time to be processed and the calculation time when the selected processing instruction is executed using the learning data held in the newly secured memory area. Information processing program. An information processing method that controls learning of a neural network including a plurality of layers executed by a processor having one or more arithmetic units including an arithmetic unit and a memory for holding data used in the arithmetic unit.
Based on the size of the training data used for learning the layer to be learned and the input batch size, a processing instruction to be executed by the processor is selected from a plurality of processing instructions having different batch sizes to be processed.
Based on the size of the training data and the batch size specified by the selected processing instruction, the memory size used for training the layer to be trained is calculated.
When the memory size of the first memory area of the memory that holds the training data does not match the calculated memory size, a second memory area having the calculated memory size is secured in the memory and the training data. An information processing method for causing an information processing apparatus to execute processing by causing the processor to execute the selected processing instruction by using the learning data transferred to the second memory area.

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