JP2021040090A - Printed wiring board and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a variation in height between bumps having different sizes in a printed wiring board. SOLUTION: A base insulating layer, a conductor layer formed on the base insulating layer, and a part of the conductor layer formed on the base insulating layer and the conductor layer and exposed as a first conductor pad. A solder resist layer having one opening and a second opening that is smaller in diameter than the first opening and exposes the other part of the conductor layer as a second conductor pad, and formed on the first conductor pad. A first bump and a second bump formed on the second conductor pad having a diameter smaller than that of the first bump are provided, and the first bump is formed on the first plating post. It has a substantially hemispherical first top plating layer, and the second bump has a substantially hemispherical second top plating layer formed on the second plating post, and the first plating post. The upper surface of the first bump and the second plating post are flat and the heights are the same as each other, and the heights of the first bump and the second bump are the same as each other. [Selection diagram] Fig. 1

Description

The present invention relates to a printed wiring board having plated bumps and a method for manufacturing the printed wiring board.

Patent Document 1 discloses bump formation using a plating method.

JP-A-2010-129996

However, as shown in FIG. 4, the base plating layers 24'and 30'are formed on the conductor pads 14a' and 14b' in the openings 16a'and 16b' of different sizes formed in the solder resist layer 16'. On the base plating layers 24'and 30', top plating layers 28' and 32' were formed via intermediate layers 26' and 31' to form plating bumps 20' and 22'of different sizes. In this case, height variation V may occur between the plating bump 20'and the plating bump 22'.

The printed wiring board according to the present invention includes a base insulating layer, a conductor layer formed on the base insulating layer, and a part of the conductor layer formed on the base insulating layer and the conductor layer. A solder resist layer having a first opening exposed as a first conductor pad and a second opening smaller in diameter than the first opening and exposing another part of the conductor layer as a second conductor pad. A first bump formed on the first conductor pad and a second bump formed on the second conductor pad and having a diameter smaller than that of the first bump are provided.
The first bump is composed of a first base plating layer formed in the first opening and a first post integrally formed on the first base plating layer with the same metal as the first base plating layer. It has a plating post of 1 and a first top plating layer having a substantially hemispherical shape formed on the first plating post.
The second bump is composed of a second base plating layer formed in the second opening and a second post integrally formed on the second base plating layer with the same metal as the second base plating layer. Has a substantially hemispherical second top plating layer formed on the second plating post.
The first plating post and the second plating post have flat upper surfaces, are flush with each other, and have the same height.
The heights of the first bump and the second bump are the same as each other.

Further, the method for manufacturing a printed wiring board according to the present invention includes forming a base insulating layer, forming a conductor layer on the base insulating layer, and solder resist on the base insulating layer and the conductor layer. Forming a layer, forming a first opening in the solder resist layer for exposing a part of the conductor layer as a first conductor pad, and forming a first opening in the solder resist layer from the first opening. To form a second opening having a small diameter and to expose another part of the conductor layer as a second conductor pad, to form a first bump on the first conductor pad, and to form the first bump. Including forming a second bump having a diameter smaller than that of the first bump on the second conductor pad.
To form the first bump, the first base plating layer is formed in the first opening, and the same metal as the first base plating layer is integrally formed on the first base plating layer. Forming a post to form a first plating post, forming a first top plating layer on the first plating post, and reflowing the first top plating layer to form a substantially hemisphere. Including forming a first top plating layer in the form of
Forming the second bump means forming a second base plating layer in the second opening and integrally using the same metal as the second base plating layer on the second base plating layer. Forming the second post to form the second plating post, forming the second top plating layer on the second plating post, and reflowing the second top plating layer to form a substantially hemisphere. Including forming a second top plating layer in the shape
Forming the first plating post and the second plating post includes aligning the heights of the first plating post and the second plating post with each other by polishing, and
Forming the first top plating layer and the second top plating layer means that the heights of the first top plating layer and the second top plating layer are adjusted to the height of the first top plating layer and the second top plating layer. This includes aligning the resists with each other by adjusting the opening diameter of the resists in forming the top plating layer of the above.

It is sectional drawing which shows the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of another Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said other Embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said other Embodiment. It is sectional drawing which shows the manufacturing method of the printed wiring board of the said other Embodiment. It is sectional drawing for demonstrating how the height variation occurs in the printed wiring board according to the prior art.

<About the printed wiring board of the present invention>
An embodiment of the printed wiring board of the present invention will be described with reference to the drawings. In FIG. 1, a part of the printed wiring board 10 of the embodiment is shown in an enlarged manner. The printed wiring board 10 may be a board with a core formed by alternately laminating conductor layers and resin insulating layers having a predetermined circuit pattern on one side or both sides of a core board (not shown). When the conductor layers are formed on both sides of the core substrate, the conductor layers facing each other via the core substrate may be connected to each other via a through-hole conductor (not shown). Alternatively, the printed wiring board 10 may be a coreless substrate obtained by alternately laminating conductor layers and resin insulating layers on a support plate (not shown) instead of the core substrate, and then removing the support plate. .. In any case, as shown in FIG. 1, the printed wiring board 10 is formed on the base insulating layer 12 and the base insulating layer 12, which are arranged on the outermost side of at least one resin insulating layer. A conductor layer 14 having a predetermined circuit pattern, and a solder resist layer 16 formed on the base insulating layer 12 and the conductor layer 14 are provided. In many cases, a plurality of other conductor layers and a resin insulating layer are alternately provided in the lower layer of the base insulating layer 12, but they are omitted in the drawing. However, the printed wiring board 10 may be composed of one layer of the base insulating layer 12 and one layer of the conductor layer 14.

The base insulating layer 12 can be made of, for example, a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin. The conductor layer 14 is formed of a conductive metal, for example, a metal containing copper as a main component.

The solder resist layer 16 has a first opening 16a that exposes a part of the conductor layer 14 as a first conductor pad 14a, and a second portion of the conductor layer 14 that is smaller in diameter than the first opening 16a. It has a second opening 16b to be exposed as the conductor pad 14b of the above. The aspect ratio of the first opening 16a, that is, the ratio of the depth to the diameter of the bottom can be 0.5 or less. The aspect ratio of the second opening 16b, that is, the ratio of the depth to the diameter of the bottom can be 0.6 or more.

The printed wiring board 10 is further formed on a first bump 20 formed on the first conductor pad 14a and a second bump 22 formed on the second conductor pad 14b and having a diameter smaller than that of the first bump 20. And have. The first and second bumps 20, 22 can be formed directly on the first and second conductor pads 14a, 14b. The first bump 20 can be used for connection with a power supply or a ground wire. The second bump 22 having a diameter smaller than that of the first bump 20 can be used for connection with the signal line.

An underlayer may be provided between the first and second conductor pads 14a and 14b and the first and second bumps 20 and 22. Examples of the base layer include a nickel layer formed on the surfaces of the first and second conductor pads 14a and 14b, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. it can. In addition, a nickel layer and a gold layer formed on the nickel layer can be exemplified.

The first bump 20 is a first plating post 24 composed of a first base plating layer formed in the first opening 16a and a substantially columnar first post integrated with the first base plating layer. And a first intermediate layer 26 composed of, for example, nickel as a main component on the first plating post 24, or a nickel layer, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. It has a substantially hemispherical first top plating layer 28 formed via the above. The thickness of the first intermediate layer 26 is preferably 7 μm or less.

The first base plating layer forming the first plating post 24 is formed of a conductive metal, preferably a metal containing copper as a main component. The first post, which also forms the first plating post 24, is formed of the same metal as the first base plating layer, that is, preferably a metal containing copper as a main component. The first base plating layer forming the first plating post 24 and the first post are sequentially formed and integrated with each other. The first plating post 24 is formed to a height sufficiently exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). As a result, the first bump 20 is stably held in the first opening 16a. The height B1 from the surface of the solder resist layer 16 to the upper end surface 24a of the first plating post 24 is preferably in the range of 3 μm to 15 μm.

The first top plating layer 28 has a melting point lower than that of the first plating post 24, and is made of a metal that is melted by a reflow treatment and shaped into a substantially hemispherical shape as shown in FIG. Become. Thickness of the first top plating layer 28 (vertical distance from the lower end of the first top plating layer 28 to the top of the first top plating layer on the outer peripheral surface of the first bump 20) A1 is 20 μm to 40 μm. It is preferably in the range. By setting the thickness A1 of the first top plating layer 28 to this range, the first bump 20 and a connection pad (not shown) for electronic components such as a semiconductor chip and a memory mounted on the printed wiring board 10 can be connected to each other. Good connection reliability can be obtained between them.

The second bump 22 is a second plating post 30 composed of a second base plating layer formed in the second opening 16b and a substantially columnar second post integrated with the second base plating layer. And a second intermediate layer 32 composed of, for example, nickel as a main component on the second plating post 30, or a nickel layer, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. It has a substantially hemispherical second top plating layer 34 formed via the above. The thickness of the second intermediate layer 32 is preferably 7 μm or less.

The second base plating layer forming the second plating post 30 is formed of a conductive metal, preferably a metal containing copper as a main component. The second post, which also forms the second plating post 30, is formed of the same metal as the second base plating layer, that is, preferably a metal containing copper as a main component. The second base plating layer forming the second plating post 30 and the second post are sequentially formed and integrated with each other. The second plating post 30 is formed to a height sufficiently exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). As a result, the second bump 22 is stably held in the second opening 16b. The height B2 from the surface of the solder resist layer 16 to the upper end surface 30a of the second plating post 30 is preferably in the range of 3 μm to 15 μm.

The second top plating layer 34 has a melting point lower than that of the second plating post 30, and is melted by a reflow treatment and shaped into a substantially hemispherical shape as shown in FIG. 1, for example, a metal containing tin as a main component. Consists of. Thickness of the second top plating layer 34 (vertical distance from the lower end of the second top plating layer 34 to the top of the second top plating layer 34 on the outer peripheral surface of the second bump 22) A2 is 20 μm to 40 μm. It is preferable that the range is. By setting the thickness A2 of the second top plating layer 34 within this range, the second bump 22 and the connection pad (not shown) of electronic components such as a semiconductor chip and memory mounted on the printed wiring board 10 can be connected to each other. Good connection reliability can be obtained between them.

In the printed wiring board 10 of the embodiment shown in FIG. 1, the upper end surface 24a of the first plating post 24 and the upper end surface 30a of the second plating post 30 are polished together to be flat and have the same height as each other. B1 = B2). Further, the first intermediate layer 26 and the second intermediate layer 32 are formed together to have the same thickness (height) as each other.

Then, the first top plating layer 28 and the second top plating layer 34 are formed together and the amount of metal plating is adjusted respectively, so that the thickness (height) after melting by the reflow treatment is the same (A1). = A2).

As a result, even if the printed wiring board 10 of the embodiment shown in FIG. 1 has bumps 20 and 22 having different sizes, there is almost or substantially no difference in height between the bumps 20 and the bumps 22. Not at all.

<About the manufacturing method of the printed wiring board of one Embodiment of this invention>
Hereinafter, a method for manufacturing a printed wiring board according to an embodiment of the present invention for manufacturing the printed wiring board 10 shown in FIG. 1 will be described with reference to FIGS. 2A to 2K.

FIG. 2A shows an intermediate in which a conductor layer 14 and a solder resist layer 16 having a predetermined circuit pattern are formed on a base insulating layer 12 by a known method. In many cases, a plurality of other conductor layers and a resin insulating layer are alternately formed in the lower layer of the base insulating layer 12, but they are omitted in the drawing. The plurality of conductor layers and the resin insulating layer can be laminated on the core substrate or on a support plate that can be removed later. However, the printed wiring board 10 may be composed of one resin insulating layer as the base insulating layer 12 and one conductor layer 14, and in this case, the resin insulating layer corresponds to the base insulating layer 12.

For the base insulating layer 12, a build-up insulating resin film containing an inorganic filler such as silica or alumina and an epoxy resin can be used. In the solder resist layer 16, a first opening 16a for exposing a part of the conductor layer 14 as a first conductor pad 14a and another part of the conductor layer 14 are formed on the solder resist layer 16 by, for example, a carbon dioxide gas laser or a UV-YAG laser. A second opening 16b to be exposed as the conductor pad 14b of 2 is formed. The aspect ratio of the first opening 16a is preferably 0.5 or less, and the aspect ratio of the second opening 16b is preferably 0.6 or more. An underlayer may be formed by plating on the first and second conductor pads 14a and 14b. Examples of the base layer include a nickel layer formed on the surfaces of the first and second conductor pads 14a and 14b, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. it can. In addition, a nickel layer and a gold layer formed on the nickel layer can be exemplified.

As shown in FIG. 2B, for example, an electroless plating treatment such as an electroless copper plating treatment is performed, and the surface of the intermediate body (the surface of the solder resist layer 16 and the side surfaces of the first and second openings 16a and 16b). A seed layer 36 is formed on the top and on the conductor pads 14a and 14b.

As shown in FIG. 2C, a plating resist 38 having a predetermined pattern having openings 38a and 38b is formed on the seed layer 36 at the planned formation sites of the first and second bumps 20 and 22 (FIG. 1).

As shown in FIG. 2D, among the portions of the seed layer 36 exposed in the openings 38a and 38b of the plating resist 38 after the electrolytic plating treatment, the first and second openings 16a of the solder resist layer 16 A first base plating layer and a second base plating layer containing, for example, copper as a main component are formed on the portion in 16b, and subsequently on the first base plating layer and the second base plating layer and on the second base plating layer. , The same metal as the first base plating layer and the second base plating layer, for example, copper, is integrally formed on the remaining portion of the seed layer 36 exposed in the openings 38a and 38b of the plating resist 38. The first post and the second post which are the main components are formed, and the first base plating layer and the first post above it become the first plating post 24, and the second base plating layer The second post above it is referred to as the second plating post 30.

As shown in FIG. 2E, when forming the first and second plating posts 24 and 30, the upper end surfaces 24a of the first and second plating posts 24 and 30 from the surface of the solder resist layer 16 The upper ends of the first and second plating posts 24 and 30 are horizontally polished together with the upper end of the plating resist 38 by a polishing machine so that the heights of 30a are aligned with each other within the range of 5 μm to 17 μm. It is preferably about 5 μm lower than before.

As shown in FIG. 2F, the etching process is performed so that the heights of the upper end surfaces 24a and 30a of the first and second plating posts 24 and 30 are preferably about 2 μm, which is lower than the upper end surfaces of the plating resist 38. , Are virtually identical to each other.

As shown in FIG. 2G, for example, an electrolytic plating process is performed, and in the opening 38a of the plating resist 38, on the upper end surfaces 24a, 30a of the first and second plating posts 24, 30, for example, a nickel layer and a nickel layer. The first and second intermediate layers 26 and 32 composed of the palladium layer formed above and the gold layer formed on the palladium layer are formed. The thicknesses of the first and second intermediate layers 26 and 32 are preferably 7 μm or less, and are substantially the same as each other.

As shown in FIG. 2H, a predetermined shape made of, for example, a dry film resist, having openings 40a and 40b at the center of the planned formation portions of the first and second bumps 20 and 22 (FIG. 1) on the plating resist 38. The pattern plating resist 40 is formed. The thickness of the plating resist 40 and the diameters of the openings 40a and 40b are adjusted so that the heights of the first and second top plating layers 28 and 34, which will be described later, are aligned with each other.

As shown in FIG. 2I, an electrolytic plating process is performed, and the first and second tops 26 and 32 are interposed on the upper end surfaces 24a and 30a of the plating posts 24 and 30. Plating layers 28 and 34 are formed. The first and second top plating layers 28 and 34 are mainly composed of a metal having a lower melting point than the first and second plating posts 24 and 30, which is melted by a reflow treatment and shaped into a substantially hemispherical shape, for example, tin. It is made of metal. The thicknesses of the first and second top plating layers 28 and 32 are substantially the same as each other, preferably in the range of 20 μm to 40 μm.

As shown in FIG. 2J, the plating resists 38 and 40 are peeled off. Further, the portion of the seed layer 36 exposed by removing the plating resists 38 and 40 is removed by etching.

As shown in FIG. 2K, a reflow process is performed to shape the first top plating layer 28 and the second top plating layer 34 into a substantially hemispherical shape.

By this reflow treatment, from the side close to the first and second conductor pads 14a and 14b, for example, a base layer in which a nickel layer, a palladium layer and a gold layer are laminated, for example, a copper plating post, and for example, a nickel layer and palladium. A first bump 20 and a second bump 22 composed of an intermediate layer in which a layer and a gold layer are laminated and a tin top plating layer are formed.

Further, the height H1 of the first top plating layer 28 shaped to be substantially hemispherical by the reflow treatment from the surface of the solder resist layer 16 is the second top plating layer shaped to be substantially hemispherical by the reflow treatment. The height H2 of 34 from the surface of the solder resist layer 16 is made substantially the same, and the heights of the first and second bumps 20 and 22 are aligned so that the first and second bumps 20 and 22 are aligned. There is almost no or virtually no variation in the height of the plating.

<About the manufacturing method of the printed wiring board of another embodiment of this invention>
Hereinafter, a method for manufacturing a printed wiring board according to another embodiment of the present invention for manufacturing the printed wiring board 10 shown in FIG. 1 will be described with reference to FIGS. 3A to 3D.

FIG. 3A shows an intermediate formed in the same manner as in the previous embodiment up to the same state as shown in FIG. 2F. The first plating post 24 and the second plating post 30 are horizontally polished together with the upper end of the plating resist 38 to align their heights with each other, and then etched to increase their height, preferably 2 μm. To some extent, it is lowered below the upper end surface of the plating resist 38 so that they are substantially the same as each other.

As shown in FIG. 3B, a predetermined shape made of, for example, a dry film resist, having openings 40a and 40b at the center of the planned formation portions of the first and second bumps 20 and 22 (FIG. 1) on the plating resist 38. The pattern plating resist 40 is formed. The thickness of the plating resist 40 and the diameters of the openings 40a and 40b are adjusted so that the heights of the first and second top plating layers 28 and 34, which will be described later, are aligned with each other.

As shown in FIG. 3C, for example, an electrolytic plating process is performed, and nickel is mainly used on the upper end surfaces 24a and 30a of the first and second plating posts 24 and 30 in the openings 38a and 38b of the plating resist 38. The first and second intermediate layers 26 and 32 as components are formed. The thicknesses of the first and second intermediate layers 26 and 32 are preferably 7 μm or less, and are substantially the same as each other.

As shown in FIG. 3D, an electrolytic plating process is performed, and the first and second tops 26 and 32 are interposed on the upper end surfaces 24a and 30a of the plating posts 24 and 30. Plating layers 28 and 34 are formed. The first and second top plating layers 28 and 34 are mainly composed of a metal having a lower melting point than the first and second plating posts 24 and 30, which is melted by a reflow treatment and shaped into a substantially hemispherical shape, for example, tin. It is made of metal. The thicknesses of the first and second top plating layers 28 and 32 are substantially the same as each other, preferably in the range of 20 μm to 40 μm.

The plating resists 38 and 40 are peeled off, and the portion of the seed layer 36 exposed by the removal of the plating resists 38 and 40 is removed by etching in the same manner as in the procedure shown in FIGS. 2J to 2K of the previous embodiment. , The reflow treatment is performed, and the first top plating layer 28 and the second top plating layer 34 are shaped into a substantially hemispherical shape.

By this reflow treatment, a first bump composed of, for example, a copper plating post, for example, an intermediate layer mainly composed of nickel, and a tin top plating layer from the side close to the first and second conductor pads 14a and 14b. 20 and a second bump 22 are formed.

Further, the height H1 of the first top plating layer 28 formed into a substantially hemispherical shape by the reflow treatment from the surface of the solder resist layer 16 is the second top plating layer formed into a substantially hemispherical shape by the reflow treatment. The height H2 of 34 from the surface of the solder resist layer 16 is made substantially the same, and the heights of the first and second bumps 20 and 22 are aligned so that the first and second bumps 20 and 22 are aligned. There is almost no or virtually no variation in the height of the plating.

10 Printed wiring board 12 Base insulating layer 14 Conductor layer 14a First conductor pad 14b Second conductor pad 16 Solder resist layer 16a First opening 16b Second opening 20 First bump 22 Second bump 24 First Plating post 24a, 30a Top surface 26 First intermediate layer 28 First top plating layer 30 Second plating post 32 Second intermediate layer 34 Second top plating layer 36 Seed layer 38,40 Plating resist 38a, 38b, 40a, 40b openings

Claims (15)

It is a printed wiring board
With the base insulation layer,
The conductor layer formed on the base insulating layer and
A first opening formed on the base insulating layer and the conductor layer and exposing a part of the conductor layer as a first conductor pad, and the conductor layer having a diameter smaller than that of the first opening. A solder resist layer with a second opening that exposes the other part as a second conductor pad,
With the first bump formed on the first conductor pad,
A second bump having a diameter smaller than that of the first bump formed on the second conductor pad is provided.
The first bump is composed of a first base plating layer formed in the first opening and a first post integrally formed on the first base plating layer with the same metal as the first base plating layer. It has a plating post of 1 and a first top plating layer having a substantially hemispherical shape formed on the first plating post.
The second bump is composed of a second base plating layer formed in the second opening and a second post integrally formed on the second base plating layer with the same metal as the second base plating layer. Has a substantially hemispherical second top plating layer formed on the second plating post.
The first plating post and the second plating post have flat upper surfaces, are flush with each other, and have the same height.
The heights of the first bump and the second bump are the same as each other. The printed wiring board according to claim 1, wherein the thickness of the first top plating layer and the second top plating layer is 20 μm to 40 μm. The printed wiring board according to claim 1, wherein the first plating post and the second plating post are each formed of a metal containing copper as a main component. The printed wiring board according to claim 1, wherein the first top plating layer is formed on the first plating post via a first intermediate layer, and the second top plating layer is the first. Formed on the 2 plating posts via a second intermediate layer,
The first intermediate layer and the second intermediate layer are composed of a nickel layer, a palladium layer, and a gold layer which are sequentially laminated. The printed wiring board according to claim 1, wherein the first top plating layer is formed on the first plating post via a first intermediate layer, and the second top plating layer is the first. Formed on the 2 plating posts via a second intermediate layer,
The first intermediate layer and the second intermediate layer are each formed of a metal containing nickel as a main component. The printed wiring board according to claim 1, wherein the first top plating layer and the second top plating layer are each formed of a metal containing tin as a main component. The printed wiring board according to claim 1, wherein the first plating post and the first conductor pad, and the second plating post and the second conductor pad are sequentially inserted. It has a base layer composed of a laminated nickel layer, a palladium layer, and a gold layer, respectively. It is a manufacturing method of printed wiring boards.
Forming the base insulation layer and
Forming a conductor layer on the base insulating layer and
Forming a solder resist layer on the base insulating layer and the conductor layer,
To form a first opening in the solder resist layer that exposes a part of the conductor layer as a first conductor pad.
To form a second opening in the solder resist layer, which has a diameter smaller than that of the first opening and exposes another part of the conductor layer as a second conductor pad.
Forming a first bump on the first conductor pad and
Including forming a second bump having a diameter smaller than that of the first bump on the second conductor pad.
To form the first bump, the first base plating layer is formed in the first opening, and the same metal as the first base plating layer is integrally formed on the first base plating layer. Forming a post to form a first plating post, forming a first top plating layer on the first plating post, and reflowing the first top plating layer to form a substantially hemisphere. Including forming a first top plating layer in the form of
Forming the second bump means forming a second base plating layer in the second opening and integrally using the same metal as the second base plating layer on the second base plating layer. Forming the second post to form the second plating post, forming the second top plating layer on the second plating post, and reflowing the second top plating layer to form a substantially hemisphere. Including forming a second top plating layer in the shape
Forming the first plating post and the second plating post includes aligning the heights of the first plating post and the second plating post with each other by polishing, and
Forming the first top plating layer and the second top plating layer means that the heights of the first top plating layer and the second top plating layer are adjusted to the height of the first top plating layer and the second top plating layer. This includes aligning the resists with each other by adjusting the opening diameter of the resists in forming the top plating layer of the above. In the method for manufacturing a printed wiring board according to claim 8, adjusting the opening diameter of the resist means that the width of the overlapping portion between the upper surface of the first plating post and the resist is changed to the width of the overlapping portion of the second plating post. Includes making it larger than the width of the overlapping portion of the upper surface and the resist. The method for manufacturing a printed wiring board according to claim 8, wherein the thickness of the substantially hemispherical first top plating layer and the substantially hemispherical second top plating layer after the reflow is 20 μm to 40 μm. Is. The method for manufacturing a printed wiring board according to claim 8, wherein the first plating post and the second plating post are each formed of a metal containing copper as a main component. The method for manufacturing a printed wiring board according to claim 8, wherein the first top plating layer is formed on the first plating post via a first intermediate layer, and the second plating is performed. Including forming the second top plating layer on the post via a second intermediate layer.
The first intermediate layer and the second intermediate layer are composed of a nickel layer, a palladium layer, and a gold layer which are sequentially laminated. The method for manufacturing a printed wiring board according to claim 8, wherein the first top plating layer is formed on the first plating post via a first intermediate layer, and the second plating is performed. Including forming the second top plating layer on the post via a second intermediate layer.
The first intermediate layer and the second intermediate layer are each formed of a metal containing nickel as a main component. The method for manufacturing a printed wiring board according to claim 8, wherein the first top plating layer and the second top plating layer are each formed of a metal containing tin as a main component. The method for manufacturing a printed wiring board according to claim 8, wherein the first plating post and the first conductor pad and the second plating post and the second conductor pad are used. Each has a base layer composed of a nickel layer, a palladium layer, and a gold layer which are sequentially laminated.

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