JP2021040061A - Circuit board with built-in electronic component and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve heat dissipation of a circuit board having a built-in electronic component. A circuit board 100 with built-in electronic components includes a conductor layer L4 formed on the lower surface of an insulating layer 111, and a conductor layer L3 formed on the upper surface of the insulating layer 111 and located between the insulating layers 111 and 112. It includes an electronic component 130 embedded between the insulating layers 112 and 113. At least a part of the conductor layer L3 is embedded in the insulating layer 111. The conductor layer L3 has a first region A1 that overlaps with the electronic component 130 in a plan view and a second region A2 that does not overlap with the electronic component 130 in a plan view, and the thickness of the conductor layer L3 in the first region A1. Is thicker than the thickness of the conductor layer L4. As a result, the heat generated by the operation of the electronic component 130 can be efficiently dissipated. Moreover, since the conductor layer L3 is embedded in the insulating layer 111, the thickness of the insulating layer 112 can be reduced, and the thermal resistance of the insulating layer 112 is also reduced. [Selection diagram] Fig. 1

Description

The present invention relates to a circuit board with built-in electronic components and a method for manufacturing the same, and more particularly to a circuit board with built-in electronic components and a method for manufacturing the same.

As a circuit board in which an electronic component such as a semiconductor IC is embedded, the circuit board with a built-in electronic component described in Patent Document 1 is known. The circuit board with built-in electronic components described in Patent Document 1 includes a heat-dissipating via conductor in contact with the back surface of the electronic component, whereby heat generated by the operation of the electronic component is efficiently dissipated.

Japanese Unexamined Patent Publication No. 2013-229548

However, since the heat-dissipating via conductor described in Patent Document 1 is a deep via conductor that reaches from the front surface of the circuit board to the back surface of the electronic component, there is a problem that it is difficult to obtain sufficient heat dissipation efficiency. It was also necessary to add a step for providing the heat-dissipating via conductor. In order to improve heat dissipation without using a deep via conductor, a method of increasing the thickness of the conductor layer adjacent to the electronic component can be considered. However, if the thickness of the conductor layer adjacent to the electronic component is simply increased, the unevenness due to the conductor layer becomes large, so that the thickness of the insulating layer located between the conductor layer and the electronic component must be increased. As a result, there is a problem that sufficient heat dissipation cannot be obtained due to the increase in thermal resistance.

Therefore, according to the present invention, in the electronic component built-in circuit board in which the heat dissipation is enhanced by increasing the thickness of the conductor layer adjacent to the electronic component and the manufacturing method thereof, the insulating layer located between the conductor layer and the electronic component. The purpose is to reduce the thermal resistance by making the thickness of the.

The circuit board with built-in electronic components according to one aspect of the present invention includes the first, second and third insulating layers, the first conductor layer formed on one surface of the first insulating layer, and the first insulation. A second conductor layer formed on the other surface of the layer and located between the first and second insulating layers, and an electronic component embedded between the second insulating layer and the third insulating layer. At least a part of the second conductor layer is embedded in the first insulating layer, and the second conductor layer overlaps with the electronic component in the plan view and the first region overlapping the electronic component in the plan view. It has a second region that does not become, and the thickness of the second conductor layer in the first region is thicker than the thickness of the first conductor layer.

According to the present invention, since the thickness of the second conductor layer overlapping the electronic component is thick, the heat generated by the operation of the electronic component can be efficiently dissipated. Moreover, since at least a part of the second conductor layer is embedded in the first insulating layer, the unevenness caused by the second conductor layer is alleviated. As a result, the thickness of the second insulating layer located between the electronic component and the second conductor layer can be reduced, so that the thermal resistance due to the second insulating layer is also reduced.

In the present invention, the other surface of the first insulating layer and the surface of the second conductor layer may form the same plane. According to this, since the unevenness due to the second conductor layer does not occur, the thickness of the second insulating layer can be made very thin, and the heat dissipation can be further improved.

In the present invention, the thickness of the second conductor layer in the first region may be thicker than the thickness of the second conductor layer in the second region. According to this, heat from the electronic component can be efficiently dissipated, and the thickness of the second conductor layer is thin in the second region that does not overlap with the electronic component, so that the heat is formed in the second region. It is possible to make the line width and the space width of the wiring pattern to be made finer. In this case, the second conductor layer in the second region may be formed on the other surface of the first insulating layer without being embedded in the first insulating layer. According to this, a wiring pattern can be formed by patterning a copper foil or the like formed on the other surface of the first insulating layer.

In the present invention, the thickness of the second insulating layer at the position where it overlaps with the electronic component in a plan view may be thinner than the thickness of the second conductor layer in the first region. According to this, since the thermal resistance due to the second insulating layer is significantly reduced, it is possible to obtain high heat dissipation.

In the present invention, the second conductor layer has an opening in the first region, and the via conductor connected to the first conductor layer may be in contact with the electronic component through the opening. According to this, it becomes possible to obtain higher heat dissipation characteristics.

The circuit board with built-in electronic components according to another aspect of the present invention includes a first, second and third insulating layers, a conductor layer located between the first and second insulating layers, and a second insulating layer. With an electronic component embedded between the third insulating layers, the conductor layer has a first region that overlaps the electronic component in plan view and a second region that does not overlap the electronic component in plan view. The thickness of the conductor layer in the first region is characterized by being thicker than the thickness of the conductor layer in the second region.

According to the present invention, the heat from the electronic component can be efficiently dissipated, and the thickness of the second conductor layer is thin in the second region that does not overlap with the electronic component. The line width and space width of the formed wiring pattern can be further miniaturized.

In the present invention, a part of the conductor layer may be embedded in the first insulating layer, and the remaining part of the conductor layer may be embedded in the second insulating layer. According to this, the conductor layer located in the first region can be selectively thickened by embedding the conductor layer located in the first region in both the first and second insulating layers. In this case, the portion of the conductor layer embedded in the first insulating layer may be thicker than the portion embedded in the second insulating layer. According to this, the thickness of the conductor layer located in the second region can be further reduced. Further, in this case, another conductor layer provided on the surface opposite to the surface on which the conductor layer of the first insulating layer is provided is further provided, and the other conductor layer is the first insulating of the conductor layers. It may be thinner than the portion embedded in the layer and thicker than the portion embedded in the second insulating layer. According to this, it is possible to clearly achieve both high heat dissipation characteristics and miniaturization of the wiring pattern.

The method for manufacturing a circuit board with built-in electronic components according to the present invention includes a first step of forming a conductor layer including a heat dissipation pattern on a support, and a first step of laminating a first insulating layer on the support so as to embed the conductor layer. The second step, the third step of exposing the conductor layer by peeling off the support, the fourth step of laminating the second insulating layer on the surface of the exposed conductor layer, and the heat dissipation pattern so as to overlap with each other. It includes a fifth step of placing an electronic component on the surface of the second insulating layer and a sixth step of laminating a third insulating layer on the surface of the second insulating layer so that the electronic component is embedded. It is characterized by that.

According to the present invention, since the conductor layer including the heat dissipation pattern is first formed and then embedded in the first insulating layer, the thickness of the heat dissipation pattern can be increased and the second insulation can be increased. The thickness of the layer can be reduced. This makes it possible to obtain a structure capable of efficiently dissipating heat generated by the operation of electronic components.

In the present invention, the conductor layer has a first portion embedded in the first insulating layer and a second portion located on the surface of the first insulating layer without being embedded in the first insulating layer. After performing the third step and before performing the fourth step, at least a part of the second portion of the conductor layer may be removed. In this case, the second part of the conductor layer may be completely removed, and by patterning the second part of the conductor layer, it does not overlap with the electronic component in a plan view and is thicker than the heat dissipation pattern. A thin wiring pattern may be formed on the conductor layer. According to the former, since the surface on which the conductor layer is formed becomes a substantially completely flat surface, it is possible to set the thickness of the second insulating layer to be very thin. Further, according to the latter, since the thickness of the wiring pattern is thin, the line width and the space width can be further miniaturized.

As described above, according to the present invention, in the electronic component built-in circuit board in which the electronic component is embedded and the manufacturing method thereof, the thickness of the conductor layer adjacent to the electronic component is thick, so that the heat generated by the operation of the electronic component is generated. Efficient heat dissipation. Moreover, since the thickness of the insulating layer located between the conductor layer and the electronic component can be reduced, the heat generated by the operation of the electronic component can be efficiently dissipated.

FIG. 1 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 100 according to the first embodiment of the present invention. FIG. 2 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 3 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 4 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 5 is a process diagram for explaining a manufacturing method of the electronic component built-in circuit board 100. FIG. 6 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 7 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 8 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 9 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 10 is a process diagram for explaining a manufacturing method of the electronic component built-in circuit board 100. FIG. 11 is a process diagram for explaining a manufacturing method of the electronic component built-in circuit board 100. FIG. 12 is a process diagram for explaining a manufacturing method of the electronic component built-in circuit board 100. FIG. 13 is a process diagram for explaining a manufacturing method of the electronic component built-in circuit board 100. FIG. 14 is a process diagram for explaining a manufacturing method of the electronic component built-in circuit board 100. FIG. 15 is a process diagram for explaining a manufacturing method of the electronic component built-in circuit board 100. FIG. 16 is a process diagram for explaining a manufacturing method of the electronic component built-in circuit board 100. FIG. 17 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 18 is a process diagram for explaining a method of manufacturing the circuit board 100 with built-in electronic components. FIG. 19 is a process diagram for explaining a method of manufacturing the electronic component built-in circuit board 100. FIG. 20 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 200 according to the second embodiment of the present invention. FIG. 21 is a process diagram for explaining a method of manufacturing the circuit board 200 with built-in electronic components. FIG. 22 is a process diagram for explaining a method of manufacturing the circuit board 200 with built-in electronic components. FIG. 23 is a process diagram for explaining a method of manufacturing the circuit board 200 with built-in electronic components. FIG. 24 is a process diagram for explaining a method of manufacturing the circuit board 200 with built-in electronic components. FIG. 25 is a process diagram for explaining a method of manufacturing the circuit board 200 with built-in electronic components. FIG. 26 is a process diagram for explaining a method of manufacturing the circuit board 200 with built-in electronic components. FIG. 27 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 300 according to the third embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 100 according to the first embodiment of the present invention.

As shown in FIG. 1, the electronic component built-in circuit board 100 according to the first embodiment of the present invention has four insulating layers 111 to 114 and conductor layers L1 to L4 located on the surfaces of the insulating layers 111 to 114. have. Although not particularly limited, the insulating layer 111 located at the bottom layer and the insulating layer 114 located at the top layer may be a core layer in which a core material such as glass fiber is impregnated with a resin material such as epoxy. I do not care. On the other hand, the insulating layers 112 and 113 may be resin layers that do not include a core material such as glass cloth. In particular, the coefficient of thermal expansion of the insulating layers 111 and 114 is preferably smaller than the coefficient of thermal expansion of the insulating layers 112 and 113. As described above, if the insulating layers 112 and 113 which are resin layers are sandwiched between the insulating layers 111 and 114 which are core layers, even if the thickness of the electronic component built-in circuit board 100 is thin, it is sufficiently mechanical. It is possible to obtain strength.

The insulating layer 114 located on the uppermost layer and a part of the conductor layer L1 formed on the surface thereof are covered with the solder resist 121. Similarly, the insulating layer 111 located at the bottom layer and a part of the conductor layer L4 formed on the surface thereof are covered with the solder resist 122. Although not particularly limited, the solder resist 121 constitutes the upper surface 101 of the electronic component built-in circuit board 100, and the solder resist 122 constitutes the lower surface 102 of the electronic component built-in circuit board 100. Although not shown, electronic components such as capacitors and inductors can be mounted on the upper surface 101 of the circuit board 100 with built-in electronic components. A user terminal connected to the motherboard can be formed on the lower surface 102. Alternatively, the circuit board 100 with built-in electronic components may be turned upside down and the electronic components may be mounted on the lower surface 102.

As shown in FIG. 1, the electronic component built-in circuit board 100 according to the present embodiment has an electronic component 130 embedded in the insulating layer 113. The electronic component 130 is, for example, a semiconductor IC, and the main surface 131 provided with the terminal electrode 133 is covered with the insulating layer 113 facing the upper surface 101 side, and the back surface 132 is covered with the insulating layer 112 facing the lower surface 102 side. There is.

The conductor layer L1 is provided on the upper surface of the insulating layer 114 and includes the wiring pattern 141. The portion of the wiring pattern 141 that is not covered with the solder resist 121 constitutes an external terminal of the electronic component built-in circuit board 100.

The conductor layer L2 is provided between the upper surface of the insulating layer 113 and the lower surface of the insulating layer 114, and includes a wiring pattern 142. A part of the wiring pattern 142 is connected to the wiring pattern 141 of the conductor layer L1 via a plurality of via conductors 151 provided so as to penetrate the insulating layer 114. Further, another part of the wiring pattern 142 is connected to the terminal electrode 133 of the electronic component 130 via a via conductor 152 provided at a position overlapping the electronic component 130 in a plan view.

The conductor layer L3 is provided between the upper surface of the insulating layer 111 and the lower surface of the insulating layer 112, and includes a heat dissipation pattern 143a and a wiring pattern 143b. Both the heat dissipation pattern 143a and the wiring pattern 143b are embedded in the insulating layer 111. The heat dissipation pattern 143a is located in the first region A1 that overlaps with the electronic component 130 in a plan view, and the wiring pattern 143b is located in a second region A2 that does not overlap with the electronic component 130 in a plan view. As shown in FIG. 1, a part of the heat dissipation pattern 143a may extend beyond the first region A1 and reach the second region A2. The wiring pattern 143b is connected to the wiring pattern 142 of the conductor layer L2 via a plurality of via conductors 153 provided so as to penetrate the insulating layers 112 and 113. The via conductor 153 is arranged at a position where it does not overlap with the electronic component 130 in a plan view.

In the present embodiment, the heat dissipation pattern 143a and the wiring pattern 143b constituting the conductor layer L3 are completely embedded in the insulating layer 111. That is, the surface of the heat dissipation pattern 143a and the wiring pattern 143b and the surface of the insulating layer 111 form the same plane. As a result, the insulating layer 112 can be formed on a flat surface without unevenness, so that the thickness of the insulating layer 112 can be set to be very thin. The thickness of the insulating layer 112 is preferably as thin as possible, and more preferably thinner than the heat dissipation pattern 143a, as long as the adhesiveness of the electronic component 130 can be ensured in the step of mounting the electronic component 130 on the insulating layer 112.

The conductor layer L4 is provided on the lower surface of the insulating layer 111, and includes a heat dissipation pattern 144a and a wiring pattern 144b. The heat radiating pattern 144a is connected to the heat radiating pattern 143a of the conductor layer L3 via a plurality of via conductors 154 provided so as to penetrate the insulating layer 111. The wiring pattern 144b is connected to the wiring pattern 143b of the conductor layer L3 via a plurality of via conductors 155 provided so as to penetrate the insulating layer 111. Further, of the heat dissipation pattern 144a and the wiring pattern 144b, the portion not covered with the solder resist 122 constitutes a terminal electrode.

As shown in FIG. 1, in the electronic component built-in circuit board 100 according to the present embodiment, the thickness of the conductor layer L3 is thicker than that of the other conductor layers L1, L2, and L4. As a result, the heat dissipation effect via the heat dissipation pattern 143a is enhanced. The thickness of the conductor layer L3 is not particularly limited, but in order to sufficiently enhance the heat dissipation effect, the thickness of the conductor layer L3 is designed to be 1.5 times or more the thickness of the other conductor layers L1, L2, L4. It is preferable to design the conductor 2.0 times or more. The thicker the conductor layer L3, the higher the heat dissipation effect. However, as the conductor layer L3 becomes thicker, the overall thickness of the electronic component built-in circuit board 100 becomes thicker. The upper limit may be set according to the thickness allowed for the circuit board 100 with built-in electronic components. However, in the circuit board 100 with built-in electronic components according to the present embodiment, since the conductor layer L3 is embedded in the insulating layer 111 and the thickness of the insulating layer 112 can be made thinner than before, the conductor layer L3 is used. Even if it is designed to be thick, the thickness of the circuit board 100 with built-in electronic components does not simply increase.

Next, a method of manufacturing the electronic component built-in circuit board 100 according to the first embodiment will be described.

2 to 19 are process diagrams for explaining a method of manufacturing the electronic component built-in circuit board 100 according to the present embodiment.

First, as shown in FIG. 2, a base material 160 having a structure in which copper foils 162 and 143c are laminated on both sides of the support 161 is prepared. As the support 161, the same ones as the insulating layers 111 and 114 can be used. Further, a peeling layer (not shown) is provided at the interface between the copper foil 162 and the copper foil 143c, and peeling can be performed at the interface between the two. Of these, since the copper foil 143c is etched in the subsequent steps, it is preferable to use one having a sufficiently thin thickness. The thickness of the copper foil 162 is arbitrary.

Next, as shown in FIG. 3, the heat dissipation pattern 143a and the wiring pattern 143b are formed on both surfaces by performing electrolytic plating using the copper foil 143c as a seed layer. By performing electrolytic plating with a mask (resist) (not shown) formed on the surface of the copper foil 143c, the heat dissipation pattern 143a and the wiring pattern 143b can be selectively formed.

Next, as shown in FIG. 4, a base material 170 having a structure in which copper foils 144c and 171 are laminated on one surface of the insulating layer 111 is prepared, and the heat dissipation pattern 143a and the wiring pattern 143b are embedded in the insulating layer 111. The base material 170 is laminated on both sides of the base material 160 so as to be. A peeling layer (not shown) is provided at the interface between the copper foil 171 and the copper foil 143c, and peeling is possible at the interface between the two. Of these, since the copper foil 144c is patterned in the subsequent steps, it is preferable to use one having a sufficiently thin thickness. The thickness of the copper foil 171 is arbitrary.

The resin material used for the insulating layer 111 is not particularly limited as long as it can be molded into a sheet or film, and can be used in addition to glass epoxy, for example, vinyl benzyl resin, polyvinyl benzyl ether compound resin, and the like. Bismaleimide triazine resin (BT resin), polyphenylene ether (polyphenylene ether oxide) resin (PPE, PPO), cyanate ester resin, epoxy + active ester cured resin, polyphenylene ether resin (polyphenylene oxaode resin), curable polyolefin resin, Benzocyclobutene resin, polyimide resin, aromatic polyester resin, aromatic liquid crystal polyester resin, polyphenylene sulfide resin, polyetherimide resin, polyacrylate resin, polyether ether ketone resin, fluororesin, epoxy resin, phenol resin, or benzoxazine Silica, talc, calcium carbonate, magnesium carbonate, aluminum hydroxide, magnesium hydroxide, aluminum borate whisker, potassium titanate fiber, alumina, glass flakes, glass fiber, tantalum nitride, etc. Materials to which aluminum nitride or the like is added, and at least one of magnesium, silicon, titanium, zinc, calcium, strontium, zirconium, tin, neodium, samarium, aluminum, bismuth, lead, lantern, lithium and tantalum to these resins. A material to which a metal oxide powder containing a seed metal is added can be used, and can be appropriately selected and used from the viewpoints of electrical properties, mechanical properties, water absorption, reflow resistance and the like. Further, as the core material contained in the insulating layer 111, a material containing resin fibers such as glass fiber and aramid fiber can be mentioned. The same applies to the other insulating layers 112 to 114 described later.

Next, as shown in FIG. 5, the two base materials 180 are separated from the support 161 by peeling off the interface between the copper foil 162 and the copper foil 143c. After that, since the same step is performed on the two base materials 180, the step on one base material 180 will be described below.

Next, as shown in FIG. 6, the base material 180 is mounted on the support 190 via the adhesive 191. As the support 190, a plate-shaped body made of stainless steel or the like can be used. By etching the copper foil 143c in this state, as shown in FIG. 7, all the copper foil 143c is removed. As a result, the surface of the insulating layer 111 is exposed, and the heat dissipation pattern 143a and the wiring pattern 143b are exposed. Further, the surfaces of the heat dissipation pattern 143a and the wiring pattern 143b form the same plane as the surface of the insulating layer 111. By this step, the conductor layer L3 is completed.

Next, as shown in FIG. 8, the insulating layer 112 is formed by laminating, for example, an uncured (B stage state) resin sheet or the like on the surface of the insulating layer 111 by vacuum pressure bonding or the like. As described above, the heat dissipation pattern 143a and the wiring pattern 143b are embedded in the insulating layer 111, and the surface thereof forms the same plane as the surface of the insulating layer 111. Therefore, the thickness of the insulating layer 112 is very high. It can be set thin.

Next, as shown in FIG. 9, the electronic component 130 is placed on the insulating layer 112 so as to overlap the heat dissipation pattern 143a. The electronic component 130 is mounted in a face-up manner so that the main surface 131 faces upward and the back surface 132 is in contact with the insulating layer 112. When the electronic component 130 is a semiconductor IC, the silicon substrate may be thinned to, for example, 200 μm or less, more preferably about 50 to 100 μm. When mounting the electronic component 130, the heat dissipation pattern 143a or the wiring pattern 143b may be used as the alignment mark. In the present embodiment, since the thickness of the insulating layer 112 is set to be very thin, when the electronic component 130 is mounted, the heat dissipation pattern 143a or the wiring pattern 143b, which are alignment marks, can be easily imaged through the insulating layer 112. It is possible to recognize.

Next, as shown in FIG. 10, the insulating layer 113 and the copper foil 142c are formed so as to cover the electronic component 130. The insulating layer 113 is formed, for example, by applying a thermosetting resin in an uncured or semi-cured state, heating the uncured resin to semi-cure it, and further using a pressing means together with the copper foil 142c. It is preferably cured and molded. The insulating layer 113 is preferably a resin sheet that does not contain fibers that hinder the embedding of the electronic component 130. As a result, the adhesion between the insulating layer 113 and the copper foil 142c, the insulating layer 112, and the electronic component 130 is improved.

Next, as shown in FIG. 11, the copper foil 142c is removed by etching using a known method such as a photolithography method to form openings 152a and 153a that expose the insulating layer 113. Of these, the opening 152a is formed at a position where it overlaps with the terminal electrode 133 of the electronic component 130, and the opening 153a is formed at a position where it does not overlap with the electronic component 130 and overlaps with the wiring pattern 143b.

Next, as shown in FIG. 12, the insulating layers 113 and 112 in the portion not covered with the copper foil 142c are removed by performing laser processing or blasting using the copper foil 142c as a mask. As a result, the via 152b is formed in the insulating layer 113 at the position corresponding to the opening 152a of the copper foil 142c, and the terminal electrode 133 of the electronic component 130 is exposed. Similarly, vias 153b are formed in the insulating layers 113 and 112 at positions corresponding to the openings 153a of the copper foil 142c, and the wiring pattern 143b is exposed.

Next, as shown in FIG. 13, via electroless plating and electrolytic plating are applied to form via conductors 152 and 153 on the inner walls of vias 152b and 153b, respectively. As a result, the terminal electrode 133 and the wiring pattern 143b of the electronic component 130 are connected to the copper foil 142c via the via conductors 152 and 153.

Next, as shown in FIG. 14, the wiring pattern 142 is formed by patterning the copper foil 142c by a known method such as a photolithography method. As a result, the conductor layer L2 is completed.

Next, as shown in FIG. 15, a sheet in which the insulating layer 114 and the copper foil 141c are laminated is vacuum-heat-pressed so as to embed the conductor layer L2, and then the interface between the copper foil 171 and the copper foil 144c is peeled off. , The support 190 is separated.

Next, as shown in FIG. 16, the opening 151a that exposes the insulating layer 114 to the copper foil 141c by removing a part of the copper foils 141c and 144c by etching using a known method such as a photolithography method. Is formed, and openings 154a and 155a for exposing the insulating layer 111 are formed in the copper foil 144c. Of these, the opening 151a is formed at a position overlapping the wiring pattern 142, the opening 154a is formed at a position overlapping the heat dissipation pattern 143a, and the opening 154a is formed at a position overlapping the wiring pattern 143b.

Next, as shown in FIG. 17, by performing laser processing or blast processing using the copper foils 141c and 144c as masks, the insulating layer 114 in the portion not covered with the copper foil 141c is removed, and the copper foil 144c is used. The insulating layer 111 in the uncovered portion is removed. As a result, the via 151b is formed in the insulating layer 114 at the position corresponding to the opening 151a of the copper foil 141c, and the wiring pattern 142 of the conductor layer L2 is exposed. Further, vias 154b and 155b are formed in the insulating layer 111 at positions corresponding to the openings 154a and 155a of the copper foil 141c, respectively, and the heat dissipation pattern 143a and the wiring pattern 143b of the conductor layer L3 are exposed.

Next, as shown in FIG. 18, via electroless plating and electrolytic plating are applied to form via conductors 151, 154, 155 on the inner walls of vias 151b, 154b, and 155b, respectively. As a result, the wiring pattern 142 of the conductor layer L2 is connected to the copper foil 141c via the via conductor 151. Further, the heat dissipation pattern 143a of the conductor layer L3 is connected to the copper foil 144c via the via conductor 154, and the wiring pattern 143b of the conductor layer L3 is connected to the copper foil 144c via the via conductor 155.

Next, as shown in FIG. 19, the wiring patterns 141 and 144 are formed by patterning the copper foils 141c and 144c by a known method such as a photolithography method. As a result, the conductor layers L1 and L4 are completed. Then, if the solder resists 121 and 122 are formed at predetermined plane positions, the electronic component built-in circuit board 100 according to the present embodiment is completed.

As described above, in the present embodiment, since the conductor layer L3 including the heat dissipation pattern 143a and the wiring pattern 143b is first formed and then embedded in the insulating layer 111, the thickness of the heat dissipation pattern 143a is increased. be able to. Moreover, since the surfaces of the heat dissipation pattern 143a and the wiring pattern 143b and the surface of the insulating layer 111 form the same plane, the thickness of the insulating layer 112 can be made very thin. As a result, the heat generated by the operation of the electronic component 130 is efficiently transferred to the heat dissipation pattern 143a, so that high heat dissipation characteristics can be obtained.

<Second embodiment>
FIG. 20 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 200 according to the second embodiment of the present invention.

As shown in FIG. 20, in the electronic component built-in circuit board 200 according to the second embodiment, the first portion B1 in which the conductor layer L3 is embedded in the insulating layer 111 and the insulating layer 111 without being embedded in the insulating layer 111. It differs from the electronic component built-in circuit board 100 according to the first embodiment in that it has a second portion B2 located on the surface of the above. Since the other basic configurations are the same as those of the electronic component built-in circuit board 100 according to the first embodiment, the same elements are designated by the same reference numerals, and duplicate description will be omitted.

In the electronic component built-in circuit board 200 according to the second embodiment, the heat dissipation pattern 143a is composed of the first and second portions B1 and B2, and the wiring pattern 143b is composed of only the second portion B2. That is, the heat dissipation pattern 143a is composed of a portion embedded in the insulating layer 111 (first portion B1) and a portion protruding from the surface of the insulating layer 111 (second portion B2), and the wiring pattern 143b is the insulating layer 111. It consists only of a portion (second portion B2) provided on the surface of the. Therefore, unlike the first embodiment, the heat dissipation pattern 143a and the wiring pattern 143b are not the same thickness, and the heat dissipation pattern 143a is thicker than the wiring pattern 143b.

With such a configuration, the line width and the space width of the wiring pattern 143b can be further miniaturized while ensuring the same heat dissipation as that of the electronic component built-in circuit board 100 according to the first embodiment.

Next, a method of manufacturing the electronic component built-in circuit board 200 according to the second embodiment will be described.

First, after preparing the base material 160 shown in FIG. 2, as shown in FIG. 21, heat dissipation patterns 143a are formed on both surfaces by performing electrolytic plating using the copper foil 143c as a seed layer. By performing electrolytic plating with a mask (resist) (not shown) formed on the surface of the copper foil 143c, the heat dissipation pattern 143a can be selectively formed. At this time, unlike the first embodiment, the wiring pattern 143b is not formed. The heat dissipation pattern 143a is thicker than the copper foil 143c.

Next, as shown in FIG. 22, a base material 170 having a structure in which copper foils 144c and 171 are laminated on one surface of the insulating layer 111 is prepared, and the base material 170 is embedded so that the heat dissipation pattern 143a is embedded in the insulating layer 111. The material 170 is laminated on both sides of the base material 160. The copper foil 144c is thinner than the heat dissipation pattern 143a and thicker than the copper foil 143c.

Next, as shown in FIG. 23, the two base materials 180 are separated from the base material 160 by peeling off the interface between the copper foil 161 and the copper foil 143c. After that, since the same step is performed on the two base materials 180, the step on one base material 180 will be described below.

Next, as shown in FIG. 24, the base material 180 is mounted on the support 190 via the adhesive 191. By patterning the copper foil 143c in this state, the wiring pattern 143b is formed as shown in FIG. That is, the copper foil 143c is the second portion B2 itself, and the copper foil 143c remaining on the surface of the insulating layer 111 by patterning becomes the wiring pattern 143b. At this time, it is preferable that the copper foil 143c located on the heat dissipation pattern 143a also remains.

Next, as shown in FIG. 26, the insulating layer 112 is formed by laminating, for example, an uncured (B stage state) resin sheet or the like on the surface of the insulating layer 111 by vacuum pressure bonding or the like. Unlike the first embodiment, in this embodiment, since the wiring pattern 143b is provided on the surface of the insulating layer 111, the forming surface of the insulating layer 112 is not a completely flat surface, but the thickness of the copper foil 143c is increased. By setting the thickness thin, the thickness of the insulating layer 112 can also be set thin.

After that, the electronic component built-in circuit board 200 according to the second embodiment is completed by sequentially performing the steps described with reference to FIGS. 9 to 19.

As described above, in the present embodiment, since the wiring pattern 143b is formed by patterning the thin copper foil 143c, in addition to the effect of the first embodiment, the line width and the space width of the wiring pattern 143b are increased. It becomes possible to make it finer.

<Third embodiment>
FIG. 27 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 300 according to the third embodiment of the present invention.

As shown in FIG. 27, in the electronic component built-in circuit board 300 according to the third embodiment, a plurality of openings 103 are formed in the heat dissipation pattern 143a located in the first region A1 that overlaps with the electronic component 130 in a plan view. Unlike the electronic component built-in circuit board 100 according to the first embodiment, the plurality of via conductors 156 connected to the heat dissipation pattern 144a are in contact with the back surface 132 of the electronic component 130 via the opening 103. There is. Since the other basic configurations are the same as those of the electronic component built-in circuit board 100 according to the first embodiment, the same elements are designated by the same reference numerals, and duplicate description will be omitted.

According to the present embodiment, since the via conductor 156 is in contact with the back surface 132 of the electronic component 130, it is possible to obtain even higher heat dissipation characteristics than the electronic component built-in circuit board 100 according to the first embodiment.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention, and these are also the present invention. Needless to say, it is included in the range.

100, 200, 300 Electronic component built-in circuit board 101 Electronic component built-in circuit board upper surface 102 Electronic component built-in circuit board lower surface 103 Opening 111-114 Insulation layer 121, 122 Solder resist 130 Electronic component 131 Electronic component main surface 132 Electronic Back side of component 133 Terminal electrodes 141, 142, 144 Wiring pattern 141c to 144c Copper foil 143a, 144a Heat dissipation pattern 143b, 144b Wiring pattern 151 to 156 Via conductor 151a to 155a Opening 151b to 155b Via 160 Base material 161 Support 161 162 Copper foil 170 Base material 171 Copper foil 180 Base material 190 Support 191 Adhesive A1 First region A2 Second region B1 First part B2 Second part L1 to L4 Conductor layer

Claims (14)

With the first, second and third insulating layers,
A first conductor layer formed on one surface of the first insulating layer and
A second conductor layer formed on the other surface of the first insulating layer and located between the first and second insulating layers,
An electronic component embedded between the second insulating layer and the third insulating layer is provided.
At least a part of the second conductor layer is embedded in the first insulating layer.
The second conductor layer has a first region that overlaps with the electronic component in a plan view and a second region that does not overlap with the electronic component in a plan view.
A circuit board with built-in electronic components, wherein the thickness of the second conductor layer in the first region is thicker than the thickness of the first conductor layer. The circuit board with built-in electronic components according to claim 1, wherein the other surface of the first insulating layer and the surface of the second conductor layer form the same plane. The electronic component built-in circuit board according to claim 1, wherein the thickness of the second conductor layer in the first region is thicker than the thickness of the second conductor layer in the second region. .. 3. The second conductor layer in the second region is formed on the other surface of the first insulating layer without being embedded in the first insulating layer. The circuit board with built-in electronic components described in. Any of claims 1 to 4, wherein the thickness of the second insulating layer at a position overlapping the electronic component in a plan view is thinner than the thickness of the second conductor layer in the first region. The circuit board with built-in electronic components described in item 1. The second conductor layer has an opening in the first region and has an opening.
The electronic component built-in circuit board according to any one of claims 1 to 5, wherein the via conductor connected to the first conductor layer is in contact with the electronic component through the opening. .. With the first, second and third insulating layers,
A conductor layer located between the first and second insulating layers,
An electronic component embedded between the second insulating layer and the third insulating layer is provided.
The conductor layer has a first region that overlaps with the electronic component in a plan view and a second region that does not overlap with the electronic component in a plan view.
A circuit board with built-in electronic components, wherein the thickness of the conductor layer in the first region is thicker than the thickness of the conductor layer in the second region. The built-in electronic component according to claim 7, wherein a part of the conductor layer is embedded in the first insulating layer, and the remaining part of the conductor layer is embedded in the second insulating layer. Circuit board. The circuit board with built-in electronic components according to claim 8, wherein the portion of the conductor layer embedded in the first insulating layer is thicker than the portion embedded in the second insulating layer. Further provided with another conductor layer provided on the surface of the first insulating layer opposite to the surface on which the conductor layer is provided.
9. The other conductor layer is characterized in that it is thinner than the portion of the conductor layer embedded in the first insulating layer and thicker than the portion embedded in the second insulating layer. Circuit board with built-in electronic components as described in. The first step of forming the conductor layer including the heat dissipation pattern on the support, and
A second step of laminating the first insulating layer on the support so as to embed the conductor layer, and
A third step of exposing the conductor layer by peeling off the support, and
A fourth step of laminating a second insulating layer on the surface of the exposed conductor layer, and
A fifth step of placing an electronic component on the surface of the second insulating layer so as to overlap the heat dissipation pattern, and
A method for manufacturing a circuit board containing an electronic component, which comprises a sixth step of laminating a third insulating layer on the surface of the second insulating layer so that the electronic component is embedded. The conductor layer has a first portion embedded in the first insulating layer and a second portion located on the surface of the first insulating layer without being embedded in the first insulating layer. ,
The built-in electronic component according to claim 11, wherein at least a part of the second portion of the conductor layer is removed after the third step and before the fourth step. How to manufacture a circuit board. The electronic component built-in circuit board according to claim 12, wherein after performing the third step and before performing the fourth step, all the second portion of the conductor layer is removed. Production method. By patterning the second portion of the conductor layer after the third step and before the fourth step, the second portion of the conductor layer does not overlap with the electronic component in a plan view, and the heat is dissipated. The method for manufacturing a circuit board with built-in electronic components according to claim 12, wherein a wiring pattern having a thickness thinner than the pattern is formed on the conductor layer.

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