JP2020028119A - Solid-state imaging device - Google Patents

Abstract

Kind Code: A1 A solid-state imaging device having an AD converter with improved processing capability and capable of obtaining a high-quality photographed image is realized. A solid-state imaging device includes analog circuits (231, 281) having charge storage elements (CR1, CS1, CR2, CS2) that temporarily hold pixel output signals, and input of the held pixel output signals. and an AD converter (230) having a single-slope AD conversion circuit (132). [Selection drawing] Fig. 3

Description

  The present invention relates to a solid-state imaging device using an AD converter.

  2. Description of the Related Art In recent years, solid-state imaging devices have become widespread and their applications are widespread. Above all, a CMOS (Complementary Metal Oxide Semiconductor) image sensor is widely used as a solid-state imaging device because it can be produced by a general-purpose semiconductor forming process.

JP 2012-85063 A (released on April 26, 2012)

  However, further improvement in the performance of the solid-state imaging device is desired, and therefore, further improvement in the processing capability of AD conversion in the solid-state imaging device is desired.

  Patent Literature 1 discloses that the frame rate of a solid-state imaging device can be improved by simultaneously performing pixel reading and column AD conversion (column ADC). However, it does not specifically disclose what kind of circuit configuration of the AD converter can be realized.

  An object of one embodiment of the present invention is to realize a solid-state imaging device that has an AD converter with improved processing capability and can obtain a high-quality captured image.

(1) One embodiment of the present invention includes a plurality of pixels and an AD converter that receives a pixel output signal from the pixel and performs AD conversion. The AD converter temporarily converts the pixel output signal. A solid-state imaging device, comprising: an analog circuit having a charge storage element for temporarily storing; and a single-slope AD conversion circuit to which the pixel output signal temporarily stored by the analog circuit is input. Device.
(2) In one embodiment of the present invention, in addition to the configuration of the above (1), the A / D converter transmits the pixel output signal to the charge storage element within one cycle of sequentially receiving the pixel output signal from a plurality of pixels. And a single slope type AD conversion of the pixel output signal held before the cycle by the analog circuit.
(3) In one embodiment of the present invention, in addition to the configuration of (1) or (2), the pixel output signal includes a reset potential and a signal potential, and the analog circuit includes at least the charge storage element. A solid-state imaging device including two pixels.
(4) In one embodiment of the present invention, in addition to the configuration of (3), the reset potential and the signal potential are input to the AD conversion circuit. is there.
(5) In one embodiment of the present invention, in addition to the configuration of (3), the AD conversion circuit includes (i) a reference potential, and (ii) the reset potential based on the reference potential. A solid-state imaging device characterized in that a composite potential that is a difference from a signal potential is input.
(6) One embodiment of the present invention includes an AD converter that receives a plurality of pixels and a pixel output signal including a reset potential and a signal potential from the pixels and performs AD conversion, and the AD converter includes: An analog circuit that includes at least two pixels of a charge storage element that temporarily holds the pixel output signal and that can output a combined potential that is a difference between the reset potential and the signal potential with reference to a reference potential. And a unit A / D converter having a single slope type A / D conversion circuit capable of inputting the combined potential and the reference potential. The unit A / D converter has a plurality of unit A / D converters. The solid-state imaging device is characterized in that a potential obtained by adding the combined potential of the unit AD converter can be input to the AD conversion circuit.
(7) In one embodiment of the present invention, in addition to the configuration of (5) or (6), the analog circuit includes a first charge storage element that holds a potential difference between the reference potential and the reset potential; A second charge storage element for holding the signal potential, wherein the combined potential is generated by connecting the first charge storage element and the second charge storage element in series. It is a solid-state imaging device.
(8) In one embodiment of the present invention, in addition to the configuration of any one of the above (1) to (7), the A / D converter supplies the charge storage element to the charge storage element during the execution of the single slope A / D conversion. A solid-state imaging device is characterized in that a switch for performing a process of storing the pixel output signal is not turned on or off.

  According to one embodiment of the present invention, an AD converter with improved processing capability that can be applied to a solid-state imaging device can be realized.

FIG. 1 is a diagram illustrating a solid-state imaging device according to a first embodiment. FIG. 2 is a schematic circuit diagram illustrating a configuration of a pixel of the solid-state imaging device according to Embodiment 1. FIG. 2 is a schematic circuit diagram illustrating a configuration of an AD converter of the solid-state imaging device according to the first embodiment. 4 is a timing chart illustrating an operation of the AD converter of the solid-state imaging device according to the first embodiment. FIG. 9 is a schematic circuit diagram illustrating a configuration of an AD converter of the solid-state imaging device according to the second embodiment. FIG. 11 is a schematic circuit diagram illustrating a state of an AD converter of the solid-state imaging device according to Embodiment 2 in a predetermined period. FIG. 9 is a schematic circuit diagram illustrating a configuration of an AD converter of a solid-state imaging device according to Embodiment 3. 9 is a timing chart illustrating the operation of the AD converter of the solid-state imaging device according to Embodiment 3.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the configuration, relative arrangement, operation, and the like of the configuration described in this embodiment are merely examples, and the scope of the present invention should not be limitedly interpreted by these. Further, the drawings are schematic, and dimensional ratios, shapes, and magnitudes and ratios of numerical values are different from actual ones. In each drawing, the same or corresponding components may be denoted by the same reference numerals.

[Embodiment 1]
Hereinafter, Embodiment 1 of the present invention will be described in detail.

(Configuration of solid-state imaging device)
FIG. 1 is a diagram illustrating a solid-state imaging device 1 according to the first embodiment. In the solid-state imaging device 1, a plurality of pixels 120 are arranged in a matrix on a plane, and each of the pixels 120 is connected to a row selection signal line 111 and a readout signal line 112. The vertical scanning circuit 110 selects a row of the pixel 120 through the row selection signal line 111 of each row. The pixel 120 selected in the row outputs a signal to the readout signal line 112 of each column. The AD converter 230 is connected to the read signal line 112 of each column, and the memory 142 is further connected. The AD converter 230 performs column AD conversion of acquiring a pixel output signal from the pixel 120 in the column, sequentially converting the pixel output signal into a digital signal, and outputting the digital signal. The horizontal scanning circuit 140 selects a column of the memory 142 through a column selection signal line 141 of each column. The selected memory 142 sequentially outputs digital signals through the horizontal output line 143. The solid-state imaging device 1 is a CMOS image sensor in the present embodiment, but may be another imaging device.

(Pixel configuration)
FIG. 2 is a circuit diagram schematically illustrating a configuration example of the pixel 120 of the solid-state imaging device 1. The pixel 120 includes a photodiode PD, a transfer transistor Ttr, a reset transistor Rtr, a selection transistor Str, an amplification transistor Atr, and a signal charge storage unit FD. Further, the pixel 120 supplies a readout signal line 112, a transfer signal line for transmitting a transfer signal TX, a reset signal line for transmitting a reset signal RST, a row selection signal line 111 for transmitting a row selection signal SEL, and a power supply voltage Vdd. Connected to the power line. Note that, in FIG. 1, for simplicity, reset signal lines, selection signal lines, and the like are omitted, but these are signal lines arranged for each row similarly to the row selection signal lines 111. It is.

  The reset transistor Rtr turns on in accordance with the reset signal RST, thereby discharging the signal charges stored in the signal charge storage unit FD, and resetting the potential of the signal charge storage unit FD to a high potential. The photodiode PD (sensor element) performs photoelectric conversion and generates signal charges corresponding to the amount of received light (incident light). The pixel 120 may include another type of light receiving element, sensor element, or the like, instead of the photodiode PD. The transfer transistor Ttr transfers the signal charge generated by the photodiode PD to the signal charge storage unit FD by being turned on in accordance with the transfer signal TX. The signal charge storage section FD is a floating diffusion region where signal charges are stored. Therefore, the potential of the signal charge storage section FD decreases according to the amount of the stored signal charge.

  In the selection transistor Str, the gate is connected to the row selection signal line 111, the drain is connected to the source of the amplification transistor Atr, and the source is connected to the read signal line 112. When the selection transistor Str is turned on in accordance with the row selection signal SEL, only the pixels 120 in the selected row among the plurality of pixels 120 arranged in the solid-state imaging device 1 output a pixel output signal to the readout signal line 112. .

  The amplification transistor Atr operates as a source follower transistor in which the source voltage (output voltage) changes so as to follow the gate voltage (input voltage) with a constant voltage gain. In the amplification transistor Atr, the gate is connected to the signal charge storage unit FD, and the drain is connected to the power supply line. Thus, the amplification transistor Atr outputs a signal voltage obtained by amplifying the potential of the signal charge storage unit FD to the read signal line 112 via the selection transistor Str.

  The voltage value (reset potential) of the pixel output signal VSIG when the potential of the signal charge storage unit FD is reset is set to VSIG (RST). In addition, the voltage value (signal potential) of the pixel output signal VSIG when the potential of the signal charge storage unit FD decreases according to the amount of signal charge stored in the PD is set to VSIG (SIG).

(Configuration of AD converter 230)
FIG. 3 is a schematic circuit diagram illustrating a configuration of the AD converter 230 according to the first embodiment. The pixel output signal VSIG is input to the AD converter 230. The pixel output signal VSIG is an output of the pixel 120 whose row is selected by the vertical scanning circuit 110. The AD converter 230 reads out (samples) the reset potential VSIG (RST) generated in the pixel 120 and the signal potential VSIG (SIG) corresponding to the amount of signal charge accumulated in the PD, and obtains a difference. A sampling (Correlated Double Sampling: abbreviated CDS) operation is performed. AD converter 230 outputs the difference as a digital signal D_OUT.

  The AD converter 230 includes a preceding circuit and a subsequent AD conversion circuit 132. In the following description, the side closer to the input end of the AD converter 230 will be referred to as the input side, and the side closer to the digital output end will be referred to as the output side. The preceding circuit has a configuration in which two analog circuits 231 and 281 having the same configuration are connected in parallel. The input terminal to which the pixel output signal VSIG is input is branched and connected to the analog circuits 231 and 281 respectively. Further, a reference potential VCDS_REF is also introduced into each of the analog circuits 231 and 281. The outputs of the respective analog circuits 231 and 281 are merged and input to the AD conversion circuit 132.

  First, the configuration of the analog circuit 231 will be described. The pixel output signal VSIG is further branched into two and connected to a switch SIG_SMP1 and a switch RST_SMP1, respectively. A switch CDS_REF_SMP1 is connected to an input terminal of the reference potential VCDS_REF. A capacitor CS1 (second charge storage element) is provided between the output side of the switch SIG_SMP1 and the ground. The switch ACDS_EN1 is provided between the output side of the switch SIG_SMP1 and the output side of the switch RST_SMP1. A capacitor CR1 (first charge storage element) is provided between the output side of the switch RST_SMP1 and the output side of the switch CDS_REF_SMP1. A switch CMP_CCNT1 is provided between the output side of the switch CDS_REF_SMP1 (the output side of the capacitor CR1) and the output end of the analog circuit 231.

  The configuration of each switch of the analog circuit 281 is similar to that of the analog circuit 231. The signs of the switches and capacitors in the analog circuit 281 are the same as those of the switches and capacitors in the analog circuit 231 except that the last one is changed to two.

  Next, the configuration of the AD conversion circuit 132 will be described. The AD conversion circuit 132 is a single slope type AD conversion circuit. The input terminal of the AD conversion circuit 132 is connected to the comparator 133 through the coupling capacitor CIN. Further, the clip voltage VAZCLP can be introduced to the input terminal of the AD conversion circuit 132 via the switch CMP_AZCLP. The ramp signal VRAMP is introduced to the other input terminal of the comparator 133 through the coupling capacitor CIN. The output of the comparator 133 is input to the counter 134. The counter 134 outputs the pulse count number of the clock signal CLK within a predetermined period as the output digital signal D_OUT of the AD converter 230. A single-slope A / D conversion circuit performs an A / D conversion by comparing an analog input signal and a ramp signal with a comparator, and digitally outputting a pulse count number of a clock signal required until the magnitude relationship is inverted. Refers to a circuit.

(Operation of AD converter 230)
FIG. 4 is a timing chart showing the on / off operation of each switch. The operation of the AD converter 230 will be described with reference to this.

  The AD converter 230 alternately performs the operation of reading the set of the reset potential and the signal potential for each pixel 120 sequentially sent by the pixel output signal VSIG by the two analog circuits 231 and 281. Further, the voltage signal for each pixel 120 held by the two analog circuits 231 and 281 is input to the AD conversion circuit 132 to perform AD conversion processing. The reading process and the AD conversion process proceed simultaneously and in parallel.

  One analog circuit 231 performs the reading process of the pixels 120 in the k-th row within one unit H time (unit horizontal time), and performs the AD conversion process in the next one unit H time. Here, the unit H time is a cycle at which the AD converter 230 reads one pixel, and also a cycle at which one pixel outputs a digital signal. The unit H time is also a line time. The other analog circuit 281 performs an AD conversion process on the pixels 120 in the (k-1) th row in the first one unit H time, and reads out the pixels 120 in the (k + 1) th row in the next one unit H time. It is carried out. The cycle of the on / off operation of each switch is 2 units of H time. In the following description, processing for one pixel (k-th row) will be described over two units of H time, and ON / OFF operations will be described for all switches.

<Periods T11 to T13>
Period T11: First, the switch CDS_REF_SMP2 is on and the other switches are off. At the beginning of the period, the switches CDS_REF_SMP1 and the switch CMP_AZCLP are turned on, and at the end of the period, the switch CMP_AZCLP is turned off.

  Period T12 (reset potential sampling period): The AD converter 230 operates so as to adapt the period T12 to a period in which the pixels 120 in the k-th row output the reset potential VSIG (RST) as the output signal VSIG. The switch RST_SMP1 is turned on at the beginning of the period, and turned off at the end of the period. Then, a reference potential VCDS_REF and a reset potential VSIG (RST) are applied to both ends of the capacitor CR1 during the period. Therefore, the potential difference between both ends of the capacitor CR becomes VCDS_REF-VSIG (RST). The period T12 is a period in which the reset potential of the pixel 120 is sampled in the capacitor CR1. Further, CMP_CCNT2 is turned on at the beginning of the period, and is turned off together with the switch CDS_REF_SMP2 by the end. At this time, CMP_AZCLP is turned on.

Period T13 (sampling period of signal potential): The AD converter 230 operates to adapt the period T13 to a period during which the pixel 120 outputs the signal potential VSIG (SIG) as the output signal VSIG. Turn off the switch CMP_AZCLP at the beginning of the period,
Turn on the switch SIG_SMP1. Then, a signal potential VSIG (SIG) and a ground potential are applied to both ends of the capacitor CS1, respectively. Therefore, the potential difference between both ends of the capacitor CS1 becomes VSIG (SIG). The period T13 is a period during which the signal potential VSIG (SIG) is sampled on the capacitor CS1. At the end of the period, the switch SIG_SMP1 is turned off. When the switch CMP_AZCLP is turned off at the beginning of the period, the switches ACDS_EN2 and CMP_CCNT2 are turned on, and turned off at the end of the period.

  In the above periods T11 to T13, the first unit H time ends, and the reading process from the pixels 120 in the k-th row is completed. The on / off operation of the switches in the analog circuits 231 and 281 in the next unit H time is performed by mutually turning on and off the switches of the analog circuits 231 and 281 in the first unit H time (T11 to T13). It will be replaced.

<Periods T21 to T23>
Period T21 (auto-zero period): The switch CDS_REF_SMP2 and the switch CMP_AZCLP are turned on at the beginning of the period, and the switch CMP_AZCLP is turned off at the end of the period. During the period, the clip voltage VAZCLP is applied to the input terminal of the comparator 133 and is auto-zeroed.

  Period T22 (AD conversion period of reference potential): At the beginning of the period T22, the CMP_CCNT1 is turned on. When the switches CDS_REF_SMP1 and the switch CMP_CCNT1 are on, the reference potential VCDS_REF is input to the comparator 133. During this time, the AD conversion circuit 132 performs AD conversion of the reference potential VCDS_REF. AD conversion is performed as follows. The counting of the number of clocks by the counter 134 and the ramping of the ramp signal VRAMP are started (single-slope AD conversion is started). Here, in the normal state, the ramp signal VRAMP is a constant value VRAMP (ST) having a slightly higher potential than the reference potential VCDS_REF, but is a signal that decreases linearly with time when the ramping is started. When the ramping ends, it returns to the initial constant value. At the start of the ramping, the ramp signal VRAMP is higher in potential than the reference potential VCDS_REF, which is the input voltage to the comparator 133. When the magnitude relation is inverted with the fall of the potential of the ramp signal VRAMP, the comparator output is inverted. Upon detecting the inversion of the comparator output, the counter 134 stops counting. (Single slope type AD conversion is completed). Therefore, here, a voltage corresponding to VRAMP (ST) -VCDS_REF, which is a reference potential VCDS_REF based on VRAMP (ST), is converted into a count number. In the A / D conversion of the reference potential (period T22), the count is down-counted. When the counting stops, the switch CMP_CCNT1 is turned off. During the period from the start to the stop of the count, the operation of turning on and off the switch inside the AD converter 230 is not performed. This is to prevent an erroneous end of counting due to switching noise. Also, the switch CDS_REF_SMP1 is turned off. At this time, CMP_AZCLP is turned on. Then, the clip voltage VVAZCLP is applied to the input terminal of the comparator 133 and is auto-zeroed. Further, the AD converter 230 operates so that the period T22 is adapted to the period in which the pixels 120 in the (k + 1) -th row output the reset potential VSIG (RST) as the pixel output signal VSIG. The switch RST_SMP2 is turned on at the beginning of the period and turned off at the end.

  Period T23 (combination of potential and AD conversion period of combined potential): At the beginning of the period, the switch CMP_AZCLP is turned off, and the auto-zero operation ends. Then, when the switches ACDS_EN1 and CMP_CCNT1 are turned on, the capacitors CR1 and CS1 are connected in series. Generally, a capacitor tries to maintain a potential difference between both ends unless electric charges enter and exit. Therefore, the potential difference VCDS_REF-VSIG (RST) held in the capacitor CR1 and the potential difference VSIG (SIG) held in the capacitor CS1 are connected in series. Since the capacitor CS1 is grounded, the input to the AD conversion circuit 132 is the combined potential VC that is VCDS_REF−VSIG (RST) + VSIG (SIG). That is, the composite potential VC is obtained by subtracting the reset potential VSIG (RST) from the reference potential VCDS_REF and further adding the signal potential VSIG (SIG). The combined potential is a difference VSIG (SIG) -VSIG (RST) between the reset potential and the signal potential with reference to the reference potential. The composite potential VC is input to the comparator 133 and AD-converted. The clock counting by the counter 134 and the ramping of the ramp signal VRAMP are executed, and the single slope AD conversion is performed in the same manner as in the above-described period T22. Then, here, the combined potential VC based on VRAMP (ST) is converted into a count number. Further, in the A / D conversion of the composite potential VC, the up-count is performed by inheriting the count number from the end of the down-count in the A / D conversion of the reference potential (period T22). Therefore, when the AD conversion of the composite potential (period T23) is completed, the count number corresponds to the difference between the AD conversion value of the composite potential and the AD conversion value of the reference potential. That is, VSIG (RST) -VSIG (SIG) corresponds to the final count number, and is output from the AD converter 230 as a digital output D_OUT. During the period from the start to the stop of the count, the operation of turning on and off the switch inside the AD converter 230 is not performed. This is to prevent an erroneous end of counting due to switching noise. At the end of the period, the switches ACDS_EN1 and CMP_CCNT1 are turned off. Further, the AD converter 230 operates so as to adjust the period T23 to a period during which the pixel 120 in the (k + 1) -th row outputs the signal potential VSIG (SIG) as the output signal VSIG. The switch SIG_SMP2 is turned on at the beginning of the period and turned off at the end.

  In the above periods T21 to T23, the next one unit H period ends, and two A / D conversions of the reference potential VCDS_REF and the combined potential VC are completed.

  The on / off operations of the switches of the analog circuits 231 and 281 in the first one unit H time (T11 to T13) are interchanged in the next one unit H time (T21 to T23). Accordingly, similarly to the operation of the analog circuit 231 in the periods T11 to T13, the analog circuit 281 performs the reading process on the pixel 120 in the next selected row k + 1 during the periods T21 to T23. Further, similarly to the operation of the analog circuit 231 in the periods T21 to T23, in the first one unit H time (T11 to T13), the analog circuit 281 performs the AD conversion process on the pixel 120 of the selected row k-1. are doing. As described above, while one analog circuit is performing read processing from the pixel 120, the other analog circuit performs predetermined processing on the pixel output signal that has already been read and temporarily stored, and supplies the pixel output signal to the AD conversion circuit 132.

(Effect of Embodiment 1)
Each of the analog circuits 231 and 281 has two capacitors (charge storage elements). In the reading period, the capacitors CR1 and CR2 read the reset potential SIG (RST) (the switches RST_SMP1 and RST_SMP2 are turned on) and hold the potential difference from a predetermined potential until AD conversion. In the read period, the capacitors CS1 and CS2 read the signal potential SIG (SIG) (the switches SIG_SMP1 and SIG_SMP2 are turned on) and hold the signal potential SIG (SIG) until the AD conversion as a potential difference from a predetermined potential. The analog circuit 231 having two capacitors (charge storage elements) can temporarily store the reset potential SIG (RST) and the signal potential SIG (SIG) for one pixel for AD conversion. The same applies to the analog circuit 281. Therefore, the AD converter 230 has a charge storage element for holding a pixel output signal including the reset potential SIG (RST) and the signal potential SIG (RST) for two pixels. In the AD converter 230, the two analog circuits 231 and 281 alternately perform read processing and output processing to the AD conversion circuit to read a pixel output signal and perform AD conversion of the previously read pixel output signal. The processing is performed in parallel within one unit H time.

  As described above, in the solid-state imaging device 1 according to the first embodiment, the pixel reading process and the A / D conversion process are performed simultaneously in parallel by the above-described circuit configuration, so that the processing capability is significantly improved. And a solid-state imaging device including the converted AD converter.

  In addition, from the AD converter 230, VSIG (RST) -VSIG (SIG) is obtained as a final output for each pixel 120, and the CDS operation is realized. A threshold variation (hereinafter, pixel variation) due to a threshold characteristic of a transistor or the like of each pixel 120 is canceled by calculating a difference between two pixel outputs of a reset potential VSIG (RST) and a signal potential VSIG (SIG). . This is realized by effectively generating the composite potential VC in the analog circuit 231 or the like in the period T22 or the like. Further, variation in characteristics of each column of the AD conversion circuit 132 (hereinafter, column variation) is canceled by taking a difference between two AD conversion results of a reference potential (digital value) and the combined potential (digital value). Is done. This is realized by a counter (up-down counter) in which a count for AD conversion of the reference potential VCDS_REF is set to a down-count, and then a count for AD conversion of the composite potential VC is an up-count. However, the method for obtaining the difference between the two AD conversion results is not limited to this, and may be replaced with another known method. For example, it is realized by a counter (up-up counter) in which a count for AD conversion of the reference potential VCDS_REF is set as an up-count, the count value is inverted for all bits, and then a count for AD conversion of the composite potential VC is an up-count. May be.

  As described above, according to the AD converter 230, a final output in which both the pixel variation and the column variation are canceled is obtained. In addition, since the operation is performed to prevent an erroneous end of counting due to switching noise, noise of the pixel due to this operation is also suppressed. In the solid-state imaging device 1 according to the first embodiment, obtaining a high-quality captured image in which such variation (noise) is suppressed is simultaneously realized.

[Embodiment 2]
Embodiment 2 of the present invention will be described below.

(Configuration of solid-state imaging device, AD converter 330)
The solid-state imaging device according to the second embodiment has the same configuration as the solid-state imaging device 1 according to the first embodiment except that the configuration of the AD converter is different. FIG. 5 is a schematic circuit diagram illustrating a configuration of the AD converter 330 of the solid-state imaging device according to the second embodiment. The AD converter 330 includes the same circuit as the AD converter 230 of the first embodiment as unit AD converters 330a and 330b. Therefore, in the solid-state imaging device according to the second embodiment, the AD converter 330 is provided over two rows.

  The unit AD converter 330a includes analog circuits 331a and 381a and an AD conversion circuit 332a, and the AD conversion circuit 332a includes a comparator 333a and a counter 334a. The unit AD converter 330b includes analog circuits 331b and 381b and an AD conversion circuit 332b, and the AD conversion circuit 332b has a comparator 333b and a counter 334b. The signs of the switches of the unit AD converters 330a and 330b are respectively obtained by adding _A and _B to the signs of the corresponding switches in the AD converter 230, respectively. The signs of the capacitors of the unit A / D converters 330a and 330b are obtained by adding a and b to the end of the signs of the corresponding capacitors in the A / D converter 230, respectively.

  However, as a point different from the AD converter 230, in the unit AD converter 330a, the ground-side terminal of the capacitor CS1a is branched into two. One of the branches is grounded via switch CB_ASE_EN1. The other is connected to the output terminal of the capacitor CR1b of the unit AD converter 330b via the switch HB_INNING_EN1. The same applies to the ground side of the capacitor CS2a. One of the branches is grounded via switch CB_ASE_EN2. The other is connected to the output terminal of the capacitor CR2b of the unit AD converter 330b via the switch HB_INNING_EN2.

(Operation of AD converter 330)
Normal operation mode: Each of the unit AD converters 330a and 330b can operate exactly the same as the AD converter 230 of the first embodiment. In the normal operation mode, the switches CB_ASE_EN1 and CB_ASE_EN2 are always on, and the switches HB_INNING_EN1 and HB_INNING_EN2 are always off. Therefore, each of the unit AD converters 330a and 330b is separated, and each has the same circuit configuration as the AD converter 230. The unit AD converter 330a performs column AD conversion of the n-th column, and the unit AD converter 330b performs column AD conversion of the (n + 1) -th column.

  Horizontal addition operation mode: Also, the unit AD converters 330a and 330b can execute the horizontal addition operation in cooperation with each other. This operation mode will be described in detail below.

  In the horizontal addition operation mode, the AD conversion circuit 332b of the unit AD converter 330b does not operate. The switches CMP_CCNT1_B and CMP_CCNT2_B input to the AD conversion circuit 332b are always off. Therefore, at this time, the number of columns of the solid-state imaging device is half that in the normal mode.

  Also in the horizontal addition operation mode, normally, the switches CB_ASE_EN1 and CB_ASE_EN2 are on, and the switches HB_INNING_EN1 and HB_INNING_EN2 are off. Thus, the analog circuits 331a, 381a, 331b, and 381b of the unit AD converters 330a and 330b normally operate in the same manner as the AD converter 230 of the first embodiment.

  However, the operation differs for the operation of synthesizing the potential difference held in the capacitor in the period corresponding to the period T23 in the first embodiment. In the AD converter 330, the potential differences held in the capacitors CR1a, CS1a, CR1b, and CS1b are combined. FIG. 6 shows the on / off state of the switch during the combining operation. In this period, the switches CB_ASE_EN1_A in the unit AD converter 330a are turned off and the switches HB_INNING_EN1 are turned on in accordance with the turning on of the switches ACDS_EN1_A and ACDS_EN1_B. Then, the capacitors CR1a, CS1a, CR1b, and CS1b are connected in series. With this operation, the potential differences held in the capacitors CR1a, CS1a, CR1b, and CS1b are combined and input to the AD conversion circuit 332a. That is, the signals of the pixels in the n-th column and the (n + 1) -th column received by the analog circuits 331a and 331b are added and input to the AD conversion circuit 332a. Similarly, during the period corresponding to the period T13 in the first embodiment, the operation of synthesizing the potential difference held in the capacitors CR2a, CS2a, CR2b, and CS2b is performed. That is, the signals of the pixels in the n-th column and the (n + 1) -th column received by the analog circuits 381a and 381b are added and input to the AD conversion circuit 332a. In any case, the magnitude of the combined potential input to the AD conversion circuit 332a is equivalent to two pixels, which is about twice as large as in the normal mode.

(Effect of Embodiment 2)
In the normal operation mode, exactly the same processing as in the first embodiment is performed on the pixel output signal VSIG [n] in the n-th column and the pixel output signal VSIG [n + 1] in the (n + 1) -th column. Therefore, the same effect as that of the solid-state imaging device 1 of the first embodiment can be obtained also in the solid-state imaging device of the present embodiment including the AD converter 330.

  Further, the AD converter 330 can add signals from a plurality of columns of pixels in the horizontal addition operation mode, and can greatly improve the sensitivity. Therefore, in the solid-state imaging device according to the present embodiment using the AD converter 330, a captured image with increased light sensitivity can be obtained.

  In the solid-state imaging device according to the second embodiment, the solid-state imaging device capable of switching between the normal operation mode and the horizontal addition operation mode can be realized by the above-described circuit configuration.

[Embodiment 3]
Embodiment 3 of the present invention will be described below.

(Configuration of solid-state imaging device, AD converter 430)
The solid-state imaging device according to the third embodiment has the same configuration as that of the solid-state imaging device 1 according to the first embodiment except that the configuration of the AD converter is different. FIG. 7 is a schematic circuit diagram illustrating a configuration of the AD converter 430 of the solid-state imaging device according to the third embodiment. The AD converter 430 includes an AD conversion circuit 132 that performs single-slope AD conversion similarly to the AD converter 230 of the first embodiment. The input terminal to which the pixel output signal VSIG is input is branched and connected to the analog circuits 431 and 481, respectively. The outputs of the analog circuits 431 and 481 are merged and input to the AD conversion circuit 132. The circuit at the preceding stage of the AD converter 430 has a configuration in which two analog circuits 431 and 481 having the same configuration are connected in parallel. The analog circuits 431 and 481 are different from the analog circuits 231 and 281 of the AD converter 230 according to the first embodiment.

  First, the configuration of the analog circuit 431 will be described. The pixel output signal VSIG is further branched into two and connected to a switch RST_SMP1 and a switch SIG_SMP1, respectively. The switch RST_CMP1 is arranged between the switch RST_SMP1 and the output terminal of the analog circuit 431. A capacitor C_RST1 is connected to a connection between the switch RST_SMP1 and the switch SIG_CMP1, and the other end of the capacitor C_RST1 is grounded. The switch SIG_CMP1 is arranged between the switch SIG_SMP1 and the output terminal of the analog circuit 431. A capacitor C_SIG1 is connected to a connection between the switch SIG_SMP1 and the switch SIG_CMP1, and the other end of the capacitor C_SIG1 is grounded.

  The configuration of the analog circuit 481 is similar to that of the analog circuit 431. The signs of the switches and capacitors in the analog circuit 481 are the same as those of the switches and capacitors in the corresponding analog circuit 431, except that the last letter of 1 is changed to 2. The capacitors C_RST1 and C_RST2 are charge storage elements for temporarily holding the reset potential VSIG (RST) of the pixel output signal VSIG. Each of the capacitors C_SIG1 and C_SIG2 is a charge storage element for temporarily holding a signal potential VSIG (SIG) of the pixel output signal VSIG.

(Operation of AD converter 430)
FIG. 8 is a timing chart showing the on / off operation of each switch. The operation of the AD converter 430 will be described with reference to this.

  The AD converter 430 alternately reads the set of the reset potential VSIG (RST) and the signal potential VSIG (SIG) of each pixel 120 sequentially sent by the pixel output signal VSIG by the two analog circuits 431 and 481. I do. Further, the voltage signals for the respective pixels 120 held by the two analog circuits 431 and 481 are input to the AD conversion circuit 132 to perform AD conversion processing. The reading process and the AD conversion process proceed simultaneously and in parallel.

  One analog circuit 431 reads out the pixels 120 in the k-th row within the first unit H time, and performs an operation for AD conversion processing in the next unit H time. The other analog circuit 281 performs an operation for AD conversion processing on the pixels 120 in the (k-1) th row in the first unit H time, and performs the operation from the pixels 120 in the (k + 1) th row in the next unit H time. Is being read. The cycle of the on / off operation of each switch is 2 units of H time. In the initial state, all switches are turned off.

  The operation of the analog circuit 431 is as follows.

  First unit H time: The analog circuit 431 turns on the switch RST_SMP1 first in conformity with the period in which the reset potential VSIG (RST) [k] of the pixel 120 in the k-th row is output as the output signal VSIG. Turn off. Then, the potential VSIG (RST) [k] is held in the capacitor C_RST1. Next, the switch SIG_SMP1 is turned on and then turned off in conformity with the period in which the signal potential VSIG (SIG) [k] of the pixel 120 in the k-th row is output as the output signal VSIG. Then, the potential VSIG (SIG) [k] is held in the capacitor C_SIG1. Thus, the reading of the pixels in the k-th row is completed.

  Next unit H time: The analog circuit 431 first turns on the switch RST_CMP1. The reset potential VSIG (RST) [k] of the pixel 120 in the k-th row held in the capacitor C_RST1 is input to the AD conversion circuit 132. The AD conversion circuit 132 starts single-slope AD conversion. The ramp signal VRAMP starts ramping, and the counter 134 starts counting down. When the output of the comparator 133 is inverted, the counting stops. Thus, the reset potential VSIG (RST) [k] is AD-converted. During the period from the start to the stop of the count, the operation of turning on and off the switch inside the AD converter 430 is not performed. This is to prevent an erroneous end of counting due to switching noise. After the counting is stopped, the switch RST_CMP2 is turned off. Next, the analog circuit 431 turns on the switch SIG_CMP1. The signal potential VSIG (SIG) [k] of the pixel 120 in the k-th row held in the capacitor C_SIG1 is input to the AD conversion circuit 132. The AD conversion circuit 132 starts single-slope AD conversion. The ramp signal VRAMP starts ramping, and the counter 134 starts up-counting. When the output of the comparator 133 is inverted, the counting stops. Thus, the reset potential VSIG (SIG) [k] is AD-converted. After the counting is stopped, the switch SIG_CMP1 is turned off. During the period from the start to the stop of the count, the operation of turning on and off the switch inside the AD converter 430 is not performed. This is to prevent an erroneous end of counting due to switching noise. In the A / D conversion of the signal potential VSIG (SIG) [k], the count is taken over from the end of the downcounting at the reset potential VSIG (RST) [k], and the count is performed. Therefore, when the A / D conversion of the signal potential VSIG (SIG) [k] is completed, the count number becomes the A / D conversion value of the reset potential VSIG (RST) [k] and the A / D conversion of the signal potential VSIG (SIG) [k]. It corresponds to the difference between the values. That is, VSIG (RST) [k] -VSIG (SIG) [k] corresponds to the final count number, and is output from the AD converter 430 as a digital output D_OUT.

  The operation of the analog circuit 481 is as follows.

  First unit H time: First, the switch RST_CMP2 is turned on, a single-slope AD conversion is performed in the AD conversion circuit 132, and after the AD conversion is completed, the switch RST_CMP2 is turned off. Next, the switch SIG_SMP2 is turned on, the single-slope AD conversion is performed in the AD conversion circuit 132, and after the completion of the AD conversion, the switch SIG_CMP2 is turned off. In the same manner as the operations of the analog circuit 431 and the AD conversion circuit 132 in the next unit H time, the AD conversion processing for the pixels 120 in the (k-1) th row read and held in the previous unit H time is completed. . Then, VSIG (RST) [k-1] -VSIG (SIG) [k-1] is output from AD converter 430 as digital output D_OUT.

  Next unit H time: The analog circuit 481 first turns on the switch RST_SMP2 in accordance with the period during which the reset potential VSIG (RST) [k + 1] of the pixel 120 in the (k + 1) th row is output as the output signal VSIG. Turn off. Next, the switch SIG_SMP2 is turned on and then turned off in conformity with the period in which the signal potential VSIG (SIG) [k + 1] of the pixel 120 in the k-th row is output as the output signal VSIG. In the same manner as the operation of the analog circuit 431 in the first unit H time, the reading of the pixels in the (k + 1) th row is completed.

(Effect of Embodiment 3)
Each of the analog circuits 431 and 481 has two capacitors (charge storage elements). The capacitors C_RST1 and C_RST2 read the reset potential SIG (RST) during the reading period and temporarily hold the potential until AD conversion. The capacitors C_SIG1 and C_SIG2 read out the signal potential SIG (SIG) during the readout period and hold the potential until AD conversion. The analog circuit 431 having two capacitors can temporarily store the reset potential SIG (RST) and the signal potential SIG (RST) for one pixel for AD conversion. The same applies to the analog circuit 481. Therefore, the AD converter 430 has a charge storage element for holding pixel output signals including the reset potential SIG (RST) and the signal potential SIG (RST) for two pixels. The two analog circuits 231 and 281 alternately perform readout processing and output processing to the AD conversion circuit, so that the readout processing of the pixel output signal and the AD conversion processing of the previously read out pixel output signal are one unit H. It is implemented in parallel in time.

  As described above, in the solid-state imaging device according to the third embodiment, with the circuit configuration specifically described above, the pixel reading process and the A / D conversion process are performed simultaneously in parallel, so that the processing capability is significantly improved. A solid-state imaging device including an AD converter can be realized.

  Further, from the AD converter 430, VSIG (RST) -VSIG (SIG) is obtained as a final output for each pixel 120, and the CDS operation is realized. A threshold variation (hereinafter, pixel variation) due to a threshold characteristic of a transistor or the like of each pixel 120 is canceled by calculating a difference between two pixel outputs of a reset potential VSIG (RST) and a signal potential VSIG (SIG). . Further, the variation in the characteristics of each column (hereinafter, column variation) such as the variation in the characteristics of each AD conversion circuit 132 is obtained by taking the difference between the two AD conversion results of the reset potential VSIG (RST) and the signal potential. Canceled. Therefore, according to the AD converter 430, a final output in which both the pixel variation and the column variation are canceled is obtained. In addition, since the operation is performed to prevent an erroneous end of counting due to switching noise, noise of the pixel due to this operation is also suppressed. In the solid-state imaging device according to the third embodiment, obtaining a high-quality captured image in which such variation (noise) is suppressed is simultaneously realized.

[Appendix]
The present invention is not limited to the embodiments described above, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 110 Vertical scanning circuit 111 Row selection signal line 112 Readout signal line 120 Pixel 230, 330, 430 AD converter 132, 332a, 332b AD conversion circuit 133, 333a, 333b Comparator 134, 334a, 334b Counter 140 Horizontal scanning Circuit 141 Column selection signal line 142 Memory 143 Horizontal output line 231, 281, 331a, 331b, 381a, 381b, 431, 481 Analog circuit 330a, 330b Unit AD converter CR1, CR2, CR1a, CR2a, CR1b, CR2b Capacitor (No. 1 charge storage element)
CS1, CS2, CS1a, CS2a, CS1b, CS2b Capacitor (second charge storage element)
C_RST1, C_SIG1, C_RST2, C_SIG2 Capacitor (charge storage element)

Claims (8)

A plurality of pixels,
An AD converter that receives a pixel output signal from the pixel and performs AD conversion,
The AD converter comprises:
An analog circuit having a charge storage element for temporarily holding the pixel output signal,
A solid-state imaging device, comprising: a single-slope type AD conversion circuit to which the pixel output signal temporarily held by the analog circuit is input. The AD converter comprises:
In one cycle of the cycle of sequentially receiving the pixel output signal from a plurality of pixels,
A process of storing the pixel output signal in the charge storage element,
2. The solid-state imaging device according to claim 1, wherein the analog circuit performs a single-slope AD conversion of the pixel output signal held before the cycle. 3. The pixel output signal includes a reset potential and a signal potential,
The solid-state imaging device according to claim 1, wherein the analog circuit includes the charge storage element for at least two pixels.   The solid-state imaging device according to claim 3, wherein the reset potential and the signal potential are input to the AD conversion circuit.   The AD conversion circuit receives (i) a reference potential and (ii) a combined potential that is a difference between the reset potential and the signal potential with reference to the reference potential. The solid-state imaging device according to claim 3. A plurality of pixels and an AD converter that receives a pixel output signal including a reset potential and a signal potential from the pixel and performs AD conversion,
The AD converter comprises:
An analog circuit that includes a charge storage element for temporarily holding the pixel output signal for at least two pixels, and that can output a combined potential that is a difference between the reset potential and the signal potential with reference to a reference potential; ,
A plurality of unit AD converters, including a single slope type AD conversion circuit capable of inputting the composite potential and the reference potential,
A solid-state imaging device, wherein a potential obtained by adding the composite potential of another unit AD converter to the composite potential of the unit AD converter can be input to the AD conversion circuit. The analog circuit includes:
A first charge storage element that holds a potential difference between the reference potential and the reset potential;
A second charge storage element that holds the signal potential,
The combined potential is generated by connecting the first charge storage element and the second charge storage element in series.
The solid-state imaging device according to claim 5.   The AD converter does not perform an ON operation and an OFF operation of a switch for performing a process of storing the pixel output signal in the charge storage device during the execution of the single slope type AD conversion, The solid-state imaging device according to claim 1.

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