JP2020096281A - Imaging device, data processing device, and data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce or prevent generation of the same data string as a control code in serially transmitted data.
An image pickup device includes an image sensor, an encoding unit that error-correction-encodes data representing an image signal read from the image sensor to generate first data, and converts the data into the first data or the first data. In the second data that has been subjected to the predetermined processing, the data portion having the same pattern as the synchronization code representing the synchronization signal is converted into a different pattern within a range that can be corrected by the error correction coding to generate the third data. A conversion unit, an addition unit that adds a synchronization code to the third data based on the timing of the synchronization signal, and a transmission unit that serially transmits the data to which the synchronization code has been added by the addition unit.
[Selection diagram]

Description

The present invention relates to a technique for serially transmitting data.

With the recent improvement in image quality and frame rate of image sensors, high-speed reading of pixel data from the image sensor is required. As a sensor that can cope with such high-speed reading of pixel data, a method is known in which digital data obtained by A/D converting analog data is serialized by parallel-serial conversion and transferred at high speed. In the transfer of such pixel data, a plurality of code strings called sync codes are embedded in the serial data and transferred in order to obtain the horizontal and vertical synchronization timing of the pixel data.

Further, in such high-speed pixel data transfer, a transfer method called a clock data recovery method is used in which a clock signal is embedded in the transfer data and the clock signal is extracted from the received transfer data. When data is transferred by AC coupling in the clock data recovery method, it is necessary to perform encoding so that the numbers of 0s and 1s in the transfer data are as uniform as possible in order to properly extract the clock. For example, Patent Document 1 discloses a method of applying scrambling to data and transferring a synchronization code and data as one means of encoding.

JP-A-63-226145

However, in the conventional technique disclosed in Patent Document 1, if the scrambled data contains the same data string as the sync code, the sync code is erroneously detected on the receiving side of the data string. Such a problem is not limited to serial transmission of image data, and may occur when transmitting data to which a control code representing some control signal is added.

An object of the present invention is to reduce or prevent the occurrence of the same data string as a control code in transmitted data.

A data processing device according to an aspect of the present invention has the following configuration. That is,
Coding means for performing error correction coding on the data to be processed to generate first data,
Using the first data and a control code representing a control signal, a generation means for generating data to be transmitted to which the control code is added,
A transmitting unit that transmits the data to be transmitted,
The generating means is
For the data to be added with the control code in the process of generating the data to be transmitted, detection means for detecting a data portion having the same pattern as the control code,
Conversion means for converting the data portion of the data to be added into a pattern different from the control code within a range that can be corrected by the error correction coding.

According to the present invention, the occurrence of the same data string as the control code in the transmitted data is reduced or prevented, so that the control code can be detected more reliably.

FIG. 3 is a block diagram showing a configuration example of an image pickup apparatus in the first embodiment. FIG. 3 is a block diagram showing a configuration example of a transmission data processing circuit in the first embodiment. FIG. 3 is a block diagram showing a configuration example of a reception data processing circuit according to the first embodiment. The figure which shows the relationship of each data in 1st Embodiment. The figure which shows the format of the transmission data in 1st Embodiment. The block diagram which shows the structural example of the imaging device in 2nd Embodiment. The block diagram which shows the structural example of the transmission data processing circuit in 2nd Embodiment. The block diagram which shows the structural example of the received data processing circuit in 2nd Embodiment. The figure which shows the relationship of each data in 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following, an example will be described in which the data to be serially transmitted is pixel data obtained from the image sensor and a synchronization signal (horizontal synchronization signal, vertical synchronization signal) is added as a control signal.

<First Embodiment>
FIG. 1 is a block diagram illustrating a configuration example of the image pickup apparatus according to the first embodiment. In FIG. 1, an oscillator 101 outputs a clock signal (hereinafter referred to as a reference clock) that serves as a reference for operation. Each unit described later operates based on the reference clock output from the oscillator 101. A synchronizing signal generator (SSG: Synchronizing Signal Generator) 110 generates and outputs a horizontal synchronizing signal HD and a vertical synchronizing signal VD in synchronization with a reference clock. The oscillator 101 and the SSG 110 may be included in either the sensor unit 120 or the image processing unit 130, or may be included in neither of them. The sensor unit 120 and the image processing unit 130 are formed on separate substrates, and data is serially transmitted between the sensor unit 120 and the image processing unit 130. However, the sensor unit 120 and the image processing unit 130 do not need to be present in the same communal body, and may be arranged in separate housings. Alternatively, the sensor unit 120 and the image processing unit 130 may be arranged on the same substrate.

The sensor unit 120 includes an image sensor (for example, a CCD image sensor or a CMOS image sensor) and generates an image signal. The timing signal generator (TG) 102 generates a drive pulse signal for driving each unit in the sensor unit 120 based on the horizontal synchronization signal (HD) and the vertical synchronization signal (VD) supplied from the SSG 110. The pixel unit 103 includes an image sensor, a transfer path that sequentially outputs pixel signals obtained by the image sensor according to a drive pulse signal (drive signal) supplied from the TG 102, an amplifier that amplifies the pixel signal, and a pixel signal. It has an A/D converter for converting into a digital signal (pixel data). The transmission data processing circuit 104 generates and outputs transmission data (parallel data) according to a predetermined protocol based on the pixel data from the pixel unit 103 and the timing signal from the TG 102. More specifically, the transmission data processing circuit 104 performs scrambling processing on pixel data, addition of a synchronization code corresponding to the horizontal synchronization signal HD, and the like.

A configuration example of the transmission data processing circuit 104 is shown in FIG. The counter 201 counts the reference clock output from the oscillator 101 and outputs a count value that defines a processing cycle of a state machine circuit (FSM: Finite State Machine) 202. The FSM 202 outputs an instruction signal for switching the output of the output selector 206 to data according to a predetermined protocol according to the count value from the counter 201 and the timing signal (synchronization signal HD/DV) from the TG 102. As described below, the output selector 206 scrambles the fixed pattern (501 in FIG. 5) output by the fixed pattern generation unit 203 and the synchronization code (502 in FIG. 5) output by the synchronization code generation unit 204. The image data added to the selected pixel data is output.

The fixed pattern generation unit 203 generates a fixed pattern in which a predetermined specific control code is repeatedly included. This specific control code is used for data processing in the image processing unit 130 described later. The FSM 202 controls the output selector 206 so that the data of this fixed pattern is output for a predetermined time at the head of the data synchronized with the vertical synchronization signal VD.

The sync code generator 204 generates a sync code corresponding to the horizontal sync signal HD. The synchronization code is data (symbol) having a predetermined word length and has a specific pattern. For example, if the sync code is composed of 4 symbols, data such as {sync code 1, sync code 2, sync code 3, sync code 4}={ALL0 symbol, ALL0 symbol, ALL1 symbol, ALL1 symbol} It is a line of. The receiving side (for example, the image processing unit 130) detects these data strings as a synchronization code by pattern matching and takes horizontal synchronization timing. The FSM 202 controls the output selector 206 so that the sync code is output immediately after the fixed pattern or at the beginning of the data synchronized with the horizontal sync signal HD.

The pixel data output from the pixel unit 103 is first supplied to the error correction coding unit 207. The error correction coding unit 207 performs error correction coding processing on the pixel data. As a coding method for error correction coding, for example, Reed-Solomon code is applied. When the Reed-Solomon code is used, the error correction coding unit 207 outputs pixel data with parity (hereinafter, first data) to which parity data is added for each fixed number of pixel data. The scramble circuit 205 scrambles the first data output from the error correction coding unit 207 to generate scramble data (hereinafter, second data). An example of the scrambling process is to take the exclusive OR of the pseudo random number generated by the linear feedback shift register and the first data. The scramble processing by the scramble circuit 205 is an example of a processing unit that performs the encoding processing for embedding the clock information in the first data to generate the second data, and is not limited to this. For example, instead of or in addition to the scramble process, the clock information may be embedded by a coding process such as 8b/10b that changes the number of bits per symbol of the first data. ..

The sync code detection circuit 209 detects, from the second data output from the scramble circuit 205, the same data string as the above-described specific pattern indicating the sync code by pattern matching. The sync code detection circuit 209 is an example of a configuration for detecting a data portion having the same pattern as the sync code representing the sync signal in the second data. When such a data string (data portion) is detected, the sync code detection circuit 209 outputs a first sync code detection signal. The data conversion unit 208 converts the data portion having the same data sequence as the specific pattern indicating the synchronization code into the data portion of the data sequence different from the specific pattern based on the first synchronization code detection signal. Data is generated (503 in FIG. 5). In the data conversion unit 208, the data portion detected by the synchronization code detection circuit 209 is converted into a pattern different from the synchronization code within a range in which the error correction encoding performed by the error correction encoding unit 207 can be corrected. 3 is an example of a configuration for generating third data.

FIG. 5 shows a configuration example of the output data of the transmission data processing circuit 104 described above. As shown in FIG. 5, the output data of the transmission data processing circuit 104 includes the fixed pattern 501 output by the fixed pattern generation unit 203, the synchronization code 502 output by the synchronization code generation unit 204, and the third data output by the data conversion unit 208. And data 503. As described above, the output selector 206, under the control of the FSM 202, adds the fixed pattern 501 in synchronization with the vertical synchronization signal VD, adds the synchronization code 502 in synchronization with the horizontal synchronization signal HD, and outputs the third pattern. The data 503 is output.

The data conversion unit 208 may change the data conversion method according to the error correction coding processing method used by the error correction coding unit 207. For example, when the Reed-Solomon code is the encoding method used by the error correction encoding unit 207 and one symbol is 8 bits, the correction can be performed in units of 8 bits (1 symbol). Therefore, the data conversion unit 208 can convert up to 8 bits of data corresponding to one symbol of the Reed-Solomon code among the matched data so that the data does not match the pattern of the synchronization code. Of course, if the Reed-Solomon code is provided with parity enough to correct a plurality of symbols, the data of a plurality of symbols may be converted so that they do not match the pattern of the synchronization code.

Returning to FIG. 1, the parallel-serial converter 106 of the sensor unit 120 converts the parallel data output from the transmission data processing circuit 104 into serial data. The converted serial data is supplied to the reception driver 111 of the image processing unit 130 via the transmission driver 107, the board and the cable. In this way, the parallel-serial converter 106 and the transmission driver 107 serially transmit the data output from the output selector 206 (the third data to which the synchronization code is added based on the timing of the synchronization signal). The PLL 105 supplies to the parallel-serial converter 106 a serial clock that matches the conversion rate from the reference clock to the serial data of the parallel-serial converter 106. Here, an example is shown in which the output data from the transmission data processing circuit 104 is output via one transmission driver, but the data may be distributed and transmitted to a plurality of drivers according to the data rate desired to be realized. Good.

In the image processing unit 130, the reception driver 111 receives the serial data serially transmitted from the transmission driver 107 and supplies the serial data to the serial/parallel converter 112. The serial-parallel converter 112 inputs the serial data from the reception driver 111, stores it in an internal shift register, and outputs the stored serial data as 8-bit parallel data, for example. Further, the serial-parallel converter 112 has a clock data recovery (CDR) function, and reproduces a clock from the serial data received by the reception driver 111. The serial-parallel converter 112 outputs the clock restored from the serial data by the CDR function to each unit that needs it.

The word align circuit 113 is a circuit for extracting data of a predetermined word length from the parallel data output from the serial/parallel converter 112. For example, assuming that the parallel data from the serial-parallel converter 112 is 8 bits and the pixel data has a word length of 12 bits per pixel, the 12-bit boundary of each pixel is searched for from the 8-bit input, and the 12-bit word is searched. To output and output. Such word synchronization (word align) operation is performed when the above-mentioned fixed pattern is received. The fixed pattern is a predetermined specific control code, and the word align circuit 113 establishes word synchronization by searching for the pattern of the specific control code by pattern matching.

The sync code detection circuit 115 receives the data signal from the word align circuit 113, detects the sync code, and outputs it as a second sync code detection signal. The reception data processing circuit 116 separates the third data corresponding to the pixel data and the synchronization code from the second synchronization code detection signal for the data signal from the word align circuit 113, and restores the pixel data. The restored pixel data is stored in the memory or subjected to predetermined image processing.

FIG. 3 shows a configuration example of the reception data processing circuit 116. The valid data acquisition unit 300 specifies the third data corresponding to the pixel data from the second sync code detection signal for the data signal from the word align circuit 113, and outputs the third data to the descramble circuit 301. To do. The synchronization code detection circuit 115 and the valid data acquisition unit 300 described above are configured to detect the synchronization code from the data obtained based on the serial data received by the reception driver 111 and separate the synchronization code and the third data. This is an example. The descramble circuit 301 performs descramble processing on the third data to generate descramble data (hereinafter, fourth data). As the descrambling process, for example, the exclusive OR of the pseudo random number generated by the linear feedback shift register and the third data can be used. The error correction decoding unit 302 performs error correction decoding processing on the fourth data output by the descramble circuit 301, and outputs the corrected data as output data of the reception data processing circuit 116. The descramble circuit 301 and the error correction decoding unit 302 perform the error correction decoding on the data obtained by performing the decoding process corresponding to the encoding process (descramble process) on the third data to thereby perform the first data correction. Is an example of a configuration for acquiring. The first data acquired by the reception data processing circuit 116 is stored as image data in a memory (not shown) or subjected to predetermined image processing.

FIG. 4 shows an example of the relationship among the pixel data, the first data, the second data, the third data, the fourth data, and the output data of the error correction decoding unit 302 described above. The pixel data 400 represents the pixel data output from the pixel unit 103. The first data is data in which the error correction coding unit 207 adds the parity 401 to the pixel data 400 output from the pixel unit 103. The second data is data in which the scramble circuit 205 has performed scramble processing on the first data having the configuration in which the parity 401 is added to the pixel data 400. The third data is data obtained by converting the data portion 402 having the same pattern as the synchronization code in the second data into the data portion 403 having a different pattern by the synchronization code detection circuit 209 and the data conversion unit 208.

For example, consider the case where the data string of the synchronization code is {ALL0 symbol, ALL0 symbol, ALL1 symbol, ALL1 symbol} as described above. In this case, the data portion 403 is obtained by converting the data portion 402 such as {ALL0 symbol, ALL0 symbol, ALL1 symbol, "ALL1 symbol XOR 1". Further, although one symbol is converted in this example, as described above, the data length to be converted may be changed depending on the coding method used in the error correction coding unit 207.

The fourth data is data that the descramble circuit 301 descrambles with respect to the third data. Since the data portion 403 has been converted by the data conversion unit 208, it is descrambled into data 404 different from the data included in the original pixel data 400. The error correction decoding unit 302 performs error correction decoding on the fourth data, whereby the data 404 is corrected and the original pixel data 400 is obtained.

As described above, according to the first embodiment, in the pixel data scrambled after the error correction coding, the data portion that matches the synchronization code is changed to another data string. Therefore, the same pattern as the sync code does not occur in the transmitted data, and the sync code that should be originally detected can be surely detected. Further, since the data portion is changed within the range of the correction capability in the error correction coding, it is possible to obtain correct data before the data portion is changed by performing error correction decoding on the receiving side. is there.

<Second Embodiment>
In the first embodiment, the synchronization code is detected for the entire third data. In the second embodiment, the data portion is extracted and converted with respect to the third data in the remaining period excluding the predetermined period from the generation of the synchronization signal. In the second embodiment, after the sync code (horizontal sync signal) is detected, the same data portion as the sync code is not detected and converted during a predetermined period in which the sync signal cannot be generated, and the sensor unit 120 is not used. The processing load on the image processing unit 130 is reduced. Hereinafter, the second embodiment will be described in detail.

FIG. 6 is a block diagram showing a configuration example of the image pickup apparatus according to the second embodiment. The components having the same functions as those of the image pickup device according to the first embodiment are designated by the same reference numerals as those shown in FIG.

In FIG. 6, the transmission data processing circuit 104a generates transmission data according to a predetermined protocol based on the pixel signal from the pixel unit 103 and the timing signal from the TG 102, and outputs it as parallel data. Specifically, a sync code corresponding to the horizontal sync signal HD is added to the pixel data. In the transmission data processing circuit 104 of the first embodiment, the sync code is detected and replaced over the entire pixel data. However, in the transmission data processing circuit 104a of the second embodiment, the synchronization code is detected within a predetermined period from the detection of the horizontal sync signal. Disables sync code detection.

A configuration example of the transmission data processing circuit 104a is shown in FIG. The components having the same functions as those in the first embodiment (FIG. 2) are designated by the same reference numerals as those shown in FIG.

The first counting unit 701 is reset when it detects the horizontal synchronization signal HD, and starts counting up the clock signal output from the SSG 110, for example. After that, the first counting unit 701 compares with a predetermined value, and outputs a detection signal to be asserted when the count value is larger to the error correction coding unit 207. Here, the detection signal is a signal indicating High when asserted, and is Low when the detection signal is deasserted, that is, when the count value is smaller than a predetermined value. The predetermined value is held in the setting register in the sensor unit 120 in advance. The predetermined value is set so that the detection signal is deasserted during the period when the horizontal synchronization signal HD is not generated, and the detection signal is asserted during the period when the horizontal synchronization signal HD is generated.

When the detection signal output from the first counting unit 701 is Low, the error correction encoding unit 207a does not perform error correction encoding and outputs the input pixel data as it is as the first data. On the other hand, the error correction coding unit 207a performs error correction coding when the detection signal output from the first counting unit 701 is High, performs error correction coding processing on the input pixel data, and then performs the error correction coding process. Output as one data. As a result, the error correction coding unit 207a executes the error correction coding on the data of the remaining period excluding the predetermined period determined by counting the reference clock from the generation of the horizontal synchronization signal. The error correction process itself is the same as in the first embodiment (error correction coding unit 207). Further, the error correction coding unit 207a outputs, to the synchronization code detection circuit 209a, an enable signal indicating High for the data that has been subjected to the error correction coding and Low for the data that has not been subjected to the error correction coding. ..

In the second embodiment, the enable signal is directly connected to the sync code detection circuit 209a, but the method is not limited to this. For example, the enable signal may be provided to the sync code detection circuit 209a via the scramble circuit 205. In addition, for example, a configuration may be adopted in which a separate counter unit is provided to instruct the operation timing of the synchronization code detection circuit 209a. In this case, the error correction coding unit 207a does not output the enable signal.

The sync code detection circuit 209a stops the operation of detecting the same pattern as the sync code in the second data when the enable signal output from the error correction coding unit 207a is Low. When the enable signal output from the error correction coding unit 207a is High, the operation of detecting the same pattern as the synchronization code in the second data is performed. The pattern detection process itself is the same as in the first embodiment (synchronization code detection circuit 209). As a result, the synchronization code detection circuit 209a and the data conversion unit 208 execute the extraction and conversion of the data portion in the data of the remaining period excluding the predetermined period determined by counting the reference clock from the generation of the horizontal synchronization signal. It will be.

Returning to FIG. 6, in the image processing unit 130, the second count unit 601 is the logical product of the second sync code detection signal output by the sync code detection circuit 115 and the signal output by the second count unit 601. The count value is reset with the third sync code detection signal. Then, the second counting unit 601 starts counting up the clock signal restored by the CDR function of the serial/parallel converter 112. Here, it is assumed that the initial value of the output signal of the second counting unit 601 is High. After that, the second counting unit 601 compares the count value with a predetermined value, and outputs High when the count value is larger than the predetermined value, and outputs Low when the count value is smaller than the predetermined value. The predetermined value is held in the setting register in the image processing unit 130. Further, the predetermined value used by the second counting unit 601 is associated with the predetermined value used by the first counting unit 701 of the transmission data processing circuit 104a. Specifically, the output of the second counting unit 601 is High at the timing when the word align circuit 113 outputs the third data corresponding to the first data that has been subjected to the error correction coding processing by the error correction coding unit 207a. The predetermined value is set so that

The reception data processing circuit 116a specifies the beginning of the third data from the third synchronization code detection signal for the data signal from the word align circuit 113, and restores the pixel data. The restored pixel data is stored in the memory or subjected to predetermined image processing. The third sync code detection signal indicates that the sync code detection circuit 115 has output the second sync code detection signal indicating that the sync code has been detected while the output signal of the second count unit 601 is High. ..

A configuration example of the reception data processing circuit 116a is shown in FIG. In FIG. 8, configurations having the same functions as those of the first embodiment are designated by the same reference numerals as the configurations shown in FIG. The third count unit 801 resets the count value according to the third synchronization code detection signal, and starts counting up the clock signal restored by the CDR function of the serial/parallel converter 112. After that, the third counting unit 801 compares the count value with the predetermined value, and outputs High when the count value is larger than the predetermined value, and outputs Low when the count value is smaller than the predetermined value. The predetermined value used by the third counting unit 801 is held in the setting register in the image processing unit 130. The predetermined value is associated with the predetermined value of the first counting section 701. Specifically, the count value becomes High at the timing when the descramble circuit 301 outputs the fourth data corresponding to the first data that has been subjected to the error correction coding processing by the error correction coding unit 207a. A predetermined value is set.

The valid data acquisition unit 300 specifies and separates the third data from the third sync code detection signal for the data signal from the word align circuit 113, and outputs the third data to the descramble circuit 301. Since the third synchronization code detection signal is used, the valid data acquisition unit 300 detects the synchronization code from the data corresponding to the data in the remaining period of the received serial data excluding the predetermined period from the synchronization signal. Will be done. Further, based on the count value of the clock restored by the CDR function of the serial/parallel converter 112 from the serially transmitted data, it is determined whether or not the predetermined period has elapsed from the sync signal detected based on the sync code. When the signal output from the third counting unit 801 is Low, the error correction decoding unit 302a does not perform error correction decoding and outputs the input fourth data as it is. When the signal output from the third counting unit 801 is High, the error correction decoding unit 302a performs error correction decoding, performs error correction decoding processing on the input fourth data, and then outputs the processed fourth data. ..

FIG. 9 shows the relationship among the pixel data, the first data, the second data, the third data, the fourth data, and the output data of the error correction decoding unit 302a described above. The data structure with the same reference numerals as in FIG. 4 is the same as that in the first embodiment.

A period 910 is a period in which the error correction coding unit 207a does not perform error correction coding, that is, a period in which the first counting unit 701 outputs Low. A period 911 is a period in which the error correction coding unit 207a performs error correction coding, that is, a period in which the first counting unit 701 outputs High. Parity 401 for error correction is added to the pixel data in the period 911.

A period 912 is a period in which the sync code detection circuit 209a stops the operation of detecting the same pattern as the sync code, that is, a period in which the enable signal output from the error correction coding unit 207a is Low. The period 913 is a period in which the sync code detection circuit 209a performs an operation of detecting the same pattern as the sync code, that is, a period in which the enable signal output from the error correction coding unit 207a is High. Extraction of data having the same pattern as the synchronization code is executed for the second data of the period 913. The example of FIG. 9 shows that the data portion 402 having the same pattern as the synchronization code is detected and replaced with the data portion 403 having a different pattern to form the third data.

A period 914 is a period in which the error correction decoding unit 302a does not perform error correction decoding, that is, a period in which the third counting unit 801 outputs Low. A period 915 is a period in which the error correction decoding unit 302a performs error correction decoding, that is, a period in which the third counting unit 801 outputs High. In the period 915, error correction decoding is executed, the data 403 in which the data portion 403 is descrambled is corrected, and the original pixel data 400 is obtained as output data.

As described above, according to the second embodiment, the processing load of the sensor unit 120 and the image processing unit 130 is reduced and the original detection is performed by limiting the period for performing the error correction coding and the scrambling process and the period for detecting the synchronization code. It is possible to reliably detect the synchronization code to be used. In the above embodiment, the error correction coding/decoding is not executed for a predetermined period from the generation of the horizontal sync signal, but the error correction coding/decoding is performed for the entire pixel data as in the first embodiment. May be performed.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes can be made within the scope of the gist thereof. That is, in the above-described embodiment, the example of the image pickup apparatus that generates serial data from the image signal and the synchronizing signal (vertical synchronizing signal, horizontal synchronizing signal) and serially transmits/receives is not limited to this. For example, the data to be transmitted is not limited to image data, and the transmission form is not limited to serial transmission. That is, it is obvious that the present invention can be applied to the configuration of the data processing device that transmits/receives the data to which the control code representing some control signal is added. Further, in such a data processing device, the scramble processing by the scramble circuit 205 and the descramble circuit 301 is not essential and may be omitted.

Therefore, according to the above, the data processing device generates the first data by performing error correction coding on the data to be processed, and adds the control code using the first data and the control code representing the control signal. The generated transmission target data is generated and transmitted. Here, the data processing device detects a data portion having the same pattern as the control code in the data to be added with the control code in the process of generating the data to be transmitted. When such a data portion is detected from the data to be added, the data processing device converts the data portion into a pattern different from the control code within a range that can be corrected by error correction coding, and Generate data. In addition, on the receiving side of the data transmitted in this way, the data obtained by separating the control code from the received transmission target data is subjected to processing including error correction decoding processing, and the original processing target data is processed. get.

(Other embodiments)
The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program. It can also be realized by the processing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

101: oscillator, 102: timing signal generator (TG), 103: pixel portion, 104: transmission data processing circuit, 105: PLL, 106: parallel-serial converter, 107: transmission driver, 110: synchronization signal generator (SSG) ), 111: reception driver, 112: serial-parallel converter, 113: word align circuit, 115: synchronization code detection circuit, 116: reception data processing circuit, 120: sensor unit, 130: image processing unit

Claims (26)

Coding means for performing error correction coding on the data to be processed to generate first data,
Using the first data and a control code representing a control signal, a generation means for generating data to be transmitted to which the control code is added,
A transmitting unit that transmits the data to be transmitted,
The generating means is
For the data to be added with the control code in the process of generating the data to be transmitted, detection means for detecting a data portion having the same pattern as the control code,
A data processing device, comprising: a conversion unit that converts the data portion of the data to be added into a pattern different from the control code within a range that can be corrected by the error correction coding. Receiving means for receiving the data transmitted by the transmitting means,
Separating means for separating the control code from the data received by the receiving means,
The data processing apparatus according to claim 1, further comprising: a processing unit that acquires the data to be processed from the data obtained by separating the control code by a process including error correction decoding. .. Coding means for generating first data by performing error correction coding on data representing an image signal read from the image sensor,
Processing means for performing encoding processing for embedding clock information in the first data to generate second data;
In the second data, detection means for detecting a data portion having the same pattern as a sync code representing a sync signal,
Conversion means for converting the data portion into a pattern different from the synchronization code and generating third data within a range that can be corrected by the error correction coding;
An image pickup apparatus comprising: a transmission unit that adds the synchronization code to the third data based on the timing of the synchronization signal and serially transmits the synchronization code. The image pickup apparatus according to claim 3, wherein the sync code represents a vertical sync signal and a horizontal sync signal for reading an image signal. The image pickup apparatus according to claim 3, wherein the processing unit includes scrambling the first data. The imaging device according to claim 3, wherein the processing unit includes changing the number of bits per symbol of the first data. Receiving means for receiving the data transmitted by the transmitting means,
Separation means for detecting the synchronization code from the data received by the reception means, and separating the synchronization code and the third data,
The third data is further subjected to a decoding process corresponding to the encoding process, and the data obtained by performing error correction decoding to obtain data representing the image signal is further included. The image pickup apparatus according to claim 3. The conversion means performs extraction and conversion of the data portion in the data of the remaining period excluding a predetermined period from the generation of the synchronization signal,
The image pickup apparatus according to claim 7, wherein the separation unit detects the synchronization code from data corresponding to the data in the remaining period of the data received by the reception unit. 9. The image pickup apparatus according to claim 8, wherein the separating unit detects and separates the sync code for data in a period except the predetermined period from the sync signal detected based on the sync code. The encoding means performs the error correction encoding on the data in the remaining period from the generation of the synchronization signal,
10. The image pickup apparatus according to claim 8, wherein the decoding unit performs the error correction decoding on the data corresponding to the data in the remaining period of the third data. The decoding means executes the error correction decoding on data of a period of the third data that is obtained by removing the predetermined period from a synchronization signal detected based on the synchronization code. Item 10. The imaging device according to item 10. 12. The predetermined period from the synchronization signal detected based on the synchronization code is determined based on a count value of a clock reproduced from the data serially transmitted by the transmission unit. The imaging device according to. An oscillator that generates a reference clock,
Generating means for generating a horizontal synchronizing signal and a vertical synchronizing signal in synchronization with the reference clock,
In synchronization with the horizontal synchronization signal and the vertical synchronization signal, the image signal is read from the image sensor,
13. The image pickup apparatus according to claim 3, wherein the transmission unit adds the synchronization code to the third data in synchronization with the horizontal synchronization signal. An encoding step of performing error correction encoding on the data to be processed to generate first data,
Using the first data and a control code representing a control signal, a generation step of generating transmission target data to which the control code is added,
A transmitting step of transmitting the data to be transmitted,
The generation step is
In the process of generating data to be transmitted, for the data to be added with the control code, a detection step of detecting a data portion having the same pattern as the control code,
And a conversion step of converting the data portion of the data to be added into a pattern different from the control code within a range that can be corrected by the error correction encoding. A receiving step of receiving the data transmitted by the transmitting step,
A separating step of separating the control code from the data received by the receiving step;
The data processing method according to claim 14, further comprising a processing step of acquiring the processing target data from the data obtained by separating the control code by a process including error correction decoding. .. A method of processing data in an image pickup device equipped with an image sensor, comprising:
An encoding step of generating error correction encoding data representing an image signal read from the image sensor to generate first data,
A processing step of performing encoding processing for embedding clock information in the first data to generate second data;
In the second data, a detection step of detecting a data portion having the same pattern as a sync code representing a sync signal,
A conversion step of converting the data portion into a pattern different from the synchronization code and generating third data within a range that can be corrected by the error correction encoding;
A step of adding the synchronization code to the third data on the basis of the timing of the synchronization signal and performing serial transmission, the data processing method. 17. The data processing method according to claim 16, wherein the synchronization code represents a vertical synchronization signal and a horizontal synchronization signal for reading an image signal. 18. The data processing method according to claim 16 or 17, wherein the processing step includes scrambling the first data. 19. The data processing method according to claim 16, wherein the processing step includes changing the number of bits per symbol of the first data. A receiving step of receiving the data transmitted by the transmitting step,
A separation step of detecting the synchronization code from the data received by the reception step, and separating the synchronization code and the third data;
And a decoding step of performing error correction decoding on the data obtained by subjecting the third data to a decoding process corresponding to the encoding process to obtain data representing the image signal. The data processing method according to any one of claims 16 to 19. The conversion step performs extraction and conversion of the data portion in the data of the remaining period excluding a predetermined period from the generation of the synchronization signal,
21. The data processing method according to claim 20, wherein the separating step detects the synchronization code from data corresponding to the data in the remaining period among the data received in the receiving step. 22. The data processing method according to claim 21, wherein in the separating step, the synchronization code is detected and separated from data in a period excluding the predetermined period from a synchronization signal detected based on the synchronization code. .. The encoding step performs the error correction encoding on the data in the remaining period from the generation of the synchronization signal,
23. The data processing method according to claim 21, wherein in the decoding step, the error correction decoding is performed on data corresponding to data in the remaining period of the third data. In the decoding step, the error correction decoding is performed on the data of the third data in a period excluding the predetermined period from the synchronization signal detected based on the synchronization code. Item 23. The data processing method according to Item 23. 25. The predetermined period from the sync signal detected based on the sync code is determined based on a count value of a clock reproduced from the data serially transmitted in the transmitting step. The data processing method described in. An image signal is read from the image sensor in synchronization with a horizontal synchronization signal and a vertical synchronization signal generated in synchronization with a reference clock,
The data processing method according to any one of claims 16 to 25, wherein the transmitting step adds the synchronization code to the third data in synchronization with the horizontal synchronization signal.

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