JP2020092285A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a new structure having good characteristics. SOLUTION: The oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and a gate on the gate insulating layer. A semiconductor device having an electrode and a source electrode and a drain electrode having an oxidation region whose side surface is oxidized. It is desirable that the oxidation regions of the source electrode and the drain electrode are formed by high-frequency power of 300 MHz or more and 300 GHz or less and plasma treatment using a mixed gas of oxygen and argon. [Selection diagram] Fig. 1

Description

The technical field of the invention relates to a semiconductor device and a manufacturing method thereof. Here, the semiconductor device refers to all elements and devices that function by utilizing semiconductor characteristics.

There are various kinds of metal oxides and they are used for various purposes. Indium oxide is a well-known material, and is used as a material for transparent electrodes required for liquid crystal display devices and the like.

Some metal oxides have semiconductor characteristics. Examples of the metal oxide exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, and zinc oxide, and thin film transistors using such a metal oxide in a channel formation region are already known (for example, See Patent Documents 1 to 4, Non-Patent Document 1 and the like).

Incidentally, as the metal oxide, a multi-component oxide is also known. For example, InGaO ₃ (ZnO) _m (m: natural number) having a homologous phase is known as a multi-component oxide semiconductor containing In, Ga, and Zn (see, for example, Non-Patent Documents 2 to 4). ).

It has been confirmed that an oxide semiconductor composed of the above In-Ga-Zn-based oxide is also applicable to the channel formation region of a thin film transistor (for example, Patent Document 5 and Non-Patent Document 5). And Non-Patent Document 6).

JP-A-60-198861 JP-A-8-264794 Japanese Patent Publication No. 11-505377 JP 2000-150900 A JP 2004-103957 A

M. W. Princes, K.; O. Grosse-Holz, G.I. Muller, J.; F. M. Collessen, J.; B. Giesbers, R.A. P. Weening, and R.M. M. Wolf, "A Ferroelectric Transparent Thin-Film Transistor," Appl. Phys. Lett. , 17 June 1996, Vol. 68 p. 3650-3652 M. Nakamura, N.; Kimizuka, and T.M. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350[deg.] C.", J. Am. Solid State Chem. , 1991, Vol. 93, p. 298-315 N. Kimizuka, M.; Isobe, and M.M. Nakamura, "Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(Zn7)8(Zn7)8". and 16) in the In2O3-ZnGa2O4-ZnO System", J. Am. Solid State Chem. , 1995, Vol. 116, p. 170-178 Masaki Nakamura, Noboru Kimizuka, Naohiko Mori, Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phase, InFeO3(ZnO)m (m: Natural Number) and Its Isomorphic Compounds", Solid State Physics, 1993, Vol. 28, No. 5, p. 317-327 K. Nomura, H.; Ohta, K.; Ueda, T.; Kamiya, M.; Hirano, and H.M. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor," SCIENCE, 2003, Vol. 300, p. 1269-1272 K. Nomura, H.; Ohta, A.; Takagi, T.; Kamiya, M.; Hirano, and H.M. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol. 432 p. 488-492

By the way, it is hard to say that the current transistor using an oxide semiconductor has characteristics sufficient for practical use, and it is required to have more excellent transistor characteristics such as S value, on-off ratio, and reliability. Has been.

Therefore, it is an object of one embodiment of the disclosed invention to provide a semiconductor device having a new structure and favorable characteristics.

Another object is to provide a method for manufacturing a semiconductor device having a new structure.

A transistor including an oxide semiconductor, which is one embodiment of the present invention, has excellent characteristics in S value, on-off ratio, reliability, and the like because a side surface of a source electrode or a drain electrode is oxidized. Specifically, for example, the following configuration can be adopted.

One embodiment of the present invention is an oxide semiconductor layer, a source electrode and a drain electrode which are electrically connected to the oxide semiconductor layer, a gate insulating layer which covers the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate insulating layer. The upper gate electrode and the source electrode and the drain electrode are semiconductor devices having oxidized regions whose side surfaces are oxidized. Note that the above-described oxidized region is formed when oxygen is supplied to the oxide semiconductor layer.

In the above, the oxidized regions of the source electrode and the drain electrode are 300 MHz or more and 300 G or more.
It is preferably formed by plasma treatment using high-frequency power of Hz or less and a mixed gas of oxygen and argon. Further, it is desirable to have a protective insulating layer on the source electrode and the drain electrode that is substantially the same in plan view as the source electrode and the drain electrode.
The expression "substantially the same" is used to mean that it is not strictly the same,
Includes ranges that can be considered identical. For example, the difference when formed by one etching process is allowed.

Further, in the above, the hydrogen concentration of the oxide semiconductor layer is preferably 5×10 ¹⁹ /cm ³ or less. Further, the off current is preferably 1×10 ⁻¹³ A or less.

According to one embodiment of the present invention, an oxide semiconductor layer is formed over a substrate, a source electrode and a drain electrode which are electrically connected to the oxide semiconductor layer are formed, side surfaces of the source electrode and the drain electrode are oxidized, and then oxidation is performed. A method for manufacturing a semiconductor device, comprising forming a gate insulating layer covering a semiconductor layer, a source electrode, and a drain electrode, and forming a gate electrode on the gate insulating layer. Note that oxygen is supplied to the oxide semiconductor layer when the side surfaces of the source electrode and the drain electrode are oxidized.

In the above, the oxidation of the side surfaces of the source electrode and the drain electrode is 300 MHz or more and 300 MHz or more.
It is desirable to perform it by high frequency power of GHz or less and plasma treatment using a mixed gas of oxygen and argon.

Further, in the above, it is desirable to form a protective insulating layer having a planar shape that is substantially the same as that of the source and drain electrodes on the source and drain electrodes.

Further, in the above, it is preferable that the off-state current be 1×10 ⁻¹³ A or less by setting the hydrogen concentration of the oxide semiconductor layer to 5×10 ¹⁹ /cm ³ or less.

Note that the term such as “over” or “below” in this specification and the like does not necessarily mean that a component is placed “directly on” or “directly under” another component. For example, the expression “first gate electrode over the gate insulating layer” does not exclude one including another component between the gate insulating layer and the gate electrode. Further, the terms “upper” and “lower” are merely expressions used for convenience of description, and include upper and lower parts thereof interchanged, unless otherwise specified.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, "electrode" may be used as part of "wiring",
The reverse is also true. Furthermore, the terms "electrode" and "wiring" also include the case where a plurality of "electrodes" and "wirings" are integrally formed.

Further, the functions of the “source” and the “drain” may be switched when a transistor having a different polarity is used or when the direction of current flow is changed in circuit operation. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably.

Note that in this specification and the like, the term “electrically connected” includes the case of being connected through “something having an electrical action”. Here, the “object having some kind of electrical action” is not particularly limited as long as it can transfer an electric signal between the connection targets.

For example, “things having some kind of electrical action” include electrodes and wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

In one embodiment of the disclosed invention, oxygen is supplied to the oxide semiconductor layer, whereby characteristics of a transistor including an oxide semiconductor are further improved. Here, the oxygen supply treatment appears in such a manner that the side surface of the source electrode or the drain electrode is oxidized in the transistor including an oxide semiconductor.

In addition, it is possible to prevent a short circuit between the gate electrode and the source or drain electrode that may be caused by thinning of the gate insulating layer or poor coverage due to oxidation of the side surface of the source or drain electrode. Is.

By supplying oxygen to the oxide semiconductor layer in this manner, a semiconductor device having a new structure with excellent characteristics can be realized.

It is sectional drawing for demonstrating a semiconductor device. 6A to 6C are cross-sectional views illustrating a manufacturing process of a semiconductor device. 6A to 6C are cross-sectional views illustrating a manufacturing process of a semiconductor device. FIG. 11 is a cross-sectional view of a transistor including an oxide semiconductor. FIG. 5 is an energy band diagram (schematic diagram) in the A-A′ cross section of FIG. 4. (A) is a diagram showing a state where a positive voltage (V _G >0) is applied to the gate (GE1), and (B) is a diagram showing a state where a negative voltage (V _G <0) is applied to the gate (GE1). is there. It is a figure which shows the vacuum level, the work function ((phi) _M ) of a metal, and the relationship of the electron affinity ((chi)) of an oxide semiconductor. It is a figure which shows the energy required for hot carrier injection in silicon (Si). FIG. 4 is a diagram showing energy required for hot carrier injection in an In—Ga—Zn—O-based oxide semiconductor (IGZO). It is a figure which shows the energy required for hot carrier injection in silicon carbide (4H-SiC). It is a figure which shows the result of the device simulation regarding a short channel effect. It is a figure which shows the result of the device simulation regarding a short channel effect. It is a figure which shows CV characteristic. It is a figure which shows the relationship between Vg and (1/C) ² . FIG. 16 is a diagram for explaining an electronic device using a semiconductor device. It is a figure which shows the relationship between the thickness of the oxidation area|region formed by plasma processing, and processing time.

An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously modified without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Further, the position, size, range, and the like of each configuration illustrated in the drawings and the like may not represent the actual position, size, range, or the like for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

Note that the ordinal numbers such as “first”, “second”, and “third” in this specification and the like are given to avoid confusion among components and are not limited numerically. To do.

(Embodiment 1)
In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS.

<Structure of semiconductor device>
FIG. 1 is a cross-sectional view showing a transistor 150 which is an example of a structure of a semiconductor device. In addition,
Although the transistor 150 is described as an n-type transistor, a p-type transistor may be used.

The transistor 150 includes an oxide semiconductor layer 104a provided over the substrate 100 with the insulating layer 102 interposed therebetween, a source or drain electrode 106a and a source or drain electrode 106b which are electrically connected to the oxide semiconductor layer 104a, Source or drain electrode 1
06a, a gate insulating layer 112 which covers the source or drain electrode 106b, and a gate electrode 114 over the gate insulating layer 112 (see FIG. 1).

In addition, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided over the transistor 150.

Here, the source or drain electrode 106a, the source or drain electrode 106
Each of b has an oxidized region 110 whose side surface is oxidized. By including the oxidized region 110, it is possible to prevent a short circuit between the gate electrode and the source or drain electrode, which may occur due to thinning of the gate insulating layer, poor coverage, or the like.

Further, it is preferable that the oxide semiconductor layer 104a be highly purified by sufficiently removing impurities such as hydrogen and supplying oxygen. Specifically, the oxide semiconductor layer 1
The hydrogen concentration of 04a is 5×10 ¹⁹ /cm ³ or less, preferably 5×10 ¹⁸ /cm ³ or less,
More preferably, it is 5×10 ¹⁷ /cm ³ or less. Note that in the oxide semiconductor layer 104a which is highly purified by supplying oxygen with sufficiently reduced hydrogen concentration, a general silicon wafer (a silicon wafer to which a trace amount of an impurity element such as phosphorus or boron is added) is used. Value of the carrier concentration (for example, less than 1×10 ¹² /cm ³ , preferably 1×10 ¹¹ /cm ³ or less) compared to the carrier concentration in (1) (about 1×10 ¹⁴ /cm ³ ). Take As described above, by using an i-type or substantially i-type oxide semiconductor, the transistor 150 with extremely excellent off-state current characteristics can be obtained. For example, drain voltage V
When d is +1V or +10V and the gate voltage Vg is in the range of -5V to -20V, the off-current is 1 x 10 ^-13 A or less. Note that the above hydrogen concentration in the oxide semiconductor layer 104a is determined by secondary ion mass spectrometry (SIMS: Secondary Ion Mas).
s Spectroscopy).

Note that the oxide semiconductor included in the oxide semiconductor layer is not particularly limited as long as it has a non-single-crystal structure. For example, an amorphous structure, a microcrystal (microcrystal, nanocrystal, etc.) structure, a polycrystal structure, a structure containing microcrystals or polycrystals in an amorphous structure, a microcrystal or polycrystal on the surface of an amorphous structure Various structures can be applied, such as a structure in which is formed.

<Method for manufacturing semiconductor device>
Next, a method for manufacturing the transistor 150 will be described with reference to FIGS.

First, the insulating layer 102 is formed over the substrate 100. Then, the oxide semiconductor layer 104 is formed over the insulating layer 102 (see FIG. 2A).

The substrate 100 may be a substrate having an insulating surface, and may be, for example, a glass substrate. The glass substrate is preferably a non-alkali glass substrate. A glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used for the non-alkali glass substrate. In addition, as the substrate 100, a ceramic substrate,
Quartz substrate, sapphire substrate or other insulating substrate, silicon or other semiconductor material surface coated with insulating material, metal or stainless steel or other conductive substrate surface insulating What was covered with the material can be used. Alternatively, a plastic substrate can be used as long as it can withstand heat treatment in a manufacturing process.

The insulating layer 102 functions as a base and can be formed by a CVD method, a sputtering method, or the like. Further, the insulating layer 102 is preferably formed so as to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the insulating layer 102 may have a single-layer structure or a stacked structure. The thickness of the insulating layer 102 is not particularly limited, but may be 10 nm or more and 500 nm or less, for example. Here, since the insulating layer 102 is not an essential component, the insulating layer 10
It is also possible to adopt a configuration in which 2 is not provided.

Note that when the insulating layer 102 contains hydrogen, water, or the like, entry of hydrogen into the oxide semiconductor layer, extraction of oxygen from the oxide semiconductor layer due to hydrogen, or the like might occur, which might deteriorate the characteristics of the transistor. .. Therefore, it is preferable that the insulating layer 102 be formed so as to contain hydrogen and water as little as possible.

For example, in the case of using a sputtering method or the like, it is desirable that the insulating layer 102 be formed in a state where moisture remaining in the treatment chamber is removed. Further, in order to remove the residual water in the processing chamber, it is desirable to use an adsorption type vacuum pump such as a cryopump, an ion pump, a titanium sublimation pump. A turbo pump provided with a cold trap may be used. Since hydrogen, water, and the like are sufficiently removed from the treatment chamber evacuated using a cryopump or the like, the concentration of impurities contained in the insulating layer 102 can be reduced.

Further, when forming the insulating layer 102, it is desirable to use a high-purity gas in which impurities such as hydrogen and water are reduced to a concentration of about ppm (desirably, a concentration of about ppb).

As the oxide semiconductor layer 104, In—Sn—Ga—Zn—O which is a quaternary metal oxide, In—Ga—Zn—O which is a ternary metal oxide, and In—Sn—Zn—O. , In-Al-
Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, and binary metal oxides In-Zn-O, Sn-Zn-O, Al. -Zn-O, Zn-Mg-
An oxide semiconductor layer including O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, Zn-O, or the like can be used. Further, SiO ₂ may be included in the above oxide semiconductor layer.

As the oxide semiconductor layer 104, a thin film containing a material represented by InMO ₃ (ZnO) _m (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn and Co. For example, M is Ga, Ga and Al, G
a and Mn, Ga and Co, etc. can be applied. Note that InMO ₃ (ZnO
) Among materials represented by _m (m>0), a material containing Ga as M is In-Ga-Zn.
-O oxide semiconductor, and its thin film is an In-Ga-Zn-O oxide semiconductor film (In-Ga).
-Zn-O amorphous film).

In this embodiment, an amorphous oxide semiconductor layer is formed by a sputtering method using an In—Ga—Zn—O-based oxide semiconductor film formation target as the oxide semiconductor layer 104. .. Note that crystallization can be suppressed by adding silicon to the amorphous oxide semiconductor layer; therefore, for example, a target containing 2 wt% to 10 wt% of SiO ₂ is used as an oxide. The semiconductor layer 104 may be formed.

As a target for forming the oxide semiconductor layer 104 by a sputtering method, for example, a metal oxide target containing zinc oxide as its main component can be used. Also, In,
A target for forming an oxide semiconductor containing Ga and Zn (as a composition ratio, In ₂ O ₃ :G
a ₂ O ₃ :ZnO=1:1:1 [mol ratio] or In:Ga:Zn=1:1:1.
5 [atom ratio]) or the like can also be used. In addition, as a target for forming an oxide semiconductor containing In, Ga, and Zn, In:Ga:Zn=1:1:1 [atom ratio] or In:Ga:Zn=1:1:2 [atom ratio]. ] A target having a composition ratio of] or the like may be used. The filling rate of the oxide semiconductor film formation target is 90% or more and 100% or less, preferably 95% or more (for example, 99.9%). The dense oxide semiconductor layer 104 is formed by using the oxide semiconductor target with high filling rate.

The atmosphere for forming the oxide semiconductor layer 104 is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides have a concentration of about ppm (
It is preferable to use a high-purity gas atmosphere removed to a concentration of about ppb).

When forming the oxide semiconductor layer 104, the substrate is held in a treatment chamber kept under reduced pressure,
The substrate temperature is heated to 100° C. or higher and 600° C. or lower, preferably 200° C. or higher and 400° C. or lower. Then, while removing residual water in the treatment chamber, a sputtering gas from which hydrogen and water are removed is introduced, and the oxide semiconductor layer 104 is formed with the metal oxide as a target. By forming the oxide semiconductor layer 104 while heating the substrate, the concentration of impurities contained in the oxide semiconductor layer 104 can be reduced. Also, damage due to sputtering is reduced. In order to remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, or the like can be used.
Alternatively, a turbo pump provided with a cold trap may be used. Hydrogen, water, and the like are removed from the treatment chamber which is evacuated using a cryopump, so that the concentration of impurities in the oxide semiconductor layer 104 can be reduced.

As a film formation condition of the oxide semiconductor layer 104, for example, the distance between the substrate and the target is 100.
mm, the pressure is 0.6 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is an oxygen (oxygen flow rate ratio 100%) atmosphere. Note that a pulse direct current (DC) power source can reduce powder substances (also referred to as particles or dust) generated in film formation,
The film thickness distribution is also uniform, which is preferable. The thickness of the oxide semiconductor layer 104 is 2 nm or more and 200
nm or less, preferably 5 nm or more and 30 nm or less. However, since an appropriate thickness varies depending on the applied oxide semiconductor material and application, the thickness may be selected according to the material and application used.

Note that before the oxide semiconductor layer 104 is formed by a sputtering method, it is preferable to perform reverse sputtering in which an argon gas is introduced and plasma is generated to remove the deposits on the surface of the insulating layer 102. Here, reverse sputtering refers to a method in which ions are made to collide with a sputter target in normal sputtering, and conversely, the surface is modified by making ions collide with the treated surface. As a method of causing ions to collide with the treated surface, there is a method of applying a high frequency voltage to the treated surface side in an argon atmosphere to generate plasma near the substrate. Note that an atmosphere of nitrogen, helium, oxygen, or the like may be applied instead of the argon atmosphere.

Next, the oxide semiconductor layer 104 is processed by a method such as etching using a mask,
The island-shaped oxide semiconductor layer 104a is formed (see FIG. 2B).

As the etching of the oxide semiconductor layer 104, either dry etching or wet etching may be used. Of course, both can be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, and the like) are set as appropriate depending on the material so that the oxide semiconductor layer 104 can be etched into a desired shape.

As the dry etching, a parallel plate type RIE (Reactive Ion Etchi) is used.
ng) method, ICP (Inductively Coupled Plasma) etching method, or the like. Also in this case, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) need to be set appropriately.

An etching gas that can be used for dry etching is, for example, a gas containing chlorine (
Chlorine gas such as chlorine (Cl ₂ ), boron chloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ).
, Carbon tetrachloride (CCl ₄ ), and the like. Further, a gas containing fluorine (a fluorine-based gas, for example, carbon tetrafluoride (CF ₄ ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ), etc.), hydrogen bromide ( HBr), oxygen (O ₂ ), helium (H
Alternatively, a gas to which a rare gas such as e) or argon (Ar) is added may be used.

As an etching solution that can be used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, an ammonia-hydrogen peroxide water mixed solution (31% by weight hydrogen peroxide water: 28% by weight ammonia water:water=5:2). : 2) etc. Further, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

After that, first heat treatment is preferably performed on the oxide semiconductor layer 104a. By this first heat treatment, water (including a hydroxyl group), hydrogen, or the like in the oxide semiconductor layer 104a can be removed. The temperature of the first heat treatment is 300 °C or higher and 750 °C or lower, preferably 400
C. or higher and 700.degree. C. or lower. For example, the substrate 100 is introduced into an electric furnace using a resistance heating element or the like, and heat treatment is performed on the oxide semiconductor layer 104a in a nitrogen atmosphere at 450° C. for 1 hour. During this time, the oxide semiconductor layer 104a is not exposed to the air and water or hydrogen is not mixed therein.

The heat treatment apparatus is not limited to an electric furnace, and may be an apparatus that heats an object to be processed by heat conduction or heat radiation from a medium such as a heated gas. For example, GRTA (Gas Rap
id Thermal Anneal device, LRTA (Lamp Rapid The)
RTA (Rapid Thermal Anneal) such as an rmal anneal device
) Devices can be used. The LRTA device is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp.
The GRTA apparatus is an apparatus that performs heat treatment using a high temperature gas. As the gas, a rare gas such as argon or an inert gas such as nitrogen which does not react with the object to be processed by the heat treatment is used.

For example, as the first heat treatment, a GRT in which a substrate is placed in an inert gas atmosphere heated to a high temperature of 650° C. or higher and 700° C. or lower, heated for several minutes, and then the substrate is taken out of the inert gas atmosphere
You may perform A process. The GRTA process enables high-temperature heat treatment in a short time. Further, since the heat treatment is performed for a short time, it can be applied even under a temperature condition exceeding the heat resistant temperature of the substrate. For example, when a glass substrate is used, the shrinking of the substrate becomes a problem at a temperature exceeding the heat resistant temperature (strain point), but this does not become a problem in the case of heat treatment for a short time. Note that the inert gas may be switched to a gas containing oxygen during the treatment. This is because defects caused by oxygen vacancies can be reduced by performing the first heat treatment in an atmosphere containing oxygen.

As the inert gas atmosphere, it is preferable to use an atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as a main component and containing no water or hydrogen. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (
That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

Depending on the condition of the first heat treatment or the material forming the oxide semiconductor layer, the oxide semiconductor layer may be crystallized to be microcrystalline or polycrystalline. For example, a microcrystalline oxide semiconductor layer with a crystallization rate of 90% or higher or 80% or higher may be formed in some cases. Further, depending on the condition of the first heat treatment or the material forming the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer containing no crystal component.

In the case where an amorphous oxide semiconductor (eg, the surface of the oxide semiconductor layer) is mixed with microcrystals (having a grain size of 1 nm to 20 nm (typically 2 nm to 4 nm)) There is also. By mixing and arranging microcrystals in an amorphous state as described above, the electrical characteristics of the oxide semiconductor layer can be changed.

For example, when an oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor film formation target, crystal grains of In ₂ Ga ₂ ZnO ₇ having electrical anisotropy are oriented. By forming the microcrystalline region, the electrical characteristics of the oxide semiconductor layer can be changed.
The microcrystalline region is preferably a region in which the c-axis of In ₂ Ga ₂ ZnO ₇ crystal is oriented so as to be perpendicular to the surface of the oxide semiconductor layer. By forming a region in which crystal grains are oriented in this manner, conductivity in a direction parallel to the surface of the oxide semiconductor layer is improved and insulating property in a direction perpendicular to the surface of the oxide semiconductor layer is improved. You can In addition, such a microcrystalline region has a function of suppressing entry of impurities such as water and hydrogen into the oxide semiconductor layer.

Note that the oxide semiconductor layer having the above microcrystalline region can be formed by heating the surface of the oxide semiconductor layer by GRTA treatment. Further, by using a sputter target in which the content of Zn is smaller than the content of In or Ga, it is possible to form more favorably.

The first heat treatment for the oxide semiconductor layer can be performed on the oxide semiconductor layer 104 which has not yet been processed into the island-shaped oxide semiconductor layer 104a. In that case, after the first heat treatment, the substrate 100 is taken out of the heating device and a photolithography step is performed.

Note that the first heat treatment can also be referred to as dehydration treatment, dehydrogenation treatment, or the like. In the dehydration treatment and dehydrogenation treatment, after the oxide semiconductor layer was formed, a source electrode or a drain electrode was stacked over the oxide semiconductor layer 104a and then a gate insulating layer was formed over the source electrode or the drain electrode. It is possible to carry out at a timing such as later. Further, such dehydration treatment and dehydrogenation treatment may be performed not only once but a plurality of times.

Next, after forming the conductive layer 106 in contact with the oxide semiconductor layer 104a, the conductive layer 106 is formed.
The insulating layer 108 is formed thereover (see FIG. 2C). Note that the insulating layer 108 is not an essential component but is effective for selectively oxidizing side surfaces of a source electrode or a drain electrode which is formed later.

The conductive layer 106 is formed by a PVD method such as a sputtering method or a CVD such as a plasma CVD method.
Can be formed using a method. The conductive layer 106 is made of aluminum, chromium, copper,
It can be formed using an element selected from tantalum, titanium, molybdenum, or tungsten, an alloy containing any of the above elements as a component, or the like. Manganese, magnesium, zirconium,
A material containing one or more of beryllium and thorium may be used. Alternatively, a material in which one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are contained in aluminum may be used.

Alternatively, the conductive layer 106 may be formed using a conductive metal oxide. Examples of conductive metal oxides include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), and zinc oxide (ZnO).
), indium oxide-tin oxide alloy (In ₂ O ₃ —SnO ₂ , sometimes abbreviated as ITO), indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO), or these metal oxide materials with silicon or A material containing silicon oxide can be used.

The conductive layer 106 may have a single-layer structure or a layered structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked are included. Here, a three-layer structure of a titanium film, an aluminum film, and a titanium film is applied.

Note that an oxide conductive layer may be formed between the oxide semiconductor layer 104a and the conductive layer 106. The oxide conductive layer and the conductive layer 106 can be formed continuously (continuous film formation).
By providing such an oxide conductive layer, resistance of the source region or the drain region can be reduced, so that high-speed operation of the transistor can be realized.

The insulating layer 108 can be formed by a CVD method, a sputtering method, or the like. Also,
The insulating layer 108 is preferably formed so as to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the insulating layer 108 may have a single-layer structure or a stacked structure. The thickness of the insulating layer 108 is not particularly limited, but can be 10 nm or more and 500 nm or less, for example.

Next, the conductive layer 106 and the insulating layer 108 are selectively etched to form the source or drain electrode 106a, the source or drain electrode 106b, the insulating layer 108a, and the insulating layer 108b. Then, oxidation treatment is performed to supply oxygen to the oxide semiconductor layer 104a. By the oxidation treatment, the oxidized region 110 is formed in part of the source or drain electrode 106a and the source or drain electrode 106b (see FIG. 2D). In addition, as shown by a dotted line, a region to which oxygen is supplied is formed in the oxide semiconductor layer 104a. Note that the range of the region to which oxygen is supplied is variously changed depending on a material forming the oxide semiconductor layer 104a, conditions of oxidation treatment, and the like. For example, the oxide semiconductor layer 104
It is also possible to supply oxygen to the lower interface of a.

It is preferable to use ultraviolet light, KrF laser light, or ArF laser light for light exposure when forming a mask used for etching. In particular, when exposure is performed with a channel length (L) of less than 25 nm, an extreme ultraviolet ray (Extreme Ultra) having a very short wavelength of several nm to several tens of nm is used.
It is preferable to carry out exposure for mask formation using a violet). Extreme ultraviolet light has high resolution and a large depth of focus. Therefore, the channel length (
L) can be 10 nm or more and 1000 nm or less. By reducing the channel length (L) by such a method, the operating speed can be improved. In addition, since the off-state current of the transistor including the oxide semiconductor is small, an increase in power consumption due to miniaturization can be suppressed.

Each material and etching conditions are adjusted as appropriate so that the oxide semiconductor layer 104a is not removed when the conductive layer 106 is etched. Note that depending on the material and etching conditions, part of the oxide semiconductor layer 104a is etched in this step and the groove portion (
In some cases, the oxide semiconductor layer may have a depression.

In order to reduce the number of masks used and the number of steps, a resist mask may be formed using a multi-tone mask that is an exposure mask that allows transmitted light to have a plurality of intensities, and an etching step may be performed using the resist mask. .. A resist mask formed using a multi-tone mask has a shape (step shape) having a plurality of thicknesses, and the shape can be further deformed by ashing.
It can be used in multiple etching steps. That is, a resist mask corresponding to at least two kinds of different patterns can be formed with one multi-tone mask. Therefore, the number of exposure masks can be reduced and the corresponding photolithography process can also be reduced, so that the process can be simplified.

The oxidation treatment is preferably an oxidation treatment (plasma oxidation treatment) using oxygen plasma excited by microwaves (300 MHz or more and 300 GHz or less). By exciting the plasma with microwaves, high-density plasma can be realized and damage to the oxide semiconductor layer 104a can be sufficiently reduced.

More specifically, for example, the frequency is 300 MHz or more and 300 GHz or less (typically 2.
45 GHz), the pressure is 50 Pa or more and 5000 Pa or less (typically 500 Pa), the substrate temperature is 200° C. or more and 400° C. or less (typically 300° C.), and the above treatment is performed using a mixed gas of oxygen and argon. be able to.

Oxygen is supplied to the oxide semiconductor layer 104a by the above oxidation treatment, so that the localized level due to oxygen vacancies can be reduced while sufficiently reducing damage to the oxide semiconductor layer 104a. it can. That is, the characteristics of the oxide semiconductor layer 104a can be further improved.

Note that the oxide semiconductor layer 104a can be sufficiently reduced in damage to the oxide semiconductor layer 104a.
There is no need to limit to the plasma oxidation process using microwaves as long as oxygen can be supplied to a. For example, a method such as heat treatment in an atmosphere containing oxygen can be used.

In addition to the oxidation treatment, treatment for removing water, hydrogen, or the like from the oxide semiconductor layer 104a may be performed. For example, plasma treatment using a gas such as nitrogen or argon can be performed.

Note that, by the above oxidation treatment, the oxidized region 110 is formed in part of the source or drain electrode 106a and the source or drain electrode 106b (in particular, a part corresponding to a side surface thereof). The oxidized region 110 is particularly effective when the transistor 150 is miniaturized (for example, when the channel length is less than 1000 nm). With the miniaturization of transistors, it is required to reduce the thickness of the gate insulating layer. However, the presence of the oxide region 110 may occur due to thinning of the gate insulating layer, poor coverage, and the like. This is because it is possible to prevent a short circuit between the gate electrode and the source or drain electrode. Note that the oxidized region 110 is sufficiently effective if it has a thickness of 5 nm or more (preferably 10 nm or more).

The oxidation treatment is also effective from the viewpoint of improving the film quality of the exposed insulating layer 102.

Note that the source or drain electrode 106a or the source or drain electrode 106a
The insulating layers 108a and 108b are important in that they have a role of preventing oxidation of the upper part of b. This is because it is very difficult to perform the above plasma treatment while leaving the mask used for etching.

Note that in FIG. 2D, the conductive layer 106 and the insulating layer 108 illustrated in FIG. 2C are selectively etched to form the source or drain electrode 106a, the source or drain electrode 106b, the insulating layer 108a, and the insulating layer 108a. Although the case where the layer 108b is formed at one time is shown as an example, one embodiment of the disclosed invention is not limited to this.

For example, only a region of the conductive layer 106 and the insulating layer 108 which overlaps with the oxide semiconductor layer 104a is selectively etched to form an opening reaching a channel formation region of a transistor, and then the plasma treatment is performed on the region. To supply oxygen to the oxide semiconductor layer 104a, oxidize the exposed portion of the conductive layer 106, and then etch again to form the source or drain electrode 106a, the source or drain electrode 106b,
The insulating layers 108a and 108b may be completed. When such a process is adopted, since the oxidation treatment can be applied only to the target portion, there is an advantage that the other portions are not adversely affected by the oxidation treatment.

Next, the gate insulating layer 112 which is in contact with part of the oxide semiconductor layer 104a is formed without being exposed to the air (see FIG. 3A). The gate insulating layer 112 can be formed by a CVD method, a sputtering method, or the like. Further, the gate insulating layer 112 is preferably formed so as to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 112 may have a single-layer structure or a stacked structure. The thickness of the gate insulating layer 112 is not particularly limited, but can be 10 nm or more and 500 nm or less, for example.

Note that an i-type or substantially i-type oxide semiconductor (a highly purified oxide semiconductor) which is obtained by removing impurities is extremely sensitive to an interface state and an interface charge. Therefore, high quality is required for the gate insulating layer 112.

For example, a high-density plasma CVD method using microwaves (eg, 2.45 GHz) is preferable because a dense gate insulating layer 112 with high withstand voltage and high quality can be formed. This is because when the highly purified oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, the interface state can be reduced and favorable interface characteristics can be obtained.

Of course, if a high-quality insulating layer can be formed as the gate insulating layer 112, another method such as a sputtering method or a plasma CVD method can be applied. Further, an insulating layer whose film quality and interface characteristics are modified by heat treatment after formation may be applied. In any case, it is sufficient to provide the gate insulating layer 112 that has good film quality and can reduce the interface state density with the oxide semiconductor layer to form a good interface.

In this way, by improving the interface characteristics with the gate insulating layer and removing impurities of the oxide semiconductor, particularly hydrogen and water, a gate bias/thermal stress test (BT test: 85° C., 2× It is possible to obtain a stable transistor in which the threshold voltage (Vth) does not change with respect to 10 ⁶ V/cm, 12 hours, and the like.

After that, second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200° C. or higher and 400° C. or lower, and preferably 250° C. or higher and 350° C. or lower. For example,
Heat treatment may be performed at 250° C. for one hour in a nitrogen atmosphere. The second heat treatment can reduce variation in electric characteristics of the transistor. Note that although the second heat treatment is performed after the gate insulating layer 112 is formed in this embodiment, the timing of the second heat treatment is as follows.
There is no particular limitation as long as it is after the first heat treatment.

Next, the gate electrode 11 is formed on the gate insulating layer 112 in a region overlapping with the oxide semiconductor layer 104a.
4 are formed (see FIG. 3B). The gate electrode 114 can be formed by forming a conductive layer over the gate insulating layer 112 and then selectively patterning the conductive layer.

The conductive layer can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten, an alloy containing any of the above elements as a component, or the like. A material containing one or more of manganese, magnesium, zirconium, beryllium, and thorium may be used. Alternatively, a material in which one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are contained in aluminum may be used.

Alternatively, the conductive layer may be formed using a conductive metal oxide. The conductive metal oxide may be abbreviated as indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium oxide-tin oxide alloy (In ₂ O ₃ —SnO ₂ , ITO). A), an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO), or a material in which silicon or silicon oxide is contained in these metal oxide materials can be used.

The conductive layer may have a single layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked are included. Here, a conductive layer is formed using a material containing titanium and processed into the gate electrode 114.

Next, the interlayer insulating layer 116 and the interlayer insulating layer 118 are formed over the gate insulating layer 112 and the gate electrode 114 (see FIG. 3C). The interlayer insulating layer 116 and the interlayer insulating layer 118 can be formed by a PVD method, a CVD method, or the like. Alternatively, a film can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Note that although a stacked-layer structure of the interlayer insulating layer 116 and the interlayer insulating layer 118 is used in this embodiment, one embodiment of the disclosed invention is not limited to this. It may have one layer, or may have a laminated structure of three or more layers.

It is desirable that the interlayer insulating layer 118 be formed so that the surface thereof is flat.
By forming the interlayer insulating layer 118 so that the surface is flat, electrodes, wirings, and the like can be favorably formed over the interlayer insulating layer 118.

Through the above steps, the transistor 150 including an oxide semiconductor is completed.

When the transistor 150 is manufactured by the above method, the hydrogen concentration of the oxide semiconductor layer 104a is 5×10 ¹⁹ /cm ³ or less and the off-state current of the transistor 150 is 1×1.
It becomes ^0-13 A or less. As described above, the transistor 150 having excellent characteristics can be obtained by applying the oxide semiconductor layer 104a which has a sufficiently reduced hydrogen concentration and is highly purified by being supplied with oxygen. Note that when oxygen is supplied immediately after the hydrogen concentration is reduced, there is no risk of hydrogen, water, or the like entering the oxide semiconductor layer; therefore, an oxide semiconductor layer with extremely favorable characteristics can be realized. It is preferable in that it can be done. Of course, if an oxide semiconductor layer with good characteristics can be realized, the hydrogen concentration reduction treatment and the oxygen supply treatment are
It does not have to be done continuously. For example, another process may be included between these processes. Moreover, these processes may be performed simultaneously.

In addition, in this embodiment, oxygen plasma treatment is performed on the oxide semiconductor layer 104a in order to supply oxygen to the oxide semiconductor layer 104a. Therefore, the characteristics of the transistor 150 are further improved. In addition, since a region corresponding to a side surface of the source electrode or the drain electrode is oxidized, a short circuit between the gate electrode and the source electrode (or the drain electrode) which may occur due to thinning of the gate insulating layer. Can be prevented.

Although much research has been conducted on physical properties of oxide semiconductors, these studies do not include the idea of sufficiently reducing the localized level itself. In one embodiment of the disclosed invention, water or hydrogen which may cause a localized level is removed from an oxide semiconductor to manufacture a highly purified oxide semiconductor. This is based on the idea of sufficiently reducing the localized levels themselves. This enables the production of extremely excellent industrial products.

When removing hydrogen, water, etc., oxygen may be removed at the same time. Therefore, by supplying oxygen to dangling bonds of a metal generated by oxygen deficiency and reducing a localized level due to oxygen defects, the oxide semiconductor can be further purified (i-type). It is suitable. For example, an oxygen-rich oxide film is formed in close contact with the channel formation region, and heat treatment is performed under temperature conditions of 200 °C to 400 °C, typically about 250 °C, so that oxygen is supplied from the oxide film. Thus, the localized level due to oxygen defects can be reduced. Also,
The inert gas may be switched to a gas containing oxygen during the second heat treatment. After the second heat treatment, oxygen can be supplied to the oxide semiconductor by a temperature lowering process in an oxygen atmosphere or an atmosphere in which hydrogen and water are sufficiently removed.

The cause of deteriorating the characteristics of the oxide semiconductor is 0.1 eV or more below the conduction band due to excess hydrogen.
It is considered to be caused by a shallow level of 2 eV or less, a deep level due to oxygen deficiency, and the like.
In order to eliminate these defects, the technical idea of thoroughly removing hydrogen and supplying sufficient oxygen would be correct.

Note that an oxide semiconductor is generally n-type; however, in one embodiment of the disclosed invention, impurities such as water and hydrogen are removed and oxygen which is a constituent element of the oxide semiconductor is supplied.
Achieve a mold. In this respect, it can be said that the present invention does not include i-type conversion by adding impurities such as silicon, but includes an unprecedented technical idea.

<Electrical Conduction Mechanism of Transistor Using Oxide Semiconductor>
Here, a conduction mechanism of a transistor including an oxide semiconductor will be described with reference to FIGS. In the following description, an ideal situation is assumed for easy understanding, and not all of them reflect the actual situation. In addition, it should be noted that the following description is merely a consideration and does not affect the effectiveness of the invention.

FIG. 4 is a cross-sectional view of a transistor (thin film transistor) including an oxide semiconductor. An oxide semiconductor layer (OS) is provided over the gate electrode (GE1) via a gate insulating layer (GI), and a source electrode (S) and a drain electrode (D) are provided thereon, and a source electrode (S). An insulating layer is provided so as to cover the drain electrode (D).

FIG. 5 shows an energy band diagram (schematic diagram) in the AA′ cross section of FIG. 4. Further, the black circles (●) in FIG. 5 indicate electrons, the white circles (◯) indicate holes, and the charges (−q, +q) respectively.
)have. A positive voltage (V _D >0) is applied to the drain electrode, and a broken line indicates a case where no voltage is applied to the gate electrode (V _G =0). A solid line indicates a positive voltage (V _G >0) to the gate electrode. The case of applying is shown. When no voltage is applied to the gate electrode, carriers (electrons) are not injected from the electrode to the oxide semiconductor side because of a high potential barrier, which means an off state in which no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier lowers, and an ON state in which current flows is shown.

FIG. 6 shows an energy band diagram (schematic diagram) in a cross section taken along the line BB′ in FIG.
6 (A) is a positive voltage to the gate electrode _{(GE1) (V G> 0} ) is a state in which a given,
An ON state in which carriers (electrons) flow between the source electrode and the drain electrode is shown. Also, FIG. 6 (B) is a state in which a negative voltage to the gate electrode (GE1) (V G _<0) is applied, a case is off (minority carriers do not flow).

FIG. 7 shows a relationship between a vacuum level, a work function of metal (φ _M ), and an electron affinity (χ) of an oxide semiconductor.

At room temperature, the electrons in the metal degenerate and the Fermi level is located in the conduction band. on the other hand,
A conventional oxide semiconductor is n-type, and its Fermi level (E _F ) is located near the conduction band apart from the intrinsic Fermi level (E _i ) located in the center of the band gap. Note that it is known that part of hydrogen in an oxide semiconductor serves as a donor and is one of factors which cause n-type conductivity.

On the other hand, the oxide semiconductor according to one embodiment of the disclosed invention has hydrogen, which is a factor of n-type conductivity, removed from the oxide semiconductor and contains elements (impurity elements) other than the main component of the oxide semiconductor as much as possible. It is made to be genuine (i-type) by making it highly purified so as not to exist, or made to be genuine. That is, it is characterized in that highly purified i-type (intrinsic semiconductor) or close to it is obtained by removing impurities such as hydrogen and water as much as possible, rather than adding an impurity element to make it i-type. Accordingly, the Fermi level (E _F ) can be made to be approximately the same as the intrinsic Fermi level (E _i ).

The band gap (E _g ) of the oxide semiconductor is 3.15 eV and the electron affinity (χ) is 4.3 V.
Is said. The work function of titanium (Ti) forming the source electrode and the drain electrode is almost equal to the electron affinity (χ) of the oxide semiconductor. In this case, a Schottky barrier against electrons is not formed at the metal-oxide semiconductor interface.

At this time, the electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the lowest energy-stable part of the oxide semiconductor), as shown in FIG.

In addition, as shown in FIG. 6B, when a negative potential is applied to the gate electrode (GE1), the number of holes, which are minority carriers, is substantially zero, so that the current is infinitely close to zero. ..

As described above, since the element (impurity element) other than the main component of the oxide semiconductor is highly purified so that the element is not included as much as possible, the element is made intrinsic (i-type) or becomes substantially intrinsic. The interface characteristics with and become apparent. Therefore, the gate insulating layer is required to have a favorable interface with the oxide semiconductor. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power source frequency in a VHF band to a microwave band, an insulating layer formed by a sputtering method, or the like is preferably used. ..

By making the interface between the oxide semiconductor and the gate insulating layer favorable while making the oxide semiconductor highly purified, for example, the channel width (W) of the transistor is 1×10 ⁴ μm and the channel length (L) is In the case of 3 μm, an off current of 10 ⁻¹³ A or less, 0.1 V/dec. Subthreshold swing value (S value) (thickness of gate insulating layer: 100 nm) can be realized.

As described above, by highly purifying elements (impurity elements) other than the main component of the oxide semiconductor as little as possible, the operation of the transistor can be favorable.

<Tolerance against hot carrier deterioration of transistor using oxide semiconductor>
Next, resistance to hot carrier deterioration of a transistor including an oxide semiconductor will be described with reference to FIGS. In the following description, an ideal situation is assumed for easy understanding, and not all of them reflect the actual situation. In addition, it should be noted that the following description is merely a consideration.

The main cause of hot carrier deterioration is channel hot electron injection (CHE injection).
And drain avalanche hot carrier injection (DAHC injection). In the following, only electrons are considered for simplicity.

CHE injection refers to a phenomenon in which electrons having energy higher than that of a barrier of a gate insulating layer in a semiconductor layer are injected into a gate insulating layer or the like. The donation of energy to electrons is performed by accelerating the electrons in a low electric field.

DAHC injection refers to a phenomenon in which new electrons are injected into a gate insulating layer or the like by collision of electrons accelerated by a high electric field. The difference between DAHC injection and CHE injection is whether or not avalanche breakdown due to impact ionization is involved. Note that DAHC injection requires electrons having a kinetic energy larger than the semiconductor band gap.

FIG. 8 shows energies required for various hot carrier injections estimated from the band structure of silicon (Si), and FIG. 9 shows various types of energy estimated from the band structure of an In—Ga—Zn—O-based oxide semiconductor (IGZO). The energy required for hot carrier injection is shown. In addition, in FIG.
A) and FIG. 9(A) represent CHE injection, and FIGS. 8(B) and 9(B) represent DAHC injection.

In silicon, deterioration due to DAHC injection is more serious than that due to CHE injection. This is because the number of carriers (eg, electrons) that are accelerated in the silicon without collision is very small, whereas the band gap of silicon is small and avalanche breakdown is likely to occur. The avalanche breakdown increases the number of electrons that can cross the barrier of the gate insulating layer,
The probability of injection is easily exceeded.

In the case of an In-Ga-Zn-O-based oxide semiconductor, the energy required for CHE injection is not significantly different from that in the case of silicon, and the probability is also low. Further, the energy required for DAHC injection is about the same as the energy required for CHE injection due to the wide band gap.

That is, the probabilities of CHE injection and DAHC injection are both low, and the resistance to hot carrier deterioration is higher than that of silicon.

By the way, the band gap of an In—Ga—Zn—O-based oxide semiconductor is about the same as that of silicon carbide (SiC), which is attracting attention as a high breakdown voltage material. FIG. 10 shows the energy required for injection of various hot carriers for 4H—SiC. Further, FIG. 10(A) shows CHE injection, and FIG. 10(B) shows DAHC injection. For CHE injection, In-Ga-Zn-
The O-based oxide semiconductor has a slightly higher threshold and can be said to be advantageous.

As described above, it is found that the In—Ga—Zn—O-based oxide semiconductor has much higher resistance to hot carrier deterioration and source-drain breakdown than silicon. Further, it can be said that a breakdown voltage comparable to that of silicon carbide can be obtained.

<Short channel effect in transistor using oxide semiconductor>
Next, the short channel effect in the transistor including an oxide semiconductor will be described with reference to FIGS. In the following description, an ideal situation is assumed for easy understanding, and not all of them reflect the actual situation. In addition, it should be noted that the following description is merely a consideration.

The short channel effect refers to deterioration of electric characteristics which is manifested with miniaturization of a transistor (reduction of channel length (L)). The short channel effect is due to the effect of the drain reaching the source. Specific examples of the short channel effect include a decrease in threshold voltage, an increase in S value, and an increase in leakage current.

Here, the device simulation was used to verify the structure capable of suppressing the short channel effect. Specifically, four types of models having different carrier concentrations and oxide semiconductor layer thicknesses were prepared, and the relationship between the channel length (L) and the threshold voltage (Vth) was confirmed. As a model, a bottom-gate transistor is used, the carrier concentration of the oxide semiconductor is set to either 1.7×10 ⁻⁸ /cm ³ or 1.0×10 ¹⁵ /cm ³ , and the oxide semiconductor layer is used. The thickness was 1 μm or 30 nm. Note that an In—Ga—Zn—O-based oxide semiconductor is used as the oxide semiconductor and 100 nm is used as the gate insulating layer.
Was used. It is assumed that the band gap of the oxide semiconductor is 3.15 eV, the electron affinity is 4.3 eV, the relative dielectric constant is 15, and the electron mobility is 10 cm ² /Vs. The relative permittivity of the silicon oxynitride film was assumed to be 4.0. The device simulation software “Atlas” manufactured by Silvaco was used for the calculation.

There is no significant difference in the calculation results between the top gate structure and the bottom gate structure.

The calculation results are shown in FIGS. 11 and 12. In FIG. 11, the carrier concentration is 1.7×10 ⁻⁸ /c.
In the case of m ³ , FIG. 12 shows the case where the carrier concentration is 1.0×10 ¹⁵ /cm ³ . 11
12 and FIG. 12, the amount of change (Δth) in the threshold voltage (Vth) when the channel length (L) is changed from 10 μm to 1 μm is based on the transistor having the channel length (L) of 10 μm as a reference.
Vth) is shown. As shown in FIG. 11, the carrier concentration of the oxide semiconductor is 1.7×1.
0 ^-8 / cm ^3, and if the thickness of the oxide semiconductor layer is 1 [mu] m, the amount of change in threshold voltage ([Delta] Vth) was -3.6 V. Further, as shown in FIG. 11, when the carrier concentration of the oxide semiconductor is 1.7×10 ⁻⁸ /cm ³ and the thickness of the oxide semiconductor layer is 30 nm,
The amount of change in threshold voltage (ΔVth) was −0.2V. Also, as shown in FIG.
When the carrier concentration of the oxide semiconductor was 1.0×10 ¹⁵ /cm ³ and the thickness of the oxide semiconductor layer was 1 μm, the amount of change in threshold voltage (ΔVth) was −3.6V. .. Further, as shown in FIG. 12, when the carrier concentration of the oxide semiconductor is 1.0×10 ¹⁵ /cm ³ and the thickness of the oxide semiconductor layer is 30 nm, the amount of change in threshold voltage (ΔVth) Is -0.2
It was V. It can be said that the result shows that in a transistor including an oxide semiconductor, the short channel effect can be suppressed by reducing the thickness of the oxide semiconductor layer. For example, when the channel length (L) is about 1 μm, the short channel effect can be sufficiently suppressed even if the oxide semiconductor layer has a sufficiently high carrier concentration and the thickness thereof is about 30 nm. To be understood.

<Carrier concentration>
The technical idea according to the disclosed invention is to make the carrier concentration in an oxide semiconductor layer sufficiently small so as to be as close to intrinsic (i-type) as possible. Hereinafter, how to obtain the carrier concentration and the actually measured carrier concentration will be described with reference to FIGS. 13 and 14.

First, how to obtain the carrier concentration will be briefly described. The carrier concentration can be obtained by producing a MOS capacitor and evaluating the CV measurement result (CV characteristic) of the MOS capacitor.

More specifically, C is a plot of the relationship between the gate voltage Vg of the MOS capacitor and the capacitance C.
-V characteristic is acquired, a graph showing the relationship between the gate voltage Vg and (1/C) ² is acquired from the C-V characteristic, and the differential value of (1/C) ² in the weak inversion region in the graph. And the value of the carrier concentration N _d is obtained by substituting the differential value into the equation (1). In the formula (1), e is an elementary charge, ε ₀ is a vacuum permittivity, and ε is a relative permittivity of an oxide semiconductor.

Next, the carrier concentration actually measured using the above method will be described. For the measurement, a titanium film having a thickness of 300 nm was formed on a glass substrate, and a titanium nitride film was formed on the titanium film by 100 nm.
nm thickness, an oxide semiconductor layer using an In—Ga—Zn—O-based oxide semiconductor is formed to a thickness of 2 μm on the titanium nitride film, and a silver film is formed on the oxide semiconductor layer. A sample (MOS capacitor) having a thickness of 300 nm was used. Note that the oxide semiconductor layer is formed of In, Ga,
And a target for forming an oxide semiconductor containing Zn (In:Ga:Zn=1:1:0.5[
Atom ratio]) was used to form a film by a sputtering method. The atmosphere for forming the oxide semiconductor layer is a mixed atmosphere of argon and oxygen (flow ratio is Ar:O ₂ =30 (sccm):1).
5 (sccm)).

FIG. 13 shows the C-V characteristic, and FIG. 14 shows the relationship between Vg and (1/C) ² . The carrier concentration obtained using the formula (1) from the differential value of (1/C) ² in the weak inversion region of FIG. 14 was 6.0×10 ¹⁰ /cm ³ .

As described above, by using an i-type or substantially i-type oxide semiconductor (for example, the carrier concentration is less than 1×10 ¹² /cm ³ , preferably 1×10 ¹¹ /cm ³ or less) ,
It is possible to obtain a transistor with extremely excellent off-state current characteristics.

As described above, the structure, the method, and the like described in this embodiment can be combined with the structure, the method, and the like described in other embodiments as appropriate.

(Embodiment 2)
In this embodiment, examples of electronic devices each including the semiconductor device obtained in any of the above embodiments will be described with reference to FIGS. The semiconductor device obtained in the above embodiment has excellent characteristics that have never been obtained. Therefore, it is possible to provide an electronic device having a new structure by using the semiconductor device. Note that the semiconductor device according to any of the above embodiments is integrated, mounted on a circuit board, or the like and mounted inside each electronic device.

FIG. 15A illustrates a laptop personal computer including the semiconductor device according to any of the above embodiments, which includes a main body 301, a housing 302, a display portion 303, a keyboard 304, and the like. By applying the semiconductor device according to the disclosed invention to a personal computer, a personal computer with excellent performance can be provided.

FIG. 15B illustrates a personal digital assistant (PDA) including the semiconductor device according to any of the above embodiments, in which a main body 311 is provided with a display portion 313, an external interface 315, operation buttons 314, and the like. .. A stylus 312 is an accessory for operation. By applying the semiconductor device according to the disclosed invention to a personal digital assistant (PDA), a personal digital assistant (PDA) with excellent performance can be provided.

In FIG. 15C, as an example of electronic paper including the semiconductor device according to any of the above embodiments,
An electronic book 320 is shown. The e-book reader 320 includes two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337,
The opening/closing operation can be performed around the shaft portion 337 as an axis. With such a structure, the electronic book 320 can be used like a paper book.

A display portion 325 is incorporated in the housing 321 and a display portion 327 is incorporated in the housing 323. The display unit 325 and the display unit 327 may be configured to display a subsequent screen or may be configured to display different screens. By configuring to display different screens, for example, a sentence is displayed on the right display unit (display unit 325 in FIG. 15C) and the left display unit (FIG. 15).
In (C), an image can be displayed on the display unit 327).

In addition, FIG. 15C illustrates an example in which the housing 321 is provided with an operation portion and the like. For example, the housing 321 includes a power source 331, operation keys 333, a speaker 335, and the like. Pages can be turned with the operation key 333. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, a configuration may be provided in which a terminal for external connection (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, and the like are provided on a back surface or a side surface of the housing. .. Further, the electronic book 320 may be configured to have a function as an electronic dictionary.

Further, the electronic book 320 may have a structure capable of wirelessly transmitting and receiving data. It is also possible to purchase desired book data and the like from an electronic book server wirelessly and to download them.

The electronic paper can be applied to all fields as long as it displays information. For example, in addition to electronic books, it can be applied to posters, advertisements in vehicles such as trains, and displays on various cards such as credit cards. By applying the semiconductor device according to the disclosed invention to electronic paper, electronic paper with excellent performance can be provided.

FIG. 15D illustrates a mobile phone including the semiconductor device according to any of the above embodiments. The mobile phone includes two housings, a housing 340 and a housing 341. The housing 341 includes a display panel 342, a speaker 343, a microphone 344, and a pointing device 3.
46, a camera lens 347, an external connection terminal 348, and the like. In addition, the housing 340
Includes a solar battery cell 349 for charging the mobile phone, an external memory slot 350, and the like. Further, the antenna is built in the housing 341.

The display panel 342 has a touch panel function, and a plurality of operation keys 345 which is displayed as images is illustrated by dashed lines in FIG. In addition, the mobile phone is a solar cell 34.
A booster circuit for boosting the voltage output at 9 to a voltage required for each circuit is mounted. Further, in addition to the above configuration, a non-contact IC chip, a small recording device, or the like may be incorporated.

The display direction of the display panel 342 changes as appropriate depending on the usage pattern. In addition, the display panel 3
Since the camera lens 347 is provided on the same surface as 42, a videophone is possible. The speaker 343 and the microphone 344 can be used for videophone calls, recording and playing sound, and the like without being limited to voice calls. Further, the housing 340 and the housing 341 can be slid so that the housing 340 and the housing 341 can be brought into a stacked state from an unfolded state as illustrated in FIG. 15D, which enables downsizing suitable for being carried.

The external connection terminal 348 can be connected to various cables such as an AC adapter and a USB cable, and charging and data communication are possible. Also, by inserting a recording medium into the external memory slot 350, it is possible to store and move a large amount of data. In addition to the above functions,
It may have an infrared communication function, a television reception function, or the like. By applying the semiconductor device according to the disclosed invention to a mobile phone, a mobile phone with excellent performance can be provided.

FIG. 15E illustrates a digital camera including the semiconductor device according to any of the above embodiments. The digital camera includes a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364.
, A display unit (B) 365, a battery 366, and the like. By applying the semiconductor device according to the disclosed invention to a digital camera, a digital camera with excellent performance can be provided.

FIG. 15F is a television device including the semiconductor device according to any of the above embodiments. In the television device 370, the display portion 373 is incorporated in the housing 371. Display unit 373
With, it is possible to display an image. Note that here, a structure in which the housing 371 is supported by the stand 375 is shown.

The television device 370 can be operated with an operation switch included in the housing 371 or a remote controller 380 which is a separate body. The operation keys 379 provided on the remote controller 380 can be used to operate the channel and volume, and the video displayed on the display portion 373 can be operated. Further, the remote controller 380 may be provided with a display portion 377 for displaying information output from the remote controller 380.

Note that it is preferable that the television device 370 be provided with a receiver, a modem, and the like. A general television broadcast can be received by the receiver. Also, by connecting to a wired or wireless communication network via a modem, one-way (sender to receiver) or bidirectional (between sender and receiver, or between receivers) information communication is performed. It is possible. By applying the semiconductor device according to the disclosed invention to a television device,
A television device with excellent performance can be provided.

The structures, methods, and the like described in this embodiment can be combined with structures, methods, and the like described in other embodiments as appropriate.

In this example, it was confirmed that the conductive layer was oxidized by the high-density plasma treatment according to one embodiment of the disclosed invention. The details will be described below.

In this example, plasma was excited from a mixed gas of oxygen and argon under the conditions of a power supply frequency of 2.45 GHz and a pressure of 500 Pa, and the conductive layer was processed using the plasma. The relationship between the processing time and the thickness of the oxidized region was investigated by setting the processing time to 3 conditions of 1 minute (60 seconds), 3 minutes (180 seconds), and 10 minutes (600 seconds).

As the conductive layer, a titanium film formed on the glass substrate and an aluminum film formed on the glass substrate were prepared. Further, the plasma treatment was performed at substrate temperatures of 300° C. and 325° C., respectively. That is, a titanium film at a substrate temperature of 300° C., a titanium film at a substrate temperature of 325° C., an aluminum film at a substrate temperature of 300° C., a substrate temperature of 3
The relationship between the processing time and the thickness of the oxidized region was investigated for the four conditions of the aluminum film at 25°C.

The survey results are shown in FIG. From FIG. 16, it can be seen that the oxidation rate of titanium is higher than that of aluminum. Further, while titanium has a large temperature dependence of the oxidation rate, aluminum has a small temperature dependence of the oxidation rate. Furthermore, it can be said that in aluminum, the thickness of the oxidized region tends to be saturated in a short time.

With any of the materials, it is possible to obtain an oxidized region having a sufficient thickness (5 nm or more) to suppress a short circuit between the gate electrode and the source or drain electrode.

By applying the oxidation treatment with high-density plasma as shown in this embodiment, oxygen deficiency can be reduced while reducing damage to the oxide semiconductor layer as compared with the case where an oxidation treatment with normal plasma treatment is applied. It is possible to reduce the localized level due to. That is, the characteristics of the oxide semiconductor layer can be further improved.

In addition, since the oxidized region is formed in a part of the source electrode or the drain electrode (particularly, a portion corresponding to the side surface thereof) by the oxidation treatment, it is possible to prevent a short circuit between the gate electrode and the source electrode or the drain electrode.

From the above, it is understood that one embodiment of the disclosed invention is extremely effective in improving reliability and other characteristics of a transistor including an oxide semiconductor.

100 substrate 102 insulating layer 104 oxide semiconductor layer 104a oxide semiconductor layer 106 conductive layer 106a source or drain electrode 106b source or drain electrode 108 insulating layer 108a insulating layer 108b insulating layer 110 oxidized region 112 gate insulating layer 114 gate electrode 116 Interlayer insulating layer 118 Interlayer insulating layer 150 Transistor 301 Main body 302 Housing 303 Display unit 304 Keyboard 311 Main body 312 Stylus 313 Display unit 314 Operation button 315 External interface 320 E-book 321 Housing 323 Housing 325 Display unit 327 Display unit 331 Power supply 333 Operation key 335 Speaker 337 Shaft 340 Housing 341 Housing 342 Display panel 343 Speaker 344 Microphone 345 Operation key 346 Pointing device 347 Camera lens 348 External connection terminal 349 Solar cell 350 External memory slot 361 Main body 363 Eyepiece 364 Operation Switch 365 Display (B)
366 Battery 367 Display (A)
370 Television device 371 Housing 373 Display 375 Stand 377 Display 379 Operation keys 380 Remote control

Claims (4)

A semiconductor device having a transistor,
An oxide semiconductor layer,
A gate electrode layer disposed above the oxide semiconductor layer,
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer,
A first insulating layer having a region in contact with the source electrode layer,
A second insulating layer having a region in contact with the drain electrode layer,
The upper surface and the side surface of the first insulating layer, the upper surface and the side surface of the second insulating layer, the side surface of the source electrode layer, the side surface of the drain electrode layer, and the upper surface of the oxide semiconductor layer are the third insulating layer. A semiconductor device having a region in contact with a layer. A semiconductor device having a transistor,
An oxide semiconductor layer,
A gate electrode layer disposed above the oxide semiconductor layer,
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer,
A first insulating layer having a region in contact with the source electrode layer,
A second insulating layer having a region in contact with the drain electrode layer,
A third insulating layer disposed above the source electrode layer and above the drain electrode layer;
A fourth insulating layer disposed below the oxide semiconductor layer,
The upper surface and side surface of the first insulating layer, the upper surface and side surface of the second insulating layer, the side surface of the source electrode layer, the side surface of the drain electrode layer, the upper surface of the oxide semiconductor layer, and the fourth insulation. The semiconductor device, wherein an upper surface of the layer has a region in contact with the third insulating layer. A semiconductor device having a transistor,
An oxide semiconductor layer,
A gate electrode layer disposed above the oxide semiconductor layer,
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer,
A first insulating layer having a region in contact with the source electrode layer,
A second insulating layer having a region in contact with the drain electrode layer,
The upper surface and the side surface of the first insulating layer, the upper surface and the side surface of the second insulating layer, the side surface of the source electrode layer, the side surface of the drain electrode layer, and the upper surface of the oxide semiconductor layer are the third insulating layer. Has a region in contact with the layer,
The oxide semiconductor layer has a first region in contact with the third insulating layer, a second region in contact with the source electrode layer, and a third region in contact with the drain electrode layer,
A semiconductor device, wherein the film thickness of the first region is smaller than the film thickness of the second region and the film thickness of the third region. A semiconductor device having a transistor,
An oxide semiconductor layer,
A gate electrode layer disposed above the oxide semiconductor layer,
A source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer,
A first insulating layer having a region in contact with the source electrode layer,
A second insulating layer having a region in contact with the drain electrode layer,
A third insulating layer disposed above the source electrode layer and above the drain electrode layer;
A fourth insulating layer disposed below the oxide semiconductor layer,
The upper surface and side surface of the first insulating layer, the upper surface and side surface of the second insulating layer, the side surface of the source electrode layer, the side surface of the drain electrode layer, the upper surface of the oxide semiconductor layer, and the fourth insulation. The upper surface of the layer has a region in contact with the third insulating layer,
The oxide semiconductor layer has a first region in contact with the third insulating layer, a second region in contact with the source electrode layer, and a third region in contact with the drain electrode layer,
A semiconductor device, wherein the film thickness of the first region is smaller than the film thickness of the second region and the film thickness of the third region.