JP2020074392A - Nonvolatile semiconductor storage device and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device capable of improving a storage density and a method for manufacturing the same. According to an embodiment, a non-volatile semiconductor storage device includes a semiconductor layer, electrodes, first to third layers, and a plurality of nitride portions of a nitride molecule. The first layer is provided between the semiconductor layer and the electrodes. The second layer is provided between the first layer and the electrode. The energy at the conduction band edge of the second layer is lower than that of the first layer. The second layer includes a first region and a second region, and the first region is provided between the first layer and the second region. The third layer is provided between the second layer and the electrode. The energy at the conduction band edge of the third layer is higher than that of the second layer. The plurality of nitride portions are provided in any of the first and second regions, the first and second layers, and the second and third layers. The nitride molecule contains the first element of any of Group 4-6 and Group 13 and nitrogen. The length of the plurality of nitrided portions in the first direction from the semiconductor layer to the electrode is equal to or less than the maximum value of the size of the nitride molecule. [Selection diagram] Fig. 1

Description

  Embodiments of the present invention relate to a nonvolatile semiconductor memory device and a method for manufacturing the same.

  It is desired to improve the storage density in a nonvolatile semiconductor memory device.

JP, 2010-135561, A

  Embodiments of the present invention provide a non-volatile semiconductor memory device capable of improving storage density and a method for manufacturing the same.

  According to an embodiment of the present invention, a nonvolatile semiconductor memory device includes a semiconductor layer, a first electrode, first to third layers, and a plurality of nitride portions of nitride molecules. The first layer is provided between the semiconductor layer and the first electrode. The second layer is provided between the first layer and the first electrode. The second energy at the conduction band edge of the second layer is lower than the first energy at the conduction band edge of the first layer. The second layer includes the first region and the second region, and the first region is provided between the first layer and the second region. The third layer is provided between the second layer and the first electrode. The third energy at the conduction band edge of the third layer is higher than the second energy. The plurality of nitride portions are between the first region and the second region, between the first layer and the second layer, and between the second layer and the third layer. It is provided in either. The first layer is a tunnel insulating film, the second layer is a charge storage film, and the third layer is a block insulating layer. The nitride molecules include at least one of TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN, WN, BN, AlN, GaN and InN. The length of the plurality of nitride portions in the first direction from the semiconductor layer toward the first electrode is less than or equal to the maximum value of the size of the nitride molecule.

1A to 1C are schematic views illustrating the nonvolatile semiconductor memory device according to the first embodiment. 2A to 2C are schematic views illustrating the nonvolatile semiconductor memory device according to the second embodiment. 3A and 3B are schematic views illustrating the nonvolatile semiconductor memory device according to the third embodiment. FIG. 4A and FIG. 4B are schematic cross-sectional views illustrating the nonvolatile semiconductor memory device according to the fourth embodiment. 5A to 5D are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment. 6A to 6D are schematic cross-sectional views in order of the processes, illustrating another method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment. 7A and 7B are schematic cross-sectional views illustrating another nonvolatile semiconductor memory device according to the fourth embodiment. FIG. 8A to FIG. 8D are schematic cross-sectional views in order of the processes, illustrating a method for manufacturing another nonvolatile semiconductor memory device according to the fourth embodiment. 9A to 9D are schematic cross-sectional views in order of the processes, illustrating another method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment. 10A and 10B are schematic cross-sectional views illustrating another nonvolatile semiconductor memory device according to the fourth embodiment. 11A to 11D are schematic cross-sectional views in order of the processes, illustrating a method for manufacturing another nonvolatile semiconductor memory device according to the fourth embodiment. 12A to 12D are schematic cross-sectional views in order of the processes, illustrating another method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment. FIG. 9 is a schematic perspective view illustrating a nonvolatile semiconductor memory device according to a fourth embodiment. 14A to 14C are schematic cross-sectional views illustrating the nonvolatile semiconductor memory device according to the fourth embodiment.

Each embodiment of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each portion, the size ratio between the portions, and the like are not always the same as the actual ones. Even when the same portion is shown, the dimensions and ratios may be different depending on the drawings.
In the specification and the drawings of the application, components similar to those described in regard to a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

(First embodiment)
1A to 1C are schematic views illustrating the nonvolatile semiconductor memory device according to the first embodiment.
FIG. 1A is a sectional view. FIG. 1B is an energy band diagram. FIG. 1C is a schematic diagram showing molecules included in the nonvolatile semiconductor memory device.

  As shown in FIG. 1A, the nonvolatile semiconductor memory device 111 according to the embodiment includes a semiconductor layer 20, a first electrode 41, a first layer 31, a second layer 32, and a third layer 33. , And a plurality of nitride portions 35.

  The first layer 31 is provided between the semiconductor layer 20 and the first electrode 41. The second layer 32 is provided between the first layer 31 and the first electrode 41. The third layer 33 is provided between the second layer 32 and the first electrode 41.

  In this example, the plurality of nitride parts 35 are provided between the first layer 31 and the second layer 32. As will be described later, the plurality of nitride portions 35 may be provided between the second layer 32 and the third layer 33, or may be provided in the second layer 32.

  The plurality of nitride parts 35 are nitride molecules. The nitride molecule contains an element (first element) of any one of Group 4 (IVB group), Group 5 (VB group), Group 6 (VIB group) and Group 13 (IIIA group), and nitrogen.

  The direction from the semiconductor layer 20 toward the first electrode 41 is the first direction. The first direction is the X-axis direction. One axis perpendicular to the X-axis direction is the Z-axis direction. The direction perpendicular to the X-axis direction and the Z-axis direction is the Y-axis direction. As described later, the semiconductor layer 20 may have a pillar shape, and in this case, the direction from the semiconductor layer 20 toward the first electrode 41 corresponds to an arbitrary direction intersecting with the extending direction of the pillar.

  The semiconductor layer 20 has a surface (first surface 20a) facing the first layer 31. For example, the plurality of nitride portions 35 are arranged along the first surface 20a of the semiconductor layer 20. For example, the plurality of nitride parts 35 are arranged in a plane parallel to the first surface 20a of the semiconductor layer 20.

  The first electrode 41 has a surface (second surface 41a) facing the third layer 33. For example, the plurality of nitride parts 35 are arranged along the second surface 41 a of the first electrode 41. For example, the plurality of nitride parts 35 are arranged in a plane parallel to the second surface 41a of the first electrode 41.

  For example, the plurality of nitride parts 35 may be arranged along a plane perpendicular to the first direction (X-axis direction).

  FIG. 1B shows an example of the conduction band edge Bc and the valence band edge Bv. In this specification, the band alignment, the conduction band barrier height, and the valence band barrier height are based on the energy at the conduction band edge of silicon.

  For example, the first energy E1 of the conduction band edge Bc of the first layer 31 is higher than the energy Es of the conduction band edge Bc of the semiconductor layer 20. The first layer 31 includes, for example, an insulating material. The first layer 31 corresponds to, for example, a tunnel insulating film.

  For example, the second energy E2 of the conduction band edge Bc of the second layer 32 is higher than the energy Es of the conduction band edge Bc of the semiconductor layer 20. The second layer 32 includes, for example, an insulating material.

  For example, the third energy E3 of the conduction band edge Bc of the third layer 33 is higher than the energy Es of the conduction band edge Bc of the semiconductor layer 20. The third layer 33 includes, for example, an insulating material. The third layer 33 corresponds to, for example, a block insulating film.

  The second energy E2 of the conduction band edge Bc of the second layer 32 is lower than the first energy E1 of the conduction band edge Bc of the first layer 31. The second energy E2 at the conduction band edge Bc of the second layer 32 is lower than the third energy E3 at the conduction band edge Bc of the third layer 33. That is, the third energy E3 of the third layer 33 is higher than the second energy E2. The second layer 3 functions as a charge storage film, for example.

  For example, the first layer 31 includes silicon oxide. For example, the second layer 32 includes silicon nitride. For example, the third layer 33 includes silicon oxide.

  In the nonvolatile semiconductor memory device 111, for example, the potential (voltage) of the semiconductor layer 20 is used as a reference. For example, when a positive voltage is applied to the first electrode 41, charges (electrons) pass from the semiconductor layer 20 through the first layer 31 (tunnel insulating film) and are injected into the second layer 32 (charge storage film). To be done. The injected charges are suppressed from moving to the first electrode 41 by the third layer 33 (block insulating film). The charges injected into the second layer 32 are trapped in the second layer 32 and accumulated in the second layer 32. The threshold value of the current flowing through the semiconductor layer 20 changes depending on the presence or absence (the amount) of charges in the second layer 32. By this operation (for example, write operation), the first state is formed. By applying a voltage having a polarity opposite to the above voltage between the semiconductor layer 20 and the first electrode 41, the charges accumulated in the second layer 32 move to the semiconductor layer 20. The second state is formed by this operation (for example, the erase operation). By detecting the threshold values in the first state and the second state, the read operation of the stored state is performed.

  The first to third layers 31 to 33 and the plurality of nitride parts 35 are included in the memory film MF. The semiconductor layer 20, the first electrode 41, and the memory film MF correspond to one memory cell (first memory cell). The semiconductor layer 20 corresponds to the channel body.

  In the embodiment, the nitride molecules of the plurality of nitride portions 35 include, for example, at least one of BN, AlN, GaN, and InN.

  As shown in FIG. 1C, the nitride molecule 35M includes a first element 35p (first atom) and a nitrogen atom 35q. The first element 35p is an element of any one of Group 4 (IVB group), Group 5 (VB group), Group 6 (VIB group) and Group 13 (IIIA group). The first element 35p is, for example, one of boron (B), aluminum (Al), gallium (Ga), and indium (In).

  The shape of the nitride molecule 35M is not spherical. As shown in FIG. 1C, the maximum value 35L of the size of the nitride molecule 35M corresponds to the length of the nitride molecule 35M along the direction connecting the first element 35p and the nitrogen atom 35q, for example. ..

  The length 35d (thickness, see FIG. 1A) of the plurality of nitride parts 35 in the first direction (direction from the semiconductor layer 20 toward the first electrode 41) is the maximum of the size of the nitride molecule 35M. The value is 35 L or less.

  For example, the plurality of nitride parts 35 are dispersed in a single molecule state of the nitride molecule 35M. The thickness of the region in which the plurality of nitride portions 35 are provided is substantially equal to or less than the maximum value 35L of the size of the nitride molecule 35M.

  In the nonvolatile semiconductor memory device 111, when an electric field (voltage) is applied, charges move from the semiconductor layer 20 to the second layer 32 (charge storage film) after passing through the first layer 31 (tunnel insulating film). .. For example, due to the barrier heights of the plurality of nitride portions 35, the probability that charges transferred to the second layer 32 are transmitted toward the first layer 31 is reduced. Thereby, for example, the probability of trapping charges in the second layer 32 increases. Since the charge storage efficiency is increased, for example, the range of possible threshold voltages is expanded.

  For example, while trap sites are formed at the interface F1 between the first layer 31 and the second layer 32, the trap efficiency of the second layer 32 can be improved. As a result, the range of possible threshold voltages can be expanded.

  For example, there is a first reference example in which a nitride layer (thickness of 3 nm, for example) is provided between the tunnel insulating film and the charge storage film. In the first reference example, the nitride layer includes a crystalline structure such as a metal dot. The size of the crystal structure is significantly larger than the size of the nitride molecule. In the first reference example, the distance between the nitride and the semiconductor layer varies within the thickness of the nitride layer (for example, 3 nm). When the distance between the metal oxide and the semiconductor layer changes, the threshold changes. Therefore, in the first reference example, the stability of the threshold value is insufficient.

  On the other hand, in the present embodiment, the length 35d (thickness) of the plurality of nitride portions 35 is equal to or smaller than the maximum value 35L of the size of the nitride molecule 35M. The plurality of nitride parts 35 are dispersed in the state of a single molecule of the nitride molecule 35M. The distance between the nitride portion 35 and the semiconductor layer 20 is substantially constant. Therefore, the fluctuation of the threshold value is small.

  On the other hand, there is a second reference example in which metal particles are provided in the memory film MF (between the silicon oxide film and the silicon nitride film or in the silicon nitride film). In the second reference example, the charge trapping property is low. Further, in the second reference example, uncontrolled bonding is likely to be formed due to incomplete oxidation of the metal. Therefore, for example, it is difficult to control the position of the trap site based on the metal particles. For example, multiple trap sites are too easily accessible. Therefore, the data retention characteristic deteriorates.

  On the other hand, in the embodiment, the plurality of nitride parts 35 of the nitride molecule 35M are provided. When the nitride molecules 35M are BN, AlN, GaN and InN, for example, traps having different trapping cross sections are formed. Thereby, the capture efficiency can be improved. Since the nitride molecule 35M is used, uncontrolled formation of metal oxide or the like is suppressed. A plurality of nitride parts 35 (nitride molecules 35M) are dispersedly arranged along the surface (in this example, the interface F1 between the first layer 31 and the second layer 32) (two-dimensionally). To be done. The plurality of nitride portions 35 form discrete traps at desired positions in the film thickness direction (first direction). Good data retention characteristics can be obtained.

In the embodiment, the density (area density) of the plurality of nitride portions 35 is, for example, 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less. This density is the density (area density) in the plane intersecting the first direction (direction from the semiconductor layer 20 toward the first electrode 41). The surface intersecting the first direction is, for example, a surface perpendicular to the first direction.

For example, when the distance between the two nitride molecules 35M is less than 3 nm, the trapped charges are likely to move to the proximity trap by direct tunneling. The distance between the two nitride molecules 35M is preferably 3 nm or more. As a result, direct tunneling can be suppressed and charge hopping can be suppressed. For example, it is assumed that the plurality of nitride molecules 35M are closest packed (corresponding to 1.156 times) as a circle having a diameter of 3 nm. Further, it is assumed that one nitride molecule 35M is arranged at eight vertices of the cube. In this case, the number of nitride molecules 35M provided in the area of 1 cm × 1 cm is 1 cm × 1 cm × 1, 156 × 8 / (3 nm × 3 nm), which is about 1.03 × 10 ¹⁵ cm ^−2. ..

By setting the density of the plurality of nitride portions 35 to 1 × 10 ¹⁵ cm ⁻² or less, for example, direct tunnels can be suppressed and good retention characteristics can be obtained. By setting the density of the plurality of nitride portions 35 to 1 × 10 ¹³ cm ⁻² or more, for example, the width of the threshold voltage that can be obtained by providing the nitride portions 35 is effectively expanded.

  In the nonvolatile semiconductor memory device 111, the nitride molecules 35M of the plurality of nitride portions 35 may include at least one of TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN, and WN. The first element 35p (first atom) is, for example, titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum ( It may be one of Mo) and tungsten (W).

  For example, the work function of Ti is 4.1 eV and the work function of TiN is 4.6 eV. The charge trapping property of metal particles is lower than the charge trapping property of nitrides. Therefore, in the second reference example using the metal particles, for example, the data retention characteristic is insufficient.

  On the other hand, in the embodiment, when the plurality of nitride portions 35 are molecules such as TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN and WN, a high charge trapping property is obtained. The length 35d (thickness) of the plurality of nitride portions 35 in the first direction is equal to or smaller than the maximum value 35L of the size of the nitride molecule 35M, and the plurality of nitride portions 35 include the nitride molecule 35M. Are dispersed in a single molecule state. Thereby, in the embodiment, for example, good data retention characteristics can be obtained.

  Since nitride has a large work function, deep level traps are formed. This makes it difficult for the trapped charges to escape. As a result, for example, the data retention characteristic is improved. Further, it is difficult for the charge to escape, which means that the trapped charge is difficult to escape even during writing. This seems to improve the writing efficiency. For example, since a high electric field is applied during writing, when the trap level is shallow, charges trapped during the writing time escape due to this high electric field. On the other hand, when the trap level is deep, this is suppressed. Therefore, it seems that the writing efficiency is improved.

  As described above, in the embodiment, in the plurality of nitride portions 35 of the memory film MF, stable bonds are formed between the first element 35p and the nitrogen atoms 35q. By using the nitride molecule 35M, for example, the work function increases and a deep level can be obtained. By using the plurality of nitride portions 35, the amount of trapped charges can be increased. A plurality of nitride portions 35 of the nitride molecule 35M are arranged along a plane intersecting the film thickness direction. Thereby, a stable threshold value can be obtained. The allowable range of write voltage and erase voltage can be expanded.

  For example, stable operation can be obtained even if the size of the memory cell is reduced. As a result, for example, the storage density can be improved.

By setting the areal density of the plurality of nitride portions 35 to, for example, 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less, diffusion of charges in the lateral direction (direction intersecting the first direction) is performed. Can be suppressed. As a result, good retention can be obtained.

  In the nonvolatile semiconductor memory device 111, particles 36 of the first element of the first element 35p contained in the nitride molecule 35M may be further provided (see FIG. 1A). The particles 36 of the first element are provided together with the plurality of nitride parts 35. In the example of FIG. 1A, the particles 36 of the first element are provided between the first layer 31 and the second layer 32.

  In this case, the average nitrogen concentration in the region including the plurality of nitride parts 35 and the particles 36 of the first element is lower than the stoichiometric nitrogen concentration of the nitride molecules 35M. Thus, nitrogen may be deficient in this region from the stoichiometric ratio. Thereby, for example, a defect level is formed in the band gap in this region. For example, in the case of aluminum nitride, a defect level is formed near the center of the band gap. This defect level is near 2.9 eV from the conduction band edge Bc and is deep. At the trap site formed by this, the charge is very hard to move. Thereby, the data retention characteristic can be improved. Furthermore, the range of possible threshold voltages can be expanded.

  As shown in FIG. 1A, in the nonvolatile semiconductor memory device 111, the second electrode 42 and the interlayer insulating film 45i are provided. As described above, the nonvolatile semiconductor memory device 111 may include the plurality of electrodes 40. The first electrode 41 and the second electrode 42 are included in the plurality of electrodes 40. The second electrode 42 is arranged with the first electrode 41 in the second direction (for example, the Z-axis direction) that intersects the first direction (the X-axis direction). An interlayer insulating film 45i is provided between the plurality of electrodes 40.

  The first layer 31 is further provided between the second electrode 42 and the semiconductor layer 20. The second layer 32 is further provided between the second electrode 42 and the first layer 31. The third layer 33 is further provided between the second electrode 42 and the second layer 32.

  The semiconductor layer 20, the second electrode 42, and the memory film MF correspond to another one memory cell (second memory cell). Also in the second memory cell, the fluctuation of the threshold value is small and the range of possible threshold voltage can be expanded. For example, the distance between the first electrode 41 and the second electrode 42 can be shortened. The memory density can be improved.

  In the embodiment, the thickness t1 (the length along the first direction, see FIG. 1A) of the first layer 31 is, for example, 2 nm or more and 8 nm or less. The thickness t2 (the length along the first direction, see FIG. 1A) of the second layer 32 is, for example, 2 nanometers or more and 8 nanometers or less. The thickness t3 (the length along the first direction, see FIG. 1A) of the third layer 33 is, for example, 3 nm or more and 10 nm or less.

(Second embodiment)
2A to 2C are schematic views illustrating the nonvolatile semiconductor memory device according to the second embodiment.
FIG. 2A is a sectional view. FIG. 2B is an energy band diagram. FIG. 2C is a schematic diagram showing molecules included in the nonvolatile semiconductor memory device.

  As shown in FIG. 2A, also in the nonvolatile semiconductor memory device 112 according to this embodiment, the semiconductor layer 20, the first electrode 41, the first to third layers 31 to 33, and the plurality of nitride parts. 35 are provided. The semiconductor layer 20, the first electrode 41, and the first to third layers 31 to 33 are the same as those in the nonvolatile semiconductor memory device 111, so the description thereof will be omitted.

  Hereinafter, the plurality of nitride parts 35 in the nonvolatile semiconductor memory device 112 will be described.

  In the nonvolatile semiconductor memory device 112, the plurality of nitride portions 35 of the nitride molecule 35M are provided between the second layer 32 and the third layer 33. The plurality of nitride portions 35 are provided along the interface F2 between the second layer 32 and the third layer 33. Also in this example, the length 35d (thickness) of the plurality of nitride parts 35 in the first direction (direction from the semiconductor layer 20 toward the first electrode 41) is the maximum value 35L of the size of the nitride molecule 35M. (See FIG. 2C) Below. For example, the plurality of nitride parts 35 are dispersed in a single molecule state of the nitride molecule 35M.

  For example, the plurality of nitride portions 35 are arranged along the first surface 20a of the semiconductor layer 20. For example, the plurality of nitride parts 35 are arranged along the second surface 41 a of the first electrode 41.

  In the nonvolatile semiconductor memory device 112, the nitride molecules 35M (see FIG. 2C) of the plurality of nitride portions 35 are, for example, at least TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN and WN. Including one.

  The first element 35p (first atom) is, for example, titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum ( Mo) and tungsten (W).

  As shown in FIG. 2B, also in the nonvolatile semiconductor memory device 112, the second energy E2 of the conduction band edge Bc of the second layer 32 is larger than the first energy E1 of the conduction band edge Bc of the first layer 31. Is also lower than the third energy E3 of the conduction band edge Bc of the third layer 33. For example, the first layer 31 includes silicon oxide. For example, the second layer 32 includes silicon nitride. For example, the third layer 33 includes silicon oxide.

  Due to the application of the electric field, the electric charge reaches the nitride portion 35 from the semiconductor layer 20 through the first layer 31 (for example, the tunnel insulating film) and the second layer 32 (the charge storage film). The nitride part 35 functions as a trap site.

  For example, the nitride portion 35 is titanium nitride. The work function of titanium nitride is 4.5 eV. Titanium nitride forms a deep level near the center of the band gap of the second layer 32 (charge storage film, eg, silicon nitride film). As a result, good data retention characteristics can be obtained. The range of possible threshold voltages can be expanded.

  In the nonvolatile semiconductor memory device 112, the number of trap sites at the interface F2 between the second layer 32 (for example, charge storage film) and the third layer 33 (for example, block insulating film) can be increased. Furthermore, the trapping efficiency at the trap site near the interface F2 can be improved. As a result, the range of possible threshold voltages can be expanded.

  For example, the distance between the nitride portion 35 and the semiconductor layer 20 is substantially constant. Therefore, the fluctuation of the threshold value is small.

  In this embodiment, for example, stable operation can be obtained even if the size of the memory cell is reduced. As a result, for example, the storage density can be improved.

In the nonvolatile semiconductor memory device 112, the density of the plurality of nitride portions 35 may be 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less. For example, direct tunneling can be suppressed and good retention characteristics can be obtained. By setting the density of the plurality of nitride portions 35 to 1 × 10 ¹³ cm ⁻² or more, for example, the width of the possible threshold voltage is effectively expanded.

  In the nonvolatile semiconductor memory device 112, particles 36 of the first element 35p contained in the nitride molecule 35M may be further provided (see FIG. 2A). In this example, the particles 36 of the first element 35p are provided between the second layer 32 and the third layer 33. Thereby, the data retention characteristic can be improved. Furthermore, the range of possible threshold voltages can be expanded.

(Third Embodiment)
3A and 3B are schematic views illustrating the nonvolatile semiconductor memory device according to the third embodiment.
FIG. 3A is a sectional view. FIG. 3B is an energy band diagram.

  As shown in FIG. 3A, also in the nonvolatile semiconductor memory device 113 according to this embodiment, the semiconductor layer 20, the first electrode 41, the first to third layers 31 to 33, and the plurality of nitrides. A section 35 is provided. The semiconductor layer 20, the first electrode 41, the first layer 31, and the third layer 33 are the same as those in the nonvolatile semiconductor memory device 111, so the description thereof will be omitted.

  The second layer 32 and the plurality of nitride portions 35 in the nonvolatile semiconductor memory device 113 will be described below.

  In the nonvolatile semiconductor memory device 113, the plurality of nitride parts 35 of the nitride molecule 35M are provided in the second layer 32.

  As shown in FIG. 3A, the second layer 32 includes a first region 32a and a second region 32b. The first region 32a is provided between the first layer 31 and the second region 32b. The first region 32a is a region on the first layer 31 side. The second region 32b is a region on the third layer 33 side.

  The plurality of nitride parts 35 are provided between the first region 32a and the second region 32b.

  Also in this example, the length 35d (thickness) of the plurality of nitride parts 35 in the first direction (direction from the semiconductor layer 20 toward the first electrode 41) is the maximum value 35L of the size of the nitride molecule 35M. (Similar to FIG. 2C) and below. For example, the plurality of nitride parts 35 are dispersed in a single molecule state of the nitride molecule 35M.

  For example, the plurality of nitride portions 35 are arranged along the first surface 20a of the semiconductor layer 20. For example, the plurality of nitride parts 35 are arranged along the second surface 41 a of the first electrode 41.

  In the nonvolatile semiconductor memory device 113, the nitride molecules 35M (similar to FIG. 2C) of the plurality of nitride portions 35 are, for example, TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN and WN. At least one of The first element 35p (first atom) is, for example, titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum ( Mo) and tungsten (W).

  As shown in FIG. 3B, also in the nonvolatile semiconductor memory device 113, the second energy E2 of the conduction band edge Bc of the second layer 32 is larger than the first energy E1 of the conduction band edge Bc of the first layer 31. Is also lower than the third energy E3 of the conduction band edge Bc of the third layer 33. For example, the first layer 31 includes silicon oxide. For example, the second layer 32 includes silicon nitride. For example, the third layer 33 includes silicon oxide.

  Due to the application of the electric field, the charges pass from the semiconductor layer 20, the first layer 31 (for example, the tunnel insulating film), the first region 32a of the second layer 32, and reach the plurality of nitride portions 35. The plurality of nitride parts 35 serve as trap sites. For example, the nitride portion 35 is a molecule of tungsten nitride. The work function of tungsten nitride is 4.6 eV. Tungsten nitride can form a deep level near the center of the bandgap of the second layer 32 (eg, silicon nitride). As a result, good data retention characteristics can be obtained. Furthermore, the range of possible threshold voltages can be expanded.

  For example, discrete trap sites are formed in the first region 32a and the second region 32b of the second layer 32. The trapping efficiency of the trap site can be improved. As a result, the range of possible threshold voltages can be expanded.

  For example, the distance between the nitride portion 35 and the semiconductor layer 20 is substantially constant. Therefore, the fluctuation of the threshold value is small.

  In this embodiment, for example, stable operation can be obtained even if the size of the memory cell is reduced. As a result, for example, the storage density can be improved.

In the nonvolatile semiconductor memory device 113, the density of the plurality of nitride portions 35 may be 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less. For example, direct tunneling can be suppressed and good retention characteristics can be obtained. By setting the density of the plurality of nitride portions 35 to 1 × 10 ¹³ cm ⁻² or more, for example, the width of the possible threshold voltage is effectively expanded.

  In the second layer 32 of the nonvolatile semiconductor memory device 113, the thickness t2a of the first region 32a may be substantially the same as the thickness t2b of the second region 32b. For example, the thickness t2a of the first region 32a is 0.5 times or more and 1.5 times or less the thickness t2b of the second region 32b.

  In the nonvolatile semiconductor memory device 113, particles 36 of the first element 35p contained in the nitride molecule 35M may be further provided (see FIG. 3A). In this example, the particles 36 of the first element are provided between the first region 32a and the second region 32b. Thereby, the data retention characteristic can be improved. Furthermore, the range of possible threshold voltages can be expanded.

  In the nonvolatile semiconductor memory devices 112 and 113, the nitride molecules of the plurality of nitride portions 35 may include at least one of BN, AlN, GaN, and InN. The nitride molecule 35M includes a first element 35p (first atom) and a nitrogen atom 35q (see, for example, FIG. 2C). The first element 35p may be any of boron (B), aluminum (Al), gallium (Ga), and indium (In). Also in this case, stable operation can be obtained even if the size of the memory cell is reduced. As a result, for example, the storage density can be improved.

  In the nonvolatile semiconductor memory devices 111 to 113 according to the first to third embodiments described above, information about at least a part of the states of the plurality of nitride portions 35 is, for example, TEM-EELS (Transmission Electron Microscope-electron energy). loss spectroscopy). The information on at least a part of the states of the plurality of nitride portions 35 is obtained by SIMS (Secondary Mass Spectrometry), for example. The information on at least a part of the states of the plurality of nitride portions 35 is obtained, for example, by analysis using a three-dimensional atom probe. As the three-dimensional atom probe, for example, LEAP4000 (CAMECA) can be used.

(Fourth Embodiment)
In the fourth embodiment, the semiconductor layer 20 has a pillar shape.
FIG. 4A and FIG. 4B are schematic cross-sectional views illustrating the nonvolatile semiconductor memory device according to the fourth embodiment.
FIG. 4B is a sectional view taken along the line A1-A2 of FIG.

  As shown in FIG. 4A, in the nonvolatile semiconductor memory device 121 according to this embodiment, the semiconductor layer 20, the first electrode 41, the second electrode 42, the interlayer insulating film 45i, and the first to third layers 31. To 33 and a plurality of nitride parts 35 are provided.

  The second electrode 42 is arranged with the first electrode 41 in the second direction (for example, the Z-axis direction) that intersects the first direction (the direction from the semiconductor layer 20 toward the first electrode 41). An interlayer insulating film 45i is provided between the plurality of electrodes 40. The parts of the nonvolatile semiconductor memory device 121 different from the nonvolatile semiconductor memory device 111 will be described below.

  The first electrode 41, the interlayer insulating film 45i, and the second electrode 42 are included in the stacked body SB. The semiconductor layer 20 extends in the stacked body SB along the second direction (Z-axis direction).

  In this example, the core pillar 20c is provided. The core pillar 20c extends in the Z-axis direction in the stacked body SB. The core pillar 20c is, for example, insulating.

  As shown in FIGS. 4A and 4B, the semiconductor layer 20 is provided around the core pillar 20c. The semiconductor layer 20 has, for example, a tubular shape. A first layer 31 is provided around the semiconductor layer 20. The second layer 32 is provided around the first layer 31. A third layer 33 is provided around the second layer 32. The first to third layers 31 to 33 are tubular. An electrode 40 (a first electrode 41, a second electrode 42, etc.) is provided around the third layer 33.

  In the nonvolatile semiconductor memory device 121, the plurality of nitride parts 35 of the nitride molecule 35M are provided between the first layer 31 and the second layer 32. Also in the nonvolatile semiconductor memory device 121, stable operation can be obtained even if the size of the memory cell is reduced, for example. As a result, for example, the storage density can be improved.

Hereinafter, an example of a method for manufacturing the nonvolatile semiconductor memory device 121 will be described.
The present manufacturing method uses the semiconductor layer 20, the first electrode 41, the first layer 31 provided between the semiconductor layer 20 and the first electrode 41, and the first layer 31 and the first electrode 41. It is a method of manufacturing the nonvolatile semiconductor memory device 121 including the provided second layer 32 and the third layer 33 provided between the second layer 32 and the first electrode 41. As described above, the second energy E2 of the conduction band edge Bc of the second layer 32 is lower than the first energy E1 of the conduction band edge Bc of the first layer 31. The third energy E3 of the conduction band edge Bc of the third layer 33 is higher than the second energy E2. The manufacturing method includes forming the first layer 31, forming the second layer 32, forming the third layer 33, and forming the plurality of nitride portions 35.

5A to 5D are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment.
As shown in FIG. 5A, a conductive layer 40f to be the electrode 40 and an insulating layer 45if to be the interlayer insulating film 45i are alternately laminated on the base 10. The conductive layer 40f is, for example, tungsten. The insulating layer 45if is, for example, silicon oxide. The stacked body SB is formed. The stacking direction corresponds to the Z-axis direction.

  As shown in FIG. 5B, the holes SBh are formed in the stacked body SB. The hole SBh extends in the Z-axis direction.

  As shown in FIG. 5C, the third layer 33 is formed on the side wall of the hole SBh, and the second layer 32 is formed thereon. A plurality of nitride parts 35 are formed on the surface of the second layer 32.

  In the formation of the plurality of nitride parts 35, for example, atomic layer deposition (ALD, using a gas containing the first element 35p (eg, titanium chloride) and a gas containing nitrogen atoms 35q (eg, ammonia). Atomic Layer Deposition) is performed. For example, the number of cycles in ALD, the atmosphere in ALD (for example, the pressure of ammonia gas, etc.), the temperature in ALD, etc. are controlled. As a result, a plurality of nitride parts 35 of the nitride molecule 35M are formed on the surface of the second layer 32. The length 35d of the plurality of nitride portions 35 in the first direction (the direction that intersects the Z-axis direction and corresponds to the direction from the semiconductor layer 20 toward the first electrode 41) is the size of the nitride molecule 35M. Is less than or equal to the maximum value of 35 L.

  As shown in FIG. 5D, the first layer 31 is formed on a part of the surface of the second layer 32 and the plurality of nitride portions 35.

  Further, the semiconductor layer 20 is formed on the surface of the first layer 31, and the remaining space is filled with an insulating material to form the core pillar 20c, whereby the nonvolatile semiconductor memory device 121 can be formed.

  In this example, the second layer 32 is formed after the formation of the third layer 33. Then, after forming the second layer 32, the plurality of nitride portions 35 are formed. Then, after forming the plurality of nitride portions 35, the first layer 31 is formed.

In the present embodiment, the density of the plurality of nitride portions 35 on the surface intersecting the first direction (Z-axis direction) (cylindrical surface between the second layer 32 and the third layer 33) is, for example, It is 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less.

  Hereinafter, another example of the method for manufacturing the nonvolatile semiconductor memory device 121 will be described. In this method, the replace method is used.

6A to 6D are schematic cross-sectional views in order of the processes, illustrating another method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment.
As shown in FIG. 6A, a plurality of first films 61 and a plurality of second films 62 are alternately laminated on the base 10. The first film 61 is, for example, a sacrificial layer. The second film 62 becomes, for example, the interlayer insulating film 45i. The first film 61 is, for example, a silicon nitride film. The second film 62 is, for example, a silicon oxide film. Thereby, the stacked body SB0 is formed.

  Further, a hole is formed in the stacked body SB0, and the third layer 33, the second layer 32, the plurality of nitride portions 35, the first layer 31, the semiconductor layer 20, and the core pillar 20c are sequentially formed in the hole. Thereby, the pillar portion PP including the third layer 33, the second layer 32, the plurality of nitride portions 35, the first layer 31, the semiconductor layer 20, and the core pillar 20c is formed.

As shown in FIG. 6B, the slit ST (may be a hole) is formed in the stacked body SB0.
As shown in FIG. 6C, the first film 61 is removed via the slit ST.
As shown in FIG. 6D, a conductive material is embedded in the space formed by removing the first film 61 to form the electrode 40. The remaining second film 62 becomes the interlayer insulating film 45i.
As a result, the nonvolatile semiconductor memory device 121 is formed.

  As described above, the present manufacturing method includes forming the sacrificial layer (first film 61), removing the sacrificial layer, and forming the first electrode 41 (electrode 40).

  The formation of the third layer 33 includes forming the third layer 33 on the surface of the sacrificial layer (first film 61). After forming the first layer 31, the semiconductor layer 20 is formed. After forming the semiconductor layer 20 (in this example, after forming the core pillar 20c), the sacrifice layer is removed. Forming the first electrode 41 includes forming the first electrode 41 on the surface of the third layer 33 exposed by removing the sacrificial layer. In this way, the nonvolatile semiconductor memory device 121 may be manufactured by the replacement method.

7A and 7B are schematic cross-sectional views illustrating another nonvolatile semiconductor memory device according to the fourth embodiment.
FIG. 7B is a sectional view taken along the line A1-A2 of FIG.

  As shown in FIG. 7A, also in the nonvolatile semiconductor memory device 122 according to this embodiment, the semiconductor layer 20, the first electrode 41, the second electrode 42, the interlayer insulating film 45i, and the first to third layers 31. To 33 and a plurality of nitride parts 35 are provided. The plurality of nitride parts 35 are provided between the second layer 32 and the third layer 33. The rest is the same as the nonvolatile semiconductor memory device 121.

  In the nonvolatile semiconductor memory device 122, the semiconductor layer 20 extends in the stacked body SB along the second direction (Z-axis direction). Other than this, the nonvolatile semiconductor memory device 112 is the same as the nonvolatile semiconductor memory device 112. Also in the nonvolatile semiconductor memory device 122, stable operation can be obtained even if the size of the memory cell is reduced, for example. As a result, for example, the storage density can be improved.

Hereinafter, an example of a method of manufacturing the nonvolatile semiconductor memory device 122 will be described.
FIG. 8A to FIG. 8D are schematic cross-sectional views in order of the processes, illustrating a method for manufacturing another nonvolatile semiconductor memory device according to the fourth embodiment.
As shown in FIGS. 8A and 8B, a laminated body in which a conductive layer 40f to be the electrode 40 and an insulating layer 45if to be the interlayer insulating film 45i are alternately laminated on the substrate 10. SB is formed, and then a hole SBh is formed in the stacked body SB.

  As shown in FIG. 8C, the third layer 33 is formed on the side wall of the hole SBh, and the plurality of nitride portions 35 are formed thereon. In the formation of the plurality of nitride portions 35, the processing described with reference to FIG.

  As shown in FIG. 8D, the second layer 32 is formed on a part of the surface of the third layer 33 and on the plurality of nitride portions 35, and further, on the surface of the second layer 32, a second layer 32 is formed. The first layer 31 is formed.

  Further, by forming the semiconductor layer 20 on the surface of the first layer 31 and further filling the remaining space with an insulating material to form the core pillar 20c, the nonvolatile semiconductor memory device 122 can be formed.

  In this example, the formation of the plurality of nitride portions 35 is performed after the formation of the third layer 33. The formation of the second layer 32 is performed after the formation of the plurality of nitride portions 35. The formation of the first layer 31 is performed after the formation of the second layer 32.

9A to 9D are schematic cross-sectional views in order of the processes, illustrating another method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment.
As shown in FIG. 9A, the stacked body SB0 is formed on the base body 10, and the pillar portion PP is formed on the stacked body SB0. In the pillar part PP, the plurality of nitride parts 35 are provided between the third layer 33 and the second layer 32.

  As shown in FIGS. 9B to 9D, a slit ST (a hole may be used) is formed in the stacked body SB0, the first film 61 is removed through the slit ST, and the first film 61 is removed. A conductive material is embedded in the space thus formed to form the electrode 40. The remaining second film 62 becomes the interlayer insulating film 45i. As a result, the nonvolatile semiconductor memory device 122 is formed.

10A and 10B are schematic cross-sectional views illustrating another nonvolatile semiconductor memory device according to the fourth embodiment.
FIG. 10B is a sectional view taken along the line A1-A2 of FIG.

  As shown in FIG. 10A, also in the nonvolatile semiconductor memory device 123 according to this embodiment, the semiconductor layer 20, the first electrode 41, the second electrode 42, the interlayer insulating film 45i, and the first to third layers 31. To 33 and a plurality of nitride parts 35 are provided. The plurality of nitride portions 35 are provided between the first region 32a and the second region 32b of the second layer 32. The rest is the same as the nonvolatile semiconductor memory device 121.

  In the nonvolatile semiconductor memory device 123, the semiconductor layer 20 extends in the stacked body SB along the second direction (Z-axis direction). The rest is the same as the nonvolatile semiconductor memory device 113. Also in the nonvolatile semiconductor memory device 123, stable operation can be obtained even if the size of the memory cell is reduced, for example. As a result, for example, the storage density can be improved.

Hereinafter, an example of a method for manufacturing the nonvolatile semiconductor memory device 123 will be described.
11A to 11D are schematic cross-sectional views in order of the processes, illustrating a method for manufacturing another nonvolatile semiconductor memory device according to the fourth embodiment.
As shown in FIGS. 11A and 11B, a laminated body in which a conductive layer 40f to be the electrode 40 and an insulating layer 45if to be the interlayer insulating film 45i are alternately laminated on the substrate 10. SB is formed, and then a hole SBh is formed in the stacked body SB.

  As shown in FIG. 11C, the third layer 33 is formed on the side wall of the hole SBh, and a part of the second layer 32 (the second region 32b) is formed thereon. Further, a plurality of nitride parts 35 are formed on the surface thereof. In the formation of the plurality of nitride portions 35, the processing described with reference to FIG.

  As shown in FIG. 11D, another part of the second layer 32 (first region 32a) is formed on part of the surface of the second region 32b and on the plurality of nitride portions 35. Further, the first layer 31 is formed on the surface of the first region 32a.

  Further, by forming the semiconductor layer 20 on the surface of the first layer 31 and further filling the remaining space with an insulating material to form the core pillar 20c, the nonvolatile semiconductor memory device 123 can be formed.

  In this example, a part of the second layer 32 (the second region 32b) is formed after the formation of the third layer 33, and a plurality of nitrides is formed after the formation of the part (the second region 32b) of the second layer 32. The object portion 35 is formed. After forming the plurality of nitride parts 35, another part (first region 32a) of the second layer 32 is formed. The formation of the first layer 31 is performed after the formation of the other part (first region 32a) of the second layer 32 described above.

12A to 12D are schematic cross-sectional views in order of the processes, illustrating another method for manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment.
As shown in FIG. 12A, the stacked body SB0 is formed on the base body 10, and the pillar portion PP is formed on the stacked body SB0. In the pillar portion PP, the plurality of nitride portions 35 are provided between the first region 32a and the second region 32b of the second layer 32.

  As shown in FIGS. 12B to 12D, a slit ST (a hole may be used) is formed in the stacked body SB0, the first film 61 is removed through the slit ST, and the first film 61 is removed. A conductive material is embedded in the space thus formed to form the electrode 40. The remaining second film 62 becomes the interlayer insulating film 45i. As a result, the nonvolatile semiconductor memory device 123 is formed.

  In the manufacturing method described with reference to FIGS. 5A to 5D, 8 </ b> A to 8 </ b> D, and 11 </ b> A to 11 </ b> D, the third layer 33 is formed. The laminated body SB is formed before the formation. That is, the first electrode 41 is formed before the formation of the third layer 33. Then, after forming the first layer 31, the semiconductor layer 20 is formed.

  On the other hand, in the manufacturing method described with reference to FIGS. 6A to 6D, 9 </ b> A to 9 </ b> D, and 12 </ b> A to 12 </ b> D, After the first layer 31 to the third layer 33, the plurality of nitride portions 35, and the semiconductor layer 20 are formed, the electrode 40 (the first electrode 41, the second electrode 42, etc.) is formed.

FIG. 13 is a schematic perspective view illustrating the nonvolatile semiconductor memory device according to the fourth embodiment.
In FIG. 13, at least a part of the insulating portion is omitted in order to make the drawing easy to see.

  A nonvolatile semiconductor memory device 131 shown in FIG. 13 has the configuration of the nonvolatile semiconductor memory devices 121 to 131 described above. In the nonvolatile semiconductor memory device 131, memory cells are three-dimensionally arranged.

  In the nonvolatile semiconductor memory device 131, the back gate BG is provided on the base body 10. The stacked body SB is provided thereon. The stacked body SB includes a plurality of conductive layers WL and a plurality of insulating layers that are alternately provided (not shown, for example, corresponding to the interlayer insulating film 45i). The stacking direction in the stacked body SB corresponds to the Z-axis direction.

  The base 10 is, for example, a semiconductor substrate (silicon substrate or the like). The back gate BG includes, for example, silicon containing impurities. The conductive layer WL includes, for example, a metal (eg, tungsten) or a semiconductor (eg, silicon containing impurities). The conductive layer WL becomes, for example, a word line.

  The nonvolatile semiconductor memory device 131 includes a plurality of memory strings MS. One memory string MS includes a pillar part PP. In this example, one memory string MS includes two pillar parts PP and a connecting part JP. The connection part JP connects the lower ends of the two pillar parts PP. The memory string MS has, for example, a U shape.

  The pillar portion PP has, for example, a columnar shape (a cylindrical shape, a flat cylindrical shape, or the like). The pillar portion PP extends in the Z-axis direction inside the stacked body SB. A drain-side selection gate SGD is provided on one upper end of the pillar portion PP. A source-side selection gate SGS is provided on another upper end of the pillar portion PP. The drain side selection gate SGD and the source side selection gate SGS are, for example, upper selection gates. The drain-side selection gate SGD and the source-side selection gate SGS are provided, for example, on the uppermost conductive layer WL via an insulating layer. The drain-side selection gate SGD and the source-side selection gate SGS include, for example, silicon containing impurities. An insulating separation film (not shown) is provided between the drain side selection gate SGD and the source side selection gate SGS. These gates extend along the Y-axis direction.

  The stacked body SB below the drain side select gate SGD and the stacked body SB below the source side select gate SGS are also separated by the insulating separation film. The stacked body SB extends in the Y-axis direction.

  A source line SL (for example, a metal film) is provided on the source-side selection gate SGS via an insulating layer. A plurality of bit lines BL (for example, a metal film) are provided on the drain-side selection gate SGD and the source line SL via an insulating layer. Each of the plurality of bit lines BL extends in the X-axis direction.

  The plurality of conductive layers WL correspond to the plurality of electrodes 40. Each of the plurality of conductive layers WL corresponds to each of the plurality of memory cells.

  The drain side select transistor STD is provided at one upper end of the pillar part PP. The source-side selection transistor STS is provided at another upper end of the pillar portion PP. The memory cell, the drain-side selection transistor STD, and the source-side selection transistor STS are vertical transistors. In these transistors, current flows along the Z-axis direction.

  The drain side selection gate SGD functions as a gate electrode (control gate) of the drain side selection transistor STD. An insulating film (not shown) is provided between the drain side select gate SGD and the semiconductor layer 20. This insulating film functions as a gate insulating film of the drain side select transistor STD. The channel body (semiconductor layer 20) of the drain side select transistor STD is connected to the bit line BL above the drain side select gate SGD.

  The source side selection gate SGS functions as a gate electrode (control gate) of the source side selection transistor STS. An insulating film (not shown) is provided between the source side selection gate SGS and the semiconductor layer 20. This insulating film functions as a gate insulating film of the source side select transistor STS. The channel body (semiconductor layer 20) of the source side selection transistor STS is connected to the source line SL above the source side selection gate SGS.

  The back gate transistor BGT is provided in the connection part JP of the memory string MS. The back gate BG functions as a gate electrode (control gate) of the back gate transistor BGT.

  The memory film MF provided in the pillar part PP may be provided also in the back gate BG. This memory film MF functions as a gate insulating film of the back gate transistor BGT.

  A plurality of memory cells are provided between the drain side select transistor STD and the back gate transistor BGT. A plurality of memory cells are also provided between the back gate transistor BGT and the source side select transistor STS. Each of the plurality of memory cells uses each of the plurality of conductive layers WL as a control gate.

  The plurality of memory cells, the drain side selection transistor STD, the back gate transistor BGT and the source side selection transistor STS are connected in series through the semiconductor layer 20. As a result, one U-shaped memory string MS is formed. The plurality of memory strings MS are arranged in the X-axis direction and the Y-axis direction. A plurality of memory cells are three-dimensionally provided in the X-axis direction, the Y-axis direction, and the Z-axis direction.

  In the embodiment, the two pillar portions PP may not be connected. The lower end of one pillar part PP may be connected to the source line SL, for example, and the upper end may be connected to the bit line BL, for example.

(Fifth Embodiment)
In the fifth embodiment, the semiconductor layer 20 has a substrate shape.
14A to 14C are schematic cross-sectional views illustrating the nonvolatile semiconductor memory device according to the fourth embodiment.
As shown in FIGS. 14A to 14C, the nonvolatile semiconductor memory devices 151 to 153 according to the present embodiment include a semiconductor layer 20, a first electrode 41, a first layer 31, and a second layer. The layer 32, the third layer 33, and the plurality of nitride portions 35 are included.

  As the semiconductor layer 20, for example, a semiconductor substrate (for example, a silicon substrate) is used. The semiconductor layer 20 may have, for example, an SOI structure. Other than this, it is the same as the nonvolatile semiconductor memory devices 111 to 113.

The nonvolatile semiconductor memory devices 151 to 153 are manufactured as follows, for example.
The first layer 31 is formed on the semiconductor layer 20. After forming the first layer 31, the second layer 32 is formed. After forming the second layer 32, the third layer 32 is formed. After forming the third layer 33, the first electrode 41 (and the second electrode 42 and the like) are formed.

  A plurality of nitride portions 35 is formed between the formation of the first layer 31 and the formation of the third layer 33.

  For example, the formation of the plurality of nitride portions 35 is performed between the formation of the first layer 31 and the formation of the second layer 32. As a result, the nonvolatile semiconductor memory device 151 is formed. For example, the formation of the plurality of nitride portions 35 is performed between the formation of the second layer 32 and the formation of the third layer 33. As a result, the nonvolatile semiconductor memory device 152 is formed. For example, the formation of the plurality of nitride portions 35 is performed between the formation of a part of the second layer 32 (the first region 32a) and the formation of another part of the second layer 32 (the second region 32b). . As a result, the nonvolatile semiconductor memory device 153 is formed.

  For example, a three-dimensional memory has been developed as a flash memory of a nonvolatile semiconductor memory device. In the three-dimensional memory, for example, MONOS memory cells are provided. In the MONOS memory cell, charges are accumulated in discrete defects in the charge accumulation film. If the density of defects is high, a large amount of charges can be stored, and the range of possible threshold voltage is expanded. On the other hand, when the density of defects is high and the distance between the defects is short, electric charges easily move between the defects and the data retention characteristic is deteriorated. When the memory cell is miniaturized, the thickness of the charge storage film is reduced. When the thickness is reduced, the amount of accumulated charge is reduced. Therefore, the allowable range of the write voltage and the erase voltage is reduced.

  In the embodiment, the plurality of nitride portions 35 of the nitride molecule 35M are provided in the memory film MF. The plurality of nitride parts 35 are arranged discretely. The length 35d (size) of the plurality of nitride portions 35 is equal to or smaller than the maximum value 35L of the size of the nitride molecule 35M. As a result, the amount of accumulated charge is increased. Makes it difficult for the accumulated charge to escape. As a result, the allowable range of write voltage and erase voltage is expanded. Good data retention characteristics can be obtained. As a result, proper operation is performed even if the size of the memory cell is reduced.

  According to the embodiment, it is possible to provide a nonvolatile semiconductor memory device capable of improving the memory density and a method for manufacturing the same.

  In the specification of the application, “vertical” and “parallel” include not only strict vertical and strict parallel but also variations in a manufacturing process, and may be substantially vertical and substantially parallel. is good.

  The embodiments of the present invention have been described above with reference to specific examples. However, the embodiments of the present invention are not limited to these specific examples. For example, regarding a specific configuration of each element such as a semiconductor layer, an electrode, first to third layers, and a nitride portion included in a nonvolatile semiconductor memory device, a person skilled in the art can appropriately select from a known range. The present invention is included in the scope of the present invention as long as the same effects can be obtained.

  Further, a combination of any two or more elements of the respective specific examples within a technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, based on the nonvolatile semiconductor memory device and the manufacturing method thereof described above as the embodiments of the present invention, all nonvolatile semiconductor memory devices and manufacturing methods thereof that can be appropriately modified and implemented by those skilled in the art As long as it includes the gist of the invention, it belongs to the scope of the present invention.

  In addition, within the scope of the idea of the present invention, those skilled in the art can think of various modified examples and modified examples, and it is understood that these modified examples and modified examples also belong to the scope of the present invention. ..

  Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.

  10 ... Base | substrate, 20 ... Semiconductor layer, 20a ... 1st surface, 20c ... Core pillar, 31 ... 1st layer, 32 ... 2nd layer, 32a ... 1st area | region, 32b ... 2nd area, 33 ... 3rd layer, 35 ... Nitride part, 35L ... Maximum value, 35M ... Nitride molecule, 35d ... Length, 35p ... First element, 35q ... Nitrogen atom, 36 ... Particle, 40 ... Electrode, 40f ... Conductive layer, 41 ... First electrode , 41a ... Second surface, 42 ... Second electrode, 45i ... Interlayer insulating film, 45if ... Insulating layer, 61 ... First film, 62 ... Second film, 111-113, 121-123, 131, 151-153 ... Nonvolatile semiconductor memory device, BG ... Back gate, BGT ... Back gate transistor, BL ... Bit line, Bc ... Conduction band edge, Bv ... Valence band edge, E1 to E3 ... First to third energy, F1, F 2 ... Interface, JP ... Connection part, MF ... Memory film, MS ... Memory string, PP ... Pillar part, SB ... Laminated body, SB0 ... Laminated body, SBh ... Hole, SGD ... Drain side selection gate, SGS ... Source side selection Gate, SL ... Source line, ST ... Slit, STD ... Drain side selection transistor, STS ... Source side selection transistor, WL ... Conductive layer, t1, t2, t2a, t2b, t3 ... Thickness

Claims (6)

A semiconductor layer,
A first electrode,
A tunnel insulating layer provided between the semiconductor layer and the first electrode,
In the charge storage layer provided between the tunnel insulating layer and the first electrode, the second energy at the conduction band edge of the charge storage layer is higher than the first energy at the conduction band edge of the tunnel insulating layer. And the charge storage layer includes a first region and a second region, the first region being provided between the tunnel insulating layer and the second region, and
A block insulating layer provided between the charge storage layer and the first electrode, wherein the third energy at the conduction band edge of the block insulating layer is higher than the second energy; ,
Nitride molecules provided either between the first region and the second region, between the tunnel insulating layer and the charge storage layer, and between the charge storage layer and the block insulating layer. A plurality of nitride portions including
Equipped with
The nitride molecule includes at least one of TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN, WN, BN, AlN, GaN and InN,
The length of the plurality of nitride portions in the first direction from the semiconductor layer to the first electrode is equal to or less than the maximum value of the size of the nitride molecule,
The nonvolatile semiconductor memory device, wherein the plurality of nitride portions are arranged along a first surface of the semiconductor layer facing the tunnel insulating layer. A semiconductor layer,
A first electrode,
A tunnel insulating layer provided between the semiconductor layer and the first electrode,
In the charge storage layer provided between the tunnel insulating layer and the first electrode, the second energy at the conduction band edge of the charge storage layer is higher than the first energy at the conduction band edge of the tunnel insulating layer. And the charge storage layer includes a first region and a second region, the first region being provided between the tunnel insulating layer and the second region, and
A block insulating layer provided between the charge storage layer and the first electrode, wherein the third energy at the conduction band edge of the block insulating layer is higher than the second energy; ,
A plurality of nitride molecules are provided between the first region and the second region, between the tunnel insulating layer and the charge storage layer, and between the charge storage layer and the block insulating layer. A nitride part,
Equipped with
The nitride molecule includes at least one of TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN, WN, BN, AlN, GaN and InN,
The length of the plurality of nitride portions in the first direction from the semiconductor layer to the first electrode is equal to or less than the maximum value of the size of the nitride molecule,
The nonvolatile semiconductor memory device, wherein the plurality of nitride portions are arranged along a second surface of the first electrode facing the block insulating layer. The nitride molecule contains a first element of any one of Groups 4, 5, 6, and 13 and nitrogen.
The non-volatile semiconductor according to claim 1 or 2, wherein a density of the plurality of nitride portions on a surface intersecting the first direction is 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less. Storage device. A semiconductor layer,
A first electrode,
A tunnel insulating layer provided between the semiconductor layer and the first electrode,
In the charge storage layer provided between the tunnel insulating layer and the first electrode, the second energy at the conduction band edge of the charge storage layer is higher than the first energy at the conduction band edge of the tunnel insulating layer. And the charge storage layer includes a first region and a second region, the first region being provided between the tunnel insulating layer and the second region, and
A block insulating layer provided between the charge storage layer and the first electrode, wherein the third energy at the conduction band edge of the block insulating layer is higher than the second energy; ,
Nitride molecules provided either between the first region and the second region, between the tunnel insulating layer and the charge storage layer, and between the charge storage layer and the block insulating layer. A plurality of nitride portions including
Equipped with
The nitride molecule includes at least one of TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN, WN, BN, AlN, GaN and InN,
The length of the plurality of nitride portions in the first direction from the semiconductor layer to the first electrode is equal to or less than the maximum value of the size of the nitride molecule,
The nonvolatile semiconductor memory device, wherein the plurality of nitride portions further include particles of the first element. The density of the plurality of nitride portions in a plane perpendicular to the first direction is 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less, any of claims 1, 2 and 4. 2. The non-volatile semiconductor memory device according to any one of the above. The nitride molecule includes the first element of any one of Groups 4, 5, 6, and 13 and nitrogen.
The nonvolatile semiconductor memory device according to claim 4, wherein a density of the plurality of nitride portions on a surface intersecting with the first direction is 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less.

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