JP2020072468A - Power amplifier module - Google Patents

Abstract

To provide a power amplifier module that can reduce current consumption in a region where a power supply voltage is low compared to other regions.SOLUTION: A power amplifier module includes a first amplifier that amplifies a first signal, a second amplifier that amplifies a second signal based on an output signal of the first amplifier, a first bias circuit that supplies a bias current to the first amplifier through a current path on the basis of a bias drive signal, and an adjustment circuit, and the adjustment circuit includes an adjustment transistor including a first terminal to which a first voltage based on a power supply voltage is supplied, a second terminal to which a second voltage based on the bias drive signal is supplied, and a third terminal connected to the current path, and adjusts the bias current on the basis of the power supply voltage supplied to the first amplifier.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to power amplification modules.

  A mobile communication terminal such as a mobile phone uses a power amplification module that amplifies an RF (Radio Frequency) signal transmitted to a base station. Such power amplification modules may operate according to different power modes depending on the required power level of the RF signal. For example, Patent Document 1 listed below discloses a power amplification module that operates according to a low power mode that operates at a relatively low power level or a high power mode that operates at a relatively high power level. In this power amplification module, an amplifier that turns on in any power mode and an amplifier that turns off in the low power mode and turns on in the high power mode are connected in parallel and operate according to the power mode. By changing the number of unit transistors, power amplification suitable for each power mode is performed.

JP, 2017-112588, A

  In recent years, there is an increasing demand for reducing current consumption, especially in the low power mode, and it is necessary to reduce the amount of current flowing through the unit transistor when the power supply voltage is relatively low. However, as described in Patent Document 1, the current consumption cannot be sufficiently reduced only by adjusting the number of operating unit transistors.

  Therefore, an object of the present disclosure is to propose a power amplification module that can reduce current consumption in a region where the power supply voltage is low as compared with other regions.

  In order to solve the above problems, a power amplification module according to the present disclosure includes a first amplifier that amplifies a first signal, a second amplifier that amplifies a second signal based on an output signal of the first amplifier, and a bias drive. A first bias circuit that supplies a bias current to the first amplifier through a current path based on a signal; and an adjusting circuit, the adjusting circuit having a first terminal to which a first voltage based on a power supply voltage is supplied, An adjustment transistor having a second terminal to which a second voltage based on the bias drive signal is supplied and a third terminal connected to the current path is included, and the bias current is adjusted based on the power supply voltage supplied to the first amplifier. To do.

  According to the present disclosure, it is possible to provide a power amplification module that can reduce current consumption in a region where the power supply voltage is low compared to other regions.

It is a figure showing an outline of composition of a power amplification module concerning a 1st embodiment of this indication. It is a figure which shows the structural example of the power amplification module which concerns on 1st Embodiment of this indication. 6 is a graph showing a relationship between a collector-emitter voltage Vce of a transistor 61 and a power supply voltage Vcc1. 7 is a graph showing the relationship between current Isub_b and power supply voltage Vcc1. 7 is a graph showing the relationship between current Isub_c and power supply voltage Vcc1. 6 is a graph showing the relationship between current Isub and power supply voltage Vcc1. It is a graph showing the relationship between current Ief_pwr and power supply voltage Vcc1. 6 is a graph showing the relationship between current Icc and power supply voltage Vcc1. It is a graph which shows the comparison result of electric current Icc in power amplification module 10A and the power amplification module which concerns on a comparative example. It is a graph which shows the comparison result of the gain in power amplification module 10A and the power amplification module which concerns on a comparative example. It is a figure which shows the structural example of the power amplification module which concerns on 2nd Embodiment of this indication.

  Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Here, the circuit elements having the same reference numerals indicate the same circuit elements, and the duplicate description will be omitted.

  FIG. 1 is a diagram showing an outline of a configuration of a power amplification module according to the first embodiment of the present disclosure. The power amplification module 10 is mounted in, for example, a mobile communication device such as a mobile phone, amplifies the power of the input signal RFin to a level required to transmit it to the base station, and outputs it as an amplified signal RFout. The input signal RFin is, for example, a radio frequency (RF: Radio Frequency) signal modulated according to a predetermined communication method by an RFIC (Radio Frequency Integrated Circuit) or the like. The communication standard of the input signal RFin is, for example, 2G (2nd generation mobile communication system), 3G (3rd generation mobile communication system), 4G (4th generation mobile communication system), 5G (5th generation mobile communication system), LTE. (Long Term Evolution) -FDD (Frequency Division Duplex), LTE-TDD (Time Division Duplex), LTE-Advanced, LTE-Advanced Pro, and the like are included, and the frequency is, for example, several hundred MHz to several tens GHz. The communication standard and frequency of the input signal RFin are not limited to these.

  The power amplification module 10 includes, for example, amplifiers 20 and 30, bias circuits 40 and 50, an adjustment circuit 60, and matching circuits 70, 80 and 90.

  The amplifier 20 (first amplifier) and the amplifier 30 (second amplifier) respectively amplify and output the input RF signal. The amplifier 20 of the first stage (driver stage) is supplied with the power supply voltage Vcc1 from the power supply terminal T1 and amplifies the input signal RFin (first signal) input from the input terminal via the matching circuit 70 to generate the RF signal RF1. Is output. The amplifier 30 in the latter stage (power stage) is supplied with the power supply voltage Vcc2 from the power supply terminal T2, amplifies the RF signal RF1 (second signal) supplied from the amplifier 20 via the matching circuit 80, and outputs the RF signal RF2. Is output. The RF signal RF2 is output as an amplified signal RFout via the matching circuit 90. Each of the amplifiers 20 and 30 is formed of a transistor such as a heterojunction bipolar transistor (HBT). The amplifiers 20 and 30 may be configured by field effect transistors such as MOSFET (Metal-oxide-semiconductor Field-Effect Transistor) instead of the HBT. In this case, the collector, base, and emitter described below may be read as drain, gate, and source, respectively. In the following, unless otherwise specified, the case where the transistor is formed of an HBT will be described as an example.

  The bias circuits 40 and 50 are supplied with a bias drive signal from the control terminal T3, and supply a bias current or a bias voltage to the amplifiers 20 and 30, respectively.

  The adjustment circuit 60 adjusts the amount of bias current supplied from the bias circuit 40 to the first-stage amplifier 20. Details of the configurations of the amplifier 20, the bias circuit 40, and the adjustment circuit 60 will be described later.

  A matching circuit (MN: Matching Network) 70 matches the impedance of a circuit (not shown) provided in the preceding stage of the power amplification module 10 with the impedance of the amplifier 20. The matching circuit 80 matches the impedance of the amplifier 20 and the impedance of the amplifier 30. The matching circuit 90 matches the impedance of the amplifier 30 with the impedance of a circuit (not shown) provided in the subsequent stage of the power amplification module 10. The matching circuits 70, 80, 90 are each configured to include, for example, an inductor and a capacitor.

  In the present specification, the configuration in which the power amplification module 10 includes the two-stage amplifiers 20 and 30 will be described as an example, but the number of amplifier stages included in the power amplification module 10 is not limited to this and may be three or more. Good.

  FIG. 2 is a diagram illustrating a configuration example of the power amplification module according to the first embodiment of the present disclosure. The power amplification module 10A shown in FIG. 2 shows the configurations of the amplifiers 20 and 30, the bias circuits 40 and 50, the adjustment circuit 60, and the matching circuit 80 in the power amplification module 10 shown in FIG. 1 in detail. However, the illustration of other components is omitted.

  The amplifiers 20A and 30A have transistors Q1 and Q2, respectively. The transistor Q1 has the collector supplied with the power supply voltage Vcc1 from the power supply terminal T1, the base supplied with the input signal RFin via the capacitor C1, and the emitter grounded. As a result, the RF signal RF1 obtained by amplifying the input signal RFin is output from the collector of the transistor Q1. The transistor Q2 has a collector supplied with the power supply voltage Vcc2 from the power supply terminal T2, a base supplied with the RF signal RF1 through the matching circuit 80, and an emitter grounded. As a result, the RF signal RF2 obtained by amplifying the RF signal RF1 is output from the collector of the transistor Q2. Each of the transistors Q1 and Q2 includes a plurality of unit transistors connected in parallel, and the plurality of unit transistors operate in the same manner to perform the same function as one transistor. May be. The unit transistor means a minimum structure that exhibits the function of a transistor.

  The input signal RFin is supplied to one end of the capacitor C1 and the other end is connected to the base of the transistor Q1. The capacitor C1 has a function of passing an AC component of the RF signal and removing a DC component.

  The bias circuit 40A (first bias circuit) supplies a bias current or a bias voltage that controls the bias point of the transistor Q1 to the base of the transistor Q1 through the resistance element R1. The operation of the bias circuit 40A is controlled based on the bias drive signal supplied from the control terminal T3. Specifically, the bias circuit 40A includes transistors 41 to 43, a resistance element 44, and a capacitor 45.

  The transistors 41 and 42 are diode-connected. By diode connection is meant connecting the base and collector of a bipolar transistor. A diode-connected bipolar transistor behaves as a bipolar element equivalent to a diode. That is, of the two terminals of the diode-connected bipolar transistor, the one with the higher potential functions as the “anode” and the one with the lower potential functions as the “cathode” when forward biased. In the bias circuit 40A, the transistor 41 and the transistor 42 are connected in series. A bias drive signal is supplied to the collector of the transistor 41 from the control terminal T3 through the resistance element 44. The collector of the transistor 42 is connected to the emitter of the transistor 41, and the emitter of the transistor 42 is grounded. As a result, a predetermined voltage (for example, about 2.8V) is generated at the collector of the transistor 41. A PN junction diode may be used instead of the diode-connected transistors 41 and 42.

  The transistor 43 has a collector supplied with the voltage Vbat, a base connected to the collector of the transistor 41, and a capacitor 45 connected to the ground. The emitter of the transistor 43 is connected to the base of the transistor Q1 through the resistance element R1. As a result, the bias current is supplied to the base of the transistor Q1.

  The bias circuit 50A supplies a bias current or a bias voltage for controlling the bias point of the transistor Q2 to the base of the transistor Q2 through the resistance element R2. The operation of the bias circuit 50A is controlled based on the bias drive signal supplied from the control terminal T4. Specifically, the bias circuit 50A includes transistors 51 to 53, a resistance element 54, and a capacitor 55. Since these configurations are similar to those of the bias circuit 40A, detailed description thereof will be omitted.

  The control terminals T3 and T4 may be respectively connected to a voltage source and supplied with a control voltage as a bias driving signal, or may be respectively connected to current sources and supplied with a control current as a bias driving signal.

  The adjustment circuit 60A is a circuit that adjusts the bias current supplied to the base of the transistor Q1. Specifically, the adjustment circuit 60A includes a transistor 61 and resistance elements 62 to 64.

  A first voltage corresponding to the power supply voltage Vcc1 is supplied to the collector (first terminal) of the transistor 61 (adjustment transistor) from the power supply terminal T1 through the resistance element 62 (first resistance element). A second voltage according to the bias drive signal is supplied to the base (second terminal) of the transistor 61 from the control terminal T3 through the resistance element 44 and the resistance element 63 (second resistance element). In the present embodiment, the base of the transistor 61 is connected to the base of the transistor 43. The emitter (third terminal) of the transistor 61 is connected to the base of the transistor Q1 through the resistance element 64 (third resistance element) and the resistance element R1. The emitter of the transistor 61 is connected to the emitter of the transistor 43 through the resistance element 64. In the present embodiment, the transistor 61 is, for example, a heterojunction bipolar transistor in which the emitter and the base form a heterojunction, and the bandgap of the emitter is larger than the bandgap of the base.

  The resistance elements R1 and R2 are provided between the bias circuits 40A and 50A and the bases of the transistors Q1 and Q2, respectively.

  The matching circuit 80A includes capacitors 81 and 82 and an inductor 83. The capacitors 81 and 82 are connected in series with each other. The inductor 83 has one end connected to a connection point between the capacitors 81 and 82 and the other end connected to ground. That is, the matching circuit 80 is composed of a so-called CLC T-type circuit. The configuration of the matching circuit 80 is not limited to this.

  Next, the operation of the power amplification module 10A will be described with reference to FIGS. 3 to 8. Here, as shown in FIG. 2, the currents flowing through the resistance elements 62 to 64 are Isub_c, Isub_b, and Isub. Further, the current output from the emitter of the transistor 43 is Ief_pwr, the bias current supplied to the base of the transistor Q1 is Ibias, and the current flowing in the collector of the transistor Q1 is Icc. The voltage between the collector and the emitter of the transistor 61 is Vce. Since Ibias = Ief_pwr + Isub, the current Ief_pwr and the current Isub each partially contribute to the adjustment of the bias point of the transistor Q1. Therefore, in the present specification, each of the current Ief_pwr and the current Isub may be referred to as a “bias current”. Note that Isub = Isub_b + Isub_c.

  FIG. 3 is a graph showing the relationship between the collector-emitter voltage Vce of the transistor 61 and the power supply voltage Vcc1. Reference numeral 201 represents the collector-emitter voltage of the transistor 61 in the power amplification module 10A according to the present embodiment, and reference numeral 202 represents the collector-emitter voltage of the transistor corresponding to the transistor 61 in the power amplification module according to the comparative example. Show. The power amplification module according to the comparative example has a configuration in which the adjustment circuit 60 is not provided as compared with the power amplification module 10A. The horizontal axis of FIG. 3 represents the power supply voltage Vcc1, and the vertical axis of FIG. 3 represents the voltage Vce.

  FIG. 4 is a graph showing the relationship between the current Isub_b and the power supply voltage Vcc1. Reference numeral 300 indicates the current Isub_b. The horizontal axis of FIG. 4 represents the power supply voltage Vcc1, and the vertical axis of FIG. 4 represents the current Isub_b.

  FIG. 5 is a graph showing the relationship between the current Isub_c and the power supply voltage Vcc1. Reference numeral 400 indicates the current Isub_c. The horizontal axis of FIG. 5 shows the power supply voltage Vcc1, and the vertical axis of FIG. 5 shows the current Isub_c.

  FIG. 6 is a graph showing the relationship between the current Isub and the power supply voltage Vcc1. Reference numeral 500 indicates the current Isub. The horizontal axis of FIG. 6 represents the power supply voltage Vcc1, and the vertical axis of FIG. 6 represents the current Isub.

  FIG. 7 is a graph showing the relationship between the current Ief_pwr and the power supply voltage Vcc1. Reference numeral 601 indicates the current Ief_pwr in the power amplification module 10A according to the present embodiment, and reference numeral 602 indicates the current corresponding to the current Ief_pwr in the power amplification module according to the comparative example. The horizontal axis of FIG. 7 indicates the power supply voltage Vcc1, and the vertical axis of FIG. 7 indicates the current Ief_pwr.

  FIG. 8 is a graph showing the relationship between current Icc and power supply voltage Vcc1. Reference numeral 701 represents the current Icc in the power amplification module 10A according to the present embodiment, and reference numeral 702 represents the current corresponding to the current Icc in the power amplification module according to the comparative example. The horizontal axis of FIG. 8 represents the power supply voltage Vcc1, and the vertical axis of FIG. 8 represents the current Icc.

  The power supply voltage Vcc1 is assumed to fluctuate in a range of, for example, a lower limit voltage or more and an upper limit voltage or less. The lower limit voltage is, for example, about 1.0V, and the upper limit voltage is, for example, about 4.5 to 5.5V.

  A path through which current flows from the bias circuit 40A to the base of the transistor Q1 through the resistance element R1 is referred to as a first current path 100. The emitter of the transistor 43 is connected to the base of the transistor Q1 through the first current path 100. The emitter of the transistor 61 is connected to the first current path 100 via the resistance element 64. A path through which current flows from the control terminal T3 to the power element T1 through the resistance element 44, the resistance element 63, the base / collector of the transistor 61, and the resistance element 62 is referred to as a second current path 101. The base of the transistor 43 is connected to the second current path 101. A path through which a current flows from the power supply terminal T1 to the base of the transistor Q1 through the resistance element 62, the collector / emitter of the transistor 61, the resistance element 64, and the resistance element R1 is defined as a third current path 102.

  Since the transistor 61 is a heterojunction bipolar transistor, the ON voltage of the PN junction between the base and collector (about 1.1V) and the ON voltage of the PN junction between the base and emitter (about 1.3V) are different. Therefore, as shown in FIG. 3, the transistor 61 behaves differently when the power supply voltage Vcc1 is at an intermediate voltage (for example, about 1.5 V) higher than the lower limit voltage and lower than the upper limit voltage. Specifically, in the range where the power supply voltage Vcc1 is higher than the intermediate voltage, the transistor 61 operates as an emitter follower circuit. On the other hand, in the range where the power supply voltage Vcc1 is equal to or lower than the intermediate voltage, the transistor 61 operates as two PN junction diodes.

  When the transistor 61 operates as an emitter follower circuit, the current Ief_pwr flows from the bias circuit 40A to the base of the transistor Q1 through the first current path 100, and the current Isub from the power supply terminal T1 to the base of the transistor Q1 through the third current path 102. Flows. At this time, the current Isub_b is so small that it can be ignored (see FIG. 4), and thus the current Isub is substantially equal to the current Isub_c (see FIGS. 5 and 6).

  On the other hand, when the transistor 61 operates as two PN junction diodes, a current flows from the bias circuit 40A to the power supply terminal T1 through the second current path 101. This is because the on-state voltage of the PN junction between the base and collector of the transistor 61 is lower than the on-state voltage between the base and emitter, so that a current flows predominantly between the base and collector of the transistor 61. At this time, the direction in which the current Isub_c flows is opposite to the direction shown in FIG. The adjustment circuit 60 increases the current Isub_c flowing from the bias circuit 40A to the power supply terminal T1 through the second current path 101 as the power supply voltage Vcc1 is lower (see FIG. 5). As the current Isub_c flowing from the bias circuit 40A to the power supply terminal T1 through the second current path 101 increases, the bias current Ief_pwr flowing from the bias circuit 40A to the base of the transistor Q1 through the first current path 100 decreases.

  That is, as shown in FIG. 7, due to the action of the adjusting circuit 60, the bias current Ief_pwr decreases when the power supply voltage Vcc1 is equal to or lower than the intermediate voltage. Further, when the power supply voltage Vcc1 is near the upper limit voltage, the bias current Ief_pwr in the power amplification module 10A approaches the value of the bias current Ief_pwr in the power amplification module according to the comparative example. Due to the decrease in the bias current Ief_pwr, the current Icc flowing through the collector of the transistor Q1 also decreases (see FIG. 8). As a result, the current Icc flowing through the transistor Q1 when the power supply voltage Vcc1 is in the range of the lower limit voltage or more and the intermediate voltage or less can be reduced.

  As described above, according to the power amplification module 10A of the present embodiment, the bias current Ief_pwr flowing through the base of the transistor Q1 can be reduced when the transistor 61 operates as two PN junction diodes. As a result, the current flowing through the transistor Q1 can be reduced and the gain of the transistor Q1 can be reduced. In particular, by using a heterojunction bipolar transistor as the transistor 61, the transistor 61 can be operated as two PN junction diodes in a region where the power supply voltage Vcc1 is equal to or higher than the lower limit voltage and equal to or lower than the intermediate voltage, and the power supply voltage Vcc1 is relatively high. In the low region, the current consumption in transistor Q1 can be reduced as compared with the region in which power supply voltage Vcc1 is relatively high.

  Further, for example, the power level of the signal output from the transistor Q2 in the subsequent stage is higher than that of the signal output from the transistor Q1 in the initial stage, so that the power supply voltage Vcc2 supplied to the transistor Q2 in the subsequent stage is the same as that of the transistor Q1 in the initial stage. It is considered that it is more susceptible to noise contained in the amplified signal than the power supply voltage Vcc1 supplied to the. In the present embodiment, since the power supply voltage Vcc1 is supplied to the transistor 61 of the adjustment circuit 60, the influence of noise included in the amplified signal is reduced as compared with the configuration in which the power supply voltage Vcc2 is supplied to the transistor 61. can do. It is not intended to exclude the configuration in which the power supply voltage Vcc2 is supplied to the transistor 61.

  In the above-described embodiment, an example in which the bias current supplied from the first-stage bias circuit 40 to the transistor Q1 is adjusted is shown, but instead of or in addition to this, the latter-stage bias circuit 50 is provided. The bias current supplied from Q to Q2 may be adjusted.

  FIG. 9A is a graph showing a comparison result of the current Icc in the power amplification module 10A and the power amplification module according to the comparative example. FIG. 9B is a graph showing gain comparison results in the power amplification module 10A and the power amplification module according to the comparative example. The graphs shown in FIGS. 9A and 9B are simulation results when the output power of the first-stage amplifier is 4 dBm and the power supply voltage Vcc1 is 1.0V.

  As shown in FIGS. 9A and 9B, it can be seen that the current Icc flowing through the transistor Q1 is reduced and the gain is reduced in the power amplification module 10A according to the present embodiment as compared with the comparative example. This is because the power amplification module 10A includes the adjustment circuit 60.

  FIG. 10 is a diagram illustrating a configuration example of the power amplification module according to the second embodiment of the present disclosure. The same elements as those of the above-described first embodiment are designated by the same reference numerals and the description thereof will be omitted. Further, in the second embodiment, description of matters common to the first embodiment will be omitted, and only different points will be described. In particular, similar effects obtained by the same configuration will not be sequentially described for each embodiment.

  The power amplification module 10B according to the present embodiment differs from the power amplification module 10A according to the above-described first embodiment in that it operates according to different operation modes depending on the power level of the output signal. Specifically, the power amplification module 10B operates according to operation modes including a low power mode (first mode) and a high power mode (second mode) in which the power level of the output signal is higher than that of the low power mode. The details of the configuration of the power amplification module 10B will be described below.

  The power amplification module 10B includes amplifiers 20B, 30B, bias circuits 40B, 40C, 50B-50D, adjustment circuits 60B-60D, and matching circuits 70, 80, 90.

  The initial stage amplifier 20B includes two first cells 20a and two second cells 20b. Each of the first cells 20a includes a first unit transistor Q1a corresponding to the transistor Q1, resistance elements R1x and R1y corresponding to the resistance element R1, a capacitor C1a corresponding to the capacitor C1, and a first unit transistor Q1a. And a resistance element R3a connected in series to the base of the. Since the configuration of the second cell 20b is the same as that of the first cell 20a, description thereof will be omitted. The cells are connected in parallel, and by operating in the same manner, they collectively function as one amplifier. Although the number of the first cells 20a and the number of the second cells 20b are both two in the present embodiment, the number of the cells is not particularly limited and the number is not limited.

  Similarly, the amplifier 30B in the subsequent stage includes 14 third cells 30a and 14 fourth cells 30b. The configurations of the third cell 30a and the fourth cell 30b are the same as those of the first cell 20a, and thus description thereof will be omitted. In the present embodiment, the number of the third cells 30a and the number of the fourth cells 30b are both 14, but the number of the cells is not particularly limited, and the number is not limited.

  ON / OFF of the unit transistor included in each cell is switched by the supplied bias current. Specifically, the bias circuit 40B (first bias circuit) supplies a bias current to the first unit transistor Q1a included in the first cell 20a. The bias circuit 40C (second bias circuit) supplies a bias current to the first unit transistor Q1a included in the first cell 20a and the second unit transistor Q1b included in the second cell 20b. The bias circuit 50B (third bias circuit) and the bias circuit 50C (fourth bias circuit) supply a bias current to the third unit transistor Q2a included in the third cell 30a. The bias circuit 50D (fifth bias circuit) supplies a bias current to the fourth unit transistor Q2b included in the fourth cell 30b. Note that the configurations of the bias circuits 40C and 50B to 50D are similar to those of the bias circuit 40A shown in FIG. The bias circuit 40B further includes a resistance element R4 and a capacitor C2 as compared with the bias circuit 40A. The resistance element R4 and the capacitor C2 are connected in series with each other so as to connect between the base and emitter of a transistor corresponding to the transistor 43 in the bias circuit 40A. Thus, negative feedback is applied to the transistor, so that the bias current can be stably supplied.

  The adjusting circuits 60B to 60D adjust the bias currents output from the bias circuits 40B, 50C, and 50D, respectively. The configurations of the adjusting circuits 60B to 60D are the same as those of the adjusting circuit 60A shown in FIG. In FIG. 10, the power supply voltage Vcc1 supplied to the resistance element is indicated by an arrow for convenience.

  When the power amplification module 10B operates according to the low power mode, the bias circuit 40B and the bias circuit 50B are driven by the bias drive signal supplied from the control terminal T5. As a result, the two first unit transistors Q1a are turned on in the first stage, and the fourteenth unit transistors Q2a are turned on in the latter stage. At this time, the two second unit transistors Q1b and the fourteenth unit transistor Q2b are turned off.

  On the other hand, when the power amplification module 10B operates according to the high power mode, the bias circuit 40C is driven by the bias drive signal supplied from the control terminal T6, and the bias circuit 50C and the bias circuit 50C are driven by the bias drive signal supplied from the control terminal T7. 50D is driven. As a result, both the two first unit transistors Q1a and the two second unit transistors Q1b are turned on in the first stage, and the fourteenth unit transistors Q2a and the four fourth unit transistors Q2b are turned on in the subsequent stage. Both are turned on.

  In this way, by switching the total number of unit transistors operating according to the power mode, power amplification suitable for each power mode is performed.

  In addition, in the present embodiment, in the low power mode, the bias current adjusted by the adjustment circuit 60B is supplied to the first unit transistor Q1a (that is, a part of the first stage amplifier 20B). Therefore, similar to the power amplification module 10A according to the first embodiment, it is possible to reduce the current flowing through the first unit transistor Q1a and the gain in the region where the power supply voltage Vcc1 is relatively low. Further, in the high power mode, the bias circuit 40C is driven instead of the bias circuit 40B, so that the influence of providing the adjustment circuit 60B can be avoided.

  The adjustment circuits 60C and 60D connected to the bias circuits 50C and 50D respond to the fluctuation of the power supply voltage when the power supply voltage Vcc1 follows a so-called envelope tracking method in which the power supply voltage Vcc1 changes following the envelope of the input signal RFin. It is provided to widen the gain difference.

  The exemplary embodiments of the present disclosure have been described above. The power amplification module 10 supplies a bias current to the amplifier 20 through a current path based on the amplifier 20 that amplifies the first signal, the amplifier 30 that amplifies the second signal based on the output signal of the amplifier 20, and the bias drive signal. A bias circuit 40 for supplying and an adjusting circuit 60 are provided. The adjusting circuit 60 is supplied with a first terminal to which a first voltage based on the power supply voltage Vcc1 is supplied and a second voltage based on a bias drive signal. The bias current is adjusted based on the power supply voltage Vcc1 supplied to the amplifier 20, including the transistor 61 having the second terminal and the third terminal connected to the current path. As a result, in the region where the power supply voltage Vcc1 is relatively low, the transistor 61 operates as two PN junction diodes, so that the bias current flowing through the base of the transistor Q1 included in the amplifier 20 can be reduced. Therefore, the current consumption of the amplifier 20 can be reduced.

  In the power amplification module 10A, the adjustment circuit 60A further includes resistance elements 62 to 64, and the first voltage of the transistor 61 is supplied to the first terminal of the transistor 61 from the power supply terminal T1 through the resistance element 62. The second voltage is supplied to the two terminals through the resistance element 63, and the third terminal of the transistor 61 is connected to the first current path 100 through the resistance element 64. Accordingly, the adjustment circuit 60A can increase the current Isub_c flowing from the bias circuit 40A to the power supply terminal T1 through the second current path 101 as the power supply voltage Vcc1 is lower.

  Further, the power amplification module 10B operates according to an operation mode including a low power mode and a high power mode, and the amplifier 20B is turned on when the power amplification module 10B operates according to the low power mode and the high power mode. And a second unit transistor Q1b that is turned off when the power amplification module 10B operates in the low power mode and is turned on when the power amplification module 10B operates in the high power mode. The circuit 40B supplies a bias current to one or more first unit transistors Q1a of the amplifier 20B. This makes it possible to reduce the current consumption in the low power mode while avoiding the influence on the amplification operation in the high power mode.

  The power amplification module 10B includes one or more third unit transistors Q2a that are turned on when the power amplification module 10B operates in the low power mode and the high power mode, and the power amplification module 10B operates in the low power mode. And one or a plurality of fourth unit transistors Q2b which are turned off in the case and are turned on when operating according to the high power mode. The power amplification module 10B includes a bias circuit 40C that supplies a bias current to one or more first unit transistors Q1a and one or more second unit transistors Q1b, and a bias current to one or more third unit transistors Q2a. Bias circuit 50B and bias circuit 50C that perform the above, and bias circuit 50D that supplies a bias current to one or a plurality of fourth unit transistors Q2b are further provided. When the power amplification module 10B operates in the low power mode, the bias circuit 40B and the bias circuit 50B are driven, and when the power amplification module 10B operates in the high power mode, the bias circuit 40C, the bias circuit 50C, and the bias circuit 50D are Driven. This makes it possible to reduce the current consumption in the low power mode while avoiding the influence on the amplification operation in the high power mode.

  The embodiments described above are for facilitating the understanding of the present disclosure, and are not for limiting the interpretation of the present disclosure. The present disclosure may be changed or improved without departing from the spirit thereof, and the present disclosure includes equivalents thereof. That is, the embodiments appropriately modified by a person skilled in the art are also included in the scope of the present disclosure as long as the features of the present disclosure are provided. The elements provided in the embodiment and the arrangement thereof are not limited to the exemplified ones, and can be changed as appropriate.

10, 10A, 10B ... Power amplification module, 20, 20A, 20B, 30, 30A, 30B ... Amplifier, 40, 40A-40C, 50, 50A-50D ... Bias circuit, 60, 60A-60D ... Adjustment circuit, 70, 80, 80A, 90 ... Matching circuit, 20a ... First cell, 20b ... Second cell, 30a ... Third cell, 30b ... Fourth cell, 41-43, 51-53, 61 ... Transistor, 44, 54, 62 ... 64 ... Resistance element, 45, 55, 81, 82 ... Capacitor, 83 ... Inductor, 100 ... First current path, 101 ... Second current path, 102 ... Third current path, Q1, Q2 ... Transistor, Q1a ... 1 unit transistor, Q1b ... 2nd unit transistor, Q2a ... 3rd unit transistor, Q2b ... 4th unit transistor, R1, R1x, R1y, R2, R a, R4 ... resistance element, C1, C1a, C2 ... capacitor, T1, T2 ... power supply terminal, T3 to T7 ... control terminal

Claims (4)

A first amplifier for amplifying the first signal;
A second amplifier for amplifying a second signal based on the output signal of the first amplifier;
A first bias circuit that supplies a bias current to the first amplifier through a current path based on a bias drive signal;
An adjustment circuit,
Equipped with
The adjustment circuit includes a first terminal supplied with a first voltage based on a power supply voltage, a second terminal supplied with a second voltage based on the bias drive signal, and a third terminal connected to the current path. Adjusting the bias current based on the power supply voltage supplied to the first amplifier.
Power amplification module. The adjustment circuit further includes first to third resistance elements,
The first voltage is supplied to the first terminal of the adjustment transistor from the power supply terminal through the first resistance element, and the second voltage is supplied to the second terminal of the adjustment transistor through the second resistance element. Is supplied and the third terminal of the adjusting transistor is connected to the current path through the third resistance element,
The power amplification module according to claim 1. The power amplification module operates according to an operation mode including a first mode and a second mode in which a power level of an output signal is higher than that of the first mode,
The first amplifier is
One or a plurality of first unit transistors that are turned on when the power amplification module operates according to the first mode and the second mode;
One or a plurality of second unit transistors that are turned off when the power amplification module operates according to the first mode and turned on when the power amplification module operates according to the second mode;
Including,
The first bias circuit supplies the bias current to the one or more first unit transistors of the first amplifier.
The power amplification module according to claim 1 or 2. The second amplifier is
One or more third unit transistors that are turned on when the power amplification module operates according to the first mode and the second mode;
One or a plurality of fourth unit transistors that are turned off when the power amplification module operates according to the first mode and turned on when the power amplification module operates according to the second mode;
Including,
The power amplification module,
A second bias circuit that supplies a bias current to the one or more first unit transistors and the one or more second unit transistors;
A third bias circuit and a fourth bias circuit for supplying a bias current to the one or more third unit transistors,
A fifth bias circuit for supplying a bias current to the one or more fourth unit transistors,
Further equipped with,
When the power amplification module operates according to the first mode, the first bias circuit and the third bias circuit are driven,
When the power amplification module operates according to the second mode, the second bias circuit, the fourth bias circuit, and the fifth bias circuit are driven.
The power amplification module according to claim 3.