JP2020072267A - Thin film capacitor, manufacturing method thereof, and electronic component built-in substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film capacitor having good heat dissipation and a manufacturing method thereof.
A thin film capacitor (1) is formed on a lower electrode (11) made of a metal foil containing a large number of metal particles, a dielectric thin film (12) formed on an upper surface (11a) of the lower electrode, and an upper surface (12a) of the dielectric thin film (12). And an upper electrode 13. The lower surface 11b of the lower electrode 11 is an etching surface showing the cross section of the metal particles, and the height difference between the cross sections of the metal particles adjacent to each other on the etching surface is 1 μm or more and 8 μm or less.
[Selection diagram] Figure 1

Description

  The present invention relates to a thin film capacitor and a manufacturing method thereof, and more particularly to a thin film capacitor configured by using a thinned electrode and a manufacturing method thereof. The present invention also relates to a substrate with a built-in electronic component that contains a thin film capacitor.

  Electronic components are rapidly becoming thinner, and for example, in capacitors, there is an increasing need for a thin film capacitor in which a dielectric thin film and an upper electrode are sequentially formed on a lower electrode made of a metal foil.

  Regarding the thin-film capacitor, for example, Patent Document 1 includes a first electrode layer, a second electrode layer, and a dielectric layer provided between the first and second electrode layers, and a dielectric layer of the first electrode layer. A thin film capacitor is described in which the ratio (S / S0) of the surface area of the opposite surface to the projected area of the first electrode layer in the thickness direction is 1.01 to 5.00. According to this thin film capacitor, it is possible to efficiently dissipate heat generated from the semiconductor element.

  Further, in Patent Document 2, a step of annealing a metal foil at a temperature of 800 ° C. or higher and a step of annealing the metal foil on the metal foil so that the ratio of the crystal grain size of the annealed metal foil to the thickness of the dielectric thin film is 104 to 560 A thin film comprising a step of forming a dielectric thin film on the substrate, a step of heating the metal foil and the dielectric thin film to sinter the dielectric thin film, and a step of forming an upper electrode on the sintered dielectric thin film. A method of manufacturing a capacitor is described.

JP, 2017-028096, A JP, 2010-171397, A

  In recent years, there has been a demand for further thinning of thin film capacitors, and in particular for the lower electrode. However, if the lower electrode is thinned by a well-known etching method, the etching of grain boundary components proceeds excessively than the metal particles in the lower electrode, and the unevenness of the etching surface becomes very large, so that the lower electrode can be thinned efficiently. There is a problem that you can not. Further, in this case, since the surface of the metal particles and the grain boundary component are exposed more and the cross section of the metal particles is not exposed, there is also a problem that the heat dissipation is not improved even if the unevenness is large.

  Therefore, an object of the present invention is to provide a thin film capacitor having good heat dissipation and a manufacturing method thereof. Another object of the present invention is to provide an electronic component-embedded substrate incorporating such a thin film capacitor.

  In order to solve the above problems, a thin film capacitor according to the present invention includes a lower electrode made of a metal foil containing a large number of metal particles, a dielectric thin film formed on an upper surface of the lower electrode, and an upper surface of the dielectric thin film. And a lower surface of the lower electrode is an etching surface showing a cross section of the metal particles, and a height difference between cross sections of the metal particles adjacent to each other on the etching surface is 1 μm or more and 8 μm or less. Characterize.

  According to the present invention, a thin film capacitor can be formed by using a lower electrode thinned by etching, and the thin film capacitor can be thinned. Further, since the lower surface of the lower electrode has appropriate irregularities and the cleaved cross section of the metal particles is exposed, the heat dissipation of the thin film capacitor can be improved. Further, since the lower surface of the lower electrode is formed with appropriate unevenness, the adhesion between the lower electrode and the resin layer can be enhanced when the lower surface of the lower electrode is covered with the resin layer.

In the thin film capacitor according to the present invention, the crystal orientation of the cross section appearing on the etching surface is (111) plane ± 20 °, the number of metal particles is N ₁₁₁ , and the crystal orientation of the cross section appearing on the etching surface is (100). ) When the number of metal particles having a surface of ± 20 ° is N ₁₀₀ , and the number of metal particles having a crystal orientation of a cross section appearing on the etching surface is a (110) surface of ± 20 ° is N ₁₁₀ , N ₁₁₁ > It is preferred to have the relationship N ₁₀₀ > N ₁₁₀ . Since the (111) plane of the metal crystal has a high atomic density, it has a strong bond with oxygen. Therefore, the (111) surface of the metal particles preferentially appears from the etching surface, whereby the (111) surface of the metal particles is bonded to oxygen in the resin, and the adhesion with the resin can be improved.

  In the present invention, the average particle size of the metal particles is preferably 10 μm or more and 25 μm or less. When the metal foil forming the lower electrode is annealed in advance, the grain growth of the metal particles forming the metal foil proceeds and the crystal grain size increases. After that, the metal particles also grow by heat treatment for sintering the precursor layer of the dielectric thin film, and the average particle diameter of the metal particles becomes 10 to 25 μm as described above. When the metal foil is composed of relatively large crystal grains as described above, the heat dissipation of the thin film capacitor is improved by exposing the cross section of the metal particle from the etching surface and setting the height difference of the cross section of the metal particle to 8 μm or less. Can be increased. Also, when the thin film capacitor is embedded in the substrate, the adhesion between the lower electrode and the resin can be improved.

  In the present invention, it is preferable that the metal foil is a Ni foil and the metal particles are Ni particles. Ni foil is inexpensive and easy to process, and is suitable as a lower electrode material for a thin film capacitor. Further, in the Ni foil, the coarsening of the crystal grains after the annealing step or the sintering step of the precursor layer of the dielectric thin film is remarkable, so that the effect of the present invention is also remarkable.

  In the present invention, the side surface of the lower electrode is preferably the etching surface in which the cross section of the metal particles appears together with the lower surface. According to this, the heat dissipation of the thin film capacitor and the adhesion to the resin can be further enhanced.

Further, the method of manufacturing a thin film capacitor according to the present invention comprises the steps of forming a dielectric thin film on the upper surface of the lower electrode, forming an upper electrode on the upper surface of the dielectric thin film, and thinning the lower electrode. And the step of thinning the lower electrode includes a step of etching the lower surface of the lower electrode using an etching solution containing Na ₂ SO ₈ .H ₂ SO ₄ as a main component.

  According to the present invention, not only the grain boundary component of the metal particles forming the lower electrode but also the metal particles can be uniformly etched. Thereby, the cross section of the metal particles can be exposed from the etching surface, and the heat dissipation of the thin film capacitor and the adhesion with the resin can be improved.

  In the present invention, the etching solution preferably contains an additive used as a leveling agent in the electrolytic plating process. According to this, the difference in dissolution rate between the metal particles and the grain boundary component can be further reduced, and the flatness of the etching surface can be further enhanced.

  In the present invention, the step of forming the dielectric thin film on the upper surface of the lower electrode includes a step of pre-annealing the lower electrode at a temperature of 300 ° C. or higher, and a precursor of the dielectric thin film on the upper surface of the lower electrode. It is preferable to include a step of forming a body layer and a step of sintering the precursor layer. When the metal foil forming the lower electrode is annealed in advance, the grain growth of the metal particles forming the metal foil proceeds and the crystal grain size increases. After that, the metal particles also grow by heat treatment for sintering the precursor layer of the dielectric thin film, and the average particle size of the metal particles becomes very large. However, when the lower electrode is etched using the above etching solution, the cross section of the metal particle can be exposed from the etching surface even if the metal foil is composed of large crystal grains, and The heat dissipation can be improved. Also, when the thin film capacitor is embedded in the substrate, the adhesion between the lower electrode and the resin can be improved.

  In the method for manufacturing a thin film capacitor according to the present invention, before the step of thinning the lower electrode, a step of covering the upper surface of the lower electrode on which the dielectric thin film and the upper electrode are sequentially formed with an upper resin layer is further included. It is preferable to include. According to this, the dielectric thin film and the upper electrode can be protected when the lower electrode is etched.

The method of manufacturing a thin film capacitor according to the present invention preferably further includes a step of covering the lower surface of the lower electrode with a lower resin layer after the step of thinning the lower electrode. According to this, it is possible to manufacture a thin film capacitor in which upper and lower surfaces of a capacitor element including a lower electrode, a dielectric thin film and an upper electrode are covered with a resin layer. According to such a thin film capacitor, it is possible to prevent the insulation resistance of the thin film capacitor from deteriorating due to the influence of hydrogen radicals, H ₂ O, etc. generated when the thin film capacitor is embedded in the substrate.

A method of manufacturing a thin film capacitor according to the present invention comprises etching a side surface of the lower electrode after the step of thinning the lower electrode and before the step of covering the lower surface of the lower electrode with the lower resin layer. The step of forming the side surface of the lower electrode by etching further includes a step of forming the side surface of the lower electrode by etching the lower electrode with an etching solution containing Na ₂ SO ₈ .H ₂ SO ₄ as a main component. The step of covering the lower surface with the lower resin layer preferably covers the side surface of the lower electrode with the lower resin layer. According to this, not only the grain boundary component but also the metal particles can be etched uniformly on the side surface of the lower electrode. Thereby, the cross section of the metal particles can be exposed not only from the lower surface of the lower electrode but also from the side surface thereof, and the heat dissipation of the thin film capacitor and the adhesion with the resin can be further enhanced.

  Also, the electronic component-embedded substrate according to the present invention is embedded in the multilayer substrate, and is electrically connected to the thin film capacitor according to the present invention having the above characteristics and the lower electrode of the thin film capacitor. A first via hole electrode formed in the multilayer substrate, and a second via hole electrode formed in the multilayer substrate so as to be electrically connected to the upper electrode of the thin film capacitor. To do. In this case, the multilayer substrate includes a first insulating layer and a second insulating layer formed on the upper surface of the first insulating layer, and the thin film capacitor is provided on the upper surface of the first insulating layer. And the second insulating layer is formed on the upper surface of the first insulating layer so as to fill the thin film capacitor, and the first via hole electrode is formed on the second insulating layer so that the lower electrode is exposed. It is preferable that the second via hole electrode is provided in a second contact hole formed in the second insulating layer so that the upper electrode is exposed. .. According to the present invention, it is possible to reduce the thickness of the electronic component built-in substrate.

  According to the present invention, it is possible to provide a thin film capacitor having good heat dissipation and a manufacturing method thereof. Further, according to the present invention, it is possible to provide an electronic component-embedded substrate incorporating such a thin film capacitor.

FIG. 1 is a schematic sectional view showing the structure of a thin film capacitor according to the first embodiment of the present invention. FIG. 2 is a flow chart for explaining the method of manufacturing the thin film capacitor. FIGS. 3A and 3B are schematic views for explaining grain growth of crystal grains in the metal foil. 4A to 4C are schematic cross-sectional views for explaining the structure of the lower electrode, where FIG. 4A is a state before etching and FIG. 4B is a state after etching by a conventional etching method. , (C) respectively show the states after etching by the etching method of the present invention. 5A and 5B are views showing a structure of a thin film capacitor according to a second embodiment of the present invention, wherein FIG. 5A is a schematic side sectional view and FIG. 5B is a schematic top view. 6 is a plan sectional view of the thin film capacitor of FIG. 5, in which (a) shows the upper electrode 13, (b) shows the dielectric thin film 12, and (c) shows the lower electrode 11, respectively. 7A to 7D are process diagrams for explaining the method of manufacturing the thin film capacitor according to the second embodiment. FIGS. 8A to 8D are process diagrams for explaining the method of manufacturing the thin film capacitor according to the second embodiment together with FIGS. 7A to 7D. FIG. 9 is a schematic cross-sectional view showing the structure of an electronic component built-in substrate that contains a thin film capacitor according to the second embodiment. FIG. 10 is a diagram showing the evaluation results of the etched surface of the lower electrode (Ni foil) in the thin film capacitor of the comparative example, (a) is an SEM image, and (b) is a graph showing changes in the height of the etched surface. Is. 11: is a figure which shows the evaluation result of the etching surface of the lower electrode (Ni foil) in Example 1, (a) is a SEM image, (b) is a graph which shows the change of the height of an etching surface. .. 12A and 12B are diagrams showing evaluation results of the etched surface of the lower electrode (Ni foil) in Example 2, where FIG. 12A is a SEM image and FIG. 12B is a graph showing changes in the height of the etched surface. ..

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic sectional view showing the structure of a thin film capacitor according to the first embodiment of the present invention.

  As shown in FIG. 1, the thin film capacitor 1 includes a lower electrode 11, a dielectric thin film 12 formed on an upper surface 11 a of the lower electrode 11, and an upper electrode 13 formed on an upper surface 12 a of the dielectric thin film 12. The dielectric thin film 12 is provided between the lower electrode 11 and the upper electrode 13.

  The lower electrode 11 is preferably a metal foil containing a noble metal such as Ni, Cu, Al, and Pt or an alloy thereof as a main component, and a Ni foil is particularly preferable. The metal foil has a function as a lower electrode, a function as a base surface on which a dielectric thin film is formed, and a function of supporting the dielectric thin film. The thickness of the metal foil is 5 to 50 μm, preferably 10 to 30 μm, particularly preferably 10 to 15 μm. By thus thinning the lower electrode 11, the thin film capacitor 1 can be thinned.

The dielectric thin film 12 includes barium titanate (BaTiO ₃ ), barium strontium titanate ((BaSr) TiO ₃ ), strontium titanate (SrTiO ₃ ), barium zirconium strontium titanate ((BaSr) (TiZr) O ₃ ), Perovskite type oxides such as barium zirconium titanate (BaTiZrO ₃ ) are preferably used. The dielectric thin film 12 may include one or more of these oxides. The film thickness of the dielectric thin film 12 is preferably about 30 nm to 5 μm, and it is preferable to appropriately adjust a suitable range based on the crystal grain size of the metal foil forming the lower electrode 11.

  The planar size of the dielectric thin film 12 is preferably smaller than that of the lower electrode 11. This is because if the dielectric thin film 12 is cut together with the metal foil forming the lower electrode 11, cracks may occur in the dielectric thin film 12.

The upper electrode 13 is preferably made of an inexpensive base metal material as a main component for cost reduction, and particularly preferably made of Cu as a main component. The upper electrode 13 is made of, for example, at least one of Ni, Pt, Pd, Ir, Ru, Rh, Re, Os, Au, Ag, Cu, IrO ₂ , RuO ₂ , SrRuO ₃ , and LaNiO _3. It may be configured to include.

  In the present embodiment, the lower surface 11b of the lower electrode 11 is thinned by etching, whereby more metal particles have more cross sections, and the height of the cross section is slightly different for each metal particle. It is preferable that the average height difference between the cross sections of adjacent metal particles is 1 μm or more and 8 μm or less. It is considered that such a difference in height of the cross section of the metal particles is caused by a difference in etching rate with respect to the crystal orientation.

  When a large number of grain boundaries appear on the surface of the lower electrode 11, the heat dissipation property decreases. This is because the grain boundary component is a low-purity component in which impurities in the metal foil are precipitated and has low thermal conductivity. However, when the cross section of the metal particles appears on the surface of the lower electrode 11, heat dissipation can be improved. The exposure ratio of the cross section of the metal particles to the entire etching surface of the lower electrode 11 is preferably 60% or more, and particularly preferably 80% or more.

  In the lower electrode 11, not only the lower surface 11b but also the side surface 11c may be etched. In this case, since the cross section of the metal particles is exposed from both the lower surface 11b and the side surface 11c of the lower electrode 11, heat dissipation can be further enhanced.

  The average particle size of the metal particles forming the lower electrode 11 is preferably 10 μm or more and 25 μm or less. Although details will be described later, in order to form the dielectric thin film 12 on the lower electrode 11, it is necessary to sinter the dielectric material formed on the upper surface 11a of the lower electrode 11, and further, the dielectric thin film 12 is cracked. It is desirable to anneal the metal foil before forming the dielectric thin film 12 so that it does not occur. When such a heat treatment is performed on the metal foil, the metal particles forming the metal foil grow large, and the range of the average particle size is as described above.

On the lower surface 11b of the lower electrode 11, the number N _{111 of} metal particles showing a cross section of (111) plane ± 20 ° is more than the number N _{100 of} metal particles showing a cross section of (100) plane ± 20 °. It is preferable that the number N _{100 of} metal particles having a (100) plane ± 20 ° cross section is larger than the number N _{110 of} metal particles having a (110) plane ± 20 ° cross section. That is, it is preferable to have a relationship of N ₁₁₁ > N ₁₀₀ > N ₁₁₀ .

  The resin contains a certain amount of oxygen, and the metal adheres to the resin by combining with the oxygen in the resin. Therefore, when the (111) plane having a high atomic number density appears preferentially on the surface of the lower electrode 11, not only the heat dissipation of the thin film capacitor 1 can be improved but also the thin film capacitor 1 is embedded in the resin. At that time, the adhesion between the lower electrode 11 and the resin can be enhanced.

  The plane orientation of the crystal grains exposed on the surface of the lower electrode 11 can be evaluated by EBSD (Electron Back Scatter Diffraction). EBSD is one of crystal analysis methods in the submicron region by SEM (Scanning Electron Microscope). When a sample tilted by about 60 to 70 ° is irradiated with an electron beam, the electron beam scatters on each crystal plane in a shallow region up to about 50 nm from the surface of the sample. A pattern (EBSD pattern) corresponding to the azimuth appears. By photographing and analyzing this EBSD pattern with an EBSD detector (CCD camera), information on the crystal orientation of the sample can be obtained, and orientation mapping of crystal grains, texture and crystalline phase distribution can be analyzed. In EBSD, it is only necessary to stop the electron beam on the crystal grain to be analyzed, so it is not necessary to add a special device to the electron optical system, and it can be realized with a simple configuration by adding an EBSD detector to the SEM. ..

  FIG. 2 is a flow chart for explaining the method of manufacturing the thin film capacitor.

  As shown in FIG. 2, in the manufacture of the thin film capacitor 1, first, a metal foil forming the lower electrode 11 is prepared (S1: metal foil preparation step). As described above, the metal foil is preferably Ni foil, and the thickness thereof is preferably 5 to 50 μm. There are electrolytic methods (plating method, sputtering method, vapor deposition method, CVD method, etc.) and rolling methods as a method for manufacturing a metal foil, but a metal foil made by an electrolytic method that does not include processing strain in the manufacturing process is more preferable. The metal foil produced by the plating method is particularly preferable because it contains a small amount of impurities and has a high purity.

  Next, the metal foil is annealed in a reducing atmosphere or a vacuum atmosphere in order to reduce strain in the metal foil (S2: annealing step). The annealing temperature is high enough to cause grain growth of crystals in the metal foil, and may be 300 ° C or higher, more preferably 300 ° C to 1300 ° C, and further preferably 300 ° C to 1000 ° C. The annealing time is preferably 1 minute to 4 hours. The rate of temperature increase may be 5 ° C./min or more, preferably 500 ° C./min or more. The strain in the foil of the metal foil can be controlled by the annealing temperature and the annealing time, and the strain in the crystal can be relaxed in a shorter time as the high temperature annealing is performed. The state in which the strain in the metal foil is relaxed is specifically preferably that the Vickers hardness of the metal foil is smaller than about 100 HV. Regarding the relationship between the annealing temperature and the annealing time, the higher the annealing temperature is, the shorter the annealing time can be.

The “vacuum atmosphere” in the present embodiment is a reduced pressure atmosphere in which the pressure is 1 × 10 ³ Pa or less, and is generally preferably 1 × 10 ⁻⁵ to 1 × 10 ² Pa, More preferably, it is 1 × 10 ^{−3 to} 10 Pa. Especially when the metal foil is mainly made of Ni, the pressure is preferably 2 × 10 ⁻³ to 8 × 10 ⁻¹ Pa. Further, the “reducing atmosphere” is an atmosphere composed of a mixed gas of nitrogen, hydrogen and water vapor, a hydrogen-containing atmosphere formed from ammonia, or a CO and CO ₂ -containing gas and oxygen partial pressure in the atmosphere. It is an atmosphere in which the concentration is controlled to 1 vol% or less. By heat-treating under such conditions, oxidation of metal foil such as Ni foil is suppressed.

  Here, "grain growth" will be described with reference to FIGS. 3 (a) and 3 (b). In the present embodiment, “grain growth” means that the grain boundary of each fine crystal is moved by initially heat-treating the metal foil having a fine polycrystalline structure, and the grain size of the crystal grain is increased while eroding adjacent crystal grains. The process of becoming.

  For example, as shown in FIG. 3A, the metal foil 11F initially has a structure including fine crystal particles 11G of various sizes having a particle size of approximately 20 nm to 60 nm. Then, as the grain growth progresses, the individual crystal grains 11G become larger as shown in FIG. When the grain growth further progresses and the crystal grain size becomes large to some extent, the grain growth may be saturated and the grain size may not be further increased. The particle size at this time is called "saturated particle size". The "crystal grain size" indicates the size of the crystal grain, specifically, the average grain size calculated by the "code method". In the code method, the surface of an object is observed with an optical microscope, a straight line L is arbitrarily drawn on the observation surface, and the number of intersection points N between the straight line L and grain boundaries is counted. Next, L is divided by N to obtain the average length l = L / N between the grain boundaries, and the average length l is multiplied by a statistical value k (for example, K = 1.7776). Then, the average particle diameter D = k × (L / N) is obtained (reference: “Ceramics characterization technology”, Ceramic Society of Japan, p7). The crystal grain size can be controlled by the impurities inside the metal foil, the annealing temperature, and the annealing time.

  Next, a dielectric thin film precursor layer of barium titanate or the like is formed on the annealed metal foil (S3: dielectric thin film precursor layer forming step). For forming the precursor layer, for example, a sputtering method, a CSD method (chemical solution method), a CVD method, or the like is used. This precursor layer is often not fully crystallized. When proceeding with crystallization, a sintering step described later is required.

  Next, the precursor layer formed on the metal foil is heated and sintered in a vacuum atmosphere or a reducing atmosphere (S4: sintering step). By this sintering step, the dielectric material that has not been sufficiently crystallized is crystallized, and the dielectric thin film 12 having a high dielectric constant is obtained. The heating temperature for the sintering process is preferably about 300 to 1000 ° C. The heating time is preferably 10 to 90 minutes. A high dielectric constant dielectric material is obtained by this sintering process. Even in the sintering step S4 of the precursor layer, the metal particles in the metal foil are regrown, so that the crystal grain size is further increased.

  Next, the upper electrode 13 is formed on the dielectric thin film 12 (S5: upper electrode forming step). The material of the upper electrode 13 is Cu, for example, and can be formed by a sputtering method. Alternatively, it can be formed by electrolytic plating, electroless plating, vapor deposition, or the like.

Next, the lower surface of the metal foil is etched to thin the lower electrode 11 (S6: lower electrode thinning step). In the thinning step S6 of the lower electrode 11, the lower surface of the lower electrode 11 is half-etched using an etching solution containing Na ₂ SO ₈ · H ₂ SO ₄ as a main component. In this case, the etching solution preferably contains an additive used as a leveling agent in the electrolytic plating process. When an etching solution containing such an additive is used, the flatness of the etching surface can be improved. Thus, the lower electrode 11 is thinned to a thickness of, for example, about 10 μm. As described above, the basic structure of the thin film capacitor according to the present embodiment is completed.

  On the lower surface 11b of the lower electrode 11 half-etched as described above, the cleaved cross section of the crystal grain appears, and the height of the cross section is slightly different for each metal particle. It is preferable that the average height difference between the cross sections of the adjacent metal particles in the etching surface is 1 μm or more and 8 μm or less. When such a difference in height is obtained by half-etching not only the lower surface 11b of the lower electrode 11 but also the side surface 11c, a cross section of crystal grains appears on the side surface 11c as well as the lower surface 11b of the lower electrode 11.

  4A to 4C are schematic cross-sectional views for explaining the structure of the lower electrode, where FIG. 4A is a state before etching and FIG. 4B is a state after etching by a conventional etching method. , (C) respectively show the states after etching by the etching method of the present invention.

  As shown in FIG. 4A, the metal foil forming the lower electrode 11 contains a large number of metal particles, and each metal particle is subjected to an annealing step of the metal foil and a sintering step of the precursor layer of the dielectric thin film 12. The grain growth is caused by the heat treatment, and the crystal grain size is much larger than that before the heat treatment. Also, due to the re-growth of the metal particles, the grain boundaries are clearly shown.

In order to half-etch such a metal foil, for example, when a well-known etching solution such as iron chloride (FeCl ₃ ) or hydrogen peroxide-based nitric acid (HNO ₃ · H ₂ O ₂ ) is used for Ni foil. As shown in FIG. 4B, while the etching inside the crystal grains does not proceed, the etching at the grain boundaries proceeds excessively, so that the metal particles remain and become an etched surface with large irregularities.

On the other hand, as shown in FIG. 4C, when a sodium sulfate-based (Na ₂ SO ₈ · H ₂ SO ₄ ) etching solution is used, not only the grain boundaries but also the crystal grains are etched, The flatness of the etching surface can be improved. In addition, the purity within the crystal grains is higher than the purity of the grain boundaries where impurities are deposited, and the thermal conductivity is high, so it is possible to enhance the heat dissipation by exposing the cleavage planes of the crystal grains to the surface of the metal foil. it can. Therefore, for example, when the thin film capacitor 1 is embedded in an LSI mounting substrate and used as a decoupling capacitor, heat generated from the LSI can be radiated. Further, since the etching surface has an appropriate surface roughness, it is possible to enhance the adhesiveness with the resin when embedding it in the mounting board.

  Next, a practical structure of the thin film capacitor will be described in detail.

  5A and 5B are views showing a structure of a thin film capacitor according to a second embodiment of the present invention, wherein FIG. 5A is a schematic side sectional view and FIG. 5B is a schematic top view. 6 is a plan sectional view of the thin film capacitor of FIG. 5, in which (a) shows the upper electrode 13, (b) shows the dielectric thin film 12, and (c) shows the lower electrode 11, respectively.

  As shown in FIGS. 5 and 6, the thin film capacitor 2 according to the present embodiment has a structure in which a capacitor element including a laminated body of a lower electrode 11, a dielectric thin film 12 and an upper electrode 13 is embedded in a resin layer 14. is doing. The resin layer 14 is composed of an upper resin layer 14a that covers the upper surface side of the lower electrode 11 on which the dielectric thin film 12 and the upper electrode 13 are laminated, and a lower resin layer 14b that covers the lower surface side of the lower electrode 11. The lower resin layer 14b covers not only the lower surface of the lower electrode 11 but also the side surface thereof. A DAF (Die Attach Film) 15 is attached to the lower surface of the resin layer 14.

A contact hole 14h ₁ exposing the upper surface of the contact plug 16 connected to the lower electrode 11 and a contact hole 14h ₂ exposing the upper surface of the upper electrode 13 are formed on the upper surface of the upper resin layer 14a. The electrical connection with the lower electrode 11 can be made via the contact plug 16 exposed from the contact hole 14h ₁ . The electrical connection with the upper electrode 13 can be made through the contact hole 14h ₂ . The contact holes 14h ₁ and 14h ₂ are holes that are also used when inspecting the capacitor.

  FIGS. 6A to 6C show patterns of each layer of the lower electrode 11, the dielectric thin film 12, and the upper electrode 13 shown in FIG. The dielectric thin film 12 shown in FIG. 6B is formed on the upper surface of the lower electrode 11 shown in FIG. 6C, and the upper electrode 13 shown in FIG. 6A is formed on the upper surface of the dielectric thin film 12. Has been formed. The dielectric thin film 12 is provided with an opening 12h exposing the upper surface of the lower electrode 11, and the upper electrode 13 is provided with an annular separation groove 13h. The separation groove 13h is provided to form a contact plug 16 that is insulated and separated from the upper electrode 13, and a part of the contact plug 16 is embedded in an opening 12h provided in the dielectric thin film 12 to form the lower electrode 11. Is connected to the upper surface of.

When the thin film capacitor 2 is embedded in an LSI mounting substrate and used as a decoupling capacitor, the insulation resistance of the thin film capacitor may be deteriorated due to the influence of hydrogen radicals, H ₂ O, etc. generated during the embedding in the substrate. .. The gas generated in the LSI mounting substrate is difficult to escape to the outside of the substrate, and the gas accumulated in the substrate gradually deteriorates the quality of the thin film capacitor. However, if the capacitor element is previously covered with the cured resin, it is not affected by such residual gas in the substrate, so that the deterioration of the insulation resistance can be prevented. When the capacitor element is embedded in the resin layer 14 as in the present embodiment, gas may be generated when the resin is cured. However, with a simple structure in which the thin film capacitor alone is covered with resin, the gas can diffuse outward and does not accumulate in the resin layer 14, so the insulation resistance of the capacitor does not deteriorate.

  The thin film capacitor 2 according to the present embodiment provides a very thin thin film capacitor because the lower surface 11b of the lower electrode 11 is etched and the lower electrode 11 is thinned, as in the first embodiment. You can Further, since the lower surface 11b and the side surface 11c of the lower electrode 11 are etched to show the cross section of the metal particles, it is possible to improve the flatness of the etching surface while ensuring an appropriate surface roughness, and also to improve the heat dissipation. You can Further, since the etching surface of the lower electrode 11 has an appropriate surface roughness and the entire exposed surface of the lower electrode 11 is covered with the resin, the adhesion between the lower electrode 11 and the resin can be enhanced, and the thin film capacitor The entire 2 can be protected.

  7 and 8 are process diagrams for explaining the method of manufacturing the thin film capacitor according to the second embodiment.

  As shown in FIGS. 7 and 8, in the manufacture of the thin film capacitor 2, first, the metal foil 11F that constitutes the lower electrode 11 is prepared, the metal foil 11F is annealed in advance, and then the dielectric thin film 12 is formed on the metal foil 11F. Are formed (FIG. 7A). Through the annealing process of the metal foil 11F and the sintering process of the precursor of the dielectric thin film 12, the metal particles in the metal foil 11F grow to have a crystal grain size of about 10 to 25 μm.

  Next, the dielectric thin film 12 is patterned (FIG. 7B). As a result, the dielectric thin film 12 is processed into a shape corresponding to each capacitor element.

  Next, a seed layer 13a for electrolytic copper plating is formed on the entire upper surface of the metal foil 11F on which the dielectric thin film 12 is formed by, for example, a sputtering method, and then a copper plating layer 13b is grown by electrolytic plating to form an upper electrode layer 13L. Are formed (FIG. 7C).

  Next, the upper electrode layer 13L is patterned (FIG. 7D). As a result, the upper electrode layer 13L is processed into an electrode shape corresponding to each capacitor element, and the upper electrode 13 and the contact plug 16 are formed.

Next, after forming the upper resin layer 14a that covers the upper surface of the metal foil 11F, contact holes 14h ₁ and 14h ₂ that expose the upper surfaces of the upper electrode 13 and the contact plug 16 are formed (FIG. 8A). The upper resin layer 14a can be formed by laminating a resin film.

  Next, the lower surface of the metal foil 11F is half-etched to thin the metal foil 11F, and is patterned so as to have a planar shape corresponding to each capacitor element (FIG. 8B). At this time, since the upper surface side of the metal foil 11F is covered with the upper resin layer 14a, the dielectric thin film 12 and the upper electrode 13 are not damaged during the etching process of the metal foil 11F. Further, when the patterning of the metal foil 11F is performed by etching similarly to the thinning step, the cross section of the metal particles appears not only on the lower surface of the metal foil 11F but also on the side surfaces thereof, so that the heat dissipation and the adhesion to the resin are further enhanced. You can do it.

  Next, the lower resin layer 14b that covers the lower surface of the metal foil 11F is formed, and the DAF 15 that covers the lower surface of the lower resin layer 14b is further formed (FIG. 8C). The lower resin layer 14b can also be formed by laminating a resin film. The DAF 15 can also be formed by laminating. As described above, the metal foil 11F is in a state in which not only the lower surface but also the side surface is covered with the resin. As described above, the assembly of the thin film capacitors 2 is completed.

  Finally, the assembly of the thin film capacitors 2 is diced into individual pieces (FIG. 8D). At this time, only the resin exists on the dicing line, and the upper electrode 13, the dielectric thin film 12 and the metal foil 11F do not exist. When the dielectric thin film 12 is diced, cracks may occur in the dielectric thin film 12, and when the metal foil 11F forming the upper electrode 13 and the lower electrode 11 is diced, the cut surface of the metal is sagged. May occur. However, when the dielectric or metal is removed from the dicing line in advance, the above problem does not occur, and a large number of capacitor elements can be easily divided. As described above, the thin film capacitor 2 according to the present embodiment is completed.

As described above, the thin film capacitor 2 according to the present embodiment is very thin because the lower surface 11b of the lower electrode 11 is etched and the lower electrode 11 is thinned, as in the first embodiment. A thin film capacitor can be provided. Further, the flatness of the etching surface of the lower electrode 11 is high, and the cross section of the metal particles has an appropriate height difference, so that the heat dissipation and the adhesion can be improved. Furthermore, since the entire exposed surface of the capacitor element including the lower electrode 11, the dielectric thin film 12 and the upper electrode 13 is covered with resin, hydrogen radicals and H ₂ O generated when the thin film capacitor is embedded in the substrate are prevented. It is possible to prevent deterioration of electrical characteristics such as insulation resistance due to influence.

  FIG. 9 is a schematic cross-sectional view showing the structure of an electronic component built-in substrate that contains a thin film capacitor according to the second embodiment.

  As shown in FIG. 9, the electronic component built-in substrate 5 includes a multilayer substrate 20, a thin film capacitor 2 embedded in the multilayer substrate 20, and a plurality of via hole electrodes 34.

  The multilayer substrate 20 according to the present embodiment includes a first resin layer 21, a first wiring layer 31, a second resin layer 22, a third resin layer 23, a second wiring layer 32, a fourth resin layer 24, and a third wiring layer 33. The fifth resin layer 25 and the fifth resin layer 25 are laminated in this order. The first resin layer 21 is, for example, a core substrate, and an organic substrate such as glass epoxy resin or BT (bismaleimide triazine) resin can be used. Further, the core substrate may have an RCC (Resin Coated Copper) structure.

  In this embodiment, the thin film capacitor 2 is provided on the upper surface of the second resin layer 22 (first insulating layer), and the lower surface of the lower electrode 11 of the thin film capacitor 2 is in contact with the upper surface of the second resin layer 22. The thin film capacitor 2 is embedded in the third resin layer 23 (second insulating layer). The second resin layer 22, the third resin layer 23, and the fourth resin layer 24 are interlayer insulating layers for insulating and separating the upper and lower wiring layers, and the fifth resin layer 25 selectively covers the third wiring layer 33. It is a protective insulating layer. The material of the second to fifth resin layers 22 to 25 is not particularly limited, but an insulating material such as polyimide resin, epoxy resin, acrylic resin, or phenol resin can be used. The resin layer may contain a filler having an insulating property or a high electric resistance.

The via-hole electrode 34 is provided so as to penetrate the corresponding resin layer in order to draw out the wiring layer in the vertical direction. In the third resin layer 23, a contact hole 14h ₁ (first contact hole) that exposes the upper surface of the contact plug 16 and a contact hole 14h ₂ (second contact hole) that exposes the upper surface of the upper electrode 13 are formed. ing. The via hole electrode 34 (first via hole electrode) formed in the contact hole 14h ₁ is connected to the lower electrode 11 of the thin film capacitor 2 via the contact plug 16. Further, the via hole electrode 34 (second via hole electrode) formed in the contact hole 14h ₂ is connected to the upper electrode 13 of the thin film capacitor 2.

  As described above, since the electronic component-embedded substrate 5 according to the present embodiment has the very thin thin-film capacitor 2 incorporated in the multilayer substrate 20, it is possible to reduce the thickness of the entire substrate.

  Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention. It goes without saying that it is included in the range.

  For example, in the second embodiment, the entire exposed surface of the lower electrode 11 which is not covered with the dielectric thin film 12 is covered with resin, but only the upper surface 11a and the lower surface 11b of the lower electrode 11 are covered with resin. The side surface 11c of the lower electrode 11 may be exposed.

<Comparative example>
A rolled Ni foil having a thickness of 28 μm was previously annealed, and then barium titanate was deposited on the Ni foil by a sputtering method. Then, the barium titanate was sintered by heating at 800 ° C. for 60 minutes. In the annealing treatment, the annealing temperature was 900 ° C., the annealing time was 2 hours, and the temperature rising rate was 100 ° C./min. Then, a Cu film having a thickness of 5 μm was formed by electrolytic plating. Then, the back surface of the Ni foil was half-etched to be thinned to 10 μm. In half etching, HNO ₃ .H ₂ O ₂ was used as an etching solution.

  Then, the etched surface of the Ni foil was observed by SEM to evaluate the surface roughness (height difference). The result is shown in FIG.

As can be seen from the SEM image in FIG. 10A, the grain boundaries existing between the Ni particles were clearly shown on the etched surface of the Ni foil, and the image had a very three-dimensional effect. Further, as shown in FIG. 10B, the height difference in the etched surface was 15 μm or more, the surface roughness Ra of the etched surface was 2.2, and the flatness of the etched surface was poor. Further, it was found from the EBSD measurement results that the variation in the plane orientation of the crystal grains was large. In particular, the number of metal particles exhibiting (111) plane ± 20 °: N ₁₁₁ , the number of metal particles exhibiting (100) plane ± 20 °: N ₁₀₀ , (110) plane ± 20 ° The relationship of the number of metal particles present: N ₁₁₀ was N ₁₀₀ > N ₁₁₀ > N ₁₁₁ .

<Example 1>
An electrolytic Ni foil having a thickness of 28 μm was previously annealed, and then barium titanate was deposited on the Ni foil by a sputtering method. Then, the barium titanate was sintered by heating at 800 ° C. for 60 minutes. In the annealing treatment, the annealing temperature was 900 ° C., the annealing time was 2 hours, and the temperature rising rate was 100 ° C./min. Then, a Cu film having a thickness of 5 μm was formed by electrolytic plating. Further, after forming a thin film capacitor sample under the same conditions as in the comparative example except that Na ₂ SO ₈ · H ₂ SO ₄ was used as an etching solution when thinning the back surface of the Ni foil by half etching. The etched surface was evaluated. The result is shown in FIG.

As can be seen from the SEM image of FIG. 11A, the cross section of Ni particles appeared on the etched surface, the number of grain boundaries was small, and the flatness of the etched surface was high. Further, as shown in FIG. 11B, the height difference in the etched surface was about 7 μm, and the surface roughness Ra of the etched surface was 1.1, which was more flat than the comparative example. Further, from the EBSD measurement results, it was found that the crystal grain in the etching plane has the largest plane orientation of the (111) plane, and the variation of the plane orientation is small. In particular, the number of metal particles exhibiting (111) plane ± 20 °: N ₁₁₁ , the number of metal particles exhibiting (100) plane ± 20 °: N ₁₀₀ , (110) plane ± 20 ° The relationship of the number of existing metal particles: N ₁₁₀ was N ₁₁₁ > N ₁₀₀ > N ₁₁₀ .

<Example 2>
A thin film capacitor sample was prepared under the same conditions as in Example 1 except that the leveling agent used in the electroplating process was added to the etching solution of Na ₂ SO ₈ · H ₂ SO ₄ , and then the etched surface was evaluated. did. The result is shown in FIG.

As can be seen from the SEM image of FIG. 12A, the cross section of Ni particles appeared on the etched surface, the number of grain boundaries was small, and the flatness of the etched surface was high. Further, as shown in FIG. 12B, the height difference in the etched surface was about 6 μm, and the surface roughness Ra of the etched surface was 0.5, and the flatness was further improved as compared with Example 1. Further, from the EBSD measurement results, it was found that the crystal grain in the etching plane has the largest plane orientation of the (111) plane, and the variation of the plane orientation is small. In the same manner as in Example 1, the number of metal particles showing (111) plane ± 20 °: N ₁₁₁ , the number of metal particles showing (100) plane ± 20 °: N ₁₀₀ , (110) plane The relationship of the number of metal particles exhibiting ± 20 °: N ₁₁₀ was N ₁₁₁ > N ₁₀₀ > N ₁₁₀ .

1, 2 thin film capacitor 5 electronic component built-in substrate 11 lower electrode 11a lower electrode upper surface 11b lower electrode lower surface 11c lower electrode side surface 11F metal foil 11G crystal particles (metal particles)
12 Dielectric Thin Film 12a Dielectric Thin Film Upper Surface 12h Dielectric Thin Film Opening 13 Upper Electrode 13L Upper Electrode Layer 13a Seed Layer 13b Copper Plating Layer 13h Upper Electrode Separation Groove 14 Resin Layer 14a Upper Resin Layer 14b Lower Resin Layer 14h ₁ Resin Layer contact hole 14h ₂ Resin layer contact hole 15 DAF
16 Contact Plug 20 Multilayer Substrate 21 First Resin Layer 22 Second Resin Layer (First Insulating Layer)
23 Third resin layer (second insulating layer)
24 Fourth Resin Layer 25 Fifth Resin Layer 31 First Wiring Layer 32 Second Wiring Layer 33 Third Wiring Layer 34 Via Hole Electrode

Claims (13)

A lower electrode formed of a metal foil containing a large number of metal particles, a dielectric thin film formed on the upper surface of the lower electrode, and an upper electrode formed on the upper surface of the dielectric thin film,
The lower surface of the lower electrode is an etching surface showing a cross section of the metal particles,
A thin film capacitor, wherein a height difference between cross sections of the metal particles adjacent to each other on the etching surface is 1 μm or more and 8 μm or less. The number of metal particles whose crystal orientation of the cross section appearing on the etched surface is (111) plane ± 20 ° is N ₁₁₁ , and the crystal orientation of the cross section appearing on the etched surface is (100) plane ± 20 °. When N ₁₀₀ is the number of metal particles and N ₁₁₀ is the number of metal particles whose crystal orientation of the cross section appearing on the etching surface is (110) plane ± 20 °,
N ₁₁₁ > N ₁₀₀ > N ₁₁₀
The thin film capacitor according to claim 1, having the relationship of   The thin film capacitor according to claim 1, wherein the average particle size of the metal particles is 10 μm or more and 25 μm or less.   The thin film capacitor according to claim 1, wherein the metal foil is a Ni foil, and the metal particles are Ni particles.   The thin film capacitor according to claim 1, wherein a side surface of the lower electrode is the etching surface in which a cross section of the metal particle appears together with the lower surface. A step of forming a dielectric thin film on the upper surface of the lower electrode,
Forming an upper electrode on the upper surface of the dielectric thin film;
A step of thinning the lower electrode,
The method of manufacturing a thin film capacitor, wherein the step of thinning the lower electrode includes a step of etching the lower surface of the lower electrode using an etchant containing Na ₂ SO ₈ .H ₂ SO ₄ as a main component. ..   The method of manufacturing a thin film capacitor according to claim 6, wherein the etching solution contains an additive used as a leveling agent in an electrolytic plating process. The step of forming the dielectric thin film on the upper surface of the lower electrode,
Pre-annealing the lower electrode at a temperature of 300 ° C. or higher;
Forming a precursor layer of the dielectric thin film on the upper surface of the lower electrode;
The manufacturing method of the thin film capacitor according to claim 6 or 7, including a step of sintering the precursor layer.   9. The method according to claim 6, further comprising a step of covering the upper surface of the lower electrode on which the dielectric thin film and the upper electrode are sequentially formed with an upper resin layer before the step of thinning the lower electrode. A method of manufacturing a thin film capacitor according to the item 1.   The method of manufacturing a thin film capacitor according to claim 9, further comprising a step of covering the lower surface of the lower electrode with a lower resin layer after the step of thinning the lower electrode. After the step of thinning the lower electrode, and before the step of covering the lower surface of the lower electrode with the lower resin layer, the method further includes a step of forming a side surface of the lower electrode by etching.
In the step of forming the side surface of the lower electrode by etching, the lower electrode is etched using an etching solution containing Na ₂ SO ₈ .H ₂ SO ₄ as a main component,
The method of manufacturing a thin film capacitor according to claim 10, wherein the step of covering the lower surface of the lower electrode with the lower resin layer covers the side surface of the lower electrode with the lower resin layer. A multilayer substrate,
The thin film capacitor according to claim 1, wherein the thin film capacitor is embedded in the multilayer substrate.
A first via hole electrode formed in the multilayer substrate so as to be electrically connected to the lower electrode of the thin film capacitor;
And a second via hole electrode formed in the multilayer substrate so as to be electrically connected to the upper electrode of the thin film capacitor. The multilayer substrate has a first insulating layer and a second insulating layer formed on the upper surface of the first insulating layer,
The thin film capacitor is provided on the upper surface of the first insulating layer,
The second insulating layer is formed on the upper surface of the first insulating layer so as to fill the thin film capacitor,
The first via hole electrode is provided in a first contact hole formed in the second insulating layer so that the lower electrode is exposed,
The electronic component built-in substrate according to claim 12, wherein the second via hole electrode is provided in a second contact hole formed in the second insulating layer so that the upper electrode is exposed.