JP2020068369A - Semiconductor device, semiconductor memory, photoelectric conversion device, moving body, photoelectric conversion device manufacturing method, and semiconductor memory manufacturing method - Google Patents

Abstract

An object of the present invention is to improve the characteristics of a transistor. A semiconductor device includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, wherein the first transistor is arranged in an active region of a semiconductor substrate and is active with a gate electrode in plan view. has a portion overlapping with the region and located between the source and drain of the first transistor in the semiconductor substrate. In the channel width direction, the impurity concentration of the second conductivity type is higher at the end portion than at the central portion side. [Selection diagram] Fig. 3

Description

  The present invention relates to a semiconductor device, a semiconductor memory, a photoelectric conversion device, a moving body, a method for manufacturing a photoelectric conversion device, and a method for manufacturing a semiconductor memory.

  Patent Document 1 discloses a technique for ensuring circuit operation stability in a SRAM (Static Random Access Memory) type semiconductor memory by properly using the threshold values of transistors. Further, Patent Document 2 describes changing the shape of the gate electrode and the film thickness of the gate insulating film in order to reduce noise of the transistor.

JP, 2000-058675, A JP, 2017-069231, A

  Patent Document 1 describes that the threshold value of the transistor is used properly, but detailed examination has not been made on a method of changing the size of the transistor. Miniaturization of transistors is a necessary study for high integration of SRAM type semiconductor memories.

  Further, in semiconductor circuits, it is required to reduce noise caused by transistors. However, changing the shape of the gate electrode and the film thickness of the gate insulating film described in Patent Document 2 leads to an increase in the area of the transistor and an increase in the manufacturing process.

  An object of the present invention is to provide a technique for improving characteristics such as size and noise of a transistor used in a semiconductor device.

  One aspect of the present invention is a semiconductor memory having an SRAM (Static Random Access Memory) type unit cell including a first transistor of a first conductivity type and a second transistor of a second conductivity type, wherein the first transistor Is disposed in an active region of a semiconductor substrate, and the active region includes a portion overlapping the gate electrode of the first transistor and located between the source and the drain of the first transistor. Of the second conductivity type arranged at the first position, the second position, and the third position arranged in order along the channel width direction of the second conductive type. A first semiconductor region and a second semiconductor region of the second conductivity type disposed at the second position, and the impurity concentration of the first semiconductor region is higher than the impurity concentration of the second semiconductor region. And said that no.

  Another aspect of the present invention is a method for manufacturing a semiconductor memory having an SRAM (static random access memory) type unit cell including a first transistor of a first conductivity type and a second transistor of a second conductivity type. A step of preparing a semiconductor substrate having a first region and a second region, and using a first mask pattern, forming a first groove in the first region and forming a second groove in the second region A step of forming a second mask pattern on the first mask pattern, the second mask pattern covering the first groove and having an opening exposing the second groove, the first mask pattern and the second mask pattern And a step of implanting impurity ions of the first conductivity type into the semiconductor substrate through the second groove, and filling the first groove and the second groove with an insulator to form the first groove. First element isolation part having And a step of forming a second element isolation portion having the second groove, and a step of forming the first transistor in the first region and forming the second transistor in the second region. Is characterized by.

  Another aspect of the present invention is a method for manufacturing a semiconductor memory having an SRAM (static random access memory) type unit cell including a first transistor of a first conductivity type and a second transistor of a second conductivity type. A step of preparing a semiconductor substrate having a first region and a second region, and using a first mask pattern, forming a first groove in the first region and forming a second groove in the second region A step of forming a second mask pattern on the first mask pattern, the second mask pattern covering the first groove and having an opening exposing the second groove, the first mask pattern and the second mask pattern And a step of implanting impurity ions of the first conductivity type into the semiconductor substrate through the second groove, and filling the first groove and the second groove with an insulator to form the first groove. First element isolation part having And a step of forming a second element isolation portion having the second groove, and a step of forming the first transistor in the first region and forming the second transistor in the second region. Is characterized by.

  Another aspect of the present invention is a semiconductor device having a CMOS circuit including a first conductivity type first transistor and a second conductivity type second transistor, wherein the first transistor is a semiconductor substrate. The first transistor is disposed in an active region, and the first transistor has a portion where the gate electrode of the first transistor and the active region overlap with each other and which is located between the source and the drain of the first transistor of the semiconductor substrate. In the portion, a second conductive type first semiconductor region is arranged at a first position along a channel width direction of the first transistor, and at a second position between the first position and the third position. A second semiconductor region of the second conductivity type is arranged, and an impurity concentration of the first semiconductor region is higher than an impurity concentration of the second semiconductor region.

  Another aspect of the present invention has a unit cell unit in which a unit cell having a photoelectric conversion element is arranged, and a signal reading unit for reading a signal from the unit cell unit, wherein the signal reading unit is At least one first-conductivity-type first transistor, wherein the first transistor is disposed in an active region of a semiconductor substrate, the active region overlapping a gate electrode of the first transistor, and The first portion, which includes a first portion located between the source and drain of one transistor, is arranged in order along the channel width direction of the first transistor, and extends over the first position, the second position, and the third position. A portion is disposed, and the first portion includes a second conductive type first semiconductor region disposed at the first position and a second conductive type second semiconductor region disposed at the second position. , The first semiconductor region Impurity concentration being higher than the impurity concentration of said second semiconductor region.

  The present invention makes it possible to improve the characteristics of a transistor.

3 is an equivalent circuit diagram illustrating a unit cell of the semiconductor memory according to the first embodiment. FIG. 3 is a schematic plan view illustrating a unit cell of the semiconductor memory according to the first embodiment. FIG. (A) Schematic cross-sectional view of the transistor according to Example 1, (b) Schematic cross-sectional view of the transistor according to Example 1, (c) Diagram showing the impurity concentration of the transistor according to Example 1. 6A and 6B are schematic cross-sectional views illustrating the method for manufacturing the photoelectric conversion device according to the second embodiment. 6A and 6B are schematic cross-sectional views illustrating the method for manufacturing the photoelectric conversion device according to the second embodiment. 6A and 6B are schematic cross-sectional views illustrating the method for manufacturing the photoelectric conversion device according to the second embodiment. 6A and 6B are schematic sectional views illustrating a method for manufacturing the photoelectric conversion device according to the third embodiment. FIG. 6 is a schematic cross-sectional view illustrating a photoelectric conversion device according to a fourth embodiment. (A) Schematic cross-sectional view of the transistor according to the fifth embodiment, (b) A diagram showing the impurity concentration of the transistor according to the fifth embodiment. FIG. 3 is a block diagram illustrating a structure of a photoelectric conversion device. 8 is an equivalent circuit diagram illustrating a photoelectric conversion device according to a fifth embodiment. FIG. FIG. 9 is an equivalent circuit diagram illustrating a photoelectric conversion device according to a sixth embodiment. FIG. 9 is an equivalent circuit diagram illustrating a photoelectric conversion device according to a seventh embodiment. 9 is a table illustrating a photoelectric conversion device according to Example 8. 9 is an equivalent circuit diagram illustrating a photoelectric conversion device according to a ninth embodiment. FIG. 3 is a perspective view illustrating a stacked photoelectric conversion device. The figure which shows the structure of an imaging system. (A) The figure which shows the structure of a moving body, (b) The figure which shows the structure of a moving body. The figure which shows the operation | movement flow of a mobile body.

  Each embodiment will be described below with reference to the drawings. In the description of each embodiment, the description of the same configuration as the other embodiments may be omitted. The N-type and P-type polarities in the following description can be changed. In that case, it can be applied by changing the polarity of the semiconductor region, changing the potential of the control signal, or the like. In the following description, electrically connecting means connecting to a common node. Further, in the connection relationship between the circuit elements, it is possible to make appropriate changes such as inserting another element (switch, buffer, etc.) between them.

(Example 1)
FIG. 1 is an equivalent circuit diagram illustrating a unit cell of a semiconductor memory according to this embodiment. The semiconductor memory according to this embodiment is a static random access memory (hereinafter, SRAM). In the SRAM, the unit cell 100 is a bit cell that holds a 1-bit signal. In the SRAM, a plurality of unit cells 100 are arranged.

  The unit cell 100 has at least six transistors M1 to M6. The two transistors M1 and M2 are P-type MOS transistors and can function as a load transistor (load transistor) of the SRAM. The two transistors M3 and M4 are N-type MOS transistors and can function as a drive transistor (driver transistor) of the SRAM. The two transistors M5 and M6 are N-type MOS transistors and can function as a transfer transistor (transfer transistor) of the SRAM. The connection of each transistor is as follows.

  The sources of the two transistors M1 and M2 are electrically connected to the node VDD of the power supply voltage. The sources of the two transistors M3 and M4 are electrically connected to the node GND of the power supply voltage which is ground. Two transistors M1 and M3 having different polarities form one inverter, and two transistors M2 and M4 having different polarities form one inverter. Specifically, the drain of the transistor M1 and the drain of the transistor M3 are electrically connected, and the gate electrodes of the transistor M1 and the transistor M3 are electrically connected. Similarly, the drain of the transistor M2 and the drain of the transistor M4 are electrically connected, and the gate electrodes of the transistor M2 and the transistor M4 are electrically connected. Further, these two inverters form one flip-flop. The gate electrode of the transistor M1 and the drain of the transistor M2 are electrically connected, and the gate electrode of the transistor M2 and the drain of the transistor M1 are electrically connected.

  The transistor M5 can control conduction between one flip-flop and one bit line BL. The transistor M6 can control conduction between one flip-flop and one bit line BLB. The gate electrodes of the two transistors M5 and M6 are electrically connected to one word line WL. In the first embodiment, these six transistors form the SRAM unit cell 100.

  FIG. 2 is a schematic plan view illustrating the unit cell 100 corresponding to FIG. In FIG. 2, the arrangement of the transistors is projected on the surface of the semiconductor substrate. The surface of the semiconductor substrate includes the X direction and the Y direction orthogonal to the X direction. The unit cell 100 is arranged in two regions 210 and 220. The region 210 is a region in which an N-type semiconductor region is provided, and the region 220 is a region in which a P-type semiconductor region is provided. It can be said that these semiconductor regions are wells. Two transistors M1 and M2 are arranged in the region 210, and four transistors M3 to M6 are arranged in the region 220.

  In the region 210, a device isolation region 211 and an active region 212 are provided on the surface of the semiconductor substrate. In FIG. 2, the transistor M1 is arranged in one active region 212, and the transistor M2 is arranged in another active region 212. However, the transistors M1 and M2 may be arranged in the same active region 212. The transistor M1 has a gate electrode 231 and P-type semiconductor regions 250 and 251 which are a source and a drain. The transistor M2 has a gate electrode 230 and P-type semiconductor regions 252 and 253 which are a source and a drain.

  In the region 220, a device isolation region 221 and an active region 222 are provided on the surface of the semiconductor substrate. In FIG. 2, transistors M3 and M5 are arranged in one active region 222, and transistors M4 and M6 are arranged in another active region 222. However, the transistors M3 to M6 may be arranged in the same active region 222. The transistor M3 has a gate electrode 231 and N-type semiconductor regions 254 and 255 which are a source and a drain. The transistor M4 has a gate electrode 230 and N-type semiconductor regions 256 and 257 which are a source and a drain. The transistor M5 has a gate electrode 232 and N-type semiconductor regions 255 and 258 which are a source and a drain. The transistor M6 has a gate electrode 232 and N-type semiconductor regions 256 and 259 which are a source and a drain. Here, the gate electrode 232 can function as the word line WL of FIG. 1 while functioning as the gate electrodes of the transistors M5 and M6. Here, the legend of FIG. 2 shows ACT indicating the active region, GATE indicating the gate electrode, FIELD indicating the element isolation region, and CNT indicating the position of the contact plug.

  The gate electrodes 230, 231, and 232 are formed of, for example, polysilicon, and can function as the gate electrodes of the transistors in a portion overlapping the active regions 212 and 222. Here, the gate electrode 231 is commonly arranged for the two transistors M1 and M3, the gate electrode 230 is commonly arranged for the two transistors M2 and M4, and the gate electrode 232 is commonly arranged for the two transistors M5 and M6. ing. The gate electrodes 230 and 231 extend from the element isolation region 211 to the active region 212, the element isolation region 211, the element isolation region 221, the active region 222, and the element isolation region 221. Also in sources and drains other than the gate electrode, if the sources and drains of the transistors are common nodes, they may be configured by one semiconductor region.

  Here, high integration of the unit cell of the SRAM will be described. In SRAM, unit cells are repeatedly arranged. The SRAM can be highly integrated by reducing the area of the unit cell even slightly. In order to reduce the area of the unit cell, it is effective to reduce the size of the transistor forming the unit cell. However, in order to stabilize the operation of the SRAM, it is necessary to set the current ratio of each transistor to a desired value, and it is not possible to form all the transistors that form the unit cell with the minimum size. If all of the transistors that form the unit cell are formed to have the minimum size, the current ratio changes, which causes a decrease in the speed of write and read operations and a malfunction. By designing the size of the load transistor to be the smallest among the transistors forming the unit cell, the size of the other transistors can be reduced, and the desired current ratio is achieved, and the operation is stabilized. That is, it is effective to reduce the area of the unit cell by minimizing the channel width that defines the size of the load transistor. Here, the channel width of a transistor is generally defined as the width of the active region during element isolation. Therefore, the element separation interval is defined by the semiconductor process rule. Therefore, in this embodiment, a semiconductor region having a conductivity type opposite to the polarity of the load transistor is provided around the element isolation portion provided with the load transistor. By providing such a semiconductor region, the effective channel width of the transistor can be made smaller than the distance between the element isolation portions. Therefore, the design value of the channel width of the drive transistor and the transfer transistor can be made relatively smaller than when the channel width of the load transistor is set to the minimum value defined by the process rule. Therefore, the area of the unit cell can be reduced.

  A specific structure of the transistor of this embodiment will be described with reference to FIG. 3A and 3B are schematic cross-sectional views of the transistor M1 which is a load transistor. FIG. 3A and FIG. 3B are schematic diagrams in which the configuration of contact plugs and the like are omitted, and are schematic diagrams focusing on a part of the transistor. FIG. 3A is a cross section of the transistor M1 along the X direction in FIG. 2, and shows a cross section in the channel length direction of the transistor M1. FIG. 3A shows the semiconductor regions 250 and 251 of the transistor M1 and the gate electrode 231 provided on the gate insulating film 602. The transistor M1 is provided in the N-type semiconductor region 58b. The transistor M1 has a portion 601 located between the semiconductor region 250 and the semiconductor region 251. The portion 601 is a portion where the gate electrode 231 and the active region 212 overlap in a plan view.

  FIG. 3B is a cross section of the transistor M1 along the Y direction in FIG. 2, and is a cross section in the channel width direction of the transistor M1. An active region 212 in which the transistor M1 is arranged is arranged between two element isolation regions 211. The element isolation region 211 is provided with the element isolation portion 31. The element isolation portion 31 has, for example, a trench isolation structure in which an insulator formed in a trench is arranged. As the trench isolation structure, there are an STI structure (shallow trench isolation structure) and a DTI (deep trench isolation structure). In this embodiment, the element isolation section 31 is STI. The gate electrode 231 extends from the element isolation region 211 to the active region 212. The gate electrode 231 extends from above the element isolation portion 31 to above the gate insulating film 602. Here, the portion 601 is the active region 212 in which the gate electrode 231 overlaps in the Z direction. This portion 601 is generally a region where the channel of the transistor can be formed.

  In this embodiment, the N-type semiconductor region 52 is provided along the side surface and the bottom surface of the groove of the element isolation portion 31. The N-type semiconductor region 52 has a higher impurity concentration than the N-type semiconductor region 58b. In FIG. 3B, n + is shown in the semiconductor region 52 and n is shown in the semiconductor region 58b. The N-type semiconductor region 52 reduces the channel width of the transistor M1 that can be actually formed, that is, the effective channel width. When the width of the region between the element isolation portions 31, that is, the width of the portion 601 is W1, the effective channel width is W2. It can be said that the effective channel width is defined by the semiconductor region 52. For example, when the width W1 is 80 nm or more and 120 nm or less, the width W2 can be, for example, 60 nm or more and 100 nm or less. The width W2 is not limited to this numerical value and can be set as appropriate by the semiconductor region 52.

  A line segment AB in FIG. 3B is a line segment along the gate width direction, and is located at the end of the portion 601. The line segment AB has a position P1, a position P2, and a position P3 on the line segment. The position P2 is a position between the position P1 and the position P3. A semiconductor region 52 is provided at the positions P1 and P3, and a semiconductor region 58b is provided at the position P2. FIG. 3C is a diagram showing the impurity concentration of the N-type semiconductor region in the line segment AB of FIG. Here, the impurity concentration means the NET concentration. In FIG. 3B, the position P1 and the position A are the same position, and the position P2 and the position B are the same position, but the positions P1 to P3 are actually between the position A and the position B. Shall exist. The density at position P1 is C1, the density at position P2 is C2, and the density at position P3 is C3. At this time, C1 = C3> C2. That is, it can be seen that the impurity concentration increases from the central portion of the portion 601 toward the boundary between the element isolation portion 31 and the portion 601.

  With such a configuration, when the gate electrode 231 is turned on, a channel is formed at the position P2 and no channel is formed at the positions P1 and P3. That is, at the position P1 and the position P3, the threshold value of the transistor becomes higher than that at the position P2. Therefore, the effective channel width of the transistor becomes smaller than the distance between the element isolation portions. By having such an impurity concentration profile, the effective channel width can be made smaller than the distance between the element isolation portions 31.

  In this embodiment, the concentrations C1 and C3 are equal, but may be different. Further, the concentration C1 and the concentration C3 are preferably twice or more the concentration C2. More preferably, the concentration C1 and the concentration C3 are 10 times or more the concentration C2. With such a concentration relationship, the effective channel width can be reliably reduced in the operating voltage range.

  Although the semiconductor region 58b in the portion 601 has been described as being N-type in this embodiment, it may be P-type as long as the transistor M1 operates. That is, among the impurity concentrations at the positions P1, P2, and P3, the donor concentrations D1, D2, and D3 and the acceptor concentrations A1, A2, and A3 are set. Here, the densities D1, D2, D3, A1, A2, and A3 have a value of 0 or more. At that time, the relationship of the densities at the respective positions is D1-A1> D2-A2, D3-A3> D2-A2.

  Further, the position P1 is between the side surface of the trench of the element isolation portion 31 and the position P2 and can be said to be adjacent to the element isolation portion 31. The position P3 is between the side surface of the trench of the element isolation portion 31 and the position P2, and can be said to be adjacent to the element isolation portion 31. In this embodiment, it is assumed that the semiconductor region 52 extends from the side surface of the trench to a position of, for example, 20 nm at the depth of the line segment AB.

  Although this embodiment is applied to the load transistor of the SRAM type semiconductor memory, it may be applied to other transistors according to the characteristics. By applying the transistor having such a structure to the SRAM type semiconductor memory, the unit cell can be miniaturized.

(Example 2)
In this embodiment, a photoelectric conversion device 300 using the semiconductor memory of the first embodiment will be described. The present embodiment is a photoelectric conversion device in which the SRAM and the photoelectric conversion unit in which the photoelectric conversion element is arranged are provided on the same semiconductor substrate. Here, the photoelectric conversion unit is a CCD sensor, a CMOS sensor, or the like. The photoelectric conversion unit of this embodiment is a CMOS sensor having a photodiode as a photoelectric conversion element, a transfer transistor, and an amplification transistor.

  A method for manufacturing the photoelectric conversion device of this embodiment will be described with reference to FIGS. 4 to 6 are schematic cross-sectional views illustrating a method for manufacturing the photoelectric conversion device 300. The area 310 is an area in which the SRAM is formed and includes the areas 210 and 220 described in the first embodiment. The area 330 is an area in which the pixels of the photoelectric conversion unit are arranged. The pixel includes at least a photodiode and a transfer transistor. In the region 340, a processing circuit portion including a circuit for operating a pixel and a circuit for signal processing is arranged. The processing circuit unit includes, for example, a logic circuit and the like, and is also called a peripheral circuit in the imaging device. The area 340 has an area 350 and an area 360. A region 350 shows a region where N-type transistors are arranged, and a region 360 shows a region where P-type transistors are arranged.

  The process shown in FIG. 4A will be described. First, the substrate 30 is prepared. The substrate 30 is, for example, a silicon single crystal substrate, but may be a substrate after being processed. The substrate 30 has a region 310, a region 330, and a region 340. Next, the mask pattern 32 is formed on the substrate 30. The mask pattern 32 is a mask pattern for forming a groove serving as an element isolation portion. The mask pattern 32 has openings provided at arbitrary positions in each of the region 220, the region 210, the region 330, and the region 340. The opening of the mask pattern 32 exposes a portion of the surface S1 of the substrate 30 where a groove will be formed later. Then, the substrate 30 is etched using the mask pattern 32 as a mask to form the grooves 31a to 31d corresponding to the respective openings. The region 220 is provided with the groove 31a, the region 210 is provided with the groove 31b, the region 330 is provided with the groove 31c, and the region 340 is provided with the groove 31d. Here, the mask pattern 32 is made of, for example, an inorganic material such as a silicon nitride film or a silicon oxide film. As the mask pattern 32, a film of an inorganic material is formed on the substrate 30, a pattern made of an organic material is formed on the film of the inorganic material, and a part of the film of the inorganic material is removed by etching using the pattern as a mask. By doing so, it can be formed. In this embodiment, a silicon nitride film is used as the inorganic material. The pattern made of an organic material is, for example, a photoresist pattern.

  In FIG. 4B, the mask pattern 33 is formed on the mask pattern 32. The mask pattern 33 is a mask pattern for forming an N-type semiconductor region on the side surface and the bottom surface of the groove of the region 210. The mask pattern 33 covers the regions 220, 330, 340 and exposes the region 210. That is, the mask pattern 33 covers the grooves 31a, 31c and 31d and exposes the groove 31b. The mask pattern 33 has an opening 51 exposing the region 210. The opening 51 may expose at least the groove 31b in the region 210. Here, as described in the first embodiment, the region 210 is a portion where the load transistor of the SRAM is formed, and is a region where the P-type transistor is formed. The mask pattern 33 is formed of photoresist. The mask pattern 33 is formed by forming a film made of a photoresist on the mask pattern 32 and then performing exposure and development. Then, using the mask pattern 32 and the mask pattern 33 as masks, ion implantation 40 is performed on the substrate 30. The ion implantation 40 forms an N-type semiconductor region 52 along the side surface and the bottom surface of the trench. The ion species of the ion implantation 40 are impurity ions such as phosphorus (P) and arsenic (As) for forming an N-type semiconductor region. The implantation angle of the ion implantation 40 can be arbitrarily selected. In this embodiment, ion implantation is performed obliquely to the surface S1 of the substrate 30, and it is preferable that the ion implantation angle be selected to be about 10 degrees. Here, the ion implantation angle is an angle formed by the perpendicular of the surface S1 and the ion implantation direction. With such an implantation angle, ions can be efficiently implanted also into the side surface of the trench. In addition, the ion implantation 40 is performed by rotating the surface S1 by 360 degrees, so that the ion implantation can be performed on all side surfaces of the trench. After that, the mask pattern 32 is left and the mask pattern 33 is removed (not shown).

In FIG. 4C, the mask pattern 34 is formed on the mask pattern 32. The mask pattern 34 is a mask pattern for forming a P-type semiconductor region on the side surface and the bottom surface of the groove of the region 330. The mask pattern 34 covers the regions 210, 220, 340 and exposes the region 330. That is, the mask pattern 34 covers the grooves 31a, 31b and 31d and exposes the groove 31c. The mask pattern 34 has an opening 53 exposing the region 330. The opening 53 may expose at least the groove 31c in the region 330. The mask pattern 34 is formed of photoresist. The mask pattern 34 is formed by forming a film made of a photoresist on the mask pattern 32 and then performing exposure and development. Then, using the mask pattern 32 and the mask pattern 34 as masks, ion implantation 41 is performed on the substrate 30. By the ion implantation 41, a P-type semiconductor region 54 is formed along the side surface and the bottom surface of the trench. The ionic species of the ion implantation 41 are impurity ions such as boron (B) and boron fluoride (BF ₂ ) for forming a P-type semiconductor region. The implantation angle of the ion implantation 41 can be arbitrarily selected, but it is preferable to select about 10 degrees with respect to the surface S1 of the substrate 30. With such an implantation angle, ions can be efficiently implanted also into the side surface of the trench. Further, the ion implantation 41 is performed by rotating the surface S1 by 360 degrees, so that the ion implantation can be performed on all side surfaces of the trench.

  After that, the mask pattern 32 is left and the mask pattern 34 is removed. Then, the mask pattern 32 is removed and an insulator is embedded in the grooves 31a to 31d to form an element isolation portion. The insulator is, for example, silicon oxide or silicon nitride. For example, first, after removing the mask pattern 34 and before forming an insulating film, a heat treatment is performed to reduce damage caused in the groove. At that time, a film by thermal oxidation may be formed on the inner wall of the groove. An insulating film is formed by a high-density plasma CVD method or the like so as to cover the grooves 31a to 31d, and an excessive insulating film is removed by a polishing technique such as etching or CMP to remove the element isolation portion 31. Is formed. The element isolation portion 31 around which the semiconductor region 52 is formed is formed in the area 210, and the element isolation portion 31 around which the semiconductor region 54 is formed is formed in the area 330. In the regions 220 and 340, neither of the semiconductor regions 52 and 54 is formed around the element isolation portion 31. In addition, a silicon oxide film is formed on the surface S1 for a later process (not shown).

  In FIG. 5A, the mask pattern 35 is formed on the surface S1 of the substrate 30. The mask pattern 35 is a mask pattern for forming a P-type semiconductor region in the regions 220, 330, and 350. The P-type semiconductor region can function as a well in which an element is formed, for example. The mask pattern 35 covers the regions 210 and 360 and exposes the regions 320, 330 and 350. That is, the mask pattern 35 has openings 55a, 55c, and 55d that expose the regions 320, 330, and 350. The mask pattern 35 is formed of photoresist and is formed by the same method as other mask patterns. Then, using the mask pattern 35 as a mask, ion implantation 42 is performed on the substrate 30. The ion implantation 42 forms P-type semiconductor regions 56a, 56c, and 56d. The ion species of the ion implantation 42 is the same as that of the ion implantation 41. The implantation angle of the ion implantation 42 can be arbitrarily selected. Note that since the region 330 is a region where a photoelectric conversion element is formed, additional ion implantation is performed in order to form an appropriate well for the photoelectric conversion element, and the well of the region 330 is formed as the regions 220 and 340. May be formed in another step. Then, the mask pattern 35 is removed (not shown).

  In FIG. 5B, the mask pattern 36 is formed on the surface S1 of the substrate 30. The mask pattern 36 is a mask pattern for forming an N-type semiconductor region in the regions 210 and 360. This N-type semiconductor region can function as a well in which an element is formed, for example. The mask pattern 36 covers the regions 220, 330 and 350 and exposes the regions 210 and 360. The mask pattern 36 has openings 57b and 57d that expose the regions 210 and 360. The mask pattern 36 is formed of photoresist and is formed by the same method as other mask patterns. Then, using the mask pattern 36 as a mask, ion implantation 43 is performed on the substrate 30. The ion implantation 43 forms N-type semiconductor regions 58b and 58d. The ion species of the ion implantation 43 is the same as that of the ion implantation 40. The implantation angle of the ion implantation 43 can be arbitrarily selected. Then, the mask pattern 36 is removed (not shown).

  In FIG. 5C, the mask pattern 37 is formed on the surface S1 of the substrate 30. The mask pattern 37 is a mask pattern for forming the P-type semiconductor region 60 in the region 210. The P-type semiconductor region 60 can be provided for adjusting the threshold value of the transistor. The mask pattern 37 covers the region 220, the region 330, and the region 340, and exposes the region 210. The mask pattern 37 has an opening 59 exposing the region 210. The mask pattern 37 is formed of photoresist and is formed by the same method as other mask patterns. Then, using the mask pattern 37 as a mask, ion implantation 44 is performed on the substrate 30. A P-type semiconductor region 60 is formed by the ion implantation 44. The ion species of the ion implantation 44 is the same as that of the ion implantation 41. The implantation angle of the ion implantation 44 can be arbitrarily selected. Then, the mask pattern 37 is removed (not shown).

  In FIG. 6A, the mask pattern 38 is formed on the surface S1 of the substrate 30. The mask pattern 38 is a mask pattern for forming the N-type semiconductor region 62 in the region 220. The N-type semiconductor region 62 can be provided for adjusting the threshold value of the transistor. The mask pattern 38 covers the region 210, the region 330, and the region 340, and exposes the region 220. The mask pattern 38 has an opening 61 that exposes the region 210. The mask pattern 38 is made of photoresist and is formed by the same method as other mask patterns. Then, using the mask pattern 38 as a mask, ion implantation 45 is performed on the substrate 30. The N-type semiconductor region 62 is formed by the ion implantation 45. The ion species of the ion implantation 45 is the same as that of the ion implantation 40. The implantation angle of the ion implantation 45 can be arbitrarily selected. Then, the mask pattern 38 is removed (not shown).

  Here, in the circuit formed in the region 340, a transistor having a low threshold value is generally used in order to speed up the operation. On the other hand, in the circuit and SRAM formed in the region 310, a transistor having a relatively high threshold value is used in order to stabilize the circuit operation. Therefore, in this embodiment, by adding the steps shown in FIGS. 5C and 6A, the transistors in the regions 310 and 340 can be manufactured in the same process. With such a manufacturing method, the photoelectric conversion device can be manufactured at low cost. Note that the steps shown in FIGS. 5C and 6A may be applied to the transistors in the regions 330 and 340.

  FIG. 6B shows a state in which an element has been formed after the step described with reference to FIG. A P-type transistor is formed in the region 210, an N-type transistor is formed in the region 220, an N-type transistor and a photoelectric conversion element are formed in the region 330, and an N-type transistor is formed in the region 340. A P-type transistor is formed. A transistor or a photoelectric conversion element can be formed by forming a gate electrode or ion implantation. After that, an interlayer insulating film, a contact plug, and a wiring layer are formed, and a color filter, a microlens, and the like are formed, so that a photoelectric conversion device is formed. When the photoelectric conversion device is of the backside illumination type, the substrate 30 may be thinned and element isolation may be formed on the backside. As described above, the photoelectric conversion device is formed through the steps shown in FIGS.

  Here, conditions of ion implantation relating to characteristics of the transistor in the region 210 will be described. The ion implantation 40 and the ion implantation 44 have a great influence on the characteristics of the transistor. Here, the dose of the ion implantation 40 is larger than the dose of the ion implantation 44. This is because the above-mentioned relation of impurity concentration is satisfied. With such a manufacturing method, a channel is not formed in the semiconductor region 52 located below the gate electrode of the transistor, and the effective channel width of the transistor can be narrowed.

  The mask pattern 32 shown in FIG. 4A may be formed of photoresist. In that case, for example, the mask pattern 32 made of photoresist is irradiated with ultraviolet rays to cure the photoresist. By forming the mask pattern 32 of photoresist in this manner, the mask pattern 33 can be removed while leaving the mask pattern 32 in the step of FIG. 4B. By forming the mask pattern 32 with a photoresist, it is possible to reduce the time required for dry etching for removing the mask pattern 32, etc., as compared with the case where the mask pattern 32 is formed with an inorganic material.

(Example 3)
In this embodiment, a modification of the photoelectric conversion device 300 using the semiconductor memory of Embodiment 2 will be described with reference to FIG. 7. FIG. 7 is a schematic sectional view illustrating the method for manufacturing the photoelectric conversion device of this example.

  In this embodiment, the polarity of the photoelectric conversion element of the second embodiment is changed. That is, the semiconductor region 54 in FIG. 6B is an N-type semiconductor region having the same polarity as the semiconductor region 52. With such a configuration, as shown in FIG. 7, the steps of forming the semiconductor region 52 and the semiconductor region 54 can be the same step. The step of forming includes a step of forming a mask pattern and an ion implantation step. According to this embodiment, it is possible to form the photoelectric conversion device having the SRAM with fewer steps.

(Example 4)
In this example, a modification of the photoelectric conversion device 300 using the semiconductor memory of Example 2 will be described. FIG. 8 is a schematic cross-sectional view of the photoelectric conversion device of this example. In this embodiment, the N-type semiconductor region 801 is provided for the transistor in the region 360. The semiconductor region 801 has the same function as the semiconductor region 52 of the second embodiment. With such a structure, the transistor can be miniaturized. Further, the configuration of the present transistor reduces noise such as random telegraph noise (hereinafter RTN) due to the channel of the transistor. In addition to the photoelectric conversion device, it can be applied to a CMOS circuit that is a circuit in which RTN should be taken into consideration.

(Example 5)
In this embodiment, a photoelectric conversion device to which a suitable transistor is applied will be described. Before the description of the photoelectric conversion device, a noise-reduced transistor will be described in detail with reference to FIGS.

  FIG. 9 is a schematic diagram for explaining an example in which the semiconductor region 52 shown in FIG. 3B is not included. FIG. 9A is a schematic cross-sectional view of the transistor corresponding to FIG. 9B is a diagram corresponding to FIG. 3C and showing the impurity concentration of the N-type semiconductor region in the line segment AB of FIG. 9A. 9, the same components as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. The transistor of the comparative example shown in FIG. 9A does not have the semiconductor region 52 shown in FIG. Therefore, the impurity concentration in the line segment AB of FIG. 9A shown in FIG. 9B is constant at the concentration C2. The difference between the maximum and the minimum change in the impurity concentration of the P-type semiconductor region 58b in the line segment AB in FIG. 9A corresponds to the change in the impurity concentration in the P-type semiconductor region in the line segment AB in FIG. 3B. Less than the difference between maximum and minimum. The difference between the maximum and minimum changes in the impurity concentration of the P-type semiconductor region along the line segment AB in FIG. 3B can be said to be the difference between the impurity concentrations of the semiconductor region 52 and the semiconductor region 58b. Here, the effective channel width of the transistor of the comparative example is W3. The effective channel width of the transistor described in FIG. 3 is W2, whereas the effective channel width of the transistor of the comparative example is W3. The width relationship is W3 = W1> W2. In the following description, assuming that the transistor shown in FIG. 3 is the first type transistor, the transistor shown in FIG. 9 is the second type transistor.

  The reverse narrow channel effect may occur in the transistor arranged close to the element isolation portion 31 having the STI structure. The inverse narrow channel effect means the following transistor operation. The channel end portion along the channel width direction of the transistor is adjacent to the STI structure. The electric field generated by the gate electrode is concentrated at the end of the channel. As a result, the threshold value of the transistor decreases at the channel end. Here, when the transistor is driven, a drain current flows. That is, in the configuration of FIG. 9, the drain current concentrates on the channel end having a low threshold value. In the vicinity of the element isolation portion 31, oxygen deficiency occurs in the semiconductor substrate. In the region where oxygen is deficient, the electron trapping and releasing phenomenon as carriers may frequently occur. If the drain current is concentrated in the channel end portion, that is, in the vicinity of the element isolation portion 31, the value of RTN may increase, that is, deteriorate. That is, in the second type transistor shown in FIG. 9, the RTN is superimposed on the signal depending on the place of use. In the case of the photoelectric conversion device, such a current situation may cause deterioration in image quality, for example, an image looks like a linear scratch due to noise. The RTN characteristic of the first type transistor is improved as compared with the second type transistor, and the second type transistor can be manufactured with a smaller number of steps as compared with the first type transistor, and the effective channel length is long, so that driving is possible. It is possible to improve power. Next, a suitable arrangement of transistors in the photoelectric conversion device will be described.

  FIG. 10 is a block diagram showing the configuration of the photoelectric conversion device. The unit cell unit 1000 has a plurality of unit cells 1001. The unit cells 1001 are arranged two-dimensionally. The unit cell 1001 may be referred to as a pixel in the photoelectric conversion device. The unit cell 1001 has, for example, a pixel configuration of a CMOS photoelectric conversion device. The vertical scanning circuit 1002 outputs a control signal for driving each unit cell 1001. The control line 1012 electrically connects the vertical scanning circuit 1002 and each unit cell 1001 and supplies a control signal to the element of each unit cell 1001. In FIG. 10, one control line 1012 is arranged for a plurality of unit cells 1001 arranged in each row, but in reality, it is assumed that a plurality of control lines 1012 are arranged in each row. The plurality of cells is the number required to control the unit cell 1001. A signal from the unit cell 1001 is output to the signal line 1013. At least one signal line 1013 is electrically connected to the plurality of unit cells 1001 arranged in each column. The signal line 1013 is electrically connected to the signal reading unit 1014.

  The signal reading unit 1014 includes a current source circuit 1003, a signal amplification circuit 1004, an AD conversion circuit 1005, and a memory circuit 1007. The current source circuit 1003 supplies a constant current for reading the signal of the unit cell 1001 to the signal line 1013. The signal line 1013 is electrically connected to the signal amplifier circuit 1004. The signal amplifier circuit 1004 amplifies the signal input from the signal line 1013. The AD conversion circuit 1005 converts the analog signal from the signal amplification circuit 1004 into a digital signal. The ramp generation circuit 1006 generates a reference signal to be compared with the signal to be AD converted by the AD conversion circuit 1005. The counter circuit 1008 outputs a count value. The memory circuit 1007 holds the count value output from the counter circuit 1008. The horizontal scanning circuit 1015 supplies a control signal for transferring the value held in the memory circuit 1007 to the signal processing circuit 1010. The signal output circuit 1011 outputs the signal processed by the signal processing circuit 1010 to the outside of the photoelectric conversion device. The drive control of these circuits is performed based on the control signal from the timing generator (TG) 1009. Note that circuits such as the signal amplifier circuit 1004 and the AD converter circuit 1005 can be omitted or changed as appropriate. Here, a portion where circuits other than the unit cell portion 1000 are arranged may be referred to as a peripheral circuit portion.

  FIG. 11 is an equivalent circuit diagram for explaining the photoelectric conversion device. FIG. 11 shows a read path of the photoelectric conversion device. FIG. 11 shows the configuration of the unit cell 1001, the current source circuit 1003, the signal amplification circuit 1004, and the AD conversion circuit 1005 shown in FIG. The unit cell 1001 includes a photodiode (hereinafter, PD) 1101, a transfer transistor 1102, a floating diffusion portion (hereinafter, FD) 1104, a reset transistor 1103, an amplification transistor 1105, and a selection transistor 1106. The PD 1101 functions as a photoelectric conversion unit that photoelectrically converts light incident through the optical system. The anode of the PD 1101 is grounded, and the cathode is connected to the source of the transfer transistor 1102. The transfer transistor 1102 is driven by the control signal TX input to its gate, and transfers the charge generated in the PD 1101 to the FD 1104. The FD 1104 temporarily accumulates electric charges, and also functions as a charge-voltage conversion unit that converts the accumulated charges into a voltage signal. The amplification transistor 1105 constitutes a source follower amplifier together with the current source circuit 1003. To the gate of the amplification transistor 1105, the electric signal which has been subjected to charge voltage conversion by the FD 1104 is input. The drain of the amplification transistor 1105 is connected to the power supply voltage VDD and the source thereof is connected to the selection transistor 1106. The reset transistor 1103 electrically connects the FD 1104 and the power supply voltage VDD. When the reset transistor 1103 is turned on by the control signal RES, the charge of the FD 1104 is discharged to the power supply voltage VDD and reset. Here, the power supply voltage VDD can also be referred to as a reference voltage. The selection transistor 1106 electrically connects the amplification transistor 1105 and the signal line 1107. When the corresponding row is selected at a certain time, the control signal SEL becomes high level. The selection transistor 1106 supplied with the high-level control signal SEL is turned on, and the signal from the amplification transistor 1105 is output to the signal line 1107. These transistors of the unit cell 1001 are N-type transistors. A constant current is supplied to the signal line 1107 to form a source follower amplifier.

  The current source circuit 1003 includes three N-type transistors 1108-1110. The three transistors 1108 to 1110 are provided so as to be directly connected between the signal line 1107 and the ground voltage GND. The transistors 1109 and 1110 are cascode-connected and function as a current source. The transistor 1108 functions as a switch for turning on and off the current source. The control signal V1108 is supplied to the gate of the transistor 1108. When the control signal V1108 becomes high level, a constant current is supplied to the signal line 1107, and when the control signal V1108 becomes low level, the supply of constant current to the signal line 1107 is stopped. The control signal V1109 is supplied to the gate of the transistor 1109, and the control signal V1110 is supplied to the gate of the transistor 1110. The control signal V1109 and the control signal V1110 are fixed bias voltages that determine the operating points of the transistors 1109 and 1110, respectively.

  The output of the source follower amplifier formed by the amplification transistor 1105 is input to the signal amplification circuit 1004. The signal amplifier circuit 1004 includes an inverting amplifier 1112, an input capacitor 1111, a feedback capacitor 1114, a switch 1113, and a switch 1115. The amplification degree of the signal can be changed by selecting or deselecting the feedback capacitor 1114 using the switch 1113 and changing the capacitance value. Further, the amplification degree of the signal may be changed by changing the position of the switch 1113 and changing the capacitance value of the input capacitance 1111. The switch 1115 resets the inverting amplifier 1112 and the input capacitor 1111 feedback capacitor 1114. The signal amplified by the signal amplification circuit 1004 is AD-converted by the AD conversion circuit 1005.

Here, the relationship between the current flowing through the signal line 1107 and the signal will be described. First, the change amount ΔVvl of the voltage Vvl of the signal line 1107 when the current Ivl flowing through the signal line 1107 changes by ΔIvl is obtained. When β is the current parameter of the amplification transistor 1105, Vvl and ΔVvl are expressed by the equations (1) and (2).
Vvl = Vfd−Vth−√2Ivl / β ... Formula (1)
ΔVvl = −√2ΔIvl / β Equation (2)
From the equation (2), it is understood that the voltage Vvl changes when the current Ivl of the signal line 1107 changes. That is, the current Ivl causes the fluctuation of the voltage Vvl. Here, since the optical signal from the PD 1101 and the reference reset signal appear in the voltage Vvl, it is desirable that the voltage Vvl does not change due to other factors. If the voltage Vvl fluctuates, the fluctuation will be superimposed on the voltage indicating the signal, resulting in noise. That is, it is desirable that the current Ivl is a constant current with little fluctuation. Therefore, as described with reference to FIGS. 3 and 9, it is desirable to apply the first type N-type transistor having a constant drain current to the transistors 1109 and 1110 that form the current source. With such a configuration, the current ΔIvl and the voltage ΔVvl can be reduced, and the deterioration of the signal due to RTN can be reduced.

(Example 6)
The photoelectric conversion device of this embodiment will be described with reference to FIG. FIG. 12 is an equivalent circuit diagram illustrating the photoelectric conversion device of this embodiment. FIG. 12 shows the inverting amplifier 1112 of the signal amplification circuit 1004 shown in FIGS. The inverting amplifier 1112 includes at least five transistors 1201 to 1205. The P-type transistor 1202 and the P-type transistor 1203 are cascode-connected to form a current source circuit. This current source supplies a constant current of 6 μA, for example. The control signal V1202 and the control signal V1203 are supplied to the gates of the transistors 1202 and 1203, respectively, and are fixed bias voltages that determine the operating points of the transistors. The P-type transistor 1201 functions as a switch for turning on and off the current source circuit. The control signal V1201 is supplied to the gate of the transistor 1201 and controls on / off of the transistor 1201. The N-type transistor 1204 is a grounded-gate transistor. The control signal V1204 is a fixed bias voltage that determines the operating point. The N-type transistor 1205 is a source-grounded transistor. The input signal Vampi is input to the gate of the transistor 1205 instead of the control signal. The output signal Vampo of the inverting amplifier 1112 is output to the common node of the transistors 1204 and 1203.

  Here, the gain Ao of the inverting amplifier 1112 is represented by Expression (3).

  Here, the mutual conductance gm and the output resistance R of the source-grounded N-type transistor 1205 are set. If the RTN of the transistor 1202 or the transistor 1203 deteriorates, the drain current of the transistor 1205 changes and the transconductance gm of the transistor 1205 changes. As a result, the gain Ao changes as shown in Expression (3). This means that, if a constant signal is input, the signal amplified by one inverting amplifier 1112 may vary in signal size depending on the amplification timing (time). Further, when there are a plurality of inverting amplifiers 1112, even if a constant signal is input, the magnitudes of the plurality of amplified signals may vary. Therefore, it is desirable to apply a P-type first type transistor to the P-type transistor 1202 and the P-type transistor 1203 that form the current source circuit. Further, control signals V1204 and V1205 that determine operating points are input to the gates of the transistors 1204 and 1205. Even in such a transistor, a change in drain current causes a change in operation, and thus it is desirable to apply the first type transistor. That is, it is preferable to apply an N-type first type transistor to the N-type transistor 1204 and the N-type transistor 1205. As in this embodiment, in the signal amplifier circuit 1004, at least the transistors 1202 and 1203 are the first type transistors, so that signal deterioration can be suppressed.

(Example 7)
The photoelectric conversion device of this embodiment will be described with reference to FIG. FIG. 13 is an equivalent circuit diagram illustrating the photoelectric conversion device of this embodiment. FIG. 13 shows the AD conversion circuit 1005 shown in FIGS. 10 and 11. The AD conversion circuit 1005 includes at least a comparator 1300. The comparator 1300 includes transistors 1301 to 1307. The P-type transistor 1301 and the P-type transistor 1302 are cascode-connected to form a current source circuit. The P-type transistor 1303 can function as a switch for turning on or off the current source circuit. The control signal V1303 is supplied to the gate of the transistor 1303 and controls the conduction of the transistor 1303. The P-type transistor 1304 functions as an input transistor. The ramp signal output from the ramp generation circuit 1006 illustrated in FIG. 10 is input to the gate of the transistor 1304. The P-type transistor 1305 functions as an input transistor. The amplified signal Vampo output from the signal amplifier circuit 1004 illustrated in FIG. 10 is input to the gate of the transistor 1305. In FIG. 13, the gate of the transistor 1304 is shown as the input terminal INN, and the gate of the transistor 1305 is shown as the input terminal INP. The drain of the transistor 1304 is electrically connected to the drain of the N-type transistor 1306, and the drain of the transistor 1305 is electrically connected to the drain of the N-type transistor 1307. The comparator 1300 of such a circuit outputs the result of comparing the signal voltage Vampo caused by the optical signal with the ramp signal serving as the reference signal. The output is output to a node where the transistor 1305 and the transistor 1307 are connected to each other, and the comparison result may be affected if the current value changes in the current source circuit through the capacitance and the latch circuit logic circuit. Therefore, it is preferable to apply a first type transistor to at least the transistor 1301 and the transistor 1302 of the comparator 1300. Further, a first type transistor may be applied to the transistors 1304 to 1307. As in this embodiment, in the AD conversion circuit 1005, by applying the first type transistor to at least the transistors 1202 and 1203, signal deterioration can be suppressed.

(Example 8)
In each of Examples 5 to 7, the details of the circuit in which it is desirable to provide the first type transistor in the photoelectric conversion device have been described. In this embodiment, description is made on which part of the photoelectric conversion device the transistor of the first type is provided. FIG. 14 is a table illustrating the photoelectric conversion device according to this embodiment. FIG. 14 shows a portion where it is desirable to apply the transistor of the first type in each block of the photoelectric conversion device shown in FIG. When the block described in the block name column includes the transistor of the first type, “◯” is added to the column of the transistor of the first type, and when not included, the column of the transistor of the first type is added. First, by applying the first type transistor to the unit cell section 1000, it is possible to reduce the influence of dark current (leakage current) generated around the element isolation section on the PD. Further, as described in the fifth to seventh embodiments, in the signal reading unit, the first portion is provided at a position where noise may be superimposed on the signal of at least one circuit of the current source circuit 1003, the signal amplification circuit 1004, and the AD conversion circuit 1005. It is desirable to apply a class of transistors. Preferably, it is desirable to apply the first type transistor to a place where noise may be superimposed on the signals of the three circuits.

  On the other hand, in the circuit of the signal reading unit, it is preferable to apply not the first type transistor but the second type transistor to the transistor used in the completely ON state, for example, the transistor functioning as a switch. The control signal for turning on / off the transistor functioning as a switch is, for example, the ground voltage GND in the case of a P-type transistor and the power supply voltage Vdd in the case of an N-type transistor. Since a uniform inversion region is generated in the channel of the transistor to which such a control signal is supplied, it is difficult for the current to concentrate and flow at the channel end near the element isolation portion. Therefore, even if the transistor of the second class is used instead of the transistor of the first class, the RTN is unlikely to increase, so that it can be applied. In the second type transistor, the semiconductor regions 52 and 54 of opposite conductivity type to the polarity of the transistor are not provided. That is, a PN junction interface with the semiconductor region 52 or the semiconductor region 54 of the conductivity type opposite to the source and drain of the transistor is not formed. Therefore, it is possible to suppress a decrease in breakdown voltage due to the PN junction. Further, if the effective channel width of the transistor is reduced, the resistance of the transistor when it is turned on is increased, which may cause a reduction in driving speed. Therefore, it is desirable to apply the second type transistor instead of the first type transistor in a circuit that requires high speed driving. The circuits that require high speed driving include the vertical scanning circuit 1002, the ramp generation circuit 1006, the memory circuit 1007, the horizontal scanning circuit 1015, the counter circuit 1008, the TG 1009, the signal processing circuit 1010, the signal output circuit 1011 and the like.

  As shown in this embodiment, in a device such as a photoelectric conversion device in which noise superimposed on a signal is desired to be reduced, by applying the first type transistor in at least one circuit of the reading circuit portion, It is possible to reduce the superimposed noise.

(Example 9)
This embodiment shows a modification of the inverting amplifier 1112 of FIG. 11 described in the fifth embodiment. In this embodiment, the inverting amplifier 1112 is changed from a single input amplifier to a differential amplifier. The other structure of the present embodiment is the same as the structure described in the fifth embodiment.

  FIG. 15 is an equivalent circuit diagram illustrating the photoelectric conversion device according to the present embodiment. FIG. 15 shows the inverting amplifier 1112. The inverting amplifier 1112 is a differential amplifier. The P-type transistor 1501, the P-type transistor 1502, the N-type transistor 1503, and the N-type transistor 1504 form a differential pair. The N-type transistor 1506 constitutes a current source circuit. The N-type transistor 1505 functions as a switch for turning on and off current. The signal is input as the voltage Vampi to the input terminal which is the gate of the transistor 1504. The reference signal Vref is input to the other input terminal. The difference between the voltages input to the two input terminals is amplified and output from the output terminal as the voltage Vampo. Here, as described in the fifth embodiment, when the RTN of the transistor deteriorates, the amount of current in the differential amplifier changes. At that time, if the balance of the currents flowing through the differential pair is lost, the voltage Vampo which is the output signal fluctuates. Here, by configuring the differential amplifier with the first type transistors, RTN can be reduced and the quality of signals can be improved. In addition, as the transistor 1505 which functions as a switch, a second type transistor is preferably used.

  The configuration of this embodiment also makes it possible to provide a photoelectric conversion device with reduced noise.

(Example 10)
In this embodiment, an example of a photoelectric conversion device will be described. The photoelectric conversion device of this embodiment is configured by stacking at least two semiconductor substrates for stacking in a state of being electrically connected. Such a photoelectric conversion device is also referred to as a stacked photoelectric conversion device. Here, the semiconductor substrate may be referred to as a member or a chip.

  FIG. 16 is a schematic diagram of the photoelectric conversion device 3000 of this embodiment, and is an exploded perspective view of the photoelectric conversion device 3000. A pixel region 3011 is provided on one semiconductor substrate 3010. A controller 3021 and a signal processor 3022 are provided on another semiconductor substrate 3020. The pixel region 3011 is a photoelectric conversion unit in which unit cells including photoelectric conversion elements are arranged. The signal processing unit 3022 is provided with the semiconductor memory described in the first embodiment and the like. At least a part of the orthogonal projections of the control unit 3021 and the signal processing unit 3022 on the semiconductor substrate 3010 overlap with the pixel region 3011. The photoelectric conversion device 3000 of this embodiment may further include a semiconductor substrate having another processing circuit, or may include three or more stacked semiconductor substrates.

  The control unit 3021 may include a vertical scanning circuit that supplies a driving signal to the pixels and a power supply circuit. Further, the control unit 3021 may include a timing generation circuit for driving the photoelectric conversion device, a reference signal supply circuit for supplying a reference signal to the conversion circuit, and a horizontal scanning circuit for sequentially reading signals from the amplification circuit or the conversion circuit. .

  The signal processing unit 3022 processes an electric signal based on the signal charge generated in the pixel area. The signal processing unit 3022 can include a noise removal circuit, an amplification circuit, a conversion circuit, and an image signal processing circuit. The noise removing circuit is, for example, a correlated double sampling (CDS) circuit. The amplifier circuit is, for example, a column amplifier circuit. The conversion circuit is, for example, an analog-digital conversion (ADC) circuit including a comparator and a counter. The image signal processing circuit includes, for example, a memory and a processor and generates image data from an analog-digital converted digital signal or performs image processing on the image data.

  The present invention can be applied to a photoelectric conversion device in which a plurality of semiconductor substrates are laminated as in this embodiment.

(Example 11)
FIG. 17 is a block diagram showing the configuration of the image pickup system 3100 according to the present embodiment. The imaging system 3100 of this embodiment includes the photoelectric conversion device 3104 described in the above embodiments. Here, as the photoelectric conversion device 3104, any of the photoelectric conversion devices described in the above embodiments can be applied. Specific examples of the imaging system 3100 include a digital still camera, a digital camcorder, a surveillance camera, and the like. In FIG. 10, an example of a digital still camera is shown as the imaging system 3100.

  The imaging system 3100 illustrated in FIG. 10 includes a photoelectric conversion device 3104, a lens 3102 for forming an optical image of a subject on the photoelectric conversion device 3104, a diaphragm 3103 for varying the amount of light passing through the lens 3102, and protection of the lens 3102. Have a barrier 3101 for. The lens 3102 and the diaphragm 3103 are an optical system that collects light on the photoelectric conversion device 3104.

  The imaging system 3100 includes a signal processing unit 3105 that processes an output signal output from the photoelectric conversion device 3104. The signal processing unit 3105 performs a signal processing operation of performing various corrections and compressions on the input signal as necessary and outputting the corrected signal. The imaging system 3100 further includes a buffer memory unit 3106 for temporarily storing image data, and an external interface unit (external I / F unit) 3109 for communicating with an external computer or the like. Furthermore, the imaging system 3100 includes a recording medium 3111 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 3110 for recording or reading on the recording medium 3111. Have. The recording medium 3111 may be built in the imaging system 3100 or may be removable. Further, the communication from the recording medium control I / F unit 3110 to the recording medium 3111 and the communication from the external I / F unit 3109 may be performed wirelessly.

  Further, the imaging system 3100 has an overall control / arithmetic unit 3108 for performing various arithmetic operations and controlling the entire digital still camera, a photoelectric conversion device 3104, and a timing generation unit 3107 for outputting various timing signals to the signal processing unit 3105. Here, a timing signal or the like may be input from the outside, and the imaging system 3100 may include at least the photoelectric conversion device 3104 and a signal processing unit 3105 which processes an output signal output from the photoelectric conversion device 3104. . The timing generator 3107 may be mounted on the photoelectric conversion device as described in the sixth embodiment. The overall control / arithmetic unit 3108 and the timing generation unit 3107 may be configured to perform some or all of the control functions of the photoelectric conversion device 3104.

  The photoelectric conversion device 3104 outputs the image signal to the signal processing unit 3105. The signal processing unit 3105 performs predetermined signal processing on the image signal output from the photoelectric conversion device 3104 and outputs image data. The signal processing unit 3105 also generates an image using the image signal. The signal processing unit 3105 and the timing generation unit 3107 may be mounted on the photoelectric conversion device. That is, the signal processing unit 3105 and the timing generation unit 3107 may be provided on the substrate on which the pixels are arranged, or may be provided on another substrate as shown in FIG. By configuring an image pickup system using the photoelectric conversion device of each of the above-described embodiments, it is possible to realize an image pickup system capable of obtaining a higher quality image.

(Example 12)
The moving body of this embodiment will be described with reference to FIGS. 18 and 19. FIG. 18 is a schematic diagram showing a configuration example of the moving body according to the present embodiment. FIG. 19 is a flowchart showing the operation of the image pickup system mounted on the moving body according to the present embodiment. In this embodiment, an example of an in-vehicle camera is shown as an imaging system. In the following description, the image pickup device is the photoelectric conversion device according to any one of the above-described embodiments.

  FIG. 18A shows an example of a vehicle system and an image pickup system mounted on the vehicle system. The imaging system 3201 includes an imaging device 3202, an image preprocessing unit 3215, an integrated circuit 3203, and an optical system 3214. The optical system 3214 forms an optical image of a subject on the imaging device 3202. The imaging device 3202 converts the optical image of the subject formed by the optical system 3214 into an electric signal. The image preprocessing unit 3215 performs predetermined signal processing on the signal output from the imaging device 3202. The function of the image preprocessing unit 3215 may be incorporated in the imaging device 3202. The imaging system 3201 is provided with at least two sets of an optical system 3214, an imaging device 3202, and an image preprocessing unit 3215, and an output from each set of the image preprocessing unit 3215 is input to the integrated circuit 3203. Has become.

  The integrated circuit 3203 is an integrated circuit for an imaging system application, and includes an image processing unit 3204 including a memory 3205, an optical distance measuring unit 3206, a parallax calculation unit 3207, an object recognition unit 3208, and an abnormality detection unit 3209. The image processing unit 3204 performs image processing such as development processing and defect correction on the output signal of the image preprocessing unit 3215. The memory 3205 stores the primary storage of the captured image and the defective position of the captured pixel. The optical distance measuring unit 3206 performs focusing of a subject and distance measurement. The parallax calculation unit 3207 calculates parallax information (phase difference of parallax images) from the plurality of image data acquired by the plurality of imaging devices 3202. The object recognition unit 3208 recognizes objects such as cars, roads, signs, and people. When the abnormality detection unit 3209 detects an abnormality in the imaging device 3202, the abnormality detection unit 3209 reports the abnormality to the main control unit 3213.

  The integrated circuit 3203 may be realized by specially designed hardware, a software module, or a combination thereof. Further, it may be realized by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like, or may be realized by a combination thereof.

  The main controller 3213 centralizes and controls the operations of the imaging system 3201, the vehicle sensor 3210, the control unit 3220, and the like. A method in which the main control unit 3213 is not provided and the imaging system 3201, the vehicle sensor 3210, and the control unit 3220 individually have a communication interface, and each transmits and receives a control signal via a communication network (for example, CAN standard). Can also be taken.

  The integrated circuit 3203 has a function of receiving a control signal from the main controller 3213 or transmitting a control signal or a set value to the imaging device 3202 by its own controller.

  The imaging system 3201 is connected to the vehicle sensor 3210 and can detect the running state of the vehicle such as the vehicle speed, the yaw rate, and the steering angle, and the environment outside the vehicle and the states of other vehicles and obstacles. The vehicle sensor 3210 is also a distance information acquisition unit that acquires distance information from the parallax image to the object. The imaging system 3201 is also connected to a driving assistance control unit 3211 that performs various driving assistance such as automatic steering, automatic cruising, and a collision prevention function. In particular, regarding the collision determination function, the collision estimation / presence / absence of collision with another vehicle / obstacle is determined based on the detection results of the imaging system 3201 and the vehicle sensor 3210. As a result, avoidance control when a collision is estimated and safety device activation at the time of collision are performed.

  The imaging system 3201 is also connected to an alarm device 3212 that issues an alarm to the driver based on the determination result of the collision determination unit. For example, when there is a high possibility of collision as a result of the collision determination unit, the main control unit 3213 performs vehicle control for avoiding a collision and reducing damage by applying a brake, returning an accelerator, suppressing an engine output, or the like. To do. The alarm device 3212 sounds a warning such as a sound, displays alarm information on a screen of a display unit such as a car navigation system or a meter panel, and gives a warning to the user by vibrating a seat belt or a steering wheel.

  In this embodiment, the image capturing system 3201 captures an image around the vehicle, for example, the front or the rear. FIG. 18B shows an arrangement example of the imaging system 3201 when the imaging system 3201 images the front of the vehicle.

  The two imaging devices 3202 are arranged in front of the vehicle 3200. Specifically, if the center line with respect to the advancing / retreating direction or the outer shape (for example, the vehicle width) of the vehicle 3200 is regarded as the axis of symmetry and the two image pickup devices 3202 are arranged in line symmetry with respect to the axis of symmetry, the vehicle 3200 and the object of This is preferable for obtaining distance information with the object to be photographed and for determining the possibility of collision. Further, the image pickup device 3202 is preferably arranged so as not to obstruct the driver's visual field when the driver visually recognizes the situation outside the vehicle 3200 from the driver's seat. The alarm device 3212 is preferably arranged so that it can be easily seen by the driver.

  Next, the failure detection operation of the imaging device 3202 in the imaging system 3201 will be described with reference to FIG. The failure detection operation of the imaging device 3202 is performed according to steps S3310 to S3380 shown in FIG.

  Step S3310 is a step of making settings at startup of the image pickup apparatus 3202. That is, the setting for the operation of the imaging device 3202 is transmitted from the outside of the imaging system 3201 (for example, the main control unit 3213) or the inside of the imaging system 3201, and the imaging operation and the failure detection operation of the imaging device 3202 are started.

  Next, in step S3320, a pixel signal is acquired from the effective pixel. Further, in step S3330, the output value from the failure detection pixel provided for failure detection is acquired. This failure detection pixel includes a photoelectric conversion unit like the effective pixel. A predetermined voltage is written in this photoelectric conversion unit. The failure detection pixel outputs a signal corresponding to the voltage written in this photoelectric conversion unit. Note that steps S3320 and S3330 may be reversed.

  Next, in step S3340, the non-determination is performed between the expected output value of the failure detection pixel and the actual output value of the failure detection pixel. As a result of the non-judgment in step S3340, if the expected output value and the actual output value match, the process proceeds to step S3350, it is determined that the imaging operation is normally performed, and the processing step proceeds to step S3360. And transition. In step S3360, the pixel signal of the scanning row is transmitted to the memory 3205 and temporarily stored. After that, it returns to step S3320 and continues the failure detection operation. On the other hand, as a result of the non-judgment in step S3340, if the output expected value and the actual output value do not match, the processing step proceeds to step S3370. In step S3370, it is determined that the imaging operation is abnormal, and an alarm is issued to the main controller 3213 or the alarm device 3212. The alarm device 3212 displays on the display unit that the abnormality is detected. After that, in step S3380, the imaging apparatus 3202 is stopped, and the operation of the imaging system 3201 ends.

  In the present embodiment, the example in which the flowchart is looped for each row is illustrated, but the flowchart may be looped for each plurality of rows, or the failure detection operation may be performed for each frame. Note that the alarm issuance in step S3370 may be notified to the outside of the vehicle via a wireless network.

  Further, in the present embodiment, the control that does not collide with another vehicle has been described, but it is also applicable to a control that automatically drives by following another vehicle, a control that automatically drives the vehicle so that it does not protrude from the lane, and the like. . Furthermore, the imaging system 3201 can be applied not only to a vehicle such as the own vehicle but also to a moving body (moving device) such as a ship, an aircraft, or an industrial robot. In addition, the invention can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent transportation systems (ITS).

  The photoelectric conversion device of the present invention may further have a configuration having a color filter or a microlens, and may have a configuration capable of acquiring various information such as distance information. For example, a plurality of photoelectric conversion elements may be provided for one input node, and one microlens common to the plurality of photoelectric conversion elements may be provided. Further, although the amplification transistor is a part of the source follower circuit, it may be a part of the AD converter. Specifically, the amplification transistor may constitute a part of the comparator included in the AD converter. Further, a part of the configuration of the comparator may be provided on another semiconductor substrate. Further, the unit circuit may not have a transfer transistor, and the photoelectric conversion element may be directly connected to the input node. Furthermore, a charge discharging unit such as an overflow drain may be provided.

  The present invention is not limited to the above embodiment, and various modifications can be made. For example, an example in which a part of the configuration of any one of the embodiments is added to another embodiment, or an example in which the configuration of a part of the other embodiment is replaced is also an embodiment of the present invention. In the above-described embodiments, the semiconductor memory, the photoelectric conversion device and the like have been described as examples, but the structure of the transistor of the present invention can be applied to other devices. The above-mentioned embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be limitedly interpreted by these exemplifications. That is, the present invention can be implemented in various modes without departing from the technical idea or the main features thereof.

M1 transistor 31 element isolation part 231 gate electrode 601 part 602 gate insulating film 52 second conductivity type semiconductor region 58b second conductivity type semiconductor region

Claims (30)

A semiconductor memory having an SRAM (Static Random Access Memory) type unit cell including a first transistor of a first conductivity type and a second transistor of a second conductivity type,
The first transistor is disposed in an active region of a semiconductor substrate,
The active region includes a portion overlapping the gate electrode of the first transistor and located between the source and drain of the first transistor,
The portion is arranged over a first position, a second position, and a third position, which are sequentially arranged along the channel width direction of the first transistor,
The portion includes a second conductivity type first semiconductor region arranged at the first position and a second conductivity type second semiconductor region arranged at the second position,
The semiconductor memory according to claim 1, wherein an impurity concentration of the first semiconductor region is higher than an impurity concentration of the second semiconductor region. A channel of the first transistor is formed at the second position,
2. The semiconductor memory according to claim 1, wherein the channel of the first transistor is not formed at the first position. In the portion, a third semiconductor region of the second conductivity type is arranged at the third position,
3. The semiconductor memory according to claim 1, wherein the impurity concentration of the third semiconductor region is higher than the impurity concentration of the second semiconductor region.   4. The semiconductor memory according to claim 1, wherein the first conductivity type is P type and the second conductivity type is N type. The unit cell includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type,
The first transistor and the third transistor function as load transistors,
5. The semiconductor memory according to claim 1, wherein the second transistor and the fourth transistor function as a driver transistor.   When the gate electrode of the first transistor is turned on, the impurity concentration of the first semiconductor region and the impurity concentration of the second semiconductor region form a channel at the second position and form a channel at the first position. 6. The semiconductor memory according to claim 1, wherein the impurity concentration is not controlled.   When the impurity concentration of the first semiconductor region is C1 and the impurity concentration of the second semiconductor region is C2, the impurity concentration of the first semiconductor region and the impurity concentration of the second semiconductor region satisfy C1 ≧ 2 × C2. 7. The semiconductor memory according to claim 1, wherein the semiconductor memory is a semiconductor memory.   8. The semiconductor memory according to claim 7, wherein the impurity concentration of the first semiconductor region and the impurity concentration of the second semiconductor region satisfy C1 ≧ 10 × C2. In a plan view, the active region is adjacent to the element isolation portion having a trench,
9. The semiconductor memory according to claim 1, wherein the gate electrode of the first transistor extends above the element isolation portion.   10. The semiconductor memory according to claim 9, wherein the first position is between a side surface of the trench and the second position. A semiconductor memory according to any one of claims 1 to 10,
A photoelectric conversion device having a photoelectric conversion portion provided with a photoelectric conversion element and the same substrate. A semiconductor memory according to any one of claims 1 to 10,
A photoelectric conversion device in which a substrate on which a photoelectric conversion unit including a photoelectric conversion element is arranged is stacked. A photoelectric conversion device according to claim 11 or 12,
A signal processing unit that processes a signal from the photoelectric conversion device. A photoelectric conversion device according to claim 11 or 12,
A parallax information based on a signal from the photoelectric conversion device, a distance information acquisition unit for acquiring distance information to the object, a moving body,
The moving body further comprising control means for controlling the moving body based on the distance information. Method of manufacturing photoelectric conversion device having SRAM (Static Random Access Memory) type memory section including first conductivity type first transistor and second conductivity type second transistor, and photoelectric conversion section including photoelectric conversion element And
Providing a semiconductor substrate having a first region, a second region, and a third region;
Forming a groove in the first region, the second region, and the third region using a first mask pattern;
A second mask pattern is formed on the first mask pattern to cover the groove formed in the first region and expose the groove formed in the second region and the groove formed in the third region. And the process of
Impurity ions of the first conductivity type are applied to the semiconductor substrate through the groove formed in the second region and the groove formed in the third region using the first mask pattern and the second mask pattern. The step of injecting
An insulator is embedded in the groove formed in the first region, the groove formed in the second region, and the groove formed in the third region, and the first element isolation portion is formed in the first region and the second region is formed. Forming a second element isolation portion in the region and a third element isolation portion in the third region,
Forming the first transistor in the first region and forming the second transistor in the second region;
And a step of forming the photoelectric conversion element in the third region, the method for manufacturing a photoelectric conversion device. Forming a second transistor of a second conductivity type in the third region,
A gate electrode of the first transistor extends over the first isolation region,
A gate electrode of the second transistor extends on the second element isolation portion,
The method of manufacturing a photoelectric conversion device according to claim 15, wherein a gate electrode of the third transistor extends above the third element isolation portion.   17. The method of manufacturing a photoelectric conversion device according to claim 15, wherein the first mask pattern is made of an inorganic material and the second mask pattern is made of an organic material. The photoelectric conversion device includes a processing circuit unit that includes a fourth transistor of the first conductivity type and a fifth transistor of the second conductivity type and that processes a signal from the photoelectric conversion element.
The semiconductor substrate has a fourth region and a fifth region,
Forming a groove in the fourth region and the fifth region,
An insulator is embedded in the groove formed in the fourth region and the groove formed in the fifth region, and a fourth element isolation part is formed in the fourth region and a fifth element isolation part is formed in the fifth region. And the process of
Forming the fourth transistor in the fourth region and forming the fifth transistor in the fifth region,
The step of forming the second mask pattern is performed after the step of forming a groove in the fourth region and the fifth region,
18. The method of manufacturing a photoelectric conversion device according to claim 15, wherein the second mask pattern covers the fourth region and the fifth region.   The first element isolation section, the second element isolation section, the third element isolation section, the fourth element isolation section, and the fifth element isolation section are element isolations having an STI structure. The method for manufacturing a photoelectric conversion device according to claim 18.   20. The photoelectric conversion device according to claim 15, wherein in the step of implanting the impurity ions, the implanting of the impurity ions is performed obliquely with respect to the surface of the semiconductor substrate. Production method. A method for manufacturing a semiconductor memory having a SRAM (static random access memory) type unit cell including a first transistor of a first conductivity type and a second transistor of a second conductivity type,
Providing a semiconductor substrate having a first region and a second region;
Forming a first groove in the first region and forming a second groove in the second region using a first mask pattern;
Forming a second mask pattern on the first mask pattern, the second mask pattern covering the first groove and having an opening exposing the second groove;
Implanting impurity ions of the first conductivity type into the semiconductor substrate through the second groove using the first mask pattern and the second mask pattern;
Filling the first groove and the second groove with an insulator to form a first element isolation portion having the first groove and a second element isolation portion having the second groove;
A step of forming the first transistor in the first region and forming the second transistor in the second region. A semiconductor device having a CMOS circuit including a first transistor of a first conductivity type and a second transistor of a second conductivity type,
The first transistor is disposed in an active region of a semiconductor substrate,
The first transistor has a portion where the gate electrode of the first transistor and the active region overlap with each other and is located between the source and the drain of the first transistor of the semiconductor substrate,
In the portion, a second conductive type first semiconductor region is arranged at a first position along a channel width direction of the first transistor, and a second semiconductor region is provided at a second position between the first position and the third position. A second semiconductor region of two conductivity type is arranged,
A semiconductor device, wherein the impurity concentration of the first semiconductor region is higher than the impurity concentration of the second semiconductor region. A unit cell portion in which a unit cell having a photoelectric conversion element is arranged,
A signal reading section for reading a signal from the unit cell section,
The signal readout unit has at least one first conductivity type first transistor,
The first transistor is disposed in an active region of a semiconductor substrate,
The active region includes a first portion that overlaps with a gate electrode of the first transistor and is located between a source and a drain of the first transistor,
The first portion is arranged over a first position, a second position, and a third position arranged in order along the channel width direction of the first transistor,
The first portion includes a second conductive type first semiconductor region arranged at the first position and a second conductive type second semiconductor region arranged at the second position,
The photoelectric conversion device, wherein the impurity concentration of the first semiconductor region is higher than the impurity concentration of the second semiconductor region. The signal reading unit includes at least one of a current source circuit, a signal amplification circuit, and an AD conversion circuit,
The photoelectric conversion device according to claim 23, wherein the at least one of the current source circuit, the signal amplification circuit, and the AD conversion circuit includes the first transistor. The signal reading unit includes at least a current source circuit and an AD conversion circuit,
The AD converter circuit includes a comparator having another current source circuit, and the current source circuit and the other current source circuit include the first transistor. 25. Photoelectric conversion device. The signal read unit has at least one second transistor of the first conductivity type,
The second transistor is disposed in another active region of the semiconductor substrate,
The active region includes a second portion overlapping the gate electrode of the second transistor and located between the source and drain of the second transistor;
The second portion is arranged over a fourth position, a fifth position, and a sixth position, which are sequentially arranged along the channel width direction of the second transistor,
The second portion includes a fourth semiconductor region of the second conductivity type arranged in the fourth position and a fifth semiconductor region of the second conductivity type arranged in the fifth position,
26. The photoelectric conversion device according to claim 23, wherein the fourth semiconductor region and the fifth semiconductor region have the same impurity concentration. The signal read unit has at least one second transistor of the first conductivity type,
The second transistor is disposed in another active region of the semiconductor substrate,
The active region includes a second portion overlapping the gate electrode of the second transistor and located between the source and drain of the second transistor;
The second portion is arranged over a fourth position, a fifth position, and a sixth position, which are sequentially arranged along the channel width direction of the second transistor,
The second portion includes a fourth semiconductor region of the second conductivity type arranged in the fourth position and a fifth semiconductor region of the second conductivity type arranged in the fifth position,
The second conductivity type is P-type, and the difference between the maximum and minimum impurity concentrations of the first semiconductor region and the second semiconductor region is the impurity concentration of the first semiconductor region and the second semiconductor region. The photoelectric conversion device according to any one of claims 23 to 25, wherein the photoelectric conversion device is smaller than a difference in impurity concentration. The unit cell includes a transfer transistor that transfers a charge from the photoelectric conversion element, and an amplification transistor that outputs a signal based on the charge,
28. The photoelectric conversion device according to claim 23, wherein the transfer transistor and the amplification transistor are the first transistors. A photoelectric conversion device according to any one of claims 23 to 28,
A signal processing unit that processes a signal from the photoelectric conversion device. A photoelectric conversion device according to any one of claims 23 to 28,
A parallax information based on a signal from the photoelectric conversion device, a distance information acquisition unit for acquiring distance information to the object, a moving body,
The moving body further comprising control means for controlling the moving body based on the distance information.

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