JP2020053561A - Printed wiring board and manufacturing method thereof - Google Patents

Abstract

To provide a printed wiring board with high reliability for fine transmission lines.SOLUTION: A first insulating layer 40 and a first conductor pattern (transmission line) 48 are arranged on a thinned glass plate 30 to form a second wiring board 10. The second wiring board 10 including a glass plate 30 having high rigidity is arranged on a first wiring board 100. The thickness of the glass plate 30 of the second wiring board is reduced to adjust the rigidity of the second wiring board.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a combined printed wiring board including a first wiring board formed at a coarse wiring pitch and a second wiring board formed at a fine wiring pitch, and a method of manufacturing the same.

  With the recent miniaturization and high integration of IC chips, the wiring pitch of a package substrate is also rapidly becoming thinner.

  Patent Document 1 discloses a method for manufacturing a printed wiring board in which a rewiring board having a high wiring density is formed on a support plate by a semiconductor process and the rewiring board is embedded in the printed wiring board. Patent Document 2 discloses a method of manufacturing a printed wiring board in which a sub-board having a high wiring density is formed on a support plate, and the sub-board is mounted on the printed wiring board.

JP 2013-214578 A JP-A-2005-50315

[Issues in Patent Literature]
In Patent Literature 1, since rewiring boards having different wiring densities are embedded in the printed wiring board, it is conceivable that the reliability of the wiring is reduced due to a difference in thermal expansion coefficient at the interface between the rewiring board and the printed wiring board. In Patent Literature 2, since sub-substrates having different wiring densities are mounted on the main substrate, it is conceivable that the reliability of the wiring may be reduced due to a difference in thermal expansion coefficient at the interface.

A connection type printed wiring board according to the present invention includes a first wiring board formed at a coarse wiring pitch and a second wiring board formed at a fine wiring pitch. The second wiring board includes a supporting plate having a reduced thickness, a first insulating layer formed on the supporting plate, a first conductor pattern formed on the insulating layer, and a first conductor. A second insulating layer formed on the pattern, a second conductor pattern formed on the second insulating layer, and the first conductor pattern and the second conductor pattern penetrating the second insulating layer. And a via conductor to be connected.

According to the present invention, there is provided a method for manufacturing a coupled printed wiring board comprising a first wiring board formed at a coarse wiring pitch and a second wiring board formed at a fine wiring pitch, wherein The manufacturing includes preparing a glass plate, polishing the glass plate to a thickness of 20 μm to 30 μm, forming a first insulating layer on the glass plate, and forming a first insulating layer on the insulating layer. Forming a conductive pattern, forming a second insulating layer on the first conductive pattern, forming a second conductive pattern on the second insulating layer, and penetrating the second insulating layer; Forming via conductors connecting the first conductor pattern and the second conductor pattern, preparing the first wiring board, and arranging the second wiring board on the first wiring board To have.

[Effects of Embodiment]
According to the embodiment of the present invention, the second wiring board having the first insulating layer, the first conductive pattern, the second insulating layer, and the second conductive pattern formed on the support plate having a reduced thickness is provided with the first wiring. Since it is arranged on the board, the rigidity of the support plate of the second wiring board is high, and the reliability of the wiring due to the difference in thermal expansion coefficient at the interface between the second wiring board and the first wiring board is unlikely to decrease. In addition, since the rigidity of the support plate is adjusted by reducing the thickness of the support plate, a decrease in the reliability of the wiring based on the rigidity difference at the interface between the second wiring board and the first wiring board is unlikely to occur. .

According to the manufacturing method of the present invention, the first insulating layer, the first conductive pattern, the second insulating layer, and the second conductive pattern formed on the glass plate whose thickness is reduced to 20 to 30 μm by polishing. Since the wiring board is disposed on the first wiring board, the rigidity of the glass plate of the second wiring board is high, and the reliability of the wiring caused by the difference in the thermal expansion coefficient at the interface between the second wiring board and the first wiring board. Is unlikely to occur. In addition, since the rigidity of the glass plate is adjusted by reducing the thickness of the glass plate, the reliability of the wiring hardly decreases due to the difference in rigidity at the interface between the second wiring board and the first wiring board.

Sectional view of a printed wiring board according to a first embodiment of the present invention. Sectional view of a printed wiring board of an application example of the first embodiment Plan view of a printed wiring board according to a first embodiment Sectional view of the second wiring board of the printed wiring board of the first embodiment Sectional view of a printed wiring board according to a second embodiment of the present invention. Sectional view of a printed wiring board of an application example of the second embodiment. Manufacturing process diagram of the second wiring board of the printed wiring board of the first embodiment Manufacturing process diagram of the second wiring board of the printed wiring board of the first embodiment Manufacturing process diagram of the printed wiring board of the first embodiment Manufacturing process diagram of the printed wiring board of the first embodiment Manufacturing process diagram of the printed wiring board of the first embodiment Manufacturing process diagram of the printed wiring board of the first embodiment

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1, 2 and 3, arrows Z1 and Z2 indicate the lamination direction (or the thickness direction of the wiring board) of the wiring board corresponding to the normal direction of the main surface (front and back) of the wiring board, respectively. . On the other hand, arrows X1 and X2 and Y1 and Y2 each indicate a direction (or a side of each layer) orthogonal to the lamination direction. The main surface of the wiring board is an XY plane. Further, the side surface of the wiring board is an XZ plane or a YZ plane. In the stacking direction, the side closer to the core of the wiring board is the lower layer, and the side farther from the core is the upper layer.

[First Embodiment]
1 and 2 show cross sections of the printed wiring board 110 according to the first embodiment.
The printed wiring board 110 according to the first embodiment is a build-up multilayer laminated substrate having a core substrate 130.
As shown in FIG. 2, on the printed wiring board 110, a microprocessor MPU (Micro-Processing Unit: logic-based semiconductor element) 92 as a first semiconductor element and a dynamic RAM DRAM (Dynamic) as a second semiconductor element. A random access memory (memory semiconductor element) 94 is mounted to form a package substrate. Printed wiring board 110 is mounted on a motherboard substrate (not shown). The space between the printed wiring board, the MPU 92, and the DRAM 94 is sealed with an underfill resin 168.

As shown in FIG. 1, the printed wiring board 110 includes a core substrate 130 having a first surface F (Z1 side) and a second surface S (Z2 side) opposite to the first surface F, and a core substrate 130. Of the core substrate 130 and a lower build-up layer 55S formed on the second surface S of the core substrate 130.
The printed wiring board 110 further includes a first solder resist layer 90F formed on the upper build-up layer 55F and a second solder resist layer 90S formed on the lower build-up layer 55S. There is also.

The core substrate 130 includes a core layer 120 having a first surface F, a second surface S opposite to the first surface F, a third conductor layer 134F formed on the first surface F of the core layer, and a third layer of the core layer. It has a fourth conductor layer 134S formed on two surfaces S. The core substrate further has a through-hole conductor 136 penetrating the core layer. The third conductor layer 134F and the fourth conductor layer 134S are connected via a through-hole conductor 136.

The upper buildup layer 55F includes a first interlayer insulating layer 150F formed on the first surface F and the third conductor layer 134F of the core substrate 130, and a first interlayer insulating layer 150F formed on the first interlayer insulating layer 150F. It has a conductor layer (158F) and a first via conductor (160F) penetrating through the first interlayer insulating layer (150F) and connected to the first conductor layer (158F). The number of first interlayer insulating layers 150F and the number of first conductor layers 158F are preferably plural. The warpage of the upper buildup layer 55F can be reduced. The concentration of stress in the upper buildup layer 55F can be suppressed. In the example of FIG. 1, the number of the first interlayer insulating layers 150F is four, and the number of the first conductor layers 158F is four. The first interlayer insulating layers 150F and the first conductor layers 158F are alternately stacked. When the number of the first interlayer insulating layers 150F is plural, the first via conductor 160F is formed in each first interlayer insulating layer 150F. The conductor layers sandwiching the first interlayer insulating layer (150F) are connected by the first via conductor (160F).
When the number of the first interlayer insulating layers is plural, the upper build-up layer 55F includes the first interlayer insulating layer (first interlayer insulating layer on the core substrate) 150F1 formed immediately above the core substrate 130 and other components. (First upper interlayer insulating layer) 150F2, 150F3, 150F4. The upper first interlayer insulating layers 150F2, 150F3, and 150F4 are sandwiched between first conductor layers 158F, and the first interlayer insulating layer 150F1 on the core substrate is sandwiched between the first conductor layer 158F and the third conductor layer 134F. The first via conductor (160F) penetrating the upper first interlayer insulating layers (150F2, 150F3, 150F4) connects the adjacent first conductor layer (158F). A first via conductor (160F) penetrating through the first interlayer insulating layer (150F1) on the core substrate connects the first conductor layer (158F) and the third conductor layer (134F).

A first solder resist layer 170F is formed on upper buildup layer 55F. The first solder resist layer 170F has a first opening 172FA having a relatively small opening diameter exposing the first conductor layer 158F, and a second opening 172FB having a relatively large opening diameter. The first conductive layer exposed from the first opening 172FA forms a first pad 174FA. On the first pad 174FA, a first solder bump 176FA for signal transmission between the MPU 92 and the DRAM 94 is formed. The first conductive layer exposed from the second opening 92FB forms a second pad 174FB. A second solder bump 176FB for mounting the MPU 92 and the DRAM 94 is formed on the second pad 174FB. A nickel plating layer and a gold plating layer (not shown) are formed between the first pad 174FA and the first solder bump 176FA and between the second pad 174FB and the second solder bump 176FB.

The lower buildup layer 55S includes a second interlayer insulating layer 150S formed on the second surface S and the fourth conductor layer 134S of the core substrate 130, and a second interlayer insulating layer 150S formed on the second interlayer insulating layer 150S. It has a second conductor layer (158S) and a second via conductor (160S) penetrating through the second interlayer insulating layer (150S) and connected to the second conductor layer (158S). It is preferable that the number of the second interlayer insulating layers 150S and the number of the second conductor layers 158S be plural. The warpage of the lower buildup layer 55S can be reduced. The concentration of stress in the lower buildup layer 55S can be suppressed. In the example of FIG. 1, the number of the second interlayer insulating layers 150S is four, and the number of the second conductor layers 158S is four. The second interlayer insulating layers 150S and the second conductor layers 158S are alternately stacked. When the number of the second interlayer insulating layers 150S is plural, the second via conductor 160S is formed in each second interlayer insulating layer 150S. Conductive layers sandwiching second interlayer insulating layer (150S) are connected by second via conductor (160S).
When the number of the second interlayer insulating layers is plural, the lower buildup layer 55S is composed of the second interlayer insulating layer (second interlayer insulating layer on the core substrate) 150S1 formed immediately above the core substrate 130 and the other. (Second upper interlayer insulating layer) 150S2, 150S3, 150S4. The upper second interlayer insulating layers 150S2, 150S3, 150S4 are sandwiched between the second conductor layers 158S, and the second interlayer insulating layer 150S1 on the core substrate is sandwiched between the second conductor layer 158S and the fourth conductor layer 134S. The second via conductor (160S) penetrating the upper second interlayer insulating layers (150S2, 150S3, 150S4) connects the adjacent second conductor layer (158S). A second via conductor (160S) penetrating through the second interlayer insulating layer (150S1) on the core substrate connects the second conductor layer (158S) and the fourth conductor layer (134S).

A second solder resist layer 170S is formed on lower buildup layer 55S. The second solder resist layer 170S has an opening 172S exposing the second conductor layer 158S. The second conductor layer 158S exposed from the first opening 172S forms a pad 174S. Solder bumps 176S for mounting on a motherboard (not shown) are formed on the pads 174S. A nickel plating layer and a gold plating layer (not shown) are formed between the pad 174S and the solder bump 176S.

The printed wiring board 110 according to the first embodiment includes a first wiring board 100 and a second wiring board 10 disposed inside the first wiring board 100. The second wiring board 10 is designed not in accordance with the wiring rules of a multilayer printed wiring board but in accordance with the wiring rules of a semiconductor element such as an IC or an LSI as will be described in detail later. It is designed so that L / S (line space) indicating the ratio of line to space, which is an index of the wiring density, is fine. Here, the line indicates the pattern width, and the space indicates the gap between the patterns. Specifically, a high wiring density such that L / S (line space) indicating the ratio of line to space is 1/1 to 5/5 (μm), preferably 3/3 to 5/5 (μm) Is formed. This is a fine level as compared with the L / S of a normal multilayer printed wiring board including the first wiring board 100 of the present embodiment being about 10/10 (μm).

The first wiring board 100 includes a power supply line to the power supply terminal Vdd of the MPU 92 and the DRAM 94, which are semiconductor elements, and a signal transmission line (see FIG. 3).

FIG. 4A shows a cross section of the second wiring board 10.
The second wiring board 10 includes a glass plate (support plate) 30 having a reduced thickness, a first insulating layer 40 on the glass plate 30, a first conductor pattern 48 on the first insulating layer 40, and a first conductor The second insulating layer 50 on the pattern 48, the second conductive pattern 58 on the second insulating layer 50, the third insulating layer 60 on the second conductive pattern 58, and the third conductive pattern on the third insulating layer 60 68, a fourth insulating layer 70 on the third conductive pattern 68, and a fourth conductive pattern 78 on the fourth insulating layer 70. The first conductor pattern 48 and the second conductor pattern 58 are connected by a via conductor 56 penetrating the second insulating layer 50. The second conductor pattern 58 and the third conductor pattern 68 are connected by a via conductor 66 penetrating the third insulating layer 60. The third conductor pattern 68 and the fourth conductor pattern 78 are connected by a via conductor 76 penetrating the fourth insulating layer 70. For the insulating layers 40, 50, 60, and 70, any of polyimide, phenol-based resin, and polybenzoxazole-based resin can be used as an insulating material. The second wiring board 10 is housed in an opening 145 formed to penetrate the first interlayer insulating layer 150F in a predetermined region.

FIG. 4B shows a part of the second wiring board 10 in an enlarged manner.
The thickness D1 of the glass plate 30 thinned by polishing from the glass plate is 20 to 30 μm. The thickness d2 of the first insulating layer 40 is 4.6 μm. The thickness d3 (the insulation distance between the first conductor pattern 48 and the second conductor pattern 58) of the second insulation layer 50 is 2 μm. The thicknesses of the third insulating layer 60 and the fourth insulating layer 70 are substantially equal to those of the second insulating layer 50. The thickness t1 of the first conductor pattern 48, the thickness t2 of the second conductor pattern 58, and the thickness t3 of the third conductor pattern 68 are 2 μm. The thickness t4 of the fourth conductor pattern 78 is 5 μm. The total thickness D2 of the insulating layer and the conductor pattern forming the second wiring board formed on the glass plate is 21.6 μm. It is preferable that the thickness D1 of the glass plate 30 is substantially equal to the total thickness D2 of the insulating layer and the conductor pattern forming the second wiring board. The thickness D1 of the glass plate 30 is preferably 0.5 to 1.5 times the total thickness D2 of the insulating layer and the conductor pattern forming the second wiring board. Thereby, while the second wiring board has sufficient rigidity to maintain the reliability of the conductor pattern, cracks in the insulating layer due to the difference in rigidity between the interlayer insulating layer on the first wiring board 100 side and the glass plate are reduced. The rigidity can be suppressed to a level that does not occur. The thermal expansion coefficient of the glass plate 30 is 3.3 ppm, and the thermal expansion coefficients of the first insulating layer 40, the second insulating layer 50, the third insulating layer 60, and the fourth insulating layer 70 are about 57 ppm. The thermal expansion coefficient of the first interlayer insulating layer 150F is about 58 ppm.

The second wiring board 10 does not include a power supply line but includes only a signal transmission line 12 (see FIG. 3) formed by the conductor patterns 48, 58, 68, and a signal between the MPU 92 and the DRAM 94. Used for transmission.
Specifically, the transmission line 12 is used for transmitting signals between the MPU 92 and the DRAM 94, and is not used for supplying power to the MPU 92 and the DRAM 94. The power supply terminals Vdd of the MPU 92 and the DRAM 94 are electrically connected to the second solder bumps 176FB (see FIG. 2) of the first wiring board 100, and power is supplied from an external DC power supply. The ground terminals Gnd of the MPU 92 and the DRAM 94 are connected to the ground via another second solder bump of the first wiring board 100.

Since the second wiring board 10 is arranged on the second interlayer insulating layer 150F2 from the bottom as in the first embodiment, the second wiring board 10F is formed by the outermost first interlayer insulating layer 150F4. The effect of the small depression that may occur on the upper surface of the first solder bump 176FA is reduced, and the height of the first solder bump 176FA is made uniform. Further, compared to the case where the second wiring board 10 is formed in the outermost layer, the printed wiring board of the first embodiment has a structure that is more resistant to damage due to stress.

The diameter (diameter on the upper surface of the insulating layer) of the via conductors 56, 66, and 76 is preferably 10 μm, and more preferably 8 μm or more and 12 μm or less. The via land has a size of 20 μm, preferably 16 μm or more and 24 μm or less. By setting the diameter of the via conductor to such a small size, the degree of freedom in routing the transmission line 12 (see FIG. 3) formed by the conductor patterns 48, 58, 68 on the second wiring board 10 is improved. Then, for example, many wires are taken out from the transmission line 12 from one of the left and right sides of the second wiring board 10.

In the printed wiring board 110 of the first embodiment, the first wiring board 100 incorporates the second wiring board 10 for transmitting signals between semiconductor elements, which has a higher wiring density than the first wiring board 100. The degree of freedom in designing the first wiring board 100, which is a multilayer printed wiring board, can be improved. For example, it is possible to prevent all of the power supply system and signal system wiring from being concentrated on a specific portion of the wiring board. Further, for example, in a region around the electronic component where no electronic component exists, it is possible to avoid a situation where no conductor exists and only resin exists.

According to the printed wiring board 110 of the first embodiment, the first insulating layer 40, the first conductive pattern 48, the second insulating layer 50, and the second conductive pattern 58 are formed on the glass plate 30 having a reduced thickness. The second wiring board 10 is placed on the first wiring board 100. The rigidity of the glass plate 30 of the second wiring board is high, due to the difference in thermal expansion coefficient at the interface between the second wiring board 10 and the first wiring board 100 (the interface between the glass board 30 and the first interlayer insulating layer 150F). The reliability of the fine transmission line 12 is hardly reduced. In addition, since the rigidity of the glass plate 30 is adjusted by reducing the thickness of the glass plate 30 to 20 to 30 μm, transmission based on the difference in rigidity at the interface between the second wiring board 10 and the first wiring board 100 is performed. The reliability of the line 12 is hardly reduced.

According to the printed wiring board of the first embodiment, the variation of the thermal shrinkage of the first insulating layer 40, the second insulating layer 50, the third insulating layer 60, and the fourth insulating layer 70 formed on the glass plate 30 is reduced. Since the bump pitch can be controlled to 2 μm, the bump pitch can be set to 55 μm or 45 μm.

Hereinafter, an example of a method for manufacturing a printed wiring board according to the present embodiment will be described. The manufacturing process of the printed wiring board includes a manufacturing process of the second wiring board 10 and a manufacturing process of the first wiring board (multi-layer printed board) including a step of mounting the second wiring board 10 on the first wiring board 100. .
The second wiring board 10 is manufactured by a process as shown in FIGS. 7 and 8, for example.

[Method of manufacturing second wiring board]
As shown in FIG. 7A, a glass plate (support plate) 30z is prepared. The glass plate 30z is made of, for example, glass having a flat surface. The glass plate is polished with a back grinder to reduce the thickness to 20 μm to 30 μm (FIG. 7B).

As shown in FIG. 7C, a first insulating layer 40 made of, for example, resin (interlayer material: WPR5100 manufactured by JSR) is arranged on the thinned glass plate 30. The first insulating layer 40 and the glass plate 30 are bonded by, for example, a heat treatment. Here, an adhesive layer may be formed between the first insulating layer 40 and the glass plate 30.

Subsequently, as shown in FIG. 7D, a first conductor pattern 48 is formed on the first insulating layer 40 by, for example, a semi-additive (SAP) method. The first conductor pattern 48 includes a first conductor film 48a and a second conductor film 48b. More specifically, the first conductor film 48a includes three layers: a TiN layer (lower layer), a Ti layer (intermediate layer), and a Cu layer (upper layer). Since each of these metal layers is formed by, for example, a sputtering method, good adhesion between the fine first conductor pattern 48 and the base material (first insulating layer) 40 is ensured. The second conductor film 48b includes an electroless copper plating film on the Cu layer and an electrolytic plating film on the electroless copper plating film.

The first conductor pattern 48 is formed with a high wiring density so that L / S (line space) indicating a line-to-space ratio is 1 μm / 1 μm to 5 μm / 5 μm, preferably 3 μm / 3 μm to 5 μm / 5 μm. . Here, the line indicates the pattern width, and the space indicates the gap between the patterns. The wiring density here is formed according to the same wiring rule as when wiring is formed on a semiconductor element such as an IC (Integrated Circuit) or an LSI (Large Scale Integrated Circuit).

Subsequently, as shown in FIG. 7E, a second insulating layer 50 is formed on the first insulating layer 40 by, for example, laminating. The second insulating layer 50 is formed so as to cover the first conductor pattern 48.

Subsequently, an opening 52 (via hole) is formed in the second insulating layer 50 by, for example, a laser (FIG. 8A). The opening 52 reaches the first conductor pattern 48 and exposes a part thereof. The diameter of the opening 52 (opening diameter on the surface of the second insulating layer) is a minute size of 1 μm or more and 10 μm or less, preferably 0.5 μm or more and 5 μm or less. Thereafter, desmearing and soft etching are performed as necessary.

Subsequently, a via conductor 56 (filled conductor) is formed in the opening 52 by, for example, a semi-additive (SAP) method, and a second conductor pattern 58 is formed on the second insulating layer 50 (FIG. 8B). )). Each of the second conductor pattern 58 and the via conductor 56 is composed of two layers of a first conductor film 58a and a second conductor film 58b. More specifically, the first conductor film 58a includes three layers: a TiN layer (lower layer), a Ti layer (intermediate layer), and a Cu layer (upper layer). The second conductor film 58b includes an electroless copper plating film on the Cu layer and an electrolytic plating film on the electroless copper plating film.

Thus, as shown in FIG. 8C, the third insulating layer 60, the fourth insulating layer 70, the third conductive pattern 68, the fourth conductive pattern 78, and the via conductors 66 and 76 are formed on the glass plate 30. Is formed, and the second wiring board 10 is completed.

[Method of manufacturing first wiring board]
9 to 12 show a method for manufacturing the first wiring board 100 of the embodiment.
A starting substrate 120z shown in FIG. 9A is prepared. The starting substrate 120z includes a core layer 120 having a first surface F and a second surface S opposite to the first surface F, a metal foil 132 laminated on the first surface F of the core layer 120, and a second surface S. It is formed of laminated metal foils 132. The core layer 120 is formed of a resin and a reinforcing material. The core layer 120 may have inorganic particles. Examples of the resin of the core layer 120 are an epoxy resin and a BT (bismaleimide triazine) resin. Examples of the reinforcing material of the core layer 120 are glass cloth and aramid fiber. Examples of the inorganic particles of the core layer 120 are silica and alumina.

According to a known manufacturing method, a third conductor layer 134F is formed on the first surface F of the core layer 120, a fourth conductor layer 134S is formed on the second surface of the core layer 120, and penetrates the core layer 120. The through-hole conductor 136 connecting the third conductor layer 134F and the fourth conductor layer 134S is formed, and the core substrate 130 is completed (FIG. 9B).

As shown in FIG. 9C, an interlayer insulating film (trade name: ABF-45SH, manufactured by Ajinomoto Co., Inc.) is laminated on the first surface F and the second surface S of the core substrate 130. A first interlayer insulating layer 150F and a second interlayer insulating layer 150S are formed.

As shown in FIG. 10A, via hole openings 152F and 152S are formed in the first interlayer insulating layer 150F and the second interlayer insulating layer 150S, respectively, using a CO 2 gas laser. Further, the substrate is immersed in an oxidizing agent such as permanganate or the like, and desmearing is performed.

An electroless plating film is formed on the surfaces of first interlayer insulating layer (150F) and second interlayer insulating layer (150S). Thereafter, a plating resist is formed on the electroless plating film. Then, an electrolytic plating film is formed on the electroless plating film exposed from the plating resist, and the first via conductor 160F and the second via conductor 160S are formed in the via hole openings 152F and 152S. After that, the plating resist is removed. The first conductor layer 158F and the second conductor layer 158S are formed by removing the electroless plating film exposed from the electrolytic plating film by etching (FIG. 10B).

The steps of FIGS. 9C to 10B are performed, and the first interlayer insulating layer (upper first interlayer insulating layer) is formed on the first interlayer insulating layer (first interlayer insulating layer on the core substrate) 150F1. 150F2 is formed, and a second interlayer insulating layer (upper second interlayer insulating layer) 150S2 is formed on second interlayer insulating layer (second interlayer insulating layer on core substrate) 150S1. A first via penetrating the upper first interlayer insulating layer (150F2) and the second conductive layer (158S) on the upper second interlayer insulating layer (150S2) and penetrating the upper first interlayer insulating layer (150F2) A second via conductor (160S) is formed in which the conductor (160F) penetrates the upper second interlayer insulating layer (150S2) (FIG. 10 (C)).

As shown in FIG. 11A, the second wiring board 10 is mounted on a predetermined region of the upper first interlayer insulating layer 150F2. Here, the second wiring board 10 may be attached via an adhesive layer (not shown).

As shown in FIG. 11B, a first interlayer insulating layer 150F3 is formed over the first interlayer insulating layer 150F2, and a second interlayer insulating layer 150S3 is formed over the second interlayer insulating layer 150S2. A first conductor layer (158F) is formed on the first interlayer insulating layer (150F3), and a second conductor layer (158S) is formed on the second interlayer insulating layer (150S3). A second via conductor (160S) penetrating through interlayer insulating layer (150S3) is formed.

As shown in FIG. 12A, a first interlayer insulating layer 150F4 is formed on second wiring board 10 and first interlayer insulating layer 150F3, and a second interlayer insulating layer 150S4 is formed on second interlayer insulating layer 150S3. It is formed. A first conductor layer (158F) is formed on the first interlayer insulating layer (150F4) and a second conductor layer (158S) is formed on the second interlayer insulating layer (150S4). A second via conductor (160S) penetrating through interlayer insulating layer (150S4) is formed.

As shown in FIG. 12B, a first solder resist layer 170F is formed on first interlayer insulating layer 150F4, and a second solder resist layer 170S is formed on second interlayer insulating layer 150S4. The first solder resist layer 170F has a first opening 172FA having a relatively small opening diameter exposing the first conductor layer 158F, and a second opening 172FB having a relatively large opening diameter. The first conductive layer exposed from the first opening 172FA forms a first pad 174FA, and the first conductive layer 158F exposed from the second opening 172FB forms a second pad 174FB. The second solder resist layer 170S has an opening 172S exposing the second conductor layer 158S. The second conductor layer 158S exposed from the opening 172S forms a pad 174S.

A first solder bump 176FA for signal transmission between the MPU 92 and the DRAM 94 is formed on the first pad 174FA, a second solder bump 176FB for mounting the MPU 92 and the DRAM 94 is formed on the second pad 174FB, and a solder bump is formed on the pad 174S. 176S is formed, and the printed wiring board 110 is completed (FIG. 1).

The MPU 92 and the DRAM 94 are mounted via the first solder bumps 176FA and the second pads 174FB (FIG. 2).

According to the method for manufacturing a printed wiring board of the first embodiment, the first insulating layer 40, the first conductive pattern 48, the second insulating layer 50, and the like are formed on the glass plate 30 whose thickness is reduced to 20 to 30 μm by polishing. Since the second wiring board 10 on which the second conductor pattern 58 is formed is arranged on the first wiring board 100, the rigidity of the glass plate 30 of the second wiring board is high, and the second wiring board and the first wiring board are not connected to each other. The reliability of the conductor pattern hardly decreases due to the difference in thermal expansion coefficient at the interface. Further, since the rigidity of the glass plate 30 is adjusted by reducing the thickness of the glass plate, the reliability of the conductor pattern and the first conductor layer due to the difference in rigidity at the interface between the second wiring board and the first wiring board is adjusted. It is unlikely that the property will decrease.

[Second embodiment]
FIG. 5 shows a cross section of the printed wiring board of the second embodiment, and FIG. 6 shows a cross section of a printed wiring board of an application example of the second embodiment.
In the printed wiring board 210 of the second embodiment, the second wiring board 10 is mounted on the first solder resist layer 170F of the first wiring board 100. A solder bump 276F is formed on the second wiring board 10, a solder bump 176F is formed on the first wiring board 100, and a solder bump 276F on the second wiring board 10 and a solder bump 176F on the first wiring board 100 are formed. The MPU 92 and the DRAM 94 are mounted via this. The method for manufacturing the second wiring board 10 of the printed wiring board of the second embodiment is the same as that of the first embodiment. The second wiring board 10 has the transmission line 12 shown in FIG. 3 as in the first embodiment.

In the printed wiring board of the second embodiment, since the second wiring board 10 is disposed outside the first wiring board 100, the second wiring board 10 is affected by stress or the like generated in the first wiring board 100. hard.

According to the printed wiring board 510 of the second embodiment, similarly to the first embodiment shown in FIG. 4, the first insulating layer 40, the first conductor pattern 48, Since the second wiring board 10 on which the second insulating layer 50 and the second conductor pattern 58 are formed is disposed on the first wiring board 100, the rigidity of the glass plate 30 of the second wiring board is high, and the second wiring board 10 The reliability of the fine transmission line 12 hardly decreases due to the difference in thermal expansion coefficient at the interface with the first wiring board 100. In addition, since the rigidity of the glass plate 30 is adjusted by reducing the thickness of the glass plate 30 to 20 to 30 μm, transmission based on the difference in rigidity at the interface between the second wiring board 10 and the first wiring board 100 is performed. The reliability of the line 12 is hardly reduced.

Reference Signs List 10 second wiring board 30 glass plate 40 first insulating layer 48 first conductive pattern 50 second insulating layer 58 second conductive pattern 92 MPU
94 DRAM
100 first wiring board 110 printed wiring board 150F first interlayer insulating layer 158F first conductor layer

Claims (10)

A combined printed wiring board comprising a first wiring board formed at a coarse wiring pitch and a second wiring board formed at a fine wiring pitch,
The second wiring board includes:
A support plate with a reduced thickness,
A first insulating layer formed on the support plate;
A first conductor pattern formed on the insulating layer;
A second insulating layer formed on the first conductor pattern;
A second conductor pattern formed on the second insulating layer;
And a via conductor penetrating the second insulating layer and connecting the first conductor pattern and the second conductor pattern. The printed wiring board according to claim 1,
The support plate is a glass plate. The printed wiring board according to claim 1,
The first conductor pattern is a signal line connecting the first semiconductor element and the second semiconductor element. The printed wiring board according to claim 3,
The first semiconductor element is a logic-based semiconductor element,
The second semiconductor device is a memory semiconductor device. The printed wiring board according to claim 2,
The thickness of the glass plate is 20 μm to 30 μm. The printed wiring board according to claim 5, wherein
The thickness of the glass plate is 0.5 to 1.5 times the thickness of the insulating layer and the conductor pattern forming the second wiring board formed on the glass plate. The printed wiring board according to claim 1,
The L / S (line space) of the first conductor pattern is 1 μm / 1 μm to 5 μm / 5 μm. The printed wiring board according to claim 1,
The second wiring board is embedded in the first wiring board. The printed wiring board according to claim 1,
The second wiring board is fixed on the first wiring board. A method of manufacturing a combined printed wiring board comprising a first wiring board formed at a coarse wiring pitch and a second wiring board formed at a fine wiring pitch,
The manufacturing of the second wiring board includes:
Prepare a glass plate,
Polishing the glass plate to a thickness of 20 μm to 30 μm,
Forming a first insulating layer on the glass plate;
Forming a first conductor pattern on the insulating layer;
Forming a second insulating layer on the first conductor pattern;
Forming a second conductor pattern on the second insulation layer, and forming a via conductor that penetrates the second insulation layer and connects the first conductor pattern and the second conductor pattern. ,
Providing the first wiring board;
Arranging the second wiring board on the first wiring board.

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