JP2019204570A - Programming method for memory device and memory cell array - Google Patents

Abstract

A programming method for a memory device and a memory cell array is provided. The memory device includes a memory cell array, a selection switch, a row decoder, a voltage generator, and a memory controller. The memory controller controls the row decoder with input data to adjust a control path sequence of an address control signal to perform a programming operation on a memory cell of the memory cell array, and the memory controller Simultaneously control the voltage generator to adjust the data path sequence of the input data signal. [Selection diagram] Fig. 3

Description

  The present invention relates to a technique for controlling a memory device, and more particularly, the present invention relates to a memory device and a method for programming a memory cell array that can reduce the time spent for performing a programming operation.

  Cache memory can be mainly classified into two types, NOR cache memory and NAND cache memory. Compared with NAND cache memory, NOR type cache memory takes a long time to perform programming / erasing operations.

  If it is desirable to accelerate the programming operation on the NOR cache memory and reduce the time required to perform the programming operation (usually referred to as tPP), the detailed process of programming the NOR cache memory can be adjusted It seems to be possible. The programming operation can typically be divided into two parts: a programming (PGM) pulse operation and a programming verification (PV) operation. In programming pulse operation, a high voltage is applied to the target memory cell in order to adjust the threshold voltage (Vt) of the target memory cell (ie, to increase the threshold voltage of the target memory cell). PV operation verifies whether the target memory cell has reached a predetermined threshold voltage, thereby confirming that the target memory cell already stores input data. The time tPP spent performing the programming operation is mainly occupied by the programming pulse operation.

  Since the programming operation of NOR cache memory requires a large amount of current and depends on the pumping capability of the hardware circuit, only a specific number of data paths can be driven with programming pulse operation, and the programming pulse operation is repeated. Write input data completely, resulting in the need to perform continuously. Nevertheless, the method of writing data in the cache memory is to perform an erase operation on all memory cells and then perform a programming operation on all of the memory cells. It may not be necessary to implement each of these.

  Therefore, one of the important topics is how to reduce the time required for programming the cache memory.

  The present invention provides a memory device and a memory cell array programming method. The data path sequence of the input data signal is rearranged according to the contents of the input data, and the control path sequence of the address control signal is rearranged at the same time so as to skip memory cells that need not be programmed. As such, the time spent on the programming operation can be reduced.

  In one embodiment, a memory device is provided that includes a memory cell array, a select switch, a row decoder, a voltage generator, and a memory controller. The memory cell array includes a plurality of memory cells. The selection switch is connected to the memory cell array. The row decoder is connected to the selection switch and receives a memory cell address to generate an address control signal. The voltage generator is coupled to the selection switch. The memory controller is coupled to the row decoder and the voltage generator. Here, the memory controller obtains input data to control the voltage generator in order to generate an input data signal. The memory controller controls the row decoder with input data to adjust a control pass sequence of the address control signal to perform a programming operation on the memory cell, and the memory controller The voltage generator is controlled simultaneously to adjust the data path sequence of the input data signal.

  In one embodiment, a method for programming a memory cell array includes the following steps. In order to generate an input data signal, input data is obtained. The control path sequence of the address control signal is adjusted according to the input data, and at the same time, the data path sequence of the input data signal is adjusted. A programming operation is performed on some or all of the plurality of memory cells of the memory cell array according to the address control signal and the input data signal.

  Based on the above, the memory controller of the memory device provided in one or more embodiments rearranges the sequence that operates the data path (ie, the control path sequence of the address control signal) according to the input data of the data buffer. The data path data supply sequence (that is, the data path sequence of the input data signal) is rearranged simultaneously. Thereby, a memory cell that requires a programming operation can receive such an operation, and a memory cell that does not require such an operation is skipped. As such, the number of times the memory device programming operation is performed can be reduced to reduce the time spent on the programming operation.

  In order to make the foregoing easier to understand, some embodiments with figures are described in detail below.

  The accompanying drawings are included and incorporated in and constitute a part of this specification to provide a further understanding of the invention. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.

1 is a block diagram of a memory device. 2 illustrates a detailed circuit of some elements of the memory device shown in FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention. The mapping relationship between physical addresses Bit00-Bit32 and logical addresses D00-D31 of memory cells is illustrated. 3 is a flowchart illustrating a method of programming a memory cell array according to an embodiment of the present invention.

  FIG. 1 is a block diagram of the memory device 100. The memory device 100 provided in the present embodiment can be a NOR cache memory. Each element shown in FIG. 1 is mainly configured to perform a PGM pulse operation on a memory cell. The memory device 100 includes a memory cell array 110, a selection switch 120, a row decoder 130, a voltage generator 140, and a control logic circuit 160. The memory device 100 also includes a column decoder 135 and a data buffer 150.

  Memory cell array 110 includes a plurality of memory cells. The selection switch 120 is connected to the memory cell array 110. In this embodiment, the selection switch 120 can be a row selection switch and can include a plurality of path switches (implemented in the form of transistors M1 and M2 in FIG. 1), each path switch being 1 Corresponds to one data path. The column decoder 135 receives the memory cell address Adr to supply the word line WL to the memory cell array 110. Row decoder 130 is coupled to selection switch 120. The row decoder 130 receives the memory cell address Adr to generate an address control signal. In the present embodiment, the address control signal is exemplified as Y0-Y3. The voltage generator 140 is coupled to the selection switch 120 for supplying an input data signal to each path switch. In the present embodiment, the input data signal is exemplified as HVDIN0-VDIN7. The voltage generator 140 can be implemented in the form of a voltage pump circuit, which can also be referred to as a high voltage (HV) circuit.

  The data buffer 150 is configured to receive and temporarily store input data Data. The control logic circuit 160 controls the data buffer 150 and the voltage generator 140 with a command CMD supplied from the outside in order to generate the input data signals HVDIN0 to VDIN7. In the present embodiment, the data buffer 150 can receive and temporarily store the command CMD. The selection switch 120 is controlled by address control signals Y0-Y3 and input data signals HVDIN0-VDIN7 to supply the bit lines BL to the memory cell array 110.

  In order to better describe the following embodiments, the “data path DP” provided in this embodiment is defined to include the following steps. (1) The input data Data is input to the memory device 100 and temporarily stored in the data buffer 150. (2) The control logic circuit 160 uses the command CMD to temporarily store the input data Data stored in the data buffer 150. Are sequentially transferred to the voltage generator 140. (3) The voltage generator 140 converts the input data Data in the logic domain into input data signals (for example, HVDIN0-VDIN7) in the high voltage domain, and the input data signal Is supplied to the data input terminal of the selection switch 120, and (4) the memory cell on which the PGM pulse operation is to be performed performs a programming bias operation on the bit line BL generated by the input data signal. If the PGM pulse operation is to be performed on a particular memory cell, the input data signal corresponding to the particular memory cell is a high voltage signal, otherwise the corresponding input data signal is 0 volts ( V). In the present embodiment, the “control path CP” is defined to include the following steps. (1) the row decoder 130 obtains the memory cell address Adr; (2) the row decoder 130 decodes the memory cell address Adr in order to control several pass switches of the selection switch 120; Thereby, an input data signal corresponding to the path switch can be transmitted through the path switch, and a specific memory cell can be reached.

  How the PGM pulse operation affects the total time spent in the programming operation will be described in detail hereinafter. In the NOR flash memory, the number of memory cell bits that can be simultaneously programmed is determined by the driving function of the voltage generator 140 with respect to the current. Programming operations performed on memory cells require a large amount of current to drive the memory cells. However, the voltage generator 140 cannot drive a large number of memory cells due to the limited drive function for current. Therefore, the control logic circuit 160 is often applied to sequentially arrange the input data Data so as to separate and partially perform the programming operation to the memory cell until the operation is completed. is there. That is, the control logic circuit 160 arranges the data path sequence of the data path DP according to the data path scheme so as to determine the time spent for the programming operation. The “pump capacity” provided in the present embodiment is the number of bits of the PGM pulse operation performed simultaneously on the memory cells to be programmed by the voltage generator 140.

  FIG. 2 illustrates a detailed circuit of some elements of the memory device 100 shown in FIG. Referring to FIG. 2, there are 32 memory cells to be programmed in the memory cell array 110, and the selection switch 120 has a plurality of data path groups 121 to 128 (ie, 8 data path groups), and each data A path group is assumed to consist of a plurality of path switches (ie, four path switches). The number of bits in the address control signals Y0 to Y3 (ie, 4) is equal to the number of path switches in the data path group (ie, 4). The number of memory cells to be programmed into the memory cell array 110 (ie, 32) multiplies the number of path switches (ie, 4) in one data path group by the number of data path groups (ie, 8). Is equal to the product obtained. The number of data path groups 121-128 (ie, 8) is greater than the pump capacity (ie, 2).

  In the present embodiment, the number of PGM pulse operation bits simultaneously performed on the memory cell to be programmed is two. That is, the pump capacity of the voltage generator 140 is 2. For example, when the first PGM pulse operation needs to be performed on the memory cell cA and the memory cell cB, a signal corresponding to the input data signals HVDIN0 and HVDIN7 should be supplied (for example, the programming operation is performed on the memory cell). The input data signal is a high voltage signal if it is required to be implemented at, and the input data signal is at 0V if the programming operation need not be performed on the memory cell. In addition, certain path switches in the data path groups 121 and 122 are controlled to be turned on by the address control signal Y0, and thus as indicated by arrows 210 and 220 in FIG. 2 to perform the PGM pulse operation. In this way, the input data signals HVDIN0 and HVDIN7 are transmitted to the memory cells cA and cB. That is, in order to complete the PGM pulse operation on the 32-bit memory cell, the PGM pulse operation needs to be performed 16 times.

Table 1 shows a control pass sequence and a data pass sequence during the PGM pulse operation performed 16 times on a 32-bit memory cell. The “control path sequence” indicates an order in which several path switches are turned on by an address control signal, and the “data path sequence” indicates an order in which input data signals are input.

  It can be seen from Table 1 that the memory device 100 of FIG. 1 performs PGM pulse operations one by one on a 32-bit memory cell. In the data path scheme, as long as the corresponding control path sequence and the corresponding data path sequence can be generated according to the order of the received memory cell address Adr and the input data Data, the row decoder 130 and the control logic circuit shown in FIG. Reference numeral 160 does not need to refer to the input data Data in order to adjust the control path sequence of the control path CP and the data path sequence of the data path DP.

  However, the data path scheme is very time consuming because many memory cells that do not require a programming operation still undergo a programming operation that will be described in detail hereinafter. Depending on the order in which data is written to the flash memory, an erase operation is performed to reset the memory cells of all the flash memory devices as a logic “1”, changing the bits of some memory cells to a logic “0”. First, a programming operation is performed on the memory cell. That is, it is not necessary to perform a programming operation every time on a 32-bit memory cell.

  For example, if the programming operation needs to be performed on the memory cell cA shown in FIG. 2 but the memory cell cB does not need to be programmed, the PGM pulse operation is performed for the first time (ie, the PGM pulse operation is performed). The number of times of execution is 1), and the voltage generator 140 transmits high voltage data to the input data signal HVDIN0 and transmits 0 V to the input data signal HVDIN1.

  In addition, various input data Data affects the efficiency of the voltage generator 140 during operation. For example, in the data path scheme according to Table 1, whether to require each memory cell to be supplied with current by the voltage generator 140, depending on the bit arrangement of the input data Data, in order to perform the PGM pulse operation. Not considered. The specific mapping relationship between the physical address and the logical address of the memory cell is described in the following embodiments. Here, for example, the bit values corresponding to the physical addresses B0 and B1 and the logical addresses D00 and D08 are captured. When the two bit values corresponding to the logical addresses D00 and D08 of the input data Data are both logical values “1”, a high voltage signal is not necessary, and the utilization factor of the voltage generator 140 is zero. When one of the bit values corresponding to the logical address D00 or the logical address D08 of the input data Data is the logical value “0” and the other bit values are the logical value “1”, the voltage generator 140 The utilization rate is 50%. When the two bit values corresponding to the logical addresses D00 and D08 of the input data Data are both logical values “0”, the utilization rate of the voltage generator 140 reaches 100%. In other words, as long as the utilization rate of the voltage generator 140 does not reach 100%, the time spent performing the PGM pulse operation is wasted.

  FIG. 3 is a block diagram of a memory device 300 according to one embodiment of the invention. The difference between FIG. 1 and FIG. 3 is that the control logic circuit 160 shown in FIG. 1 is replaced by the memory controller shown in FIG. The memory controller 360 shown in FIG. 3 is connected to the row decoder 130 as well as the data buffer 150 and the voltage generator 140. In this embodiment, the memory controller 360 can directly read the input data Data and the command CMD, and can also read the necessary input data Data from the data buffer 150. In other words, the memory controller 360 and the data buffer 150 can be connected bidirectionally, so that the memory controller 360 controls the data buffer 150 to read and temporarily store the input data Data. Can do. In order to perform a programming operation on the memory cells of the memory cell array 110, the memory controller 360 shown in FIG. 3 controls the row decoder 130 according to the input data Data in order to adjust the control pass sequence of the address control signals Y0-Y3. The memory controller 360 simultaneously controls the voltage generator 140 to adjust the data path sequence of the input data signals HVDIN0 to HVDIN7 according to the input data Data. Memory controller 360 may be implemented in the form of a control device such as a logic circuit, a microprocessor, or the like.

  When the memory device 100 shown in FIG. 1 is compared with the memory device 300 shown in FIG. 3, the control logic circuit 160 shown in FIG. 1 can only control the data path DP. In contrast, the memory controller 360 shown in FIG. 3 can simultaneously control the data path DP and the control path CP with the bit data of the input data Data in order to rearrange the contents of the data path sequence and the control path sequence. it can. Thereby, a memory cell that requires a programming operation can receive the operation, and a memory cell that does not require a programming operation skips the operation. As such, the number of times the programming operation is performed in the memory device 300 can be reduced to reduce the time spent on the programming operation. In the following, embodiments that can cover the scope and spirit of the present invention will be provided, and those who apply the embodiments can make necessary adjustments to the following embodiments according to their needs.

  Here, the mapping relationship between the physical address and the logical address of the memory cell will be described. FIG. 4 illustrates the mapping relationship between the physical addresses Bit00-Bit32 and the logical addresses D00-D31 of the memory cells. As shown in FIG. 4, based on the application of the cache memory device, the physical address of the memory cell is different from the logical address of the memory cell. If it is intended to access memory cells sequentially, the access speed is too slow. Therefore, in the present embodiment, the memory cells to be programmed (that is, 32-bit memory cells) are the number of data path groups 121 to 128 (that is, eight) of the memory cells to be programmed and the physical address Bit00−. According to Bit 32, the memory cell groups are classified into a plurality of memory cell groups (that is, eight memory cell groups G1-G8). Each of memory cell groups G1-G8 corresponds to one of data path groups 121-128, respectively. The mapping relationship between the physical address and the logical address of the memory cell to be programmed is as follows: The physical address of the j-th memory cell in the i-th memory cell group is [(i−1) × 4 + (j−1)], and the logical address of the j-th memory cell in the i-th memory cell group is [(J−1) × 8 + (i−1)], i and j are positive integers, i is less than or equal to the number of data path groups 121-128 (ie, 8), and j is The number of one path switch in the data path group (that is, four) or less. For example, the physical address of the first memory cell of the first memory cell group is Bit00 (“0 × 8 + 0”), the logical address is D00 (“0 × 8 + 0”), and the third memory cell group The physical address of the first memory cell is Bit08 (“2 × 4 + 0”), the logical address is D02 (“0 × 8 + 2”), and the physical address of the third memory cell in the fifth memory cell group is The address is Bit 18 (“4 × 4 + 2”), and the logical address is D20 (“2 × 8 + 4”). The logical addresses D00-D31 of the memory cells in the memory cell group G1-G8 are the same as the logical address of the input data Data.

  The data path scheme used by the memory controller 360 of FIG. 3 will be described with reference to FIG. 5 in order to implement the PGM pulse operation described in the embodiment of the present invention. FIG. 5 is a flowchart illustrating a method of programming a memory cell array according to an embodiment of the present invention. Here, input data Data [31: 0] equal to (1111-1110-1111-1100-1111-0010-1111-1100) is taken as an example. For example, the bits Data [0], Data [8], Data [16], Data [24], Data [1], Data [17], Data [10] and Data [11] are all logical values “0”. The other bits of the input data Data are logical values “1”. In addition, the logical address of Data [0] is D00, the logical address of bit Data [1] is D01, and the others can be estimated from them.

  Referring to FIGS. 3 and 5, in step S510, the memory controller 360 performs initialization, and sets the first memory cell group G1 as a memory cell group to be searched in the following steps. That is, the memory controller 360 sets i as 1 (i = 1) to indicate the first memory cell group G1.

  The memory controller 360 then searches the input data Data for at least one first bit having a specific value, the at least one first bit corresponding to the logical address of the memory cell of the memory cell group. However, a specific value indicates that a programming operation is required. For example, in step S520, since the memory cell group to be searched is set as the first memory cell group G1 prior to step S510, the memory controller 360 sets the logical address of the memory cell in the first memory cell group G1. Bits of input data Data (ie, Data [0], Data [8], Data [16] and Data [24]) corresponding to (ie logical addresses D00, D08, D16 and D24) require programming operation Whether or not it has a specific value (ie, logical value “0”). In step S530, the bits of input data Data, Data [0], Data [8], Data [16] and Data [corresponding to the logical addresses D00, D08, D16 and D24 of the memory cells in the first memory cell group G1. 24] the memory controller 360 determines whether none of the values have a specific value. Bits of input data Data, Data [0], Data [8], Data [16] and Data [24] corresponding to logical addresses D00, D08, D16 and D24 of the memory cells of the first memory cell group G1 are logical. If the memory controller 360 determines that is not a value “0” but a logic value “1”, then step S532 is further performed after step S530, and the memory controller 360 has the memory cell group as the last memory cell group. Determine if it is G8. That is, the memory controller 360 determines whether i is 8. If the memory cell group is not the last memory cell group, step S534 is further performed after step S532, 1 is added to the value i representing the number of the memory cell group (ie, i ++ 1), and step S520 is performed again. And the bits of the input data Data mapped to the logical addresses of the memory cells of the next memory cell group (ie, the second memory cell group G2) (ie, the logical addresses D01, D09, D17, and D25) are Determine if it has a specific value (ie, logical “0”) indicating that a programming operation is required.

  A specific value (ie, logical value “0”) from at least one first bit corresponding to the logical addresses D00, D08, D16 and D24 of the memory cells of the specific memory cell group (ie, first memory cell group G1) ") Is already determined by the memory controller 360, that is, if the bit Data [0] is the logical value" 0 ", step S540 is performed after step S530, and the memory controller 360 Count the number of one first bit and determine whether the number of the first bit of the input data Data has reached the pumping capability (ie 2) of the voltage generator. In the present embodiment, since the bits Data [0] and Data [8] corresponding to the logical addresses D00 and D08 are both logical values “0”, the bits Data [0] and Data [8] are both It belongs to the “first bit” and the number of “first bits” reaches two.

If the number of first bits of the input data Data reaches the pumping capability (ie, 2), step S560 is performed after step S540, and the memory controller 360 receives the specific data corresponding to the specific memory cell group G1. The path group 121 sets the input data signal HVDIN0, and the logical address D00 and D08 corresponding to the first bit of the input data Data (ie, bits Data [0] and Data [8]) causes the address control signal Y0 and Set Y1. The logical addresses D00 and D08 correspond to the address control signals Y0 and Y1, respectively. In addition, the logical addresses D00 and D08 correspond to the physical addresses Bit00 and Bit01 of the memory cell, respectively. At this time, the number of times of performing the PGM pulse operation, the control path sequence, and the data path sequence are shown in Table 2.

  In step S570, the address control signal Y0 / Y1 in which the data of the row corresponding to the number of times of performing the PGM pulse operation shown in Table 2 above (ie, 1) and the set input data signal HVDIN0 are In order to adjust the control path sequence of the address control signal, the memory controller 360 controls the row decoder 130 to adjust the data path sequence of the input data signal to perform the programming operation on the corresponding memory cell. The memory controller 360 controls the voltage generator 140 at the same time. After completing step S570, the process returns to step S520, and further, a programming operation on the memory cell is performed.

In this embodiment, the bits Data [16] and Data [24] of the input data Data of the same memory cell group G1 are logical values as given in steps S520, S530, S540, S560 and S570. Since it is “0”, the programming operation is performed on the specific data path group G1 and memory cells corresponding to the logical addresses D16 and D24 by the set input data signal and the set address control signal. The logical addresses D16 and D24 correspond to the physical addresses Bit02 and Bit03 of the memory cell, respectively. Data in the row corresponding to the number of times the PGM pulse operation is performed (ie, 2) is added to Table 2 and shown in Table 3 below.

  After step S570, step S520 is then performed. Since each memory cell in the memory cell group G1 receives the PGM pulse operation, the memory controller 360 causes the logical address (ie, logical address D01) of the memory cell in the next memory cell group (ie, the second memory cell group G2). , D09, D17 and D25), the bits of the input data Data (ie Data [1], Data [9], Data [17] and Data [25]) indicate that a programming operation is required (I.e., the logical value "0").

The memory controller 360 determines that the bits Data [1] and Data [17] of the input data Data corresponding to the logical addresses D0 and D17 of the memory cells in the memory cell group G2 are logical values “0”. After steps S530 and S540, step S540 is performed, and the memory controller 360 counts the number of first bits (bits Data [1] and Data [17]) to two. Step S570 is performed after steps S540 and S560, and the memory controller 360 sets the input data signal HVDIN01 by the specific data path group 122 corresponding to the specific memory cell group G2, and the first bit of the input data Data Address control signals Y0 and Y3 are set by logical addresses D01 and D17 corresponding to (that is, bits Data [1] and Data [17]). The logical addresses D01 and D17 correspond to the address control signals Y0 and Y3, respectively. The memory controller 360 then selects the memory cell corresponding to the specific memory cell group G2 and the logical addresses D01 and D17 according to the data in the row corresponding to the number of times of performing the PGM pulse operation in Table 4 below (ie, 3). Perform the above programming operation. Logical addresses D01 and D17 correspond to physical addresses Bit04 and Bit06, respectively.

  The process returns to step S520. The memory controller 360 specifies that the bit (ie, Data [25]) of the input data Data corresponding to the logical address (ie, logical address D25) of the memory cell in the memory cell group G2 indicates that a programming operation is required. (I.e., the logical value "0"). Since the bit Data [25] is not the logical value “0” and all the bits of the input data Data of the memory cell of the corresponding memory cell group G2 have been searched, step S534 is then performed after steps S530 and S532. Then, 1 is added to the numerical value i representing the memory cell group (ie, i = 3), and the process returns to step S520.

  The memory controller 360 includes bits (that is, Data [2], Data [10], Data of input data Data corresponding to logical addresses (that is, logical addresses D02, D10, D18, and D26) of the memory cells of the memory cell group G3. [18] and Data [26]) determine whether they have a specific value (ie, logical “0”). The memory controller 360 determines that only the bit Data [10] of the bits Data [2], Data [10], Data [18], and Data [26] is the logical value “0”, so that step S530 is performed. After step S540, the memory controller 360 counts the number of first bits, and whether the number of first bits of the input data Data has reached the voltage generator's pumping capability (ie, 2). To decide. In the present embodiment, only the bit Data [10] corresponding to the logical address of the memory cell group G3 is the “first bit”. Here, if the number of first bits of the input data Data does not reach the pumping capability (ie, 2) of the voltage generator, step S550 is performed after step S540, and another memory cell group (ie, memory cell) is executed. A second group having an address control signal that is identical to the address control signal Y1 of the first bit (ie, Data [10]) of the particular memory cell group (ie, memory cell group G3) from the group G4 to G8) The memory controller 360 searches for bits. In the present embodiment, the address control signal corresponding to the bit Data [10] is Y1, and therefore the memory cell groups G4 to G8 have the same address control signal Y1 and have a specific value (logical value “0”). The memory controller 360 searches for bits that need to have. As such, bit Data [11] in memory cell group G4 is found.

  When the memory controller 360 finds the second bit (ie, Data [11]) from another memory cell group (eg, memory cell group G4), step S562 is performed after step S550, and subsequent PGM pulses The memory controller 360 records the second bit to prevent the operation from being performed repeatedly on the second bit. After step S562, step S565 is then performed, and the memory controller 360 performs a specific data path group 123 corresponding to the specific memory cell group G3 and another data path group 124 corresponding to the other memory cell group G4. The input data signals HVDIN02 and HVDIN3 are set, and the address control signal Y1 is set by the logical address D10 corresponding to the first bit (that is, Data [10]) of the input data Data. The reason why the single address control signal Y1 is set is that the address control signal corresponding to the bit Data [10] and the bit Data [11] is Y1. That is, the bits Data [10] and Data [11] share the address control signal Y1.

Table 5 shows the number of times the PGM pulse operation is performed, the control path sequence, and the data path sequence at this time.

  The memory cell (physical address) corresponding to the set input data signal HVDIN2 / HVDIN3 and the set address control signal Y1 according to the data of the row corresponding to the number of times of performing the PGM pulse operation of Table 5 below (ie, 4) The memory controller 360 performs a PGM pulse operation.

  The process returns to step S520. Since all the bits of the input data Data corresponding to the logical addresses of the memory cell groups G5 to G8 have the logical value “1”, the memory cells corresponding to these bits do not need to undergo the PGM pulse operation. Therefore, after steps S530, S532, and S590 are performed, the programming operation on the memory cell array 110 ends.

  The above embodiment does not disclose a state where the second bit is not found in step S550, which will be described below. Assume that the bit Data [11] is a logical value “1” instead of the logical value “0” described in the previous embodiment. If the bit Data [10] of the input data Data corresponding to the memory cell group G3 has already been found and step S550 is performed, the following other memory cell groups (ie, memory cell groups G4-G8) From the memory controller 360, the second bit having the same address control signal as the address control signal Y1 of the first bit (ie, Data [10]) of the specific memory cell group (ie, the memory cell group G3). Search for. However, since all the bits of the input data Data corresponding to the logical addresses of the memory cell groups G4 to G8 are the logical value “1”, the second bit is not found. Therefore, after step S550, step S560 is then performed, and the memory controller 360 sets the input data signal HVDIN02 by the specific data path group 123 corresponding to the specific memory cell group G3, and sets the input data Data The address control signal Y1 is set by the logical address D10 corresponding to 1 bit (that is, Data [10]).

At this time, Table 6 shows the number of times the PGM pulse operation is performed, the control path sequence, and the data path sequence.

  In step S570, the data in the row corresponding to the number of times of performing the PGM pulse operation in Table 6 below (ie, 4) corresponds to the specific memory cell group G3 and the logical address D10 (first bit Data [10]). The memory controller 360 performs the PGM pulse operation on the memory cell (having the physical address Bit09) corresponding to

  According to the previous embodiment, a smaller number of times of performing the PGM pulse operation on the memory to be programmed of the memory cell array 110 is required, for example, the memory device 100 shown in FIG. While the memory device 300 shown in FIG. 3 and given in Table 5 or 6 requires four times to perform the PGM pulse operation, thereby generating the voltage generation shown in FIG. The usage rate of the device 140 is maximized.

  In summary, the memory controller of the memory device provided in one or more embodiments rearranges the sequence that activates the data path according to the input data of the data buffer (ie, the control path sequence of the address control signal), The data path data supply sequence (that is, the data path sequence of the input data signal) is rearranged simultaneously. Thereby, a memory cell that requires a programming operation can receive such an operation, and a memory cell that does not require such an operation is skipped. As such, the number of times the memory device programming operation is performed can be reduced to reduce the time spent on the programming operation.

  It will be apparent to those skilled in the art that various changes and modifications can be made to the disclosed embodiments without departing from the scope and spirit of the invention. In view of the foregoing, it is intended that the present invention cover changes and modifications provided they are within the scope of the following claims and their equivalents.

  The memory device and the memory cell array programming method can be applied to a storage device or an electronic device.

100, 300 Memory device 110 Memory cell array 120 Select switch 121-128 Data path group 130 Row decoder 135 Column decoder 140 Voltage generator 150 Data buffer 160 Control logic circuit 210, 220 Arrow 360 Memory controller S510-S590 Steps
Adr memory cell address
Data input data
Y0-Y3 Address control signal

Claims (16)

A memory cell array comprising a plurality of memory cells;
A selection switch coupled to the memory cell array;
A row decoder coupled to the select switch and receiving a memory cell address to generate an address control signal;
A voltage generator coupled to the selection switch;
A memory controller, coupled to the row decoder and the voltage generator, for obtaining input data for controlling the voltage generator to generate an input data signal,
The memory controller controls the row decoder according to input data to adjust a control pass sequence of the address control signal to perform a programming operation on the plurality of memory cells, and the memory controller A memory device that simultaneously controls the voltage generator to adjust a data path sequence of the input data signal.   The memory device of claim 1, wherein the memory device is a NOR cache memory.   The selection switch includes a plurality of data path groups, and each of the plurality of data path groups includes a plurality of path switches, and the number of one bit in the address control signal is the number of the plurality of data path groups. And the number of the plurality of memory cells to be programmed into the memory cell array is equal to the number of the plurality of path switches in one of the plurality of path switches in one of the plurality of data path groups. The memory device of claim 1, wherein the number of switches is equal to a product obtained by multiplying the number of the plurality of data path groups. The memory cells to be programmed are classified into a plurality of memory cell groups according to the number and physical addresses of the plurality of data path groups of the memory cells to be programmed, and the plurality of memory cell groups are respectively Corresponding to the plurality of data path groups,
The mapping relationship between the physical address and the logical address of the memory cell to be programmed is the j-th memory cell of the plurality of memory cells in the i-th memory cell group of the plurality of memory cell groups. The physical address is [(i−1) × 4 + (j−1)], and the logical address of the j th memory cell in the i th memory cell group is [(j−1) × 8 +. (I-1)], i and j are positive integers, i is less than or equal to the number of the plurality of data path groups, and j is the one of the plurality of data path groups. Less than or equal to the number of path switches,
4. The memory device according to claim 3, wherein the logical address of the plurality of memory cells of the plurality of memory cell groups is the same as the logical address of the input data. The memory controller searches for at least one first bit having a specific value in the input data, and the at least one first bit is the plurality of memory cells of the plurality of memory cell groups. The specific value indicates that the programming operation is required, and
When the at least one first bit corresponding to the logical address of the plurality of memory cells of a specific memory cell group has the specific value, the memory controller has a number of the at least one first bit. And the specific memory cell group is one of the plurality of memory cell groups,
If the number of the at least one first bit of the input data reaches the pumping capability of the voltage generator, the memory controller identifies the plurality of data path groups corresponding to the particular memory cell group. The input data signal is set by the data path group, and the address control signal is set by the logical address corresponding to the at least one first bit of the input data, and the logical address and the specific 4. The memory device of claim 3, wherein the programming operation is performed on the plurality of memory cells corresponding to a plurality of data path groups. If the number of the at least one first bit of the input data does not reach the pumping capability of the voltage generator, the memory controller may, from another memory cell group, the at least one of the specific memory cell groups. Searching for a second bit having an address control signal identical to the address control signal of one first bit;
When the memory controller finds the second bit from the other memory cell group, the memory controller sets the specific data path group and the other memory cell group corresponding to the specific memory cell group. The input data signal is set by another corresponding data path group, and the address control signal is set by the logical address corresponding to the at least one first bit of the input data. 6. The memory device according to claim 5, wherein the programming operation is performed on the plurality of memory cells corresponding to a data path group, the other data path group, and the logical address.   If the memory controller does not find a second bit from another memory cell group, the memory controller sets the input data signal according to the specific data path group corresponding to the specific memory cell group. And the address control signal is set by the logical address corresponding to the at least one first bit of the input data, on the plurality of memory cells corresponding to the specific data path group and the logical address. 6. The memory device of claim 5, wherein the programming operation is performed.   When the at least one first bit corresponding to the logical address of the plurality of memory cells of the plurality of memory cell groups does not have the specific value, the memory controller performs the programming on the memory cell array. The memory device according to claim 5, wherein the memory device stops performing an operation. Obtaining input data;
Adjusting the control path sequence of the address control signal according to the input data, and simultaneously adjusting the data path sequence of the input data signal;
Performing a programming operation on some or all of a plurality of memory cells of the memory cell array according to the address control signal and the input data signal. The programming method according to claim 9, wherein the memory cell array is arranged in a NOR cache memory.   The address control signal controls a plurality of data path groups, and each of the plurality of data path groups is constituted by a plurality of path switches, and the number of one bit in the address control signal is the number of the plurality of data path groups. The number of the plurality of memory cells to be programmed into the memory cell array is equal to the number of the plurality of path switches in one of the groups, the number of the plurality of memory cells in one of the plurality of data path groups The programming method of claim 9, wherein the number of path switches is equal to a product obtained by multiplying the number of the plurality of data path groups. Classifying the memory cells to be programmed into a plurality of memory cell groups according to the number and physical addresses of the plurality of data path groups of the memory cells to be programmed, wherein the plurality of memory cell groups Each further includes a step corresponding to the plurality of data path groups,
The relationship between the physical address and the logical address of the memory cell to be programmed is the j-th memory cell of the plurality of memory cells in the i-th memory cell group of the plurality of memory cell groups. The physical address is [(i−1) × 4 + (j−1)], and the logical address of the j th memory cell in the i th memory cell group is [(j−1) × 8 + ( i-1)], i and j are positive integers, i is less than or equal to the number of the plurality of data path groups, and j is the plurality of data paths in one of the plurality of data path groups. Less than or equal to the number of path switches
The programming method according to claim 11, wherein the logical address of the plurality of memory cells of the plurality of memory cell groups is the same as a logical address of the input data. Adjusting the control path sequence of the address control signal according to the input data, and simultaneously adjusting the data path sequence of the input data signal;
Searching for at least one first bit having a specific value in the input data, wherein the at least one first bit is stored in the plurality of memory cells of the plurality of memory cell groups; Corresponding to a logical address, wherein the specific value indicates that the programming operation is required; and
Counting the number of the at least one first bit when the at least one first bit corresponding to the logical address of the plurality of memory cells of the specific memory cell group has the specific value; The specific memory cell group is one of the plurality of memory cell groups; and
When the number of the at least one first bit of the input data reaches the pumping capability of the voltage generator, according to a specific data path group of the plurality of data path groups corresponding to the specific memory cell group And setting the address control signal according to the logical address corresponding to the at least one first bit of the input data. Programming method. Adjusting the control path sequence of the address control signal according to the input data and simultaneously adjusting the data path sequence of the input data signal;
If the number of the at least one first bit of the input data does not reach the pumping capability of the voltage generator, from at least one other memory cell group, the at least one first of the particular memory cell group Searching for a second bit having an address control signal that is identical to the address control signal of bits;
When the second bit is found from the other memory cell group, the specific data path group corresponding to the specific memory cell group and the other data path group corresponding to the other memory cell group are: The programming of claim 13, comprising setting the input data signal and setting the address control signal with the logical address corresponding to the at least one first bit of the input data. Method. Adjusting the control path sequence of the address control signal according to the input data and simultaneously adjusting the data path sequence of the input data signal;
If the second bit is not found from the other memory cell group, the input data signal is set by the specific data path group corresponding to the specific memory cell group, and the input data The programming method according to claim 14, further comprising setting the address control signal according to the logical address corresponding to the at least one first bit. Adjusting the control path sequence of the address control signal according to the input data and simultaneously adjusting the data path sequence of the input data signal;
When the at least one first bit corresponding to the logical address of the plurality of memory cells of the plurality of memory cell groups does not have the specific value, the programming operation is performed on the memory cell array. The programming method according to claim 14, further comprising the step of stopping.