JP2019201394A - Analog-to-digital converter device and method for generating signal to be tested - Google Patents

Abstract

An analog-to-digital converter device is provided. SOLUTION: The clock signal is used to generate a plurality of quantized outputs by converting an input signal based on a plurality of interleaved clock signals respectively corresponding to a plurality of channels, and each of the clock signals has a sampling frequency. A plurality of analog-digital converter circuit systems, and a data output circuit system that performs a downsampling operation based on a control signal and the quantized output to output a digital signal, wherein the digital signal is an analog-digital converter circuit. An analog-to-digital converter device used for determining the performance of a system, wherein the frequency of a digital signal is equivalent to N / M times the sampling frequency, where N is a positive integer and the number of channels. [Selection diagram] Figure 1A

Description

  The present disclosure relates to an analog-to-digital converter device, and more particularly to a time-interleaved analog-to-digital converter and a method for generating a signal under test thereof.

  Analog-to-digital converters (e.g., U.S. Pat. No. 5,637,097) are often used in various electronic devices to convert analog signals to digital signals for signal processing.

US Pat. No. 8,730,072

  The higher the resolution and operating speed of an analog-to-digital converter, the higher the cost and difficulty of measuring the performance of the analog-to-digital converter. For example, the higher the resolution and the more pins the analog-digital converter needs to measure, the larger the circuit area. Alternatively, the higher the operating speed, the higher the data transmission rate of the converted digital signal, and the higher the specification requirements of the measuring device.

  In order to solve the above problem, an aspect of the present disclosure is to generate a plurality of quantized outputs by converting an input signal based on a plurality of interleaved clock signals corresponding to a plurality of channels, respectively. A plurality of analog-to-digital converter circuit systems, each of which has a sampling frequency, coupled to the analog-to-digital converter circuit system, and a downsampling operation based on a first control signal and the quantized output And a data output circuit system used to output a first digital signal, wherein the first digital signal is used to determine the performance of the analog-to-digital converter circuit system, The frequency of the first digital signal is N / M times the sampling frequency, and N is a positive integer and And to provide an analog-to-digital converter device is the number of the channel.

One aspect of the present disclosure converts an input signal based on a plurality of clock signals interleaved by a plurality of analog-to-digital converter circuit systems to generate a plurality of quantized outputs, each of the clock signals having a sampling frequency. And performing a downsampling operation based on the first control signal and the quantized output to output a first digital signal, the first digital signal being the analog-to-digital converter circuit system The frequency of the first digital signal is N / M times the sampling frequency, and N is a positive integer and the number of channels. is there.
In one embodiment, the frequency of the first control signal is N / M times the sampling frequency.

  In one embodiment, the data output circuit system is coupled to the analog-to-digital converter circuit system and selects one of the quantized outputs based on a second control signal for output as a second digital signal. And a multiplexer coupled to the multiplexer and used to generate the first digital signal by performing the downsampling operation based on the first control signal and the second digital signal. And a downsampling circuit in which M is a prime number different from N.

  In one embodiment, the frequency of the second control signal is N times the sampling frequency.

  In one embodiment, the data output circuit system is coupled to the analog to digital converter circuit system and selects one of the quantized outputs based on the first control signal as a second digital signal. A multiplexer used to output, and a sequence circuit coupled to the multiplexer and used to generate the first digital signal by combining the second digital signal and at least one redundant data. .

  In one embodiment, the frequency of the second control signal is equal to the sampling frequency.

  In one embodiment, the data output circuit system is coupled to the analog to digital converter circuit system and performs a data combination operation based on a second control signal and the quantized output to generate a second digital signal. A first data output subcircuit used to generate a third digital signal by performing the downsampling operation based on the first control signal and the second digital signal; and the analog-to-digital conversion Is coupled to the circuit system, selects one of the quantized outputs based on a third control signal, outputs a fourth digital signal, and performs the downsampling operation based on the fourth digital signal A second data output subcircuit used to generate a fifth digital signal, the first data output subcircuit, and the Coupled to the second data output sub-circuit, and a control circuit for use with one of said third digital signal and said fifth digital signal to selectively output as the first digital signal.

  In one embodiment, the control circuit is coupled to the first data output sub-circuit to receive the third digital signal and when the first switch is turned on, the first data output sub-circuit Is coupled to the first switch for outputting the third digital signal as the first digital signal by the first switch and the second data output sub-circuit for receiving the fifth digital signal. When the second switch is turned on, the second data output subcircuit includes a second switch for outputting the fifth digital signal as the first digital signal by the second switch.

  In summary, the analog-to-digital converter device and the signal-under-test generation method provided in the present disclosure perform a low-sampling operation on a quantized output of a plurality of channels, thereby generating a signal under test for low frequencies. Can be generated. In this way, the hardware cost and difficulty of measuring the overall performance of the analog-to-digital converter device can be reduced.

The drawings of the present disclosure are as follows.
FIG. 3 is a schematic diagram illustrating an analog-to-digital converter device according to an embodiment of the present disclosure. 1B is a waveform schematic diagram illustrating a plurality of clock signals in FIG. 1A according to an embodiment of the present disclosure. FIG. 1B is a circuit schematic diagram illustrating the data output circuit system in FIG. 1A according to an embodiment of the present disclosure. FIG. 1B is a circuit schematic diagram illustrating the data output circuit system in FIG. 1A according to an embodiment of the present disclosure. FIG. 2 is a circuit schematic diagram showing a data output circuit system and a control circuit according to an embodiment of the present disclosure. FIG. FIG. 5 is a flow diagram illustrating a method for generating a signal under test according to an embodiment of the present disclosure.

  All terms used in this specification have a general meaning. The above vocabulary is defined in commonly used dictionaries, and examples of use that include the vocabulary discussed herein herein are merely exemplary and do not limit the scope or meaning of the present disclosure. As such, the present disclosure is not limited to the various embodiments shown herein.

  As used herein, “coupled” or “connected” means that two or more elements are directly or substantially in contact with each other or indirectly or in contact with each other. Alternatively, two or more elements may operate or operate on each other.

  As used herein, the term “circuitry” refers to a single system consisting of one or more circuits. The term “circuit” generally refers to an object in which one or more transistors and / or one or more active and passive elements are connected in a certain manner to process signals.

  As used herein, “about”, “substantially” or “equivalent” generally has a numerical error or range within 20%, preferably within 10%, more preferably 5%. Is within. In the text, unless expressly stated otherwise, all numerical values referred to are considered approximations, such as errors or ranges expressed as, for example, “about”, “substantially”, or “equivalent”.

  Please refer to FIG. 1A and FIG. 1B. FIG. 1A is a schematic diagram illustrating an analog-to-digital converter (ADC) apparatus 100 according to an embodiment of the present disclosure. FIG. 1B is a schematic waveform diagram illustrating a plurality of clock signals CLK1 to CLKN in FIG. 1A according to an embodiment of the present disclosure. In one embodiment, the ADC device 100 is operated as a time-interleaved ADC with multiple channels.

  In one embodiment, the ADC device 100 includes a plurality of analog to digital converter circuit systems AD1 to ADN and a data output circuit system 130. Each of the analog-to-digital converter circuit systems AD1-ADN is operated as a single channel. That is, in this example, the ADC device 100 includes N channels, and N is a positive integer larger than 1. The data output circuit system 130 generates a digital signal D0 by performing a data combination operation and a downsampling operation based on the quantized outputs Q1 to QN from a plurality of channels, or by performing only a downsampling operation. Used for. In one embodiment, as shown in FIG. 3 below, the data output circuit system 130 can generate the digital signal D0 when the data combination operation is not performed.

  As shown in FIG. 1A, the plurality of analog-to-digital converter circuit systems AD1 to ADN perform analog-to-digital conversion on the input signal VIN based on the corresponding ones of the plurality of clock signals CLK1 to CLKN, thereby Used to generate corresponding ones in the digitized outputs Q1-QN. As shown in FIG. 1B, each cycle of the plurality of clock signals CLK1 to CLKN is set to TS and equal to 1 / fs. That is, the sampling frequency of the plurality of analog-digital converter circuit systems AD1 to ADN is fs.

  Taking the first channel as an example, the analog-to-digital converter circuit system AD1 includes a sampling circuit 110 and an ADC circuit 120. The sampling circuit 110 samples the input signal VIN based on the corresponding clock signal CLK1 to generate the sampling signal S1. The ADC circuit 120 is coupled to the sampling circuit 110 and receives the sampling signal S1. The ADC circuit 120 performs analog-digital conversion based on the corresponding clock signal CLK1, and generates a quantized output Q1. The output of the ADC circuit 120 is coupled to the data output circuit system 130 to transmit the quantized output Q1 to the data output circuit system 130. The operation of the remaining channels is the same as that of the first channel and will not be described in detail here.

  In one embodiment, there is a scheduled delay TD between two adjacent clock signals in the plurality of clock signals CLK1-CLKN. For example, as shown in FIG. 1B, there is a scheduled delay TD between the clock signal CLK1 and the clock signal CLK2. Thus, the first channel and the second channel perform sampling operations and analog-digital conversion at different times. By analogy with this, the N channels may operate with a plurality of interleave timings.

  The data output circuit system 130 is coupled to the plurality of ADC circuits 120 and receives the plurality of quantized outputs Q1 to QN. As described above, the data output circuit system 130 performs a data combination operation and a downsampling operation on the quantized outputs Q1 to QN by a plurality of channels to generate the digital signal D0. In one embodiment, the data output circuit system 130 performs a data combination operation (as shown in FIG. 2 below) on the plurality of quantized outputs Q1 to QN based on the control signal C1, and the frequency of the control signal C1 is The sampling frequency fs is N times. By the data combination operation, a plurality of quantized outputs Q1 to QN by N channels can be combined into a single digital signal (digital signal D1 in FIG. 2 below) having an N times sampling frequency fs. In one embodiment, the single digital signal resulting from the data combination operation process is valid digital data to be output from the ADC device 100.

  For example, the number of channels N is 20, the resolution of each channel is 10 bits, and the sampling frequency fs is set to 500 megahertz (MHz). Under this condition, the data combination operation allows the ADC device 100 to output a digital signal having 10 bits, and the frequency thereof is 1 billion hertz (GHz) (ie, 20 × 500 M).

  In one embodiment, the data output circuit system 130 performs a downsampling operation on the plurality of quantized outputs Q1 to QN based on the control signal C2 to generate the digital signal D0, and the frequency of the control signal C2 is The sampling frequency fs may be N / M times (for example, as shown in FIG. 2 below) or may be equal to the sampling frequency fs (for example, as shown in FIG. 3 below). Thus, the frequency of the digital signal D0 (or the data transmission rate (data rate)) may be reduced to be equivalent to N / M times fs. In an embodiment, the performance of the entire ADC circuit systems AD1 to ADN (that is, the ADC device 100) can be determined by measuring the digital signal D0.

  In some embodiments (as shown in FIG. 2 below), M may be set to N−1 or N + 1. For example, when the number of channels N is 20, M may be set to 19 or 21. Under this condition, the ADC device 100 can output the digital signal D0 having 10 bits by the downsampling operation, and the frequency is (20/19) × 500 MHz or (20/21) × 500 MHz. The setting mode related to M is merely an example, and the present disclosure is not limited to this. Any other prime number (for example, M is 2N + 1 or 2N−1) that can set various other M is included in the scope of the present disclosure. Setting M to a prime number is sufficient to prevent the data output circuit system 130 from outputting the same quantized output, and the digital signal D0 is sufficient to reflect the performance of the ADC device 100. Can be secured.

  In a related technology, in order to measure the performance of a time interleaved ADC, the ADC output in each channel is provided with a plurality of pins corresponding to the measurement connected to the measuring instrument, or the output data is sent to an external device. A separate memory is provided to store valid digital data as provided and measured. In these techniques, there are many different pin counts for measurement (eg, if the output of the channel ADC is a 10-bit signal, there are 10 channels because 10 pins need to be installed) 100 pins need to be installed) or another memory with a large storage space. In this way, unnecessary hardware costs are significantly improved. Further, when valid digital data is measured, it is necessary that the device can support high-speed digital data (for example, N times the sampling frequency fs). Based on the above cause, the current related technology is not easy to measure the performance of the time interleave ADC.

  In the present disclosure, the digital signal D0 resulting from the downsampling operation has a low frequency (that is, equivalent to N / M times the sampling frequency fs). Thus, the performance of the ADC device 100 can be supervised by measuring the digital signal D0. Compared to the above technique, the number of pins required (for example, 10 pins may be installed when the digital signal D0 is 10 bits) is reduced, and measurement is performed without installing another memory. Can do. In this way, the related hardware costs can be saved and the specification requirements required for the equipment can be reduced. In an embodiment (the number of channels N = 16 and the resolution of the ADC circuit system is 10 bits), the digital signal D1 or the digital signal D0 is analyzed by the above installation form and the fast Fourier transform, and the analyzed measurement results are similar. There are typical results.

  Please refer to FIG. 2 is a schematic circuit diagram illustrating the data output circuit system in FIG. 1A according to an embodiment of the present disclosure. For ease of understanding, similar elements in FIG. 2 are designated with the same reference numbers with reference to FIG. 1A.

  In one embodiment, the data output circuit system 130A includes a multiplexer 132 and a downsampling circuit 134, as shown in FIG. Multiplexer 132 is coupled to the outputs of the plurality of ADC circuits 120 in FIG. 1A and receives a plurality of quantized outputs Q1-QN. The multiplexer 132 is used to generate the digital signal D1 by performing the data combination operation based on the control signal C1. For example, the multiplexer 132 selects one of the plurality of quantized outputs Q1 to QN based on the control signal C1, and outputs the selected digital signal D1. The data transmission rate (data rate) of the digital signal D1 is N times the sampling frequency fs.

  Still referring to FIG. The downsampling circuit 134 is coupled to the output of the multiplexer 132 and receives the digital signal D1. The downsampling circuit 134 is used to generate a digital signal D0 by performing a downsampling operation on the digital signal D1 based on the control signal C2, and the frequency of the control signal C2 is N / M times the sampling frequency fs. is there. Thus, the data transmission rate of the digital signal D0 is equivalent to a sampling frequency fs that is N / M times. In this example, M may be an arbitrary prime number larger or smaller than the number of channels N.

  In this example, M may be set to a prime number different from N, for example, N-1 or N + 1 (not limited to this). When M is set to an even number that is divisible by N, the downsampling circuit 134 performs downsampling on the digital signal D1 at a fixed time. As an example, when N is 16 and M is set to 4, the down-sampling circuit 134 is fixed at the fourth, eighth, twelfth and sixteenth sampling points and the digital signal D1. Downsampling for. Thus, the data output circuit system 130A may not be able to effectively reflect the status of the overall operation of the ADC device 100. Therefore, by setting M to a prime number different from N, it is possible to prevent the above situation and ensure that the digital signal D0 by the data output circuit system 130A sufficiently reflects the overall performance of the ADC device 100.

  Please refer to FIG. 3 is a circuit schematic diagram illustrating the data output circuit system in FIG. 1A according to an embodiment of the present disclosure. For ease of understanding, similar elements in FIG. 3 are designated with the same reference numerals with reference to FIGS. 1A and 2.

  Compared to FIG. 2, in this example, the data output circuit system 130 can generate the digital signal D0 when no data combination operation is performed (ie, the multiplexer 132 is not included). As shown in FIG. 3, the data output circuit system 130 </ b> B includes a multiplexer 136 and a sequence circuit 138. Multiplexer 136 is coupled to the outputs of the plurality of ADC circuits 120 in FIG. 1A and receives a plurality of quantized outputs Q1-QN. The multiplexer 136 is used to generate the digital signal D2 by performing the downsampling operation based on the control signal C2. For example, the multiplexer 136 selects one of the plurality of quantized outputs Q1 to QN in order based on the control signal C2 and outputs the selected one as the digital signal D2, and the frequency of the control signal C2 is equal to the sampling frequency fs.

  Still referring to FIG. The sequence circuit 138 is coupled to the output of the multiplexer 136 and receives the digital signal D2. The sequence circuit 138 is used to synchronize the multiple digital signals D2, add at least one redundant data, and perform the downsampling operation equivalently. For example, in this example, M is set to be larger than the number of channels N (for example, N + 1) so as to generate a digital signal D0 by adding one redundant data when combining multiple digital signals D2. Good. As an example, when N = 16 and M = 17, the sequence circuit 138 receives 15 digital signals D2, adds 1 redundant data (for example, bit 0), and the 15 digital signals D2 and The redundant data may be combined and output as a digital signal D0. In one embodiment, the sequence circuit 138 can delay the digital signal D2 based on the operating schedule of the ADC circuit 120 in the N channels.

  In some embodiments as shown in FIG. 3, M may be set to be the same as or different from N. In one embodiment, the at least one redundant data may have a preset scheduled data value. As described above, in the case of the later measurement, by recognizing the scheduled data value, it is possible to remove the at least one redundant data from the digital signal D0 to ensure that the performance of the ADC device 100 is correctly determined. it can.

  In some embodiments, the sequence circuit 138 may be implemented with a data buffer. In one embodiment, the sequence circuit 138 may be implemented with a first in first out (FIFO) circuit. The implementation related to the sequence circuit 138 is merely an example, and any of various other circuits capable of data synchronization are included in the scope of the present disclosure.

  Please refer to FIG. FIG. 4 is a circuit schematic diagram showing the data output circuit systems 130A and 130B and the control circuit 400 according to an embodiment of the present disclosure. For ease of understanding, like elements in FIG. 4 are designated with the same reference numerals with reference to FIGS.

  In each embodiment, the ADC circuit system employs a single data output circuit system 130 (eg, data output circuit system 130A of FIG. 2 or data output circuit system 130B of FIG. 3) alone, or two data outputs. Circuit systems 130A and 130B may be employed simultaneously. For example, as shown in FIG. 4, in one embodiment, the ADC device 100 may include the two data output circuit systems 130 </ b> A and 130 </ b> B and the control circuit 400. In this example, the data output circuit systems 130A and 130B are operated as two data output subcircuits of the data output circuit system 130 in FIG. 1A.

  The control circuit 400 includes two switches SW1 and SW2. Switch SW1 is coupled to the output of data output circuit system 130A. Switch SW2 is coupled to the output of data output circuit system 130B. When the switch SW1 is turned on, the digital signal D0-1 (that is, the digital signal D0 in FIG. 2) output by the data output circuit system 130A is output as the digital signal D0 by the switch SW1. Alternatively, when the switch SW2 is turned on, the digital signal D0-2 (that is, the digital signal D0 in FIG. 3) output by the data output circuit system 130B is output as the digital signal D0 by the switch SW2.

  As described above, the frequency of the control signal C2 (for example, the control signal C2-1 in FIG. 4) for controlling the data output circuit system 130A is N times the sampling frequency fs, and the data output is to be described. The frequency of the control signal C2 (for example, the control signal C2-2 in FIG. 4) for controlling the circuit system 130B is equal to the sampling frequency fs.

  In this example, both the switch SW1 and the data output circuit system 130A are provided to be controlled by the operation signal EN1, and both the switch SW2 and the data output circuit system 130B are provided to be controlled by the operation signal EN2. . That is, the switch SW1 may be turned on by the operation signal EN1. The data output circuit system 130A may be activated by the operation signal EN1 to perform the related operations shown in FIG. Alternatively, the switch SW2 may be turned on by the activation signal EN2, and the data output circuit system 130B may be activated by the activation signal EN2 to perform the related operations of FIG.

  The installation form related to the control circuit 400 is used for illustration only, and any other control circuit capable of performing the same function is included in the scope of the present disclosure.

  FIG. 5 is a flow diagram illustrating a method for generating a signal under test 500 according to an embodiment of the present disclosure. For ease of understanding, the test signal generation method 500 will be described with reference to the drawings.

  In operation S501, the ADC device 100 having a multi-channel generates a plurality of quantized outputs Q1 to QN based on the input signal VIN and the plurality of interleaved clock signals CLK1 to CLKN, and each of the clock signals CLK1 to CLKN is generated. It has a sampling frequency fs.

  For example, as shown in FIG. 1A and FIG. 1B, ADC circuit systems AD1 to ADN of N channels are provided in the ADC device 100 and operate so as to be time interleaved ADCs. The N-channel ADC circuit system can convert the input signal VIN with a plurality of interleaved clock signals CLK1 to CLKN to generate a plurality of quantized outputs Q1 to QN.

  In operation S502, the data output circuit system 130 performs a downsampling operation based on the plurality of quantized outputs Q1 to QN to generate a digital signal D0 for testing, and the frequency of the digital signal D0 is (N / M ) × fs.

  For example, as shown in FIG. 2, the data output circuit system 130A performs a data combination operation based on the control signal C1 and the plurality of quantized outputs Q1 to QN to generate the digital signal D1, and also controls the control signal C2. The digital signal D0 can be generated by performing a downsampling operation based on the digital signal D1. Alternatively, as shown in FIG. 3, the data output circuit system 130B can generate a digital signal D0 by performing a direct downsampling operation based on the control signal C2 and the plurality of quantized outputs Q1 to QN.

  Through operation S502, a low-frequency digital signal D0 to be tested can be generated. Thus, the hardware cost and difficulty of measurement of the ADC device 100 can be effectively reduced.

  The plurality of steps of the signal-under-test generation method 500 are only examples, and are not limited to being performed according to the order in the examples. As long as it does not violate the operation mode and scope of each embodiment of the present disclosure, it may be appropriately added, replaced, omitted, or performed in a different order with respect to each operation of the signal generation method under test 500.

  In summary, the ADC analog-to-digital converter device and the test signal generation method provided by the present disclosure perform a downsampling operation on the output of the ADC of a plurality of channels, thereby generating a test signal for a low frequency. Can be generated. In this way, the hardware cost and difficulty of measuring the overall performance of the ADC device can be reduced.

  Although the present disclosure has been disclosed by the embodiments as described above, this does not limit the present disclosure, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure content is based on the content specified in the following claims.

Reference explanation

100 Analog-to-digital converter device 130, 130A, 130B Data output circuit system 110 Sampling circuit VIN Input signal fs Sampling frequency Q1-QN Quantized output N × fs N times sampling frequency C1, C2 Control signal TD Scheduled delay 132, 136 Multiplexer D0-1, D0-2, D0-D2 Digital signal EN1, EN2 Actuation signal SW1, SW2 Switch 500 Method C2-1, C2-2 Control signal AD1-ADN Analog-digital converter circuit system 120 Analog converter circuit CLK1-CLKN Clock signal S1 to SN Sampling signal (N / M) × fs N / M times sampling frequency TS Cycle 134 Downsampling circuit 138 Sequence circuit 400 Control circuit S501, S502 Operation

Claims (16)

A plurality of analog signals each corresponding to a plurality of channels and used to convert an input signal based on a plurality of interleaved clock signals to generate a plurality of quantized outputs, each of the clock signals having a sampling frequency. A digital converter circuit system;
A data output circuit system coupled to the analog to digital converter circuit system and used to output a first digital signal by performing a downsampling operation based on a first control signal and the quantized output;
Including
The first digital signal is used to determine the performance of the analog-to-digital converter circuit system, the frequency of the first digital signal is the sampling frequency N / M times, N is a positive integer and the Analog-digital converter device that is the number of channels.   The analog-to-digital converter device according to claim 1, wherein the frequency of the first control signal is the sampling frequency of N / M times. The data output circuit system includes:
A multiplexer coupled to the analog-to-digital converter circuit system and used to select one of the quantized outputs based on a second control signal and output as a second digital signal;
A prime number coupled to the multiplexer and used to generate the first digital signal by performing the downsampling operation based on the first control signal and the second digital signal, wherein M is different from N A downsampling circuit,
The analog-digital converter apparatus of Claim 1 or 2 containing these.   The analog-to-digital converter device according to claim 3, wherein the frequency of the second control signal is N times the sampling frequency. The data output circuit system includes:
A multiplexer coupled to the analog-to-digital converter circuit system and used to select one of the quantized outputs based on the first control signal and output as a second digital signal;
A sequence circuit coupled to the multiplexer and used to generate the first digital signal by combining the second digital signal and at least one redundant data;
An analog-to-digital converter device according to claim 1 comprising:   The analog-digital converter device according to claim 1 or 5, wherein the frequency of the first control signal is equal to the sampling frequency. The data output circuit system includes:
Coupled to the analog-to-digital converter circuit system, performing a data combination operation based on a second control signal and the quantized output to generate a second digital signal, the first control signal and the second A first data output subcircuit used to perform the downsampling operation based on a digital signal to generate a third digital signal;
Coupled to the analog-to-digital converter circuit system, selecting one of the quantized outputs based on a third control signal and outputting as a fourth digital signal, and down-converting based on the fourth digital signal A second data output subcircuit used to perform a sampling operation to generate a fifth digital signal;
Coupled to the first data output subcircuit and the second data output subcircuit, and selectively outputs one of the third digital signal and the fifth digital signal as the first digital signal. A control circuit used for
An analog-to-digital converter device according to claim 1 comprising: The control circuit includes:
When coupled to the first data output sub-circuit to receive the third digital signal and the first switch is turned on, the first data output sub-circuit is moved by the first switch to the first data output sub-circuit. A first switch for outputting three digital signals as the first digital signal;
When coupled to the second data output sub-circuit to receive the fifth digital signal and the second switch is turned on, the second data output sub-circuit is driven by the second switch. A second switch for outputting a digital signal of 5 as the first digital signal;
An analog-to-digital converter device according to claim 7 comprising: Converting an input signal based on a plurality of clock signals interleaved by a plurality of analog-to-digital converter circuit systems to generate a plurality of quantized outputs, each of the clock signals having a sampling frequency;
Performing a downsampling operation based on a first control signal and the quantized output to output a first digital signal;
Including
The first digital signal is used to determine the performance of the analog-to-digital converter circuit system, the frequency of the first digital signal is the sampling frequency N / M times, N is a positive integer and the A method for generating a signal under test that is the number of channels.   The method for generating a signal under test according to claim 9, wherein the frequency of the first control signal is the sampling frequency of N / M times. The step of performing the downsampling operation includes:
A multiplexer selecting one of the quantized outputs based on a second control signal and outputting as a second digital signal;
Performing a downsampling operation based on the first control signal and the second digital signal by a downsampling circuit to generate the first digital signal, wherein M is a prime number different from N;
11. A method for generating a signal under test according to claim 9 or 10.   The method of generating a signal under test according to claim 11, wherein the frequency of the second control signal is N times the sampling frequency. The step of performing the downsampling operation includes:
A multiplexer selecting one of the quantized outputs based on the first control signal and outputting as a second digital signal;
Combining the second digital signal and at least one redundant data by a sequence circuit to generate the first digital signal;
10. A method for generating a signal under test according to claim 9.   14. The method for generating a signal under test according to claim 9 or 13, wherein a frequency of the first control signal is equal to the sampling frequency. The step of performing the downsampling operation includes:
A first data output subcircuit performs a data combination operation based on the second control signal and the quantized output to generate a second digital signal, and the first control signal and the second digital signal Performing the downsampling operation based on generating a third digital signal;
A second data output subcircuit selects one of the quantized outputs based on a third control signal and outputs it as a fourth digital signal, and performs the downsampling operation based on the fourth digital signal. Performing a fifth digital signal; and
Selectively outputting one of the third digital signal and the fifth digital signal as the first digital signal;
10. A method for generating a signal under test according to claim 9. Selectively outputting one of the third digital signal and the fourth digital signal as the first digital signal,
When the first switch is turned on and the first switch is turned on, the first data output subcircuit outputs the third digital signal as the first digital signal by the first switch. Process,
When the second switch is turned on and the second switch is turned on, the second data output subcircuit outputs the fifth digital signal as the first digital signal by the second switch. Process,
16. A method for generating a signal under test according to claim 15, further comprising:

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