JP2019135779A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which inhibits cracks from occurring on an insulation film positioned below wiring while inhibiting increase of wiring resistance.SOLUTION: A semiconductor device 1 includes a semiconductor substrate 12. A passivation film 14 is formed on the semiconductor substrate 12. Wiring 15 containing copper as a main component is formed on the passivation film 14. A barrier metal film 26 having higher rigidity than that of copper is disposed between the passivation film 14 and the wiring 15.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device including a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a copper wiring formed on the insulating film.

JP 2010-171386 A

  One object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of cracks in an insulating film located below a wiring while suppressing an increase in wiring resistance.

  When copper wiring is arranged on an insulating film, a barrier metal film may be interposed between them. When heat is applied to the semiconductor device during or after the manufacturing process, the wiring, the barrier metal film, and the insulating film undergo thermal expansion. The wiring and the barrier metal film usually have a higher coefficient of thermal expansion than that of the insulating film, and a stress in a direction along the surface of the insulating film is generated by the thermal expansion. The barrier metal film transmits the stress from the wiring to the insulating film in addition to the stress due to its thermal expansion. When the barrier metal film has a lower rigidity than the wiring, the barrier metal film is deformed by receiving stress from the wiring and transmits the stress of the wiring to the insulating film located below. Due to this stress, the stress is concentrated on the periphery of the wiring, and there is a possibility that a crack (crack) may occur in the insulating film located below the wiring. Such a crack may be avoided by making the wiring thin, but in this case, there is a tradeoff in that the resistance value of the wiring increases.

Therefore, a semiconductor device of the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a wiring mainly composed of copper formed on the insulating film, and the insulating film and the wiring. And a barrier metal film having a higher rigidity than copper.
According to the configuration of the present invention, the barrier metal film having a higher rigidity than copper is interposed between the insulating film and the wiring mainly composed of copper. Therefore, even if the wiring generates a stress in a direction along the surface of the insulating film due to thermal expansion, the barrier metal film is hardly deformed by the stress. Thereby, it is possible to suppress the stress from the wiring from being transmitted to the insulating film by the barrier metal film. As a result, generation of cracks in the insulating film can be suppressed. In addition, since the generation of cracks can be suppressed by the barrier metal film, the wiring can be thickened, so that an increase in the resistance value of the wiring can be suppressed or the resistance can be reduced.

In the semiconductor device, the barrier metal film preferably has a lower coefficient of thermal expansion than copper. According to this configuration, the deformation amount due to the thermal expansion of the barrier metal film can be made smaller than the deformation amount due to the thermal expansion of the wiring. Thereby, since the stress given to an insulating film from a barrier metal film is small, it can suppress effectively that a crack arises in an insulating film.
In the semiconductor device, the barrier metal film may have a rigidity of 50 Gpa to 180 Gpa. In the semiconductor device, the barrier metal film may have a coefficient of thermal expansion of less than 8.6 μm / m · K. In the semiconductor device, the barrier metal film may include one or more metal species selected from the group including tantalum, tungsten, molybdenum, chromium, and ruthenium.

  In the semiconductor device, the barrier metal film may have a rigidity of 100 Gpa or more and 180 Gpa or less and a thermal expansion coefficient of less than 5 μm / m · K. In the semiconductor device, the barrier metal film may include one or more metal species selected from the group including tungsten, molybdenum, and chromium. In the semiconductor device, the insulating film may include a nitride film or an oxide film. In the semiconductor device, the insulating film includes a nitride film, and the barrier metal film has a stacked structure of a titanium film formed on the insulating film and a tungsten film formed on the titanium film. It may be. In the semiconductor device, the barrier metal film may have a thickness smaller than that of the wiring.

The semiconductor device may further include a multilayer wiring structure formed on the semiconductor substrate and having a plurality of wiring layers stacked via an interlayer insulating film. In this case, the insulating film may be formed on the multilayer wiring structure so as to cover the multilayer wiring structure, and the wiring may be formed on the insulating film as a top layer wiring.
When the side surface of the uppermost layer wiring is not supported by a protective film or the like, cracks in the insulating film due to thermal expansion of the wiring are likely to occur. In such a case, the occurrence of cracks can be avoided while suppressing an increase in the wiring resistance value by interposing a barrier metal film having a high rigidity between the wiring and the insulating film.

  The semiconductor device may further include a bonding wire electrically connected to the wiring. For example, when connecting a bonding wire to a wiring, the semiconductor substrate or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transferred to the wiring directly or via a semiconductor substrate or the like, and causes thermal expansion thereof. At this time, since the barrier metal film relieves stress from the wiring, generation of cracks in the insulating film can be suppressed.

  The semiconductor device includes an on-wiring insulating film formed on the insulating film so as to cover the wiring, and a rewiring formed on the on-wiring insulating film so as to be electrically connected to the wiring. May further be included. The said structure WHEREIN: The bonding wire electrically connected to the said rewiring may further be included. For example, when connecting the bonding wire to the rewiring, the semiconductor substrate or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transferred to the wiring through the semiconductor substrate, rewiring, or the like. At this time, since the barrier metal film relieves stress from the wiring, generation of cracks in the insulating film can be suppressed.

  The semiconductor device may further include a connection electrode electrically connected to the wiring and a wiring substrate having a bonding surface in which the semiconductor substrate is flip-chip bonded via the connection electrode. For example, when the connection electrode is connected to the wiring substrate, the semiconductor substrate may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring through the semiconductor substrate, the connection electrode, and the like. At this time, since the barrier metal film relieves stress from the wiring, generation of cracks in the insulating film can be suppressed.

  The semiconductor device may further include a land disposed on a surface opposite to the bonding surface of the wiring substrate and electrically connected to the wiring via a via electrode. For example, the semiconductor device is mounted on a mounting board via solder that contacts the land. During this mounting, the semiconductor device is heated to melt the solder. As a result, the wiring is also heated, but the barrier metal film relieves stress from the wiring, so that generation of cracks in the insulating film can be suppressed.

  The semiconductor device may further include a connection electrode electrically connected to the wiring, and a sealing resin that covers a front surface, a back surface, and a side surface of the semiconductor substrate so as to expose the connection electrode. . For example, the connection electrode may be formed as an external terminal for achieving electrical connection with the outside. In this case, the semiconductor device may be mounted on the mounting substrate via solder in contact with the connection electrode. During this mounting, the semiconductor device is heated to melt the solder. As a result, the wiring is also heated, but the barrier metal film relieves stress from the wiring, so that generation of cracks in the insulating film can be suppressed.

FIG. 1 is a bottom view showing the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view showing the internal structure of the semiconductor device of FIG. FIG. 3 is a cross-sectional view taken along section line III-III in FIG. 4 is an enlarged cross-sectional view of a portion surrounded by a broken-line circle IV in FIG. FIG. 5 is a cross-sectional view showing an embodiment of the barrier metal film. FIG. 6A is a diagram for explaining a part of the manufacturing process of the wiring of FIG. 4. 6B is a diagram showing a step subsequent to FIG. 6A. FIG. 6C is a diagram showing a step subsequent to FIG. 6B. FIG. 6D is a diagram showing a step subsequent to FIG. 6C. FIG. 6E is a diagram showing a step subsequent to that in FIG. 6D. FIG. 6F is a diagram showing a step subsequent to that in FIG. 6E. FIG. 7 is an enlarged cross-sectional view showing a portion where the wiring of the semiconductor device according to the second embodiment of the present invention is formed. FIG. 8 is a cross-sectional view showing a semiconductor device according to the third embodiment of the present invention. FIG. 9 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention. FIG. 11 is an enlarged cross-sectional view showing a portion where the wiring of the semiconductor device according to the sixth embodiment of the present invention is formed. FIG. 12A is a diagram for explaining a part of the manufacturing process of the wiring of FIG. 11. FIG. 12B is a diagram showing a step subsequent to FIG. 12A. FIG. 12C is a diagram showing a step subsequent to FIG. 12B. FIG. 12D is a diagram showing a step subsequent to FIG. 12C. FIG. 12E is a diagram showing a step subsequent to FIG. 12D. FIG. 12F is a diagram showing a step subsequent to that in FIG. 12E. FIG. 12G is a diagram showing a step subsequent to that in FIG. 12F. FIG. 13 is a cross-sectional view showing a modification of the wiring.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a bottom view showing a semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a plan view showing the internal structure of the semiconductor device 1 of FIG. FIG. 3 is a cross-sectional view taken along section line III-III in FIG. 4 is an enlarged cross-sectional view of a portion surrounded by a broken-line circle IV in FIG.

The semiconductor device 1 is a semiconductor device to which QFN (Quad Flat Non-leaded Package) is applied. The semiconductor device 1 includes a semiconductor chip 2, a die pad 3, leads 4, bonding wires 5, and a resin package 6 that seals them. The outer shape of the resin package 6 (semiconductor device 1) is a flat rectangular parallelepiped shape.
A plurality of pads 7 are arranged on the surface of the semiconductor chip 2. Each pad 7 is formed, for example, at the peripheral edge of the semiconductor chip 2. Each pad 7 is electrically connected to, for example, a semiconductor element. A back metal 8 made of a metal layer such as gold (Au), nickel (Ni), or silver (Ag) is formed on the back surface of the semiconductor chip 2.

  The die pad 3 and the lead 4 are formed by punching a metal thin plate (for example, a copper thin plate). A plated layer 9 made of silver is formed on the surfaces of the die pad 3 and the leads 4. The die pad 3 has a square shape in plan view, and the semiconductor chip 2 is disposed at the center thereof. At the peripheral edge of the back surface of the die pad 3, a recess having a substantially elliptical cross section is formed over the entire circumference by crushing from the back surface side. A sealing resin constituting the resin package 6 enters the recess.

  Thereby, the peripheral part of the die pad 3 is sandwiched by the sealing resin (resin package 6) from above and below, so that the die pad 3 is prevented from falling off from the resin package 6 (preventing detachment). The back surface of the die pad 3 is exposed from the back surface of the resin package 6 except for a portion recessed in an approximately elliptical cross section. A plating layer 10 made of solder is formed on the back surface of the die pad 3 exposed from the resin package 6.

  The same number (for example, nine) of leads 4 is provided at a position facing each side surface of the die pad 3. At each position facing the side surface of the die pad 3, the lead 4 extends in a direction perpendicular to the facing side surface and is arranged at equal intervals in a direction parallel to the side surface. At the end of the back surface of the lead 4 on the die pad 3 side, a recess having an approximately elliptical cross section is formed by crushing from the back surface side. A sealing resin constituting the resin package 6 enters the recess.

  As a result, the end of the lead 4 on the die pad 3 side is sandwiched from above and below by the sealing resin (resin package 6), and the lead 4 is prevented from falling off (resining) from the resin package 6. The back surface of the lead 4 is exposed from the back surface of the resin package 6 except for a portion recessed in a substantially elliptical cross section. Further, the side surface of the lead 4 opposite to the die pad 3 side is exposed from the side surface of the resin package 6. A plating layer 10 made of solder is formed on a portion of the back surface of the lead 4 exposed from the resin package 6.

  In this embodiment, the back surface of the semiconductor chip 2 is bonded to the surface of the die pad 3 (plating layer 9) via the bonding material 11 with the surface on which the pads 7 are disposed facing upward. . The bonding material 11 is, for example, a solder paste. When electrical connection between the semiconductor chip 2 and the die pad 3 is not required, the back metal 8 is omitted, and the back surface of the semiconductor chip 2 is placed on the surface of the die pad 3 with a bonding material made of an insulating paste or the like. May be joined together. In this case, the plating layer 9 on the surface of the die pad 3 may be omitted.

The bonding wire 5 has one end bonded to the pad 7 of the semiconductor chip 2 and the other end bonded to the surface of the lead 4. The bonding wire 5 includes, for example, a copper wire or a gold wire.
Referring to FIG. 4, the semiconductor chip 2 includes a semiconductor substrate 12, a multilayer wiring structure 13, a passivation film 14 as an example of an insulating film of the present invention, and a wiring 15. The semiconductor substrate 12 is made of, for example, a silicon substrate having an element formation surface 16 on which semiconductor elements (diodes, transistors, resistors, capacitors, etc.) are formed.

The multilayer wiring structure 13 has a plurality of wiring layers stacked in order from the element formation surface 16 of the semiconductor substrate 12 via an interlayer insulating film. In the present embodiment, the multilayer wiring structure 13 includes a first metal layer 18 stacked on the element formation surface 16 of the semiconductor substrate 12 via the first interlayer insulating film 17 and a first metal via the second interlayer insulating film 19. A second metal layer 20 stacked on the metal layer 18 and a third interlayer insulating film 21 covering the second metal layer 20 are included. The first interlayer insulating film 17, the second interlayer insulating film 19, and the third interlayer insulating film 21 include an insulating material such as silicon oxide (SiO ₂ ) and silicon nitride (SiN), for example. The first metal layer 18 and the second metal layer 20 contain aluminum.

  An upper surface barrier film 22 and a lower surface barrier film 23 are formed on the upper and lower surfaces of the first metal layer 18 to prevent diffusion of impurities into the first interlayer insulating film 17 and the second interlayer insulating film 19, respectively. Similarly, an upper barrier film 22 and a lower barrier film 23 that prevent diffusion of impurities into the second interlayer insulating film 19 and the third interlayer insulating film 21 are formed on the upper and lower surfaces of the second metal layer 20, respectively. . Upper surface barrier film 22 formed on each upper surface of first metal layer 18 and second metal layer 20 may include, for example, titanium nitride. On the other hand, the lower surface barrier film 23 formed on each lower surface of the first metal layer 18 and the second metal layer 20 is formed by stacking titanium nitride and titanium sequentially from the lower surfaces of the first metal layer 18 and the second metal layer 20, for example. It may have a two-layer structure.

  The passivation film 14 is formed on the multilayer wiring structure 13 so as to cover the multilayer wiring structure 13. More specifically, the passivation film 14 is formed on the third interlayer insulating film 21. The passivation film 14 may be, for example, silicon oxide, BPSG (Boron Phosphorus Silicon Glass), or silicon nitride. The passivation film 14 may have a stacked structure in which silicon nitride and silicon oxide are stacked in order from the surface of the third interlayer insulating film 21.

  A first via 24 a penetrating through the second interlayer insulating film 19 is connected to the upper surface of the first metal layer 18. The first via 24 a passes through the second interlayer insulating film 19 and is connected to the lower surface of the second metal layer 20. The first via 24a includes tungsten. A first barrier film 25a containing, for example, titanium nitride is interposed between the first via 24a and the second interlayer insulating film 19.

  On the other hand, a second via 24 b penetrating the third interlayer insulating film 21 and the passivation film 14 is connected to the upper surface of the second metal layer 20. The second via 24 b is exposed from the surface of the passivation film 14. The second via 24 b is formed flush with the surface of the passivation film 14. The second via 24b includes tungsten. Between each of the second via 24b and the third interlayer insulating film 21 and the passivation film 14, a second barrier film 25b containing, for example, titanium nitride is interposed.

  With reference to the enlarged view of FIG. 2 and FIG. 4, a plurality of wirings 15 are formed on the passivation film 14 at intervals. Each wiring 15 is disposed so as to cover the second via 24 b exposed from the surface of the passivation film 14. Each wiring 15 integrally has a connection part 40 electrically connected to the bonding wire 5 and a lead part 41 selectively drawn from the connection part 40. In the present embodiment, the connection portion 40 is formed in a substantially rectangular shape in plan view as a part of the pad 7 (see FIG. 3). In each wiring 15, the lead portions 41 adjacent to each other may be formed so as to run in parallel with each other at a predetermined interval.

Each wiring 15 has a flat upper surface 27 along the surface of the passivation film 14. The width W of each wiring 15 is, for example, not less than 7 μm and not more than 20 μm. Further, the thickness T of each wiring 15 is, for example, 7 μm or more and 20 μm or less. In the range of these numerical values, the aspect ratio R ₁₅ (= thickness T / width W) of each wiring 15 may be 0 <R ₁₅ ≦ 1. The inter-wiring distance L of the plurality of wirings 15 may be 20 μm or less, for example.

The wiring 15 may contain a metal whose main component is copper. The metal having copper as a main component means a metal having the highest mass ratio (mass%) of copper with respect to other components (hereinafter the same). For example, when the wiring 15 is made of an aluminum-copper (Al—Cu) alloy, an aluminum-silicon-copper (Al—Si—Cu) alloy, or the like, the copper mass ratio R _Cu is equal to the aluminum mass ratio R _Al or silicon. The mass ratio is higher than R _Si (R _Cu > R _Al, R _Cu > R _Si ). Although the metal which has copper as a main component may contain a trace amount of impurities, high purity copper with a purity of 99.9999% (6N) or higher, high purity copper with a purity of 99.99% (4N) or higher, etc. included.

  A barrier metal film 26 and a copper seed film (not shown) are arranged between each wiring 15 and the passivation film 14. The barrier metal film 26 is formed on the passivation film 14, and a copper seed film (not shown) is formed on the barrier metal film 26. In the present embodiment, a copper seed film (not shown) is integrated with each wiring 15. The barrier metal film 26 is formed so that both end portions thereof are located inside the side surface 28 of the wiring 15 in a sectional view. That is, the width of the barrier metal film 26 is smaller than the width W of the wiring 15. The barrier metal film 26 has a thickness smaller than the thickness of the wiring 15. The thickness of the barrier metal film 26 may be, for example, not less than 0.1 μm and not more than 0.3 μm. Each wiring 15 is electrically connected to the second via 24 b through the copper seed film (not shown) and the barrier metal film 26.

  A laminated film of a Ni (nickel) film 29, a Pd (palladium) film 30 and an Au (gold) film 31 is formed on the surface of each wiring 15. The Ni film 29 is formed along the upper surface 27 and the side surface 28 of each wiring 15 so that one surface and the other surface of the Ni film 29 cover each wiring 15. In the present embodiment, a portion of the Ni film 29 formed on the upper surface 27 of each wiring 15 is formed thicker than the other portions. The Ni film 29 may have a uniform thickness. The thickness of the Ni film 29 may be, for example, 2 μm or more and 4 μm or less.

  The Pd film 30 covers the entire area of the Ni film 29 with a uniform thickness (for example, 0.1 μm or more and 0.5 μm or less). The Au film 31 covers the entire area of the Pd film 30 with a uniform thickness (for example, 0 μm or more and 0.05 μm or less) thinner than that of the Pd film 30, for example. The laminated film of the Ni film 29, the Pd film 30, and the Au film 31 functions as a protective film that protects the wiring 15. The bonding wire 5 is connected to the Au film 31. That is, in this embodiment, the pad 7 is formed by the connection portion 40 of each wiring 15, the Ni film 29, the Pd film 30, and the Au film 31.

  Here, as a reference example, a semiconductor device including a barrier metal film 26 having a lower rigidity than copper is considered with reference to Table 1 below. Table 1 shows materials of the wiring 15, the barrier metal film 26, and the passivation film 14 of the semiconductor device according to the reference example. Hereinafter, the wiring 15 is made of high-purity copper having a purity of 99.9999% (6N) or higher, high-purity copper having a purity of 99.99% (4N) or higher (hereinafter simply referred to as “copper”), or the like. Let's take an example.

  The semiconductor device according to the reference example includes a barrier metal film 26 made of titanium having a rigidity lower than that of copper between the passivation film 14 made of an oxide film or a nitride film and the wiring 15 made of copper. When heat is applied to the semiconductor device during or after the manufacturing process, the wiring 15, the barrier metal film 26, and the passivation film 14 are thermally expanded. The wiring 15 and the barrier metal film 26 have a higher coefficient of thermal expansion than that of the passivation film 14, and generates stress in the direction along the surface of the passivation film 14 due to thermal expansion.

  The barrier metal film 26 transmits the stress from the wiring 15 to the passivation film 14 in addition to the stress due to its own thermal expansion. When the barrier metal film 26 has a lower rigidity than the wiring 15, the barrier metal film 26 is deformed by receiving stress from the wiring 15, and transmits the stress of the wiring 15 to the passivation film 14 located below the wiring 15. Due to this stress, the stress is concentrated on the periphery of the wiring 15, and there is a possibility that a crack (crack) may be generated in the passivation film 14 located below the wiring 15. Such a crack may be avoided by making the wiring 15 thin, but in this case, there is a tradeoff in that the resistance value of the wiring 15 increases.

  In view of the above, the occurrence of cracks in the passivation film 14 can be achieved by adopting a metal material having a rigidity higher than that of copper (48 GPa) for the barrier metal film 26 instead of or in addition to titanium. It can be suppressed. Further, it is considered that the increase in the resistance value of the wiring 15 can be suppressed or the resistance can be reduced by increasing the thickness of the wiring 15.

  Further, by setting the thermal expansion coefficient of the barrier metal film 26 to a thermal expansion coefficient of copper (16.5 μm / m · K), more preferably less than that of titanium (8.6 μm / m · K), It is considered that generation of cracks can be effectively suppressed. In other words, it is considered that the occurrence of cracks in the passivation film 14 can be effectively suppressed by bringing the coefficient of thermal expansion of the barrier metal film 26 close to the coefficient of thermal expansion of the passivation film 14. In these cases, from the viewpoint of suppressing an increase in resistance value, it is desirable to employ a metal material smaller than the electrical resistivity (= 420 nΩ · m) of titanium as the metal material of the barrier metal film 26. An example of the metal material of the barrier metal film 26 having the above conditions is shown in Table 2 below.

  As shown in Table 2, the barrier metal film 26 is made of one or more metals selected from the group including tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and ruthenium (Ru). Species can be included. According to these metal species, a barrier metal film having a thermal expansion coefficient of 4 μm / m · K to 7 μm / m · K, a rigidity of 50 Gpa to 180 Gpa, and an electrical resistivity of 50 nΩ · m to 150 nΩ · m. 26 can be obtained.

  That is, according to these metal species, the barrier metal film having a thermal expansion coefficient smaller than that of copper (16.5 μm / m · K) and that of titanium (8.6 μm / m · K). 26 can be realized. Moreover, according to these metal species, the barrier metal film 26 having a rigidity higher than that of copper (48 Gpa) or titanium (44 Gpa) can be realized. Furthermore, according to these metal species, the barrier metal film 26 having an electrical resistivity smaller than that of titanium (420 nΩ · m) can be realized.

  Referring to Table 2, at least one condition of a thermal expansion coefficient of 4 μm / m · K or more and less than 5 μm / m · K, a rigidity of 100 Gpa or more and 180 Gpa or less, and an electric resistivity of 50 nΩ · m or more and 100 nΩ · m or less The barrier metal film 26 provided may be formed. When all of these conditions are satisfied, the barrier metal film 26 can include at least one of tungsten and molybdenum.

  For example, the barrier metal film 26 may have a thermal expansion coefficient of 4 μm / m · K or more and less than 5 μm / m · K and a rigidity of 100 Gpa or more and 180 Gpa or less. In this case, the barrier metal film 26 can include one or more metal species selected from the group including tungsten, molybdenum, and chromium. The barrier metal film 26 may have a thermal expansion coefficient of 4 μm / m · K or more and less than 5 μm / m · K and an electrical resistivity of 50 nΩ · m or more and 100 nΩ · m or less. In this case, the barrier metal film 26 can include at least one of tungsten and molybdenum. The barrier metal film 26 may have a rigidity of 100 Gpa to 180 Gpa and an electrical resistivity of 50 nΩ · m to 100 nΩ · m. In this case, the barrier metal film 26 can include one or more metal species selected from the group including tungsten, molybdenum, and ruthenium.

  Referring to FIG. 4, when a metal material having a higher rigidity than copper is used for barrier metal film 26 instead of titanium, passivation film 14 may include an oxide film or a nitride film. In this case, the barrier metal film 26 can include one or more metal species selected from the group including tantalum, molybdenum, chromium, and ruthenium. With these metal species, the barrier metal film 26 can be formed on the passivation film 14 while maintaining good adhesion to the passivation film 14. Moreover, since the barrier metal film 26 has an electrical resistivity smaller than that of titanium, the resistance of the semiconductor device 1 can be reduced.

On the other hand, when a metal material having a higher rigidity than copper in addition to titanium is employed for the barrier metal film 26, the configuration is as shown in FIG. FIG. 5 is a cross-sectional view showing an embodiment of the barrier metal film 26. In FIG. 5, only the structure of the wiring 15, the barrier metal film 26 and its periphery is shown.
As shown in FIG. 5, a barrier metal film 26 having a stacked structure in which a plurality of metal films are stacked is interposed between the wiring 15 and the passivation film 14. The barrier metal film 26 includes a first metal film 26a formed on the passivation film 14 and a second metal film 26b formed on the first metal film 26a. The first metal film 26a is a titanium film and is electrically connected to the second via 24b. The thickness of the first metal film 26a may be, for example, not less than 0.1 μm and not more than 0.3 μm. On the other hand, the second metal film 26b is a metal film including one or more metal species selected from the group including tantalum, tungsten, molybdenum, chromium, and ruthenium. The thickness of the second metal film 26b may be, for example, not less than 0.1 μm and not more than 0.3 μm.

  In this configuration, the passivation film 14 may be a nitride film, and the second metal film 26b may be a tungsten film. If the passivation film 14 is a nitride film, the first metal film 26a (titanium film) can be formed on the passivation film 14 while maintaining good adhesion. In addition, the second metal film 26b (tungsten film) can be formed on the first metal film 26a (titanium film) while maintaining good adhesion.

  As described above, according to the present embodiment, the barrier metal film 26 having a higher rigidity than copper is interposed between the wiring 15 mainly composed of copper and the passivation film 14. Therefore, even if the wiring 15 generates stress in the direction along the surface of the passivation film 14 due to thermal expansion, the barrier metal film 26 is not easily deformed by the stress. Thereby, the barrier metal film 26 can suppress the stress from the wiring 15 being transmitted to the passivation film 14. In addition, since the barrier metal film 26 has a lower coefficient of thermal expansion than copper, the deformation amount due to the thermal expansion of the barrier metal film 26 can be made smaller than the deformation amount due to the thermal expansion of the wiring 15. As a result, the stress applied from the barrier metal film 26 to the passivation film 14 can be reduced. As a result, the generation of cracks in the passivation film 14 can be effectively suppressed. In addition, since the generation of cracks can be suppressed by the barrier metal film 26, the wiring 15 can be thickened, so that an increase in the resistance value of the wiring 15 can be suppressed or its resistance can be reduced.

  In the present embodiment, the bonding wire 5 is connected to the wiring 15. For example, when the bonding wire 5 is connected to the wiring 15, the semiconductor substrate 12 or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring 15 directly or via the semiconductor substrate 12 or the like, and causes thermal expansion thereof. At this time, the barrier metal film 26 relieves stress from the wiring 15, so that the generation of cracks in the passivation film 14 can be suppressed.

6A to 6F are diagrams for explaining a part of the manufacturing process of the wiring 15 of FIG. In the following description, reference is made to FIG. 4 as necessary. Hereinafter, a case where the wiring 15 is made of high-purity copper will be described as an example.
First, prior to the formation of the wiring 15, the multilayer wiring structure 13 (see FIG. 4) is formed on the semiconductor substrate 12. Next, a passivation film 14 is formed on the multilayer wiring structure 13. Next, the second via 24b (see FIG. 4) penetrating the passivation film 14 is formed. Next, as shown in FIG. 6A, a barrier metal film 26 and a copper seed film 32 are formed in this order on the surface of the passivation film 14 by, eg, sputtering.

  Next, as shown in FIG. 6B, a resist film 33 having an opening 34 selectively formed in a region where each wiring 15 is to be formed is formed on the copper seed film 32. Next, copper is grown by electroplating from the surface of the copper seed film 32 exposed from the opening 34. Copper is grown (buried) to the middle of the opening 34. In this step, the plated copper is integrated with the copper seed film 32. Thereby, the wiring 15 is formed.

Next, as shown in FIG. 6C, Ni is grown from the upper surface 27 of the wiring 15 by electroless plating using the opening 34 of the resist film 33. Thereby, a part of the Ni film 29 is formed. Thereafter, as shown in FIG. 6D, the resist film 33 is removed.
Next, as shown in FIG. 6E, the copper seed film 32 and the barrier metal film 26 are selectively removed by wet etching, for example. In this step, the barrier metal film 26
The end portion of the barrier metal film 26 is formed so that the end portion of the barrier metal film 26 is located on the inner side of the side surface 28 of the wiring 15. Thereby, a step is formed between the end of the barrier metal film 26 and the side surface 28. In this step, the side surface 28 of the wiring 15 may be etched together with the copper seed film 32 so that the side surface 28 of the wiring 15 is located inside the end of the Ni film 29.

Next, as shown in FIG. 6F, Ni, Pd, and Au are plated and grown in this order from the side surface 28 of the wiring 15 and the Ni film 29 by electroless plating. Thereby, a laminated film of the Ni film 29, the Pd film 30, and the Au film 31 is formed. Thereafter, the temperature of the semiconductor substrate 12 is set to 200 ° C. or more (eg, 260 ° C.), and the bonding wire 5 (see FIG. 4) is connected to the wiring 15 (Au film 31).
Second Embodiment
FIG. 7 is an enlarged cross-sectional view showing a portion where the wiring 15 of the semiconductor device 61 according to the second embodiment of the present invention is formed. FIG. 7 corresponds to an enlarged view of a portion surrounded by a broken line circle IV in FIG. In FIG. 7, portions corresponding to the respective portions shown in FIG. 4 and the like described above are denoted by the same reference numerals and description thereof is omitted.

  The semiconductor device 61 includes a first resin film 62 as an example of an on-wiring insulating film of the present invention formed on the passivation film 14 so as to cover the wiring 15 and a first resin film 62 so as to be electrically connected to the wiring 15. 1 and a rewiring 63 formed on the resin film 62. The first resin film 62 includes, for example, a polyimide resin. The first resin film 62 has a pad opening 65 that exposes a part of the wiring 15 as an electrode pad 64. On the first resin film 62, the rewiring 63 is routed.

  The rewiring 63 is formed so as to enter the pad opening 65 from the surface of the first resin film 62. The rewiring 63 is electrically connected to the electrode pad 64 in the pad opening 65. In this embodiment, the rewiring 63 has a two-layer structure including a UBM (under bump metal) film 66 and a wiring film 67 formed on the UBM film 66. The UBM film 66 has one surface and the other surface formed along the surface of the first resin film 62 and the surface of the electrode pad 64. The UBM film 66 may have a two-layer structure including a titanium film and a copper film formed on the titanium film. The wiring film 67 is formed along the UBM film 66 so that the UBM film 66 enters the concave space formed by entering the pad opening 65. The wiring film 67 may contain a metal whose main component is copper. A second resin film 68 is formed on the rewiring 63 so as to cover the rewiring 63.

  The second resin film 68 has a rewiring pad opening 70 that exposes a part of the rewiring 63 as a rewiring pad 69. An electrode post 71 is formed on the rewiring pad 69. The electrode post 71 corresponds to the pad 7 (see FIG. 2). The electrode post 71 is formed so as to enter the rewiring pad opening 70 from the surface of the second resin film 68. The electrode post 71 is electrically connected to the rewiring pad 69 in the rewiring pad opening 70. In the present embodiment, the electrode post 71 has a two-layer structure including a UBM film 72 and a wiring film 73 formed on the UBM film 72.

  The UBM film 72 has one surface and the other surface formed along the surface of the second resin film 68 and the surface of the rewiring pad 69. The UBM film 72 may have a two-layer structure including a titanium film and a copper film formed on the titanium film. The wiring film 73 is formed along the UBM film 72 so that the UBM film 72 enters a concave space formed by entering the pad opening 65. The wiring film 73 may contain a metal whose main component is copper. A bonding wire 5 is connected to the electrode post 71.

  As described above, according to the present embodiment, the bonding wire 5 is electrically connected to the rewiring 63 via the electrode post 71. For example, when the bonding wire 5 is connected to the electrode post 71, the semiconductor substrate 12 or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring 15 through the semiconductor substrate 12, the electrode post 71, the rewiring 63, and the like. At this time, since the barrier metal film 26 relieves stress from the wiring 15, the generation of cracks in the passivation film 14 can be suppressed (see also FIGS. 4 and 5).

In the present embodiment, the UBM film 66 of the rewiring 63 is formed of one or more metal species selected from the group including tantalum, tungsten, molybdenum, chromium, and ruthenium, whereby cracks in the first resin film 62 are formed. You may make it suppress generation | occurrence | production of. Further, the UBM film 72 of the electrode post 71 is formed of one or more metal species selected from the group including tantalum, tungsten, molybdenum, chromium, and ruthenium, thereby generating cracks in the second resin film 68. You may make it suppress.
<Third Embodiment>
FIG. 8 is a sectional view showing a semiconductor device 81 according to the third embodiment of the present invention. In FIG. 8, parts corresponding to those shown in FIG. 2 and the like described above are denoted by the same reference numerals and description thereof is omitted.

  The semiconductor device 81 includes a connection electrode 82 connected to each of a plurality of pads 7 (wiring 15) formed on the surface of the semiconductor chip 2, and the semiconductor chip 2 (semiconductor substrate 12) is flip-chip bonded via the connection electrode 82. And a wiring board 83 having a bonded surface 83a. The connection electrode 82 may be a block-like or columnar conductor, or may be solder. A plurality of lands 84 and solder balls 85 that are electrically connected to the lands 84 are formed on the back surface 83b of the wiring board 83 that is located on the opposite side of the bonding surface 83a. Each land 84 and each solder ball 85 is electrically connected to the corresponding connection electrode 82 and pad 7 (wiring 15) via a via electrode 86 formed on the wiring board 83. A sealing resin 88 is formed in the gap 87 between the semiconductor chip 2 and the wiring board 83 so as to fill the gap 87.

  As described above, according to the present embodiment, the semiconductor chip 2 is connected to the wiring substrate 83 via the connection electrode 82. For example, when connecting the connection electrode 82 to the wiring substrate 83, the semiconductor chip 2 (semiconductor substrate 12) or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring 15 through the semiconductor substrate 12, the connection electrode 82, and the like. At this time, since the barrier metal film 26 relieves stress from the wiring 15, it is possible to suppress cracks in the passivation film 14 (see also FIGS. 4 and 5).

Further, according to the present embodiment, the semiconductor device 81 is mounted on a mounting board (not shown) via the solder balls 85 that are in contact with the lands 84. During this mounting, the semiconductor device 81 is heated to melt the solder balls 85. As a result, the wiring 15 is also heated, but the barrier metal film 26 relieves stress from the wiring 15, so that cracks in the passivation film 14 can be suppressed (see also FIGS. 4, 5, etc.).
<Fourth embodiment>
FIG. 9 is a sectional view showing a semiconductor device 91 according to the fourth embodiment of the present invention. 9, parts corresponding to those shown in FIG. 2 and the like described above are denoted by the same reference numerals and description thereof is omitted.

The semiconductor device 91 includes a connection electrode 92 connected to each of the plurality of pads 7 (wirings 15) formed on the surface of the semiconductor chip 2, and the semiconductor chip 2 (semiconductor substrate 12) so as to expose the connection electrode 92. Element forming surface 16, sealing resin 93 covering the back surface and the side surface. The sealing resin 93 also serves as the resin package 6.
As described above, according to the present embodiment, the connection electrode 92 is formed as an external terminal for achieving electrical connection with the outside. In this case, the semiconductor device 91 is mounted on a mounting substrate (not shown) via solder in contact with the connection electrode 92. At the time of mounting, the semiconductor device 91 is heated to melt the solder. As a result, the wiring 15 is also heated, but the barrier metal film 26 relieves stress from the wiring 15, so that cracks in the passivation film 14 can be suppressed (see also FIGS. 4, 5, etc.).

Further, a rewiring 63 as shown in FIG. 7 may be formed on the connection electrode 92, for example. In this case, the semiconductor device 91 is mounted on a mounting substrate (not shown) via solder in contact with the electrode pad 64 (see FIG. 7). During this mounting, the solder is melted by heating. The heat at the time of mounting is transmitted to the wiring 15 via the rewiring 63 etc., for example. Even in such a case, the concentration of stress from the wiring 15 is alleviated by the barrier metal film 26. Thereby, the crack of the passivation film 14 resulting from the heating at the time of mounting can be suppressed (refer also to FIG. 4, FIG. 5 etc.).
<Fifth Embodiment>
FIG. 10 is a sectional view showing a semiconductor device 101 according to the fifth embodiment of the present invention. In FIG. 10, parts corresponding to those shown in FIG. 2 and the like described above are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 10, the semiconductor device 101 is a semiconductor device to which an SOP (Small Outline Package) having leads 4 drawn out of the resin package 6 (sealing resin) is applied. Similar to the semiconductor device 1 described above, the semiconductor chip 2 is disposed on the die pad 3. Although the lower surface of the die pad 3 is not exposed from the resin package 6 in the present embodiment, the lower surface of the die pad 3 may be formed so as to be exposed from the resin package 6.

  The lead 4 includes an inner lead portion 4 a sealed in the resin package 6 and an outer lead portion 4 b formed integrally with the inner lead portion 4 a and drawn out of the resin package 6. The inner lead portion 4 a is electrically connected to the pad 7 (wiring 15) of the corresponding semiconductor chip 2 through the bonding wire 5 in the resin package 6. The outer lead portion 4 b is formed so as to extend toward the lower surface of the resin package 6. The outer lead portion 4b is a mounting terminal connected to the mounting substrate.

As described above, the configuration of the present embodiment can provide the same effects as those described in the first embodiment. In the present embodiment, the semiconductor device 101 to which SOP is applied has been described. However, the semiconductor device 101 may be of a type other than the SOP as long as it has the leads 4 drawn out of the resin package 6 (sealing resin). In other words, the semiconductor device 101 includes an SOJ (Small Outline J-leaded), a CFP (Ceramic Flat Package), an SOT (Small Outline Transistor), a QFP (Quad Flat Package), a DFP (Dual Flat Package), and a PLCC (Plastic leaded chip carrier). , DIP (Dual Inline Package), SIP (Single Inline Package), and the like.
<Sixth Embodiment>
FIG. 11 is an enlarged cross-sectional view showing a portion where the wiring 15 of the semiconductor device 111 according to the sixth embodiment of the present invention is formed. FIG. 11 corresponds to an enlarged view of a portion surrounded by a broken line circle IV in FIG. In FIG. 11, portions corresponding to the respective portions shown in FIG. 4 and the like described above are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 11, in this embodiment, a metal film 112 is formed on the wiring 15. The metal film 112 includes a laminated film composed of a plurality of metal films. In the present embodiment, the metal film 112
Includes a laminated film of a Ni (nickel) film 113 and a Pd (palladium) film 114. The width of the metal film 112 is larger than the width W of the wiring 15. In other words, the width W of the wiring 15 is smaller than the width of the metal film 112.

  More specifically, the Ni film 113 of the metal film 112 has a flat surface, and is formed on the wiring 15 so that both ends are located outside the side surface 28 of the wiring 15 in a cross-sectional view. Yes. The Ni film 113 has a thickness smaller than the thickness of the wiring 15. The Ni film 113 may be formed with a uniform thickness. The thickness of the Ni film 113 may be, for example, 2 μm or more and 4 μm or less.

  On the other hand, the Pd film 114 of the metal film 112 has a flat surface, and is formed on the Ni film 113 so that both end portions are located outside the side surface 28 of the wiring 15 in a sectional view. The Pd film 114 is formed on the Ni film 113 so as to match the Ni film 113. That is, the end of the Pd film 114 is formed so as to be flush with the end of the Ni film 113. The Pd film 114 has a thickness smaller than the thickness of the Ni film 113. The Pd film 114 may be formed with a uniform thickness. The thickness of the Pd film 114 may be, for example, not less than 0.1 μm and not more than 0.5 μm.

The bonding wire 5 is connected to the metal film 112 (Pd film 114). That is, in the present embodiment, the pad 7 is formed by the connection portion 40 of each wiring 15 and the metal film 112 (Ni film 113 and Pd film 114).
As described above, the configuration of the present embodiment can provide the same effects as those described in the first embodiment.

12A to 12G are diagrams for explaining a part of the manufacturing process of the wiring 15 of FIG. In the following description, FIG. 11 described above is referred to as necessary. Hereinafter, a case where the wiring 15 is made of high-purity copper will be described as an example.
First, as shown in FIG. 12A, prior to the formation of the wiring 15, the multilayer wiring structure 13 (see FIG. 11) is formed on the semiconductor substrate 12. Next, a passivation film 14 is formed on the multilayer wiring structure 13. Next, a second via 24b penetrating the passivation film 14 is formed.

Next, as shown in FIG. 12B, a barrier metal film 26 and a copper seed film 32 are formed in this order on the surface of the passivation film 14 by, eg, sputtering. Next, as shown in FIG. 12C, a resist film 33 having an opening 34 selectively formed in a region where each wiring 15 is to be formed is formed on the copper seed film 32.
Next, as shown in FIG. 12D, copper is grown by electroplating from the surface of the copper seed film 32 exposed from the opening 34. Copper is grown (buried) to the middle of the opening 34. In this step, the plated copper is integrated with the copper seed film 32. Thereby, the wiring 15 is formed.

  Next, as shown in FIG. 12E, Ni is grown from the upper surface 27 of the wiring 15 by electroless plating using the opening 34 of the resist film 33. Thereby, the Ni film 113 is formed. Next, using the opening 34 of the resist film 33, Pd is grown from the Ni film 113 by electroless plating. In this step, a Pd film having a thickness smaller than that of the Ni film 113 is formed. Thereby, the metal film 112 including the Ni film 113 and the Pd film 114 is formed. Thereafter, as shown in FIG. 12F, the resist film 33 is removed.

Next, as shown in FIG. 12G, the copper seed film 32 and the barrier metal film 26 are selectively removed by wet etching, for example. In this step, the side surface 28 of the wiring 15 is etched together with the copper seed film 32 so that the side surface 28 of the wiring 15 is located inside the end of the metal film 112. Thereby, a step is formed between the side surface 28 of the wiring 15 and the end portion of the metal film 112. Further, in this step, the end of the barrier metal film 26 is etched (over-etched) inside the side surface 28 of the wiring 15, and both end portions of the barrier metal film 26 are positioned inside the side surface 28 of the wiring 15. To be formed. Thereby, a step is formed between the end of the barrier metal film 26 and the side surface 28.

Thereafter, the temperature of the semiconductor substrate 12 is set to 200 ° C. or higher (for example, 260 ° C.), and the bonding wire 5 (see FIG. 11) is connected to the Pd film 114.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in each of the foregoing embodiments, the barrier metal film 26 is one or more selected from the group including tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and ruthenium (Ru). An example including the above metal species has been described. However, these metal species have a rigidity higher than that of copper (titanium), a coefficient of thermal expansion lower than that of copper (titanium), and an electric resistivity lower than that of titanium. Are not intended to limit the material of the barrier metal film 26. Therefore, the barrier metal film 26 can contain various metal materials within a range that satisfies the above conditions. For example, the metal material having the above condition includes one or more metal species selected from the group including tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and ruthenium (Ru). An alloy may be included.

In the first embodiment described above, the example in which the laminated film of the Ni film 29, the Pd film 30, and the Au film 31 covering the wiring 15 is formed has been described. However, as shown in FIG. 13, the bonding wire 5 may be directly connected to the wiring 15 without forming the laminated film of the Ni film 29, the Pd film 30 and the Au film 31.
In the sixth embodiment, the example in which the metal film 112 including the stacked film of the Ni film 113 and the Pd film 114 is formed has been described. In this configuration, the metal film 112 may include an Au (gold) film formed on the Pd film 114. Furthermore, the metal film 112 may be a metal film including one or more metal species selected from the group including Ni, Pd, and Au.

  In the first embodiment, the second embodiment, the fifth embodiment, and the sixth embodiment, the example in which the semiconductor devices 1, 61, 101, and 111 include the bonding wires 5 has been described. However, the semiconductor devices 1, 61, 101, and 111 may include a connection member having a relatively large current passage area such as a conductor plate instead of or in addition to the bonding wire 5.

  In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 5 Bonding wire 12 Semiconductor substrate 13 Multilayer wiring structure 14 Passivation film 15 Wiring 26 Barrier metal film 61 Semiconductor device 62 1st resin film 63 Rewiring 81 Semiconductor device 82 Connection electrode 83 Wiring board 83a Bonding surface 83b Back surface 84 Land 86 Via electrode 88 Sealing resin 91 Semiconductor device 92 Connection electrode 93 Sealing resin 101 Semiconductor device 111 Semiconductor device

Claims (18)

A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A wiring mainly composed of copper formed on the insulating film;
A semiconductor device including a barrier metal film interposed between the insulating film and the wiring and having a higher rigidity than copper.   The semiconductor device according to claim 1, wherein the barrier metal film has a lower coefficient of thermal expansion than copper.   The semiconductor device according to claim 1, wherein the barrier metal film has a rigidity of 50 Gpa or more and 180 Gpa or less.   The semiconductor device according to claim 1, wherein the barrier metal film has a coefficient of thermal expansion of less than 8.6 μm / m · K.   The semiconductor device according to claim 1, wherein the barrier metal film includes one or more metal species selected from the group including tantalum, tungsten, molybdenum, chromium, and ruthenium.   5. The semiconductor device according to claim 1, wherein the barrier metal film has a rigidity of 100 Gpa or more and 180 Gpa or less and a thermal expansion coefficient of less than 5 μm / m · K.   5. The semiconductor device according to claim 1, wherein the barrier metal film includes one or more metal species selected from the group including tungsten, molybdenum, and chromium.   The semiconductor device according to claim 1, wherein the insulating film includes a nitride film or an oxide film. The insulating film includes a nitride film,
5. The barrier metal film according to claim 1, wherein the barrier metal film has a laminated structure of a titanium film formed on the insulating film and a tungsten film formed on the titanium film. Semiconductor device.   The semiconductor device according to claim 1, wherein the barrier metal film has a smaller thickness than the wiring. A multilayer wiring structure formed on the semiconductor substrate, wherein a plurality of wiring layers are stacked via an interlayer insulating film;
The insulating film is formed on the multilayer wiring structure so as to cover the multilayer wiring structure;
The semiconductor device according to claim 1, wherein the wiring is formed on the insulating film as an uppermost layer wiring.   The semiconductor device according to claim 1, further comprising a bonding wire electrically connected to the wiring. The semiconductor device according to claim 12, wherein the bonding wire includes a copper wire or a gold wire. An on-wiring insulating film formed on the insulating film so as to cover the wiring;
The semiconductor device according to claim 1, further comprising a rewiring formed on the insulating film on the wiring so as to be electrically connected to the wiring.   The semiconductor device according to claim 14, further comprising a bonding wire electrically connected to the rewiring. A connection electrode electrically connected to the wiring;
The semiconductor device according to claim 1, further comprising a wiring substrate having a bonding surface on which the semiconductor substrate is flip-chip bonded via the connection electrode.   The semiconductor device according to claim 16, further comprising a land disposed on a surface of the wiring board opposite to the bonding surface and electrically connected to the wiring through a via electrode. A connection electrode electrically connected to the wiring;
The semiconductor device according to claim 1, further comprising a sealing resin that covers a front surface, a back surface, and a side surface of the semiconductor substrate so as to expose the connection electrode.

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