JP2019125649A - Substrate for semiconductor light-emitting element and semiconductor light-emitting element - Google Patents

Abstract

A semiconductor light emitting device having excellent light emission efficiency is manufactured with high yield. A substrate for a semiconductor light emitting device (100) includes a substrate and a semiconductor non-growth site (102) and a semiconductor growth site (103) on a main surface of the substrate. A semiconductor light emitting device in which at least a first semiconductor layer, a light emitting semiconductor layer, and a second semiconductor layer are stacked in this order on a substrate is formed. The semiconductor non-growth part (102) has a convex structure, the semiconductor growth part (103) has a concave structure, and at least a part of the bottom surface of the concave structure is a non-flat surface. By securing the semiconductor growth site (103) and reducing crystal dislocation defects, the internal quantum efficiency is improved. Moreover, the convex structure of the semiconductor non-growth site (102) scatters light and increases the light extraction efficiency. Drop is suppressed by reducing the compressive stress applied to the semiconductor layer. [Selection] Figure 1

Description

  The present invention relates to a substrate for a semiconductor light emitting device and a semiconductor light emitting device.

  A light emitting diode (LED), which is a semiconductor light emitting element using a semiconductor layer, has characteristics such as small size, high power efficiency, and quick on / off response as compared with conventional light emitting devices such as conventional fluorescent lamps and incandescent bulbs. Because it is made entirely of solids, it has many advantages such as vibration resistance and long instrument life.

Among them, GaN-based semiconductor light emitting devices represented by blue LEDs are manufactured by laminating n layers, light emitting layers and p layers by epitaxial growth on a single crystal substrate, and generally a sapphire single crystal substrate or SiC single crystal substrate is used as a substrate. Used. However, for example, since there is a lattice mismatch between the sapphire crystal and the GaN-based semiconductor crystal, crystal dislocation defects occur due to the lattice mismatch. The density of the dislocation defects reaches 1 × 10 ⁹ / cm ² . The crystal dislocation defects reduce the internal quantum efficiency inside the LED, and as a result, the light emission efficiency of the LED decreases.

  In addition, since the refractive index of the GaN-based semiconductor layer is larger than that of the sapphire substrate, light generated in the semiconductor light-emitting layer is not emitted from the interface with the sapphire substrate at an angle greater than the critical angle. And there is a problem that the external quantum efficiency is lowered as a result.

  On the other hand, as a phenomenon unique to the blue LED, there is a problem that the light emission efficiency is lowered with the increase of the injected current. This is caused by the lattice mismatch between GaInN, GaN, and the sapphire base, and the difference in the thermal expansion coefficient between GaN and the sapphire base when the temperature is raised from room temperature to the room temperature during GaN deposition. It is believed that the cause is compressive stress.

  In order to solve the above-mentioned problems, a technique has been reported in which a periodic uneven structure is provided on the surface of a sapphire substrate on which a GaN-based semiconductor layer is epitaxially grown, and the GaN-based semiconductor layer is epitaxially grown using a lateral growth mode ( For example, refer to Patent Document 1). According to this technique, in the process of epitaxial growth of the semiconductor layer, the semiconductor layer grown from the C-plane flats the uneven structure, so that crystal dislocation defects (penetration transition defects) are reduced, and the crystal quality of the obtained semiconductor layer is reduced. It can be improved.

  In addition, since unevenness is present at the interface between the semiconductor layer thus obtained and the sapphire substrate, light propagating in the lateral direction is scattered, whereby the light extraction efficiency is improved (for example, see Patent Document 2). .

  Furthermore, a flat portion extending along the crystal plane of the substrate and a plurality of large diameter protrusions protruding from the flat portion are formed on the upper surface of the substrate, and a plurality of small diameter protrusions smaller than the large diameter protrusion are large diameter protrusions By forming on the outer surface of the part, there is reported a technology capable of suppressing the total reflection at the interface between the light emitting structure and the substrate and improving the light extraction efficiency (see, for example, Patent Document 3).

  Furthermore, by arranging the concavo-convex structure formed on the substrate surface to have regular tooth loss, the internal quantum efficiency is improved, and the waveguide mode is eliminated by light scattering to achieve light extraction efficiency. A technology that can be enhanced has been reported (see, for example, Patent Document 4).

Unexamined-Japanese-Patent No. 2006-352084 JP, 2011-129718, A International Publication No. 2015/053363 International Publication No. 2017/057529

  Electron injection efficiency EIE (Internal Injection Efficiency), internal quantum efficiency IQE (Internal Quantum Efficiency), and light extraction efficiency LEE (Light Extraction Efficiency) as factors for determining the external quantum efficiency EQE (External Quantum Efficiency) indicating the luminous efficiency of the LED Can be mentioned. Among these, the internal quantum efficiency IQE depends on the crystal dislocation defect density caused by the crystal lattice mismatch of the GaN-based semiconductor crystal. The light extraction efficiency LEE is improved by breaking the waveguide mode inside the GaN-based semiconductor crystal layer by light scattering by the concavo-convex structure provided on the substrate. Further, due to the influence of compressive stress applied to the light emitting layer, a phenomenon (Droop) in which the internal quantum efficiency IQE decreases with an increase in current becomes remarkable, which is an important issue for improving the light emission efficiency.

  Therefore, in order to improve the light emission efficiency of the LED, the crystal dislocation defect density due to the crystal lattice mismatch of the GaN-based semiconductor crystal is reduced, and the degree of light scattering by the concavo-convex structure provided in the substrate is increased. , It is necessary to reduce Droop.

  However, in the technique described in Patent Document 1, in order to reduce crystal dislocation defects caused by lattice mismatch of the semiconductor crystal, the plane density of the valley portion serving as the starting point of crystal growth in the concavo-convex structure of the substrate surface is You need to reduce it. However, if the plane density is reduced too much, the area of the substrate plane (e.g., the C plane of the sapphire substrate) fitted with the lattice plane necessary for epitaxial growth decreases, and the crystal plane of the epitaxial film in the initial stage of crystal growth is unstable. On the contrary, there is a problem that crystal dislocation defects resulting from lattice mismatch increase.

  Even in the technique described in Patent Document 2, the light extraction efficiency LEE can be improved by closely arranging the convex portions formed on the substrate surface, but when the gaps between the convex portions are eliminated, the lattice plane which becomes the starting point of the epitaxial growth. There is a problem that there is no substrate surface (for example, the C-plane of sapphire substrate) to which C. conforms, crystal dislocation defects due to lattice mismatch increase, crystal quality is deteriorated, and the light emission efficiency of the resulting LED is not improved .

  Moreover, in any of Patent Documents 1-4, a strong compressive stress is applied to the light emitting layer, and there is a problem that Droop occurs when a high current flows.

  This invention is made in view of this point, and it is an object of the present invention to provide a substrate for a semiconductor light emitting device and a semiconductor light emitting device capable of manufacturing a semiconductor light emitting device having excellent luminous efficiency with high yield. To be

  A substrate for a semiconductor light emitting device according to one aspect of the present invention comprises a substrate, and a semiconductor non-growth site and a semiconductor growth site on the main surface of the substrate, and at least a first semiconductor layer, a light emitting semiconductor layer and It is a base material for semiconductor light emitting elements for forming the semiconductor light emitting element by which the 2nd semiconductor layer was laminated in this order, and the above-mentioned semiconductor non-growth part has convex structure, and the above-mentioned semiconductor growth part has concave structure. It is characterized in that the bottom surface of at least a part of the concave structure is a non-flat surface.

  According to this configuration, when epitaxially growing the semiconductor layer on the main surface of the semiconductor light emitting element substrate, the semiconductor growth site serving as the epitaxial growth promoting portion and the semiconductor non-growth site serving as the epitaxial growth suppressing portion coexist in the main surface. doing. By securing the epitaxial growth promoting portion by the semiconductor growth site, crystal defects in the semiconductor layer can be suppressed, and the internal quantum efficiency IQE of the obtained semiconductor light emitting device can be increased. Further, by securing the area of the convex structure by the semiconductor non-growth portion, light can be scattered by the convex structure in the semiconductor light emitting element. Thus, the light extraction efficiency LEE can be improved while maintaining the internal quantum efficiency IQE of the semiconductor light emitting device.

  In addition, a large number of edge dislocations can be formed at the interface between the substrate and the semiconductor layer by epitaxially growing the semiconductor layer from a semiconductor growth site having a concave structure in which at least a part of the bottom surface is a non-flat surface. When the semiconductor layer is grown in the lateral direction, the edge dislocations are also bent in the lateral direction, and a plurality of edge dislocations are put together according to the association of the stacked semiconductor layers, and the number of edge dislocations is drastically reduced. By reducing the volume gap of the edge dislocations as the edge dislocations decrease, the compressive stress applied to the semiconductor layer is greatly relaxed. Thereby, it is possible to suppress a drop (Droop) of the internal quantum efficiency IQE of the semiconductor light emitting device.

  In addition, since the epitaxial growth promoting portion is uniformly formed in the substrate surface by the semiconductor growth portion of a predetermined area, the flatness of the semiconductor layer formed on the concave structure and the convex structure is improved. Therefore, the efficiency of the semiconductor light emitting device can be enhanced, and the warping of the substrate can be suppressed, and the light emission wavelength distribution in the substrate surface can be improved. As a result, semiconductor light emitting devices having excellent luminous efficiency can be manufactured with high yield.

  In the base material for a semiconductor light emitting device according to one aspect of the present invention, the bottom surface of the concave structure between the semiconductor non-growth portion and the semiconductor non-growth portion adjacent to each other is formed in a continuous wave shape. preferable.

  In the base material for a semiconductor light emitting device according to one aspect of the present invention, when the cross section is observed along the longer one of the lines connecting opposite centers of the four non-growth parts of the semiconductors closest to each other. It is preferable that a distance between a lowermost part of the concave structure and a reference surface formed by connecting inflection points of the curves of the contours of the facing convex structures forming the semiconductor non-growth part be 10 nm or more and 200 nm or less .

  In the substrate for a semiconductor light emitting device according to one aspect of the present invention, the convex structure includes a convex portion group in which at least a plurality of convex portions are adjacent to each other at an equal closest distance P1 to one another; It is preferable that the said convex parts which comprise the outermost part of a group are adjacent, without mutually separating.

  In the base material for a semiconductor light emitting device according to one aspect of the present invention, the concave structure is preferably formed around the convex portion group.

  The semiconductor light emitting device according to one aspect of the present invention is a laminated semiconductor layer formed by laminating at least two semiconductor layers and a light emitting layer laminated on the main surface side of the above-mentioned base material for semiconductor light emitting device. It is characterized by including.

  According to this configuration, the internal quantum efficiency IQE is improved by securing the semiconductor growth site and reducing crystal dislocation defects. In addition, light is scattered by the convex structure of the semiconductor non-growth portion, and the light extraction efficiency LEE is enhanced. By reducing the compressive stress applied to the semiconductor layer, Droop is suppressed.

  According to the present invention, a semiconductor light emitting device having excellent light emission efficiency can be manufactured with high yield.

It is a plane schematic diagram of a substrate for semiconductor light emitting elements of this embodiment. It is a cross-sectional schematic diagram which shows the X-X 'cross section in FIG. It is a plane schematic diagram for demonstrating the distance of the reference plane of this Embodiment, and the lowest part of concave structure. It is a cross-sectional schematic diagram for demonstrating the distance of the reference plane of this Embodiment, and the lowest part of concave structure. It is a plane schematic diagram which shows an example of the convex part group in the other aspect of the base material for semiconductor light-emitting devices of this Embodiment. It is a plane schematic diagram which shows an example of the convex part group in the other aspect of the base material for semiconductor light-emitting devices of this Embodiment. It is a cross-sectional schematic diagram which shows the semiconductor light-emitting device of this Embodiment. It is a plane schematic diagram of the resin mold used for the example. It is sectional drawing of the sapphire base material used for the Example. It is sectional drawing of the sapphire base material used for the comparative example.

  Hereinafter, an embodiment of the present invention (hereinafter, abbreviated as “embodiment”) will be described in detail. The present invention is not limited to the following embodiments, and can be variously modified and implemented within the scope of the invention.

  Hereafter, the base material for semiconductor light-emitting devices concerning this Embodiment is demonstrated in detail.

(Base material for semiconductor light emitting device)
A substrate for a semiconductor light emitting device according to the present embodiment includes a substrate and a concavo-convex structure formed on a part or the whole of the main surface of the substrate, and at least a first semiconductor layer and a light emitting semiconductor on the concavo-convex structure. It is a base material for forming the semiconductor light emitting element in which the layer and the second semiconductor layer are laminated in this order.

  Furthermore, in the substrate for a semiconductor light emitting device according to the present embodiment, a semiconductor non-growth site and a semiconductor growth site are formed on the main surface of the substrate. The semiconductor non-growth portion has a convex structure, the semiconductor growth portion has a concave structure, and the bottom surface of at least a part of the concave structure is a non-flat surface.

  According to this configuration, when epitaxially growing the semiconductor layer on the main surface of the semiconductor light emitting element substrate, the semiconductor growth site serving as the epitaxial growth promoting portion and the semiconductor non-growth site serving as the epitaxial growth suppressing portion coexist in the main surface. doing. By securing the epitaxial growth promoting portion by the semiconductor growth site, crystal defects in the semiconductor layer can be suppressed, and the internal quantum efficiency IQE of the obtained semiconductor light emitting device can be increased. Further, by securing the area of the convex structure by the semiconductor non-growth portion, light can be scattered by the convex structure in the semiconductor light emitting element. Thus, the light extraction efficiency LEE can be improved while maintaining the internal quantum efficiency IQE of the semiconductor light emitting device.

  Further, by epitaxially growing the semiconductor layer from a semiconductor growth site having a concave structure in which at least a part of the bottom surface is a non-flat surface, it is possible to form a large number of edge dislocations at the interface between the substrate and the semiconductor layer. When the semiconductor layer is grown in the lateral direction, the edge dislocations are also bent in the lateral direction, and a plurality of edge dislocations are combined and the number is drastically reduced according to the meeting of the stacked semiconductor layers. By reducing the volume gap of the edge dislocations as the edge dislocations decrease, the compressive stress applied to the semiconductor layer is greatly relaxed. By this effect, the piezoelectric field generated in the light emitting semiconductor layer is reduced, and a semiconductor light emitting device in which Droop is suppressed can be manufactured.

  In addition, since the epitaxial growth promoting portion is uniformly formed in the substrate surface by the semiconductor growth portion of a predetermined area, the flatness of the semiconductor layer formed on the concave structure and the convex structure is improved. Therefore, the efficiency of the semiconductor light emitting device can be enhanced, and the warping of the substrate can be suppressed, and the light emission wavelength distribution in the substrate surface can be improved. As a result, semiconductor light emitting devices having excellent luminous efficiency can be manufactured with high yield.

The semiconductor light emitting device according to the present embodiment has the following characteristic configuration.
(1) A semiconductor non-growth site and a semiconductor growth site are provided on the main surface of the substrate.
(2) The semiconductor non-growth part has a convex structure, and the semiconductor growth part has a concave structure.
(3) The bottom surface of at least a part of the concave structure is a non-flat surface.

Furthermore, preferably, the following characteristic features are included. That is, although the above (1), (2) and (3) are essential constituent requirements in the present embodiment, the following (4), (5), (6) and (7) are optional It is a configuration requirement.
(4) The bottom of the concave structure between the semiconductor non-growth site and the adjacent semiconductor non-growth site is formed in a continuous wave shape.
(5) When the cross-section is observed along the longer one of the lines connecting the opposing centers of the four semiconductor non-growth regions closest to each other, the contours of the opposing convex structures forming the semiconductor non-growth region The distance between the reference surface formed by connecting the inflection points of the curve and the lowermost portion of the concave structure is 10 nm or more and 200 nm or less.
(6) The convex structure includes at least a plurality of convex portions arranged adjacent to each other at the closest distance P1 equal to each other, and the convex portions constituting the outermost portion of the convex portions do not separate from each other Adjacent to
(7) A concave structure is formed around the convex portion group.

  Hereinafter, a substrate for a semiconductor light emitting device according to the present embodiment will be described with reference to the attached drawings. FIG. 1 is a schematic plan view of a substrate for a semiconductor light emitting device of the present embodiment. FIG. 2 is a schematic cross-sectional view showing the X-X 'cross section in FIG.

  As shown in FIG. 1, the base material 100 for semiconductor light-emitting devices according to the present embodiment includes a region having a convex structure (semiconductor non-growth region 102) and a region having a concave structure (semiconductor growth region) on the main surface of the substrate. 103) is formed and configured. A semiconductor growth site 103 having a concave structure is formed around the semiconductor non-growth site 102 having a convex structure. In the semiconductor non-growth region 102, a plurality of convex portions 101 and 104 are formed adjacent to each other, and a plurality of convex portions 101 and 104 constitute a convex portion group.

  The convex portions 101 and 104 of the convex portion group are configured to be adjacent to each other at the closest distance P1 equal to each other. Further, the convex portions 101 and 104 constituting the outermost portion of the convex portion group are adjacent to each other without being separated from each other to constitute the non-semiconductor-grown portion 102. The semiconductor non-growth region 102 is surrounded by the semiconductor growth region 103 having a concave structure, and the bottom surface of at least a part of the semiconductor growth region 103 is a non-flat surface. In addition, in the semiconductor growth site 103, at least a part of the bottom surface may be a non-flat surface, and the semiconductor growth site 103 may have a flat surface in part.

  In the present embodiment, when the protrusions 101 and 104 are not separated from each other, at least the edges of the bottom of the protrusion are in contact with each other without a flat surface between them in plan view. is there. The fact that the convex portions 101 and 104 are adjacent to each other means that there is no other convex portion between the two convex portions 101 and 104 and they are adjacent to each other.

  Further, the closest distance P1 in the present embodiment is defined as follows. That is, in the semiconductor non-growth region 102, the shortest distance among the distances between the apexes of two adjacent convex portions 101 and 104 without being separated from each other is defined as the shortest distance. In the present embodiment, when the fluctuation of each P1 is within ± 10% with respect to the average value P0 of the closest distance P1 between the convex portions 101 and 104 in the semiconductor non-growth region 102, the semiconductor non-growth is In the portion 102, the plurality of convex portions 101 and 104 are configured to have the closest distance P1 equal to each other.

  The average value P0 of the closest distance P1 described above is defined as the arithmetic mean of the distances between the closest vertices of the convex portions 101 and 104. The local range used for measurement is defined as a range of about 5 to 50 times the average pitch P of the convex portions 101 and 104.

  Here, the average pitch of the plurality of convex portions 101 and 104 is defined as follows. The center-to-center distance between the center of a certain convex portion and the center of the convex portion closest to this convex portion is the pitch. The pitch is measured between each of the convex portions 101 and 104, and their arithmetic mean value is defined as the average pitch P of the plurality of convex portions 101 and 104. In addition, it is preferable that the number N of the convex part selected when calculating | requiring the said arithmetic mean value is ten or more points.

  For example, if the average pitch P is 700 nm, the closest distance P1 is measured in the measurement range of 3500 nm to 35000 nm. Therefore, for example, a field image of 7500 nm is imaged at, for example, a central position in the region having the convex portions 101 and 104, and this imaging is used to determine an arithmetic mean. For example, a scanning electron microscope (SEM) or an atomic force microscope (AFM) can be used for imaging the visual field image.

相加平均を算出する際のサンプル点数Ｎは、２０として定義する。２０としたのは、局所的範囲内で任意に個々の凸部１０１、１０４を選んだ際、十分な統計平均を取るためである。 (The arithmetic mean of the closest contact distance P1 of the convex portion)
When N measured values of the distribution of a certain element (variation) are x1, x2, ..., xn, the arithmetic mean value is defined by the following equation (1).

The number of sample points N when calculating the arithmetic mean is defined as 20. The reason for using 20 is to obtain a sufficient statistical average when the individual projections 101 and 104 are arbitrarily selected within the local range.

  In the present embodiment, the closest distance P1 is preferably 100 nm or more and 4000 nm or less because the internal quantum efficiency IQE and the light extraction efficiency LEE are improved. When the closest contact distance P1 between the convex portions 101 and 104 is 100 nm or more, the optical wavelength (wavelength / refractive index) of the emitted light is equal to or greater than that of the inside of the semiconductor light emitting element. And 500 nm or more, and more preferably 700 nm or more. Further, from the viewpoint of preventing difficulty in flattening when epitaxially growing the semiconductor layer on the main surface of the semiconductor light emitting element substrate 100, the closest contact distance P1 is preferably 4000 nm or less, and 3000 nm or less. More preferable.

  As described above, in the present embodiment, the periphery of the semiconductor non-growth region 102 is surrounded by the semiconductor growth region 103 having a concave structure in which at least a part of the bottom surface is a non-flat surface. For example, as shown in FIG. 2, in the semiconductor growth site 103, the main surface of the substrate provided to the base material 100 for semiconductor light emitting element is in a curved state. For example, a C-plane sapphire substrate is used as the substrate. When used, at the semiconductor growth site 103, the C plane of the sapphire substrate is curved. As described above, it is sufficient that at least a part of the semiconductor growth site 103 is curved, and the semiconductor growth site 103 may have a flat surface in part. In addition, as shown in FIG. 2, the semiconductor growth site 103 may be curved at one place or at multiple places (see FIG. 4).

  Since a part of the semiconductor growth site 103 is formed of a structure in which the main surface of the substrate is curved, when epitaxially growing the semiconductor layer on the main surface of the substrate 100 for semiconductor light emitting element It can be done. On the other hand, the semiconductor non-growth portion 102 constituted by the convex portions 101 and 104 serves as an epitaxial growth suppression portion. By mixing the concave structure and the convex structure in the main surface of the substrate which is the crystal growth surface, both the epitaxial growth promoting portion and the epitaxial growth suppressing portion can be present. For this reason, it is possible to scatter the light with the convex structure and improve the light extraction efficiency LEE while enhancing the internal quantum efficiency IQE of the semiconductor light emitting device obtained by suppressing the crystal defects in the semiconductor layer.

  Moreover, in the base material 100 for semiconductor light-emitting elements, it is preferable that the non-semiconductor-growth part 102 comprised by the convex part group of the convex parts 101 and 104 is repeatedly arrange | positioned with a fixed period. The period of the semiconductor non-growth region 102 is defined by the distance 105 between the convex portions. The distance 105 between the convex portion groups is defined by the distance between the centers of the respective convex portion groups in the two semiconductor non-growth portions 102 adjacent to each other with the semiconductor growth portion 103 interposed therebetween. The center of the convex portion group is the center of gravity in plan view of the semiconductor non-growth region 102. When the distance 105 between the convex portions has a constant value, the semiconductor non-growth portions 102 are arranged at a constant cycle.

  Thus, by arranging the semiconductor non-growth parts 102 at a constant cycle, the area of the semiconductor growth part 103 between the semiconductor non-growth parts 102 becomes constant, and the epitaxial growth promoting part is equalized in the substrate plane. The flatness of the semiconductor layer obtained on the main surface of the substrate is improved.

  The period of the semiconductor non-growth area 102, that is, the distance 105 between adjacent convex portions is preferably 500 nm or more and 10000 nm or less. When it is 500 nm or more, the light scattering property to the emitted light by the convex portion group of the semiconductor non-growth region 102 is preferably increased, and it is more preferably 800 nm or more, further preferably 1000 nm or more. In addition, from the viewpoint of shortening the time required for planarization to prevent a decrease in throughput and additionally preventing warping of the substrate at the time of film formation, the distance 105 between the convex portions is preferably 10000 nm or less, and 9000 nm or less Is more preferable, and 8000 nm or less is more preferable. In addition, the plurality of semiconductor non-growth sites 102 are equal to each other when the variation of the distance 105 between the convex groups is within ± 10% with respect to the average of the distance 105 between the convex groups in the substrate plane. It is assumed that it is composed of cycles.

  In the semiconductor light emitting element substrate 100 according to the present embodiment, the semiconductor layer is epitaxially grown from the semiconductor growth portion 103 having a concave structure in which at least a part of the bottom surface is not flat, thereby forming an edge at the interface between the substrate and the semiconductor layer. It can form dislocations. When the distance 105 of the semiconductor non-growth site 102 is constant, the semiconductor growth site 103 can be secured and the distance at which the edge dislocations are associated with each other can be increased, so that the probability of association increases. When the edge dislocations are associated and the crystal dislocation is reduced, the volume of the crystal layer is reduced by the reduced dislocation, and a tensile strain is generated in the planarized semiconductor layer. In this state, when the substrate 100 for semiconductor light emitting element is cooled to room temperature, the semiconductor layer is apparently shrunk more, so the dimensional difference between the sapphire substrate and the semiconductor layer is reduced, and as a result, the warpage of the substrate after forming the semiconductor layer is suppressed. can do.

  Moreover, in the base material 100 for semiconductor light-emitting elements concerning this Embodiment, light extraction efficiency LEE improves by arrangement | positioning of the convex parts 101 and 104. FIG. In order to improve the light extraction efficiency LEE, it is necessary to increase the sloped area of the convex part that scatters light. However, in the prior art, for example, in the arrangement in which the convex portions are periodically arranged, since the gaps between the convex portions become the epitaxial growth promoting portions, it is necessary to form the gaps a certain amount or more. For this reason, the density per unit area of the convex slope portion is limited.

  On the other hand, in the base material 100 for semiconductor light emitting devices according to the present embodiment, the semiconductor growth site 103 is formed around the semiconductor non-growth site 102, and the epitaxial growth promotion site is secured by the semiconductor growth site 103. At the same time, it is possible to increase the sloped surface area of the convex portions 101 and 104 by the convex portion group of the semiconductor non-growth portion 102. Therefore, the light extraction efficiency LEE can be improved. In addition, since the heights of the convex portions 101 and 104 of the semiconductor non-growth portion 102 described later are sufficiently larger than the wavelength of the emitted light, a scattering element for light is newly added as compared with the simple arrangement of the convex portions in the prior art As a result, the light extraction efficiency LEE is further improved.

  Next, parameters of the semiconductor growth portion 103 having a concave structure in which at least a part of the bottom surface is a non-flat surface between the semiconductor non-growth portions 102 will be described in detail.

(Height of convex part)
The height H of the convex portions 101 and 104, that is, the height of the convex structure is defined as the difference in height between the top of the convex portions 101 and 104 and the bottom of the convex portion on the flat surface (see FIG. 2). When the heights H of the convex portions 101 and 104 are high, the film thickness required for planarizing the semiconductor layer becomes large, and the film tends to be warped at the time of film formation.

(The distance D between the reference surface and the bottom of the concave structure)
The distance D between the reference surface and the lowermost portion of the concave structure will be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic plan view for explaining the distance between the reference surface of the present embodiment and the lowermost part of the concave structure. FIG. 4 is a schematic cross-sectional view for explaining the distance between the reference surface of the present embodiment and the lowermost portion of the concave structure. FIG. 4 is a schematic cross-sectional view showing the YY ′ cross section in FIG.

  The reference plane is a cross-section along the longer line (the line formed by Y-Y ') of the lines connecting the opposing centers of the four semiconductor non-growth parts 102 (convex part group) closest to each other. The surface formed by connecting the inflection points C of the curves of the contours of the facing convex portions 101 among the outermost convex portions 101 forming the semiconductor non-growth portion 102 when observed, that is, the broken line Z- in FIG. It refers to the surface formed by Z '. The distance D between the reference surface and the lowermost portion of the concave structure is the length from the deepest position of the curved bottom surface of the semiconductor growth portion 103 to the reference surface.

  The distance D between the reference surface and the lowermost portion of the concave structure is preferably 10 nm or more and 200 nm or less, more preferably 20 nm or more and 180 nm or less, and still more preferably 30 nm or more and 160 nm or less. When the distance D is 10 nm or more, it is possible to prevent the occurrence of edge dislocation at the interface between the substrate and the semiconductor layer when the semiconductor layer is epitaxially grown. In addition, when the semiconductor layers meet with the lateral growth of the semiconductor layers, it is possible to prevent the number of edge dislocations to be reduced from being reduced, and to prevent the relaxation of the compressive stress applied to the semiconductor layers to be reduced. Therefore, it is possible to prevent the decrease in the external quantum efficiency EQE from becoming large due to the Droop. When the distance D between the reference surface and the lowermost portion of the concave structure is 200 nm or less, it becomes easy to form a uniform semiconductor layer while preventing epitaxial growth from becoming difficult from the non-flat surface of the semiconductor growth portion 103. .

  The distance D between the reference surface and the lowermost part of the concave structure is obtained by cutting the substrate and observing its cross section with a scanning electron microscope (SEM) or measuring it three-dimensionally with an atomic force microscope (AFM) It can be measured.

  In addition, it is preferable that the bottom surface of the concave structure be formed in a continuous wave shape between the semiconductor non-growth portion 102 and the adjacent semiconductor non-growth portion 102. At this time, it is preferable that the distance D between the reference surface and the lowermost portion of the concave structure be smaller than the height H of the convex portions 101 and 104. The “wave-shaped” concave structure is a continuous smooth curved surface-shaped concave structure, and is formed of, for example, a substantially sine wave or a rounded substantially triangular wave. For example, in the case of using a C-plane of a sapphire substrate as the substrate, if a smoothly continuous concave structure is formed between the semiconductor non-growth sites 102, the exposure of a plane slightly inclined from the C-plane is increased. A large number of edge dislocations are generated from the interface between such a sapphire substrate and the semiconductor layer. These edge dislocations are combined by association with the growth of the semiconductor layer, and are rapidly reduced, whereby the compressive stress applied to the semiconductor layer is reduced and the Droop is reduced.

  In the substrate for a semiconductor light emitting device according to the present embodiment, the semiconductor non-growth region 102 may be constituted by a convex portion group in which the outermost convex portions 101 and 104 are not separated but adjacent to each other. Alternatively, it may be constituted by an isolated convex portion 101. Further, the number of convex portions 101 constituting the semiconductor non-growth region 102 may be one or more. FIG.5 and FIG.6 is a plane schematic diagram which shows an example of the convex part group in the other aspect of the base material for semiconductor light-emitting devices of this Embodiment.

  For example, as shown in FIG. 5A, in the base material 500 for semiconductor light emitting elements, the semiconductor non-growth portion 502 is constituted by seven convex portions 501 and 504, and seven convex portion groups are surrounded by the semiconductor growth portion 503. It may be done. In addition, as shown in FIG. 5B, the non-semiconductor-growing region 502 may be configured by three convex portions 501, and three convex-member groups may be surrounded by the semiconductor growth region 503. Moreover, as shown to FIG. 5C, the semiconductor non-growth part 502 may be comprised by one convex part 501, and the isolated convex part 501 may be enclosed by the semiconductor growth part 503. FIG.

  Further, as shown in FIG. 6, in the base material for semiconductor light emitting element 600, the convex portion disposed at the center is removed from the arrangement of the convex portion group constituted by the convex portions 101 and 104 of FIG. The parts 601 and 604 may be arranged. A semiconductor non-growth portion 602 consisting of a convex portion group without a central convex portion is surrounded by the semiconductor growth portion 603.

  In the present embodiment, sapphire, SiC, SiN, silicon, GaP, GaAs or the like can be used as the material of the substrate. For example, a sapphire substrate having a C plane (0001) as a main surface can be used as the substrate. Furthermore, in the semiconductor light emitting element substrate 100, the convex portions 101 and 104 forming the convex structure on the main surface of the substrate may be the same material as the substrate, and the convex portions 101 and 104 are made of a material different from the substrate. It may be a heterostructure.

(Method of manufacturing base material for semiconductor light emitting device)
Then, the manufacturing method of the base material for semiconductor light emitting elements concerning this Embodiment is demonstrated. However, the manufacturing method shown below is an example, and is not limited to this.

  It does not restrict | limit especially as a manufacturing method of the above base materials for semiconductor light emitting elements, A normal photolithography method, an imprint method, a nanoimprint method, a nanoimprint lithography method etc. are mentioned. For example, in the nanoimprint lithography method, after forming a resist layer on a predetermined substrate surface, the pattern is transferred to the resist layer by the nanoimprint method using the reverse type of the required transfer pattern, and the necessary uneven pattern is on the surface The formed resist layer is obtained.

  In addition, a dry film pattern sheet having a dry film resist layer formed is formed on the sheet surface on which a concavo-convex reverse structure of a predetermined concavo-convex pattern required is formed in advance, and the dry film pattern sheet is bonded to the substrate surface. A dry film imprint lithography method of forming a dry film resist layer on which a pattern is formed on the surface of a substrate can also be used.

  According to the above dry film imprint lithography method, it is possible to form a concavo-convex pattern with a dry film resist layer having high etching resistance, and using this as a mask layer, there is an advantage that the concavo-convex pattern can be easily formed on the substrate surface by etching the substrate. Yes, it is preferable. Further, the dry film pattern sheet needs only to be bonded to the substrate, and an imprint apparatus and an exposure apparatus with high accuracy are not required, and the production efficiency can be enhanced, which is useful in industrial production. From the above, it is preferable to use a dry film imprint lithography method as a method of manufacturing a substrate for a semiconductor light emitting device.

  Here, the case of using a sapphire substrate will be described. First, the first main surface of the sapphire substrate is polished. At this time, the surface roughness Ra of the first main surface can be controlled by controlling the type of abrasive grains, the number of abrasive grains, the polishing rate, and the pH. In particular, polishing may be performed until the arithmetic mean roughness is 1.5 nm or less. This surface polishing accuracy is correlated with the surface roughness Ra of the epitaxial growth promoting portion to be manufactured. Among them, it is more preferable that the arithmetic average roughness is 0.5 nm or less, because the distribution of the epitaxial growth promoting portion to be manufactured is smaller than that of a sapphire substrate such as 4 inches or 6 inches. In terms of internal quantum efficiency IQE improvement and stable epitaxial growth, the arithmetic average roughness is most preferably 0.3 nm or less. In addition, the off-angle, the plane orientation, and the like of the substrate to be selected can be selected as appropriate to meet the required specifications of the semiconductor light emitting element.

  The sapphire substrate having a predetermined surface roughness Ra is cleaned, for example, with a mixed solution of sulfuric acid and hydrogen peroxide solution (SPM solution) and cleaned. On the other hand, a dry film pattern sheet is prepared in which position information of the convex portion and the convex portion group is provided with an accuracy of 0.9 or more. First, for example, a thermal lithography method is applied to a glass mother roll to form a pattern. At this time, by controlling the irradiation pulse of the laser, it is possible to form the position information of the convex portion and the convex portion group on the mother roll of glass. A mold is manufactured from this mother roll by an optical nanoimprinting method. Additionally, the mold may be transferred from the mold and replicated.

  Next, the mold obtained as described above is filled with a first resist of an inorganic or organic-inorganic hybrid composition. For example, organic metal or metal oxide fine particles can be contained in the first resist. The filling state at this stage is a state in which the first resist is not completely filled and is not planarized by the first resist in the pattern of the mold, and is after the application of the first resist. Even part of the mold pattern is exposed.

  Next, a second resist which is an organic resist is applied to the mold filled with the first resist. Here, unlike the previous step, the second resist is deposited to be planarized. The mold on which the first resist and the second resist are formed is referred to as a dry film pattern sheet. Here, although it is described as a two-layer resist, in the method of manufacturing a base material for a semiconductor light emitting device, a single-layer resist in which only the second resist is formed may be used, and a multilayer dry film pattern further having a third resist Sheets can also be used. The organic resist may be negative type or positive type, and preferably contains at least a radical polymerization type resist which exhibits an effect by ultraviolet light, or a chemical amplification type resist. The organic resist is preferably one containing phenol novolac, cresol novolac, acrylic modified epoxy novolac, methacrylic modified epoxy novolac, adamantane, fluorene, carbazole, polyvinylcarbazole, polyparahydroxystyrene and the like to improve the processability of the substrate. In particular, when the organic resist is a mixture containing an oligomer or a polymer, a monomer and a polymerization initiator, it is desirable because the function of maintaining the thin film state of the applied resist is improved.

  Next, the dry film pattern sheet is bonded to the sapphire substrate through the second resist. After bonding, the resist is stabilized by light or heat, and then the mold is removed. Alternatively, after removing the mold, the resist is stabilized by light or heat.

  By the above operation, the second resist layer and the first resist layer are transferred onto the main surface of the sapphire substrate. The inverted structure of the mold is transferred onto the surface of the resist, and this inverted structure has an arrangement of convex portions and convex portion groups as position information.

Finally, the convex portion and the convex portion group can be formed on the substrate surface by etching the substrate using the resist layer formed on the substrate surface as a mask. As an etching method, wet etching, dry etching, a method combining both, or the like can be applied. In particular, it is preferable to use a dry etching method from the viewpoint of controlling the convex portion and the convex portion group. Among dry etching methods, anisotropic dry etching is preferable, and ICP-RIE and ECM-RIE are more preferable. The reaction gas used for dry etching is not particularly limited as long as it reacts with the material of the substrate, but BCl ₃ , Cl ₂ , CHF ₃ , or a mixed gas of these is preferable, and Ar, O, etc. are suitably used. ₂ , N ₂ etc. can be mixed.

  The base material for a semiconductor light emitting device according to the present embodiment can be formed by the dry film imprint lithography method and the dry etching method described above.

(Semiconductor light emitting device)
Next, with reference to FIG. 7, the semiconductor light emitting device according to the present embodiment will be described. FIG. 7 is a schematic cross-sectional view showing the semiconductor light emitting device of the present embodiment.

  In the semiconductor light emitting device 700 according to the present embodiment, the configuration includes at least one or more semiconductor light emitting element substrates according to the above-described present embodiment. As a result, the internal quantum efficiency IQE can be improved, the light extraction efficiency LEE can be improved, and the Droop can be reduced.

  The semiconductor light emitting device 700 includes a stacked semiconductor layer 760 formed by stacking at least two semiconductor layers and a light emitting layer on the main surface of the semiconductor light emitting device base 701.

  The semiconductor light emitting device 700 is formed by laminating a semiconductor layer and a light emitting layer on a semiconductor light emitting device base 701. On the main surface of the semiconductor light emitting element substrate 701, a semiconductor non-growth portion 712 constituted of a plurality of convex portions 711 is formed. The periphery of the semiconductor non-growth portion 712 is a semiconductor growth portion 713, and the semiconductor growth portion 713 has a concave structure in which at least a part of the bottom surface is a non-flat surface. An undoped semiconductor layer 751, an n-type semiconductor layer 752, a light emitting semiconductor layer 753, and a p-type semiconductor layer 754 are provided on the semiconductor non-growth portion 712 and the semiconductor growth portion 713 provided on the main surface of the semiconductor light emitting device substrate 701. Are sequentially stacked. In addition, a transparent conductive film 755 is formed on the p-type semiconductor layer 754.

  Further, a cathode electrode 757 is formed on the surface of the n-type semiconductor layer 752, and an anode electrode 756 is formed on the surface of the transparent conductive film 755. Note that the n-type semiconductor layer 752, the light-emitting semiconductor layer 753, and the p-type semiconductor layer 754 stacked on the semiconductor light-emitting element substrate 701 are referred to as a stacked semiconductor layer 760.

  Here, the main surface of the undoped semiconductor layer 751 is preferably a flat surface. When the main surface of the undoped semiconductor layer 751 is a flat surface, the performance of the n-type semiconductor layer 752, the light-emitting semiconductor layer 753, and the p-type semiconductor layer 754 can be made efficient, and the internal quantum efficiency IQE is improved.

  Furthermore, it is preferable that a buffer layer (not shown) be present at the interface between the undoped semiconductor layer 751 and the semiconductor light emitting element substrate 701. The presence of the buffer layer improves nucleation and nuclear growth which are initial conditions for crystal growth of the undoped semiconductor layer 751, and improves the performance of the laminated semiconductor layer 760 as a semiconductor, thereby improving the internal quantum efficiency IQE.

  The buffer layer may be formed to cover the entire surface of the semiconductor non-growth portion 712 and the semiconductor growth portion 713, but can be partially provided on the surface of the semiconductor non-growth portion 712 and the semiconductor growth portion 713. The buffer layer can be provided preferentially on the non-flat surface of the semiconductor growth portion 713 on the surface of the semiconductor light emitting element substrate 701.

  The thickness of the buffer layer is preferably 5 nm or more and 100 nm or less, and more preferably 10 nm or more and 50 nm or less. By setting the thickness of the buffer layer in this range, the variation in the growth rate of the undoped semiconductor layer 751 can be reduced, and the junction point of the semiconductor layers can be easily controlled.

  For the buffer layer, for example, a GaN structure, an AlGaN structure, an AlN structure, an AlInN structure, an InGaN / GaN super lattice structure, an InGaN / GaN laminated structure, an AlInGaN / InGaN / GaN laminated structure or the like can be adopted. Among them, the GaN structure, the AlGaN structure, and the AlN structure are most preferable. Thereby, the variation in the growth rate of the undoped semiconductor layer 751 is further reduced, so that the controllability of the junction points of the semiconductor layers is improved, and the surface roughness of the undoped semiconductor layer 751 can be easily reduced.

  Moreover, about film-forming of a buffer layer, film-forming temperature can be made into the range of 350 degreeC-600 degreeC. The buffer layer is preferably formed, for example, by metal organic chemical vapor deposition (MOCVD) or sputtering.

  In the semiconductor light emitting device 700, the undoped semiconductor layer 751 and the buffer layer are collectively defined and described as a base layer.

As the undoped semiconductor layer 751, for example, an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as III-V group, II-VI group, or IVI-IV group can be applied. In particular, the undoped semiconductor layer 751 is preferably an undoped nitride layer. The undoped nitride layer can be formed, for example, by supplying NH ₃ and TMGa at a growth temperature of 900 ° C. to 1500 ° C.

  The film thickness of the undoped semiconductor layer 751 is preferably 0.5 μm or more and 10 μm or less, and more preferably 1.3 μm or more and 8 μm or less from the viewpoint of the residual stress with respect to the undoped semiconductor layer 751.

  As the n-type semiconductor layer 752, for example, GaN obtained by doping an n-type dopant can be applied. Further, in the n-type semiconductor layer 752 and the p-type semiconductor layer 754, an n-type cladding layer and a p-type cladding layer not shown can be provided as appropriate.

The n-type GaN layer as the n-type semiconductor layer 752 is, for example, 3 × 10 ^{−2 to} 4.2 × 10 ⁻² mol / min of NH ₃ and 0.8 × 10 ⁻⁴ to 1 of trimethylgallium (TMGa). It can be formed by supplying a silane gas containing 5.8 × 10 ⁻⁴ mol / min and an n-type dopant typified by Si at 5.8 × 10 ^{−9 to} 6.9 × 10 ⁻⁹ mol / min. . The film thickness of the n-type semiconductor layer 752 is preferably 800 nm or more, and more preferably 1500 nm or more, from the viewpoint of the electron injection property to the active layer.

  As the light emitting semiconductor layer 753, InGaN, AlGaN, AlInGaN, GaN or the like can be used.

  The light emitting semiconductor layer 753 preferably has a single quantum well structure (SQW) or a multiple quantum well structure (MQW).

For example, in the case of a single quantum well structure, using an nitrogen as a carrier gas and supplying NH ₃ , TMGa and trimethylindium (TMIn) at a growth temperature of 600 ° C. to 850 ° C., an active layer consisting of INGaN / GaN Can be grown to a thickness of 100 Å to 1250 Å. Further, in the case of a multiple quantum well structure, the In element concentration can also be changed for InGaN constituting one layer.

  In addition, an electron blocking layer (not shown) can be provided between the light emitting semiconductor layer 753 and the p-type semiconductor layer 754. The electron blocking layer is made of, for example, p-AlGaN.

As the p-type semiconductor layer 754, for example, GaN obtained by doping a p-type dopant can be applied. In the case of a p-type GaN layer, the growth temperature can be raised to 900 ° C. or more, and TMGa and CP ₂ Mg can be supplied to form a film with a thickness of several hundred Å to several thousand Å.

  The stacked semiconductor layer 760 (the n-type semiconductor layer 752, the light-emitting semiconductor layer 753, and the p-type semiconductor layer 754) can be formed on the surface of the base by a known technique. For example, as a film forming method, MOCVD, hydride vapor phase epitaxy (HVPE), molecular beam epitaxial growth (MBE) or the like can be applied.

The material of the transparent conductive film 755 is not particularly limited as long as it can be used as a transparent conductive film suitable for a semiconductor light emitting element. For example, metal thin films such as Ni / Au electrodes, and conductive oxide films such as ITO, ZnO, In ₂ O ₃ , SnO ₂ , IZO and IGZO can be applied. In particular, ITO is preferable from the viewpoint of transparency and conductivity.

  The thickness of the transparent conductive film 755 is preferably 30 nm or more and 100 nm or less. The role of the transparent conductive film 755 is to diffuse the current from the anode electrode 756 and inject it into the p-type semiconductor layer 754. The thickness (T_TE) of the transparent conductive film 755 is preferably 30 nm or more, and more preferably 40 nm or more because the resistance of the transparent conductive film 755 decreases as the thickness increases. In addition to the suppression of light absorption, thin film interference can be used to significantly increase the transmittance for incident angles less than the critical angle, and from the viewpoint of suppressing the transmittance distribution less than the critical angle, the transparent conductive film 755 As an upper limit of thickness (T_TE) of the above, 100 nm or less is preferable, and 80 nm or less is more preferable.

  The thickness (T_TE) of the transparent conductive film 755 can be measured by, for example, a scanning transmission electron microscope (STEM). The measurement of the thickness of the transparent conductive film 755 by STEM is preferable because the boundary between the transparent conductive film 755 and the stacked semiconductor layer 760 can be clarified from the contrast of the image.

  Further, in the semiconductor light emitting device 700 according to the present embodiment, the height of the convex portion 711 of the semiconductor light emitting device base 701 can be 1 μm or less, as compared with the conventional case. As described above, when the convex structure is particularly nano-order, the thickness necessary for planarizing the convex structure in the undoped semiconductor layer 751 is reduced. For this reason, the semiconductor layer which absorbs the light from the light emitting semiconductor layer 753 becomes thinner, and thus, further improvement of the light extraction efficiency LEE is expected. In addition, warpage of the n-type semiconductor layer 752 and the light-emitting semiconductor layer 753 and the p-type semiconductor layer 754 sequentially stacked thereon can be suppressed, and a semiconductor light-emitting element 700 having a larger area than before can be manufactured. Can. Accordingly, the thickness of the underlayer is preferably 5 μm or less, more preferably 4 μm or less, still more preferably 3.5 μm or less, still more preferably 2.5 μm or less, and most preferably 1.5 μm or less.

(Reflective layer)
In the semiconductor light emitting device 700 according to this embodiment, a reflection layer (not shown) may be provided on the surface opposite to the main surface on which the laminated semiconductor layer 760 of the substrate for semiconductor light emitting device 701 is formed.

  The material of the reflective layer is not particularly limited as long as the reflectance at the emission wavelength is high. For example, as the metal, Ag, Al or an alloy thereof is selected, for example, from the viewpoints of the reflectance and the adhesion with the substrate 701 for a semiconductor light emitting device. Alternatively, a dielectric multilayer film may be formed as a reflective layer in order to achieve higher reflectance. The film thickness and the number of layers of the reflective layer are not particularly limited as long as the reflectance is in a desired range, and, for example, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, nitride oxide as a high refractive index layer Aluminum, silicon oxide can be used as the low refractive index layer. In addition, after the dielectric multilayer film is formed, a metal may be formed.

  In order to improve the adhesion between the reflective layer and the semiconductor light emitting element substrate 701, an adhesive layer may be provided between the reflective layer and the semiconductor light emitting element substrate 701. For example, silicon oxide can be used for the adhesion layer.

  In the substrate for a semiconductor light emitting device 701 according to the present embodiment, the semiconductor growth portion 713 having a concave structure serving as an epitaxial growth promoting portion and the semiconductor non-growth portion 712 constituted by the convex portion 711 are mixed in the main surface It is formed. By securing the semiconductor growth portion 713, crystal dislocation defects in the stacked semiconductor layers 751 to 754 can be reduced, and the crystal quality can be improved. Therefore, in the semiconductor light emitting device 700 manufactured using the semiconductor light emitting device base 701, the internal quantum efficiency IQE is improved. In addition, the semiconductor light emitting device 700 scatters light and cancels the waveguide mode by the convex portion 711 of the semiconductor non-growth portion 712, and the light extraction efficiency LEE is enhanced.

  The semiconductor growth portion 713 has a concave structure in which at least a part of the bottom surface is not flat, and by growing the undoped semiconductor layer 751 epitaxially from this non-flat surface, a large number of layers are formed at the interface between the substrate and the undoped semiconductor layer 751. Edge dislocations can be formed. When the undoped semiconductor layer 751 is grown in the lateral direction, the edge dislocations are also bent in the lateral direction, and a plurality of edge dislocations are combined and the number is drastically reduced according to the association of the stacked semiconductor layers 760 to be stacked. The reduction of the void volume of the edge dislocations along with the reduction of edge dislocations greatly relieves the compressive stress applied to the semiconductor layers 751 to 754. Due to this effect, in the manufactured semiconductor light emitting device 700, the piezoelectric field generated in the light emitting semiconductor layer 753 is reduced, and the Droop is suppressed.

  In addition, since the epitaxial growth promoting portion is uniformly formed in the substrate surface by the semiconductor growth portion 713 having a predetermined area, the flatness of the semiconductor layers 751 to 754 formed on the semiconductor light emitting element substrate 701 is improved. . Therefore, the efficiency of the semiconductor light emitting device can be enhanced, and the warping of the substrate can be suppressed, and the light emission wavelength distribution in the substrate surface can be improved. Thus, the semiconductor light emitting device 700 is manufactured with high yield and has excellent light emission efficiency.

  Hereinafter, the present invention will be specifically described by way of Examples and Comparative Examples, but the present invention is not limited to these Examples and Comparative Examples.

Example 1
First, a substrate for a semiconductor light emitting device was produced. The pattern of the base material for semiconductor light emitting devices was created using a nano processed sheet (dry film pattern sheet). The nanofabricated sheet will be described later.

A 2-inch single-sided mirror c-plane sapphire substrate was prepared and cleaned. Subsequently, the sapphire substrate was placed on a 120 ° C. hot plate. Next, the nano machined sheet was bonded to a sapphire substrate using a laminating roll heated to 120 ° C. Bonding was performed at a linear velocity of 50 mm / sec under a pressure of 0.5 MPa. The ultraviolet light was irradiated over the sapphire with respect to the bonded sapphire substrate of the nano processed sheet. The ultraviolet light was irradiated from a UV-LED light source with a wavelength of 365 nm, and was set so that the integrated light amount would be 1500 mJ / cm ² .

  Next, the nano-processed sheet and the sapphire substrate were sandwiched between two parallel flat plates heated to 120 ° C. The clamping pressure was 0.3 MPa and the time was 10 seconds. Subsequently, it was cooled to room temperature by air cooling, and the resin mold of the nanofabricated sheet was peeled from sapphire at a speed of 50 mm / sec. The two-layered resist layer was transferred and applied onto the main surface of the sapphire substrate by the above-described operation. An uneven structure was provided on the main surface of the resist layer. The pattern of the substrate for a semiconductor light emitting device was controlled by the shape and arrangement of the concavo-convex structure, the layer configuration of the two-layer resist, and the dry etching conditions described later.

<Nano processing sheet>
A nanofabricated sheet is a molded body to which a processing mask can be transferred and applied on a processing object by a bonding operation and a peeling operation. The nanomachined sheet is composed of a resin mold (resin mold), a first resist layer, and a second resist layer. The resin mold has a concavo-convex structure on the main surface, and the first resist layer is filled inside the concave portion of the concavo-convex structure. Then, the second resist layer is disposed to planarize the uneven structure of the resin mold and the first resist layer.

(Resin mold)
First, a resin mold was manufactured using roll-to-roll photo nanoimprinting. The width is 500 mm and the length is 180 m. The layer structure of the resin mold is a structure in which a transfer layer of 1.5 μm in thickness is adhered on the easy adhesion surface of a PET (polyethylene terephthalate) film of 50 μm in thickness. The concave and convex portions transferred were formed.

  The resin mold used is shown in FIG. FIG. 8 is a schematic plan view of a resin mold used in the examples. In the main surface of the resin mold 800, a plurality of recesses 801 and 804 are formed, and a recess group 802 is formed. The periphery of the concave portion group 802 and the center of the concave portion group 802 are the convex portion 803. The distance P8 between adjacent concave portions 801 and 804 is 1300 nm, the aperture diameter 88 of the concave portion 801 is 1200 nm, and the distance L8 between the concave portion group 802 and the concave portion group 802 is 1948 nm. Moreover, the contact angle of the water droplet with respect to the surface of the recessed part 801 of the resin mold 800, and the convex part 803 was between 140 degrees-153 degrees. The material of the transfer layer of the resin mold 800 was a mixture shown below.

(Transfer layer)
Fluorine-containing urethane (meth) acrylate (OPTOOL (registered trademark) DAC HP (manufactured by Daikin Industries, Ltd.)): trimethylolpropane (EO modified) triacrylate (M350 (manufactured by Toagosei Co., Ltd.)): 1-hydroxycyclohexyl phenyl ketone (Irgacure) (Registered trademark) 184 (manufactured by BASF Corporation): 2-benzyl-2-dimethylamino-1- (4-morpholinophenyl) -butanone-1 (Irgacure® 369 (manufactured by BASF Corporation)) = 17. It mixed in 5 g: 100 g: 5.5 g: 2.0 g.

  Next, a first resist layer was formed by die coating on the concave portion of the resin mold. As a material of the first resist layer, the following compounds were mixed to prepare a titanium-containing organic-inorganic composite resist.

(First resist layer)
Titanium tetrabutoxide monomer (manufactured by Wako Pure Chemical Industries, Ltd.): 3-acryloxypropyltrimethoxysilane (manufactured by Shin-Etsu Silicone Co., Ltd.): phenyl-modified silicone (manufactured by Toray Dow Corning): 1-hydroxy-cyclohexyl-phenyl-ketone Irgacure (registered trademark) 184, manufactured by BASF: 2-benzyl-2-dimethylamino-1- (4-morpholinophenyl) -butanone-1 (Irgacure 369, manufactured by BASF) = 65.2 g The titanium-containing organic-inorganic hybrid resist was prepared by mixing 34.8 g: 5.0 g: 1.9 g: 0.7 g and diluting with propylene glycol monomethyl ether. Furthermore, high molecular weight surfactant KF-945 (manufactured by Shin-Etsu Chemical Co., Ltd.) was added so as to be 0.006255 mass% with respect to the solid content. The molecular weight of KF-945 is about 2500, and the molecular structure is estimated to be the following chemical formula (1).

  The titanium-containing organic-inorganic composite resist is diluted with a mixed solvent in which a solvent A having a surface tension of 24.0 mN / m or less and a solvent B having a surface tension of 27.0 mN / m or more are mixed, and this is used as a coating solution And When the coating solution was applied to the inside of the recess by the die coating method, the pressure on the upstream side of the die lip was reduced. The coating speed was 10 m / min, and the discharge amount was controlled to control the filling amount of the first resist layer in the recess. After the application, air was blown and dried at 120 ° C., and then the resin mold was wound up and collected.

  Here, the resin mold on which the first resist layer was formed was analyzed to grasp the state of the first resist layer. The analysis used a scanning electron microscope, a transmission electron microscope, and energy dispersive X-ray spectroscopy in combination. The first resist layer was filled in the concave portions 801 and 804 of the concavo-convex structure of the resin mold 800. On the other hand, although the residue (aggregates) of the first resist layer on the order of several nanometers was sometimes observed on the upper surface of the convex portion 803 of the concavo-convex structure of the resin mold 800, the first resist on the upper surface The layer was not deposited thick. In addition, regarding the die coat film formation, it was confirmed that the filling amount of the first resist layer was changed by changing the discharge amount of the coating liquid, and the filling diameter of the first resist layer was changed accordingly.

  Next, a second resist layer was formed on the resin mold filled with the first resist layer. The film formation method was performed in the same manner as in the case of the first resist layer. The material of the second resist layer was a mixture of the following composition, which was diluted with a solvent having a surface tension of 25.0 mN / m or less to form a coating solution.

(2nd resist layer)
Epoxy novolac resin having a 100% acryloyl group modification ratio (CNEA-100 (manufactured by Kaes M Co.)): dipentaerythritol polyacrylate (NK ester A-DPH (manufactured by Shin-Nakamura Chemical Co., Ltd.)): 2, 2-dimethoxy-1 It mixed in 2, 2- diphenyl ethane 1-one (Irgacure (trademark) 651 (made by BASF)) = 80 g: 20 g: 4.5 g.

  Drying was performed at 105 ° C. After drying, a PE / EVA protective film having a haze (turbidity) of 10% or less was attached to the second resist layer, and in this state, the resin mold was wound up and collected. Here, the manufactured nano-processed sheet was analyzed to grasp the states of the first resist layer and the second resist layer. The analysis used a scanning electron microscope, a transmission electron microscope, and energy dispersive X-ray spectroscopy in combination. The first resist layer did not change before and after the film formation of the second resist layer. The second resist layer could be formed to planarize the uneven structure of the resin mold 800 and the first resist layer. In addition, it was confirmed that the film thickness of the second resist layer can be controlled by changing the discharge amount of the coating liquid for die coat film formation. That is, the filling diameter of the first resist layer and the film thickness of the second resist layer were changed by controlling the discharge amount of the coating liquid for die coat film formation.

  In Example 1, the filling diameter of the first resist layer was 1020 nm, and the film thickness of the second resist layer was 2550 nm.

<Fabrication of base material for semiconductor light emitting device>
Using the manufactured nanofabricated sheet, as described above, a two-layered resist layer consisting of the first resist layer and the second resist layer was transferred and applied onto the main surface of the sapphire substrate. Next, etching for processing the resist layer and etching for processing the sapphire substrate were continuously performed in the same chamber. The etching was performed using Gigax's Maxis 300 LCH ^plus ICP plasma etcher. Oxygen gas was used to etch the resist layer. Here, the first resist layer functions as an etching mask for the second resist layer, and the second resist layer is etched until the main surface of the sapphire substrate is partially exposed. The etching conditions were a processing gas pressure of 15 mTorr, an O ₂ flow rate of 130 SCCM, an ICP strength of 1200 W, a BAIS strength of 200 W, a substrate cooling He pressure of 4 Torr, a flow rate of 4 SCCM, and a processing time of 240 s.

Subsequently, reactive ion etching using BCl ₃ gas was performed to etch the sapphire substrate. Here, the sapphire substrate was etched using the second resist layer as an etching mask. The processing conditions were: processing gas pressure 3.2 mTorr, BCl ₃ flow rate 120 SCCM, ICP intensity 1700 W, BIAS intensity 300 W, substrate cooling He pressure 4 Torr, flow rate 4 SCCM, processing time 4500 s.

  The etched sapphire substrate (sapphire substrate) was taken out and washed with a solution in which sulfuric acid and hydrogen peroxide water were mixed at a weight ratio of 2: 1. At this time, the temperature of the treatment liquid was controlled to 100 ° C. or more.

  FIG. 9 is a cross-sectional view of a sapphire substrate used in the examples. FIG. 9A shows a SEM image of a cross-sectional view of the produced sapphire substrate, and FIG. 9B shows a schematic view thereof.

  As shown in FIG. 9, on the main surface of the manufactured sapphire substrate, a semiconductor non-growth portion which is a convex portion group is formed, and a semiconductor growth portion which is a concave structure is formed around the convex portion group. It was Further, no convex portion was formed at the center of the convex portion group (not shown), and the convex portions constituting the outermost portion of the convex portion group were adjacent to each other without being separated from each other. In addition, part of the bottom of the semiconductor growth site was curved. The height of the convex part which comprises a semiconductor non-growth part was 820 nm. When the distance D (see FIG. 4) between the reference surface and the lowermost part of the concave structure was measured from the SEM image of the cross sectional view, it was 30 nm. From this, it was found that the distance D is preferably 10 nm or more and 200 nm or less, more preferably 20 nm or more and 180 nm or less, and still more preferably 30 nm or more and 160 nm or less.

<Fabrication of semiconductor light emitting device>
On the sapphire substrate thus obtained, a low-temperature growth buffer layer of Al _x Ga _1-x N (0 ≦ x ≦ 1) was deposited to a thickness of 100 Å as a buffer layer. Next, undoped GaN was deposited as an undoped first semiconductor layer. Thereafter, Si-doped GaN was formed as a doped first semiconductor layer. Subsequently, a strain absorption layer is provided, and as the light emitting semiconductor layer, the well layers are formed with respective film thicknesses (60 Å, 250 Å) of the active layer (well layer, barrier layer = undoped InGaN, Si doped GaN) of multiple quantum wells. Six layers and seven barrier layers were laminated alternately. On the light emitting semiconductor layer, Mg-doped AlGaN, undoped GaN, and Mg-doped GaN were stacked as a second semiconductor layer so as to include an electroblocking layer, to obtain a stacked semiconductor layer.

  Then, ITO was formed into a film as a transparent conductive film, and the leak current was measured after the electrode formation process. Leakage current (Ir) when -5 V (reverse bias) is applied between the p electrode pad and the n electrode pad using an auto prober for 3,000 or more LED elements obtained on a 2-inch sapphire substrate Was measured. As a result, it was confirmed that Ir was smaller than 0.01 μA in all LED elements.

  After that, the mounting process was performed. The sapphire substrate was polished to a thickness of 160 μm and a reflective layer was provided on the back surface. The reflective layer was formed of an Ag-Pd-Cu alloy. Thereafter, with respect to the semiconductor light emitting devices obtained through the cutting step, 20 of the 3000 semiconductor light emitting devices described above were mounted, and the average was determined. The light emission output was measured by passing a current between the p electrode pad and the n electrode pad by bonding the silver plated TO can with Ag paste and wire bonding. The size of the chip was 350 μm square, the current was 20 mA, and the emission wavelength was 450 nm.

Here, in general, the Droop ratio is defined as a value obtained by dividing IQE (rated current) when a predetermined current (rated current) flows at maximum IQE _peak at low current. The relationship between the external quantum efficiency EQE, the internal quantum efficiency IQE, and the light extraction efficiency LEE is EQE = IQE × LEE, and since LEE does not depend on current, the Droop rate can be expressed by the following equation.
Droop ratio = IQE (rated current) / IQE _peak
= EQE (rated current) / LEE ÷ (EQE _peak / LEE)
= EQE (Rated current) / EQE _peak
The Droop ratio is closer to 1 and indicates that the reduction in IQE at high current can be suppressed, which is considered to be a high performance LED.

In Example 1, the value of EQE at 350 mA / mm ² (rated current density) divided by the maximum EQE _peak at low current was 0.88.

Comparative Example 1
The resin mold used in Comparative Example 1 was the same as in Example 1. A nanomachined sheet was manufactured by setting the filling diameter of the first resist layer to 1020 nm and the film thickness of the second resist layer to 1700 nm.

Using the manufactured nanofabricated sheet, a two-layer resist layer consisting of a first resist layer and a second resist layer was transferred and applied onto the main surface of the sapphire substrate. Next, etching for processing the resist layer and etching for processing the sapphire substrate were continuously performed in the same chamber. The etching was performed using Gigax's Maxis 300 LCH ^plus ICP plasma etcher. Oxygen gas was used to etch the resist layer. Here, the first resist layer functions as an etching mask for the second resist layer, and the second resist layer is etched until the main surface of the sapphire substrate is partially exposed. The etching conditions were a processing gas pressure of 15 mTorr, an O ₂ flow rate of 130 SCCM, an ICP strength of 1200 W, a BAIS strength of 200 W, a substrate cooling He pressure of 4 Torr, a flow rate of 4 SCCM, and a processing time of 240 s.

Subsequently, reactive ion etching using BCl ₃ gas was performed to etch the sapphire substrate. Here, the sapphire substrate was etched using the second resist layer as an etching mask. The processing conditions were a processing gas pressure of 3.2 mTorr, a BCl ₃ flow rate of 120 SCCM, an ICP strength of 1700 W, a BIAS strength of 400 W, a substrate cooling He pressure of 5 Torr, a flow rate of 5 SCCM, and a processing time of 2100 s.

  The etched sapphire substrate was taken out and washed with a solution in which sulfuric acid and hydrogen peroxide solution were mixed at a weight ratio of 2: 1. At this time, the temperature of the treatment liquid was controlled to 100 ° C. or more.

  FIG. 10 is a cross-sectional view of a sapphire substrate used in a comparative example. FIG. 10A shows a SEM image of a cross-sectional view of the produced sapphire substrate, and FIG. 10B shows a schematic view thereof.

  As shown in FIG. 10, a semiconductor non-growth site was formed on the main surface of the manufactured sapphire substrate. The height of the convex portion at this semiconductor non-growth portion was 820 nm. From the SEM image of the cross-sectional view, it was confirmed that there is no non-flat surface at the semiconductor growth site.

  After that, in the same manner as in Example 1, the evaluation was performed through the film formation of the semiconductor layer, the electrode formation, and the mounting process. The size of the chip was 350 μm square, the current was 20 mA, and the emission wavelength was 450 nm.

  At this time, the Droop ratio was 0.85, and the external quantum efficiency EQE at high current was apparently reduced, that is, the internal quantum efficiency IQE was reduced, as compared with Example 1.

  The embodiments of the present invention are not limited to the above-described embodiments and examples, and various changes, substitutions, and modifications may be made without departing from the scope of the technical idea of the present invention. Furthermore, if technical progress of the technology or another technology derived therefrom can realize the technical concept of the present invention in another way, it may be implemented using that method. Therefore, the claims cover all the embodiments that can be included within the scope of the technical idea of the present invention.

  As described above, the present invention has the effect of being able to manufacture a semiconductor light emitting device having excellent luminous efficiency with a high yield, and in particular, can be suitably used for a semiconductor light emitting device such as an LED.

100, 500, 600, 701 Substrates for semiconductor light emitting devices 101, 104, 501, 504, 601, 604, 711 Convex portions 102, 502, 602, 712 Semiconductor non-growth sites 103, 503, 603, 713 Semiconductor growth sites 700 Semiconductor light emitting device

Claims (6)

A substrate,
Comprising a semiconductor non-growth site and a semiconductor growth site on the main surface of the substrate,
It is a base material for semiconductor light emitting elements for forming a semiconductor light emitting element in which at least a first semiconductor layer, a light emitting semiconductor layer and a second semiconductor layer are laminated in this order on the substrate.
The semiconductor non-growth region has a convex structure, the semiconductor growth region has a concave structure, and at least a part of the bottom surface of the concave structure is a non-flat surface. Base material.   The base for a semiconductor light emitting device according to claim 1, wherein the bottom surface of the concave structure between the semiconductor non-growth portion and the semiconductor non-growth portion adjacent to each other is formed in a continuous wave shape. .   When the cross-section is observed along the longer one of the lines connecting the opposing centers of the four semiconductor non-growth sites closest to each other, the contours of the convex structures facing each other forming the semiconductor non-growth site The base material for a semiconductor light emitting device according to claim 2, wherein a distance between a reference surface formed by connecting inflection points of a curve and a lowermost part of the concave structure is 10 nm or more and 200 nm or less.   The convex structure includes a convex portion group in which at least a plurality of convex portions are configured to be adjacent to each other at an equal closest distance P1, and the convex portions constituting the outermost portion of the convex portion group are not separated from each other The base material for semiconductor light-emitting devices according to any one of claims 1 to 3, which is adjacent to   The substrate for a semiconductor light emitting device according to claim 4, wherein the concave structure is formed around the convex portion group. A laminated semiconductor layer formed by laminating at least two or more semiconductor layers and a light emitting layer laminated on the main surface side of the base material for a semiconductor light emitting device according to any one of claims 1 to 5. What is claimed is: 1. A semiconductor light emitting device comprising:

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