JP2019122240A - Power control device - Google Patents

Abstract

To reduce power consumption at light load and no load.
A power supply control device 100 serving as a control entity of an isolated switching power supply comprises a first output detection signal (= monitor voltage Vm) according to a DC output voltage to a load, a DC output voltage, and a target value thereof. A controller that monitors a second output detection signal (= feedback current Ifb) according to a difference value, and switches between different operation modes (= normal mode and at least one power saving mode) with different power consumption according to both monitoring results And 110. The controller 110 switches the operation mode between the normal mode and the power saving mode or between a plurality of power saving modes according to the monitoring result of the first output detection signal, and selects the monitoring result of the second output detection signal. It is preferable to return to the normal mode accordingly.
[Selected figure] Figure 2

Description

  The invention disclosed herein relates to a power control device.

  BACKGROUND ART Conventionally, a power supply control device (so-called power supply IC) has been widely and generally used as a control main body of an isolated switching power supply.

  In addition, patent document 1 can be mentioned as an example of the prior art relevant to the above.

JP, 2014-112996, A

  However, in the conventional power supply control device, there is room for further improvement in reducing the power consumption at the time of light load and no load.

  The invention disclosed in the present specification provides a power supply control device capable of reducing power consumption at the time of light load and no load in view of the above problems found by the inventors of the present application. The purpose is

  The power supply control device disclosed in the present specification is a control main body of the isolated switching power supply, and comprises: a first output detection signal according to a DC output voltage to a load; The controller is configured to monitor a second output detection signal according to a difference value from the target value, and switch a plurality of operation modes with different power consumption according to both monitoring results.

  Further, the power supply control device disclosed in the present specification is a control main body of the isolated switching power supply, and is a peak current switching unit that raises the peak current value of the primary current flowing to the output switch when light load is detected. It is set as having composition.

  Other features, elements, steps, advantages and characteristics of the present invention will become more apparent from the detailed description of the embodiments that follows and the accompanying drawings related thereto.

  According to the invention disclosed in the present specification, it is possible to provide a power supply control device capable of reducing power consumption under light load and no load.

Diagram showing the overall configuration of an electronic device equipped with an isolated switching power supply A diagram showing an exemplary configuration of a power supply IC Diagram showing conditions of operation mode switching in power supply IC Timing chart showing an example of operation mode switching in a power supply IC The figure which shows the 1st structural example (part related to operation mode switching) of a controller Diagram showing the internal operating state of the power supply IC in light load mode Timing chart showing an example of peak current control in light load mode Diagram showing the internal operating state of the power supply IC in no-load mode Timing chart showing an example of peak current control in no load mode The figure which shows the 2nd configuration example (part related to burst control) of a controller Timing chart showing an example of burst control in no load mode A diagram showing an exemplary configuration of a gain adjustment unit Diagram showing an example of package layout

<Insulated switching power supply>
FIG. 1 is a diagram showing an entire configuration of an electronic device provided with an isolated switching power supply. The electronic device X of this configuration example includes an isolated switching power supply 1 and a load 2 that operates by receiving power supply from the isolated switching power supply 1.

  The insulation type switching power supply 1 is an alternating current supplied from the commercial alternating current power supply PW to the primary circuit system 1p while electrically insulating between the primary circuit system 1p (GND1 system) and the secondary circuit system 1s (GND2 system). A means for converting an input voltage Vac (for example, AC 85 to 265 V) into a desired DC output voltage Vo (for example, DC 10 to 30 V) and supplying it to the load 2 of the secondary circuit system 1s. And a conversion unit 20.

  The rectifying unit 10 is a circuit block that generates a DC input voltage Vi (for example, DC 120 to 375 V) from the AC input voltage Vac and supplies it to the DC / DC conversion unit 20. The rectifying unit 10 is a filter 11, a diode bridge 12, a capacitor 13, and And 14. The filter 11 removes noise and surge from the AC input voltage Vac. The diode bridge 12 full-wave rectifies the AC input voltage Vac to generate a DC input voltage Vi. Capacitor 13 removes harmonic noise of AC input voltage Vac. Capacitor 14 smoothes DC input voltage Vi. Note that a protective element such as a fuse may be provided at the front stage of the rectifying unit 10. When the direct current input voltage Vi is directly supplied to the isolated switching power supply 1, the rectifying unit 10 can be omitted.

  The DC / DC conversion unit 20 is a circuit block that generates a desired DC output voltage Vo from the DC input voltage Vi and supplies it to the load 2. The power supply IC 100 and various discrete components (transformer TR , Resistors R1 to R8, capacitors C1 to C4, diodes D1 to D4, an N-channel type MOS (metal oxide semiconductor) field effect transistor N1, a light emitting diode LED, a phototransistor PT, and a shunt regulator REG).

  The transformer TR has a primary winding L1 (number of turns Np) and a secondary winding L2 (number of turns Ns) magnetically coupled to each other in reverse polarity while electrically insulating between the primary circuit system 1p and the secondary circuit system 1s. including. Also, the transformer TR includes an auxiliary winding L3 (number of turns Nd) provided in the primary circuit system 1p as a means for generating the power supply voltage Vcc of the power supply IC 100.

  The first end of the primary winding L1 is connected to the application end of the DC input voltage Vi (= the output end of the diode bridge 12). The second end of the primary winding L11 is connected to the drain of the transistor N1. The first end of the secondary winding L2 is connected to the anode of the diode D4. The second end of the secondary winding L2 is connected to the ground terminal GND2 of the secondary circuit system 1s.

  The number of turns Np and Ns may be adjusted arbitrarily to obtain a desired DC output voltage Vo. For example, the DC output voltage Vo decreases as the number of turns Np increases or as the number of turns Ns decreases, and conversely, as the number of turns Np decreases or as the number of turns Ns increases, the DC output voltage Vo increases.

  The power supply IC 100 is a semiconductor integrated circuit device provided in the primary circuit system 1 p, and corresponds to a power supply control device serving as a control main body of the isolated switching power supply 1 (in particular, the DC / DC conversion unit 20). The power supply IC 100 includes external terminals T1 to T8 as means for establishing an electrical connection with the outside of the apparatus. Of course, the power supply IC 100 may be provided with an external terminal other than the above.

  The external terminal T1 (auxiliary winding monitor / external latch stop terminal) is connected to a connection node (= application end of monitor voltage Vm) of the resistor R1 and the resistor R2. The resistances R1 and R2 are connected in series between the first end (corresponding to the application end of the induced voltage Vp) and the second end (= the ground end GND1 of the primary circuit system 1p) of the auxiliary winding L3. There is. The resistors R1 and R2 connected in this manner output a monitor voltage Vm (= {R2 / (R1 + R2)} × Vp) according to the induced voltage Vp of the auxiliary winding L3 from the connection node between them. Act as a department.

  Here, assuming that the voltage value of the induced voltage Vp in the on period of the transistor N1 is Vpon and the voltage value of the induced voltage Vp in the off period of the transistor N1 is Vpoff, then Vponpon-Vi × (Nd / Np). Vo Vo × (Nd / Ns).

  That is, the voltage value Vpon fluctuates according to the DC input voltage Vi, and the voltage value Vpoff fluctuates depending on the DC output voltage Vo. Therefore, for example, during the off period of the transistor N1, by monitoring the monitor voltage Vm according to the induced voltage Vp, overvoltage protection of the DC output voltage Vo or operation mode switching according to the DC output voltage Vo (details (Described later) can be performed.

  Thus, the above-mentioned circuit element group (TR and R1 to R2) generates the monitor voltage Vm (= corresponding to the first output detection signal) corresponding to the absolute value of the DC output voltage Vo. Act as a department.

  The external terminal T2 (= feedback signal input terminal) is connected to the collector of the phototransistor PT and the first end of the capacitor C1. The emitter of the phototransistor PT and the second end of the capacitor C1 are both connected to the ground terminal GND1. The phototransistor PT functions as a photocoupler together with the light emitting diode LED provided in the secondary circuit system 1s, and generates the feedback current Ifb according to the light signal from the light emitting diode LED.

  The external terminal T3 (= primary current sense terminal) is connected to the source and back gate of the transistor N1 and the first end of the resistor R3. The second end of the resistor R3 is connected to the ground terminal GND1. The resistor R3 functions as a sense resistor for detecting the primary current Ip flowing through the transistor N1 as a sense voltage Vcs (= Ip × R3).

  The external terminal T4 (= ground terminal) is connected to the ground terminal GND1.

  The external terminal T5 (= externally connected MOS drive terminal) is connected to the gate of the transistor N1 and externally outputs the gate signal G1. Transistor N1 turns on / off primary current Ip flowing through primary winding L1 by turning on / off a current path from the application end of DC input voltage Vi to ground end GND1 via primary winding L1. It is an output switch. The transistor N1 turns on when the gate signal G1 is at high level, and turns off when the gate signal G1 is at low level.

  The external terminal T6 (= power supply terminal) is connected to a connection node between the cathode of the diode D1 and the first end of the capacitor C2 (= application end of the power supply voltage Vcc). The anode of the diode D1 is connected to the first end of the auxiliary winding L3. The second end of the capacitor C2 is connected to the ground terminal GND1. The diode D1 and the capacitor C2 connected in this manner function as a power supply voltage generation unit that rectifies and smoothes the induced voltage Vp generated in the auxiliary winding L3 to generate the power supply voltage Vcc of the power supply IC 100. The winding ratio between the primary winding L1 and the auxiliary winding L3 of the transformer TR may be set appropriately in consideration of the power supply voltage Vcc required for the power supply IC 100.

  The external terminal T7 (non-connect terminal) is not connected anywhere.

  The external terminal T8 (= start / AC input voltage monitor terminal) is connected to the first end of the resistor R4 (= application end of the high voltage VH). The second end of the resistor R4 is connected to the cathode of each of the diodes D2 and D3. The anodes of the diodes D2 and D3 are connected to the positive and negative input ends of the diode bridge 12 (= application end of the AC input voltage Vac).

  Next, the connection relationship of the circuit elements provided in the secondary circuit system 1s will be described.

  The anode of the diode D4 is connected to the first end of the secondary winding L2, as described above. The cathode of the diode D4 and the first end of the capacitor C3 are both connected to the output end of the DC output voltage Vo. The second end of the capacitor C3 is connected to the ground terminal GND2. The diode D4 and the capacitor C3 connected in this way function as a rectifying and smoothing unit that rectifies and smoothes the induced voltage Vs generated in the secondary winding L2 to generate a DC output voltage Vo.

  The first end of the resistor R5 is connected to the output end of the DC output voltage Vo. The second end of the resistor R5 is connected to the anode of the light emitting diode LED. The cathode of the light emitting diode LED is connected to the cathode of the shunt regulator REG. The anode of the shunt regulator REG is connected to the ground terminal GND2. The gate (equivalent to a control terminal) of shunt regulator REG is a connection node between resistors R7 and R8 connected in series between the output end of DC output voltage Vo and ground terminal GND2 (= application of divided voltage Vod) The terminal is connected to Vod = {R8 / (R7 + R8)} × Vo). The resistor R6 and the capacitor C4 are connected in series between the gate and the cathode of the shunt regulator REG.

  The shunt regulator REG controls the drive current ILED of the light emitting diode LED so that the divided voltage Vod applied to the gate and the predetermined internal reference voltage VoREF cause an imaginary short.

  More specifically, when Vod> VoREF, the drive current ILED is increased as the difference value (= | Vod−VoREF |) between the two is larger. As a result, since the light emission of the light emitting diode LED becomes strong, the feedback current Ifb flowing to the phototransistor PT increases. On the other hand, when Vod <VoREF, the drive current ILED is reduced as the difference value between the two (= | Vod−VoREF |) increases. As a result, since the light emission of the light emitting diode LED becomes weak, the feedback current Ifb flowing to the phototransistor PT decreases.

  That is, in the above-mentioned circuit element group (R5 to R8, C4, LED, REG, and PT), a difference value between DC output voltage Vo and its target value (= {(R7 + R8) / R8} x VoREF) It functions as a second output detection unit that generates the feedback current Ifb (= corresponding to the second output detection signal).

  Further, in the isolated switching power supply 1 of the present configuration example, a function of performing variable control of the DC output voltage Vo in accordance with the operation state of the electronic device X is incorporated. By implementing such a function, it is possible to realize low standby power of the electronic device X.

  The power supply IC 100 provided in the primary circuit system 1 p does not have the function of setting the target value of the DC output voltage Vo. Therefore, variable control of the DC output voltage Vo is performed by the secondary circuit system 1s. Although the figure illustrates a configuration in which the DC output voltage Vo is variably controlled by switching the voltage division ratio of the divided voltage Vod by adjusting the resistance value of the resistor R8 using a microcomputer, the DC output voltage Vo The variable control method is not limited to this.

  Further, in the DC / DC conversion unit 20 configured as described above, the transistor N1, the transformer TR, the diode D4, and the capacitor C3 generate a DC output voltage Vo from the DC input voltage Vi and a flyback step-down switching output stage Act as.

  The step-down operation of the switching output stage will be briefly described. When the transistor N1 is turned on, the primary current Ip flows from the application end of the DC input voltage Vi to the ground terminal GND1 through the primary winding L1, transistor N1 and resistor R3. Is stored.

  Thereafter, when the transistor N1 is turned off, an induced voltage Vs is generated in the secondary winding L2 magnetically coupled to the primary winding L1, and the second winding L2 is directed to the ground terminal GND2 via the diode D4. The next current Is flows. At this time, the load 2 is supplied with a DC output voltage Vo obtained by rectifying and smoothing the induced voltage Vs of the secondary winding L2.

  Thereafter, the switching operation similar to the above is repeated by turning on / off the transistor N1.

  As described above, according to the isolated switching power supply 1 of this configuration example, the DC output voltage Vo is generated from the AC input voltage Vac while electrically insulating between the primary circuit system 1p and the secondary circuit system 1s. Load 2 can be supplied.

<Power supply IC>
FIG. 2 is a view showing an example of the configuration of the power supply IC 100. As shown in FIG. The power supply IC 100 of this configuration example includes comparators 101 to 108, a starter 109, a controller 110, an RS flip flop 111, a driver 112, a gain adjustment unit 113, a slope compensation unit 114, and an addition unit 115. The oscillator 116, the maximum duty setting unit 117, the resistor 118, and the P-channel MOS field effect transistor 119 are integrated.

  The comparator 101 compares the monitor voltage Vm input from the external terminal T1 to the non-inverting input terminal (+) with the threshold voltage Vth1 (= corresponding to the over voltage detection value) input to the inverting input terminal (−). An overvoltage detection signal S1 is generated. The overvoltage detection signal S1 is high when Vm> Vth1, and is low when Vm <Vth1.

  The comparator 102 compares the monitor voltage Vm input from the external terminal T1 to the noninverting input terminal (+) and the threshold voltage Vth2 (<Vth1, corresponding to the light load detection value) input to the inverting input terminal (−). A light load detection signal S2 is generated in comparison. The light load detection signal S2 becomes high level when Vm> Vth2, and becomes low level when Vm <Vth1.

  The comparator 103 compares the monitor voltage Vm input from the external terminal T1 to the non-inverting input terminal (+) and the threshold voltage Vth3 (<Vth2, corresponding to no-load detection value) input to the inverting input terminal (-). The non-load detection signal S3 is generated by comparison. The no-load detection signal S3 becomes high level when Vm> Vth3, and becomes low level when Vm <Vth3.

  The comparator 104 compares the feedback voltage Vfb input from the external terminal T2 to the noninverting input terminal (+) with the threshold voltage Vth4 (= corresponding to the immediate recovery detection value) input to the inverting input terminal (−). Thus, an immediate return detection signal S4 is generated. The immediate recovery detection signal S4 is high when Vfb> Vth4, and is low when Vfb <Vth4.

  The comparator 105 compares the feedback voltage Vfb input from the external terminal T2 to the inverting input terminal (-) with the threshold voltage Vth5 (<Vth4, corresponding to the burst detection value) input to the non-inverting input terminal (+) Thus, the burst detection signal S5 is generated. Therefore, the burst detection signal S5 becomes high level when Vfb <Vth5, and becomes low level when Vfb> Vth5.

  The comparator 106 receives the reference voltage Vref input from the adding unit 115 to the non-inversion input terminal (+) and the divided feedback voltage Vfb2 (= α × Vfb) input from the gain adjustment unit 113 to the inversion input terminal (−). However, the off timing signal S6 is generated by comparing 0 <α <1). The off timing signal S6 is high when Vref> Vfb2, and is low when Vref <Vfb2.

  The comparator 107 compares the sense voltage Vcs input from the external terminal T3 to the noninverting input terminal (+) with the threshold voltage Vth7 (= corresponding to the overload detection value) input to the inverting input terminal (−). The overload detection signal S7 is generated. The overload detection signal S7 becomes high level when Vcs> Vth7, and becomes low level when Vcs <Vth7.

  The comparator 108 compares the sense voltage Vcs input from the external terminal T3 to the noninverting input terminal (+) with the threshold voltage Vth8 (= corresponding to the overcurrent detection value) input to the inverting input terminal (−). Thus, the overcurrent detection signal S8 is generated. The overcurrent detection signal S8 becomes high level when Vcs> Vth8, and becomes low level when Vcs <Vth8.

  Although not shown in the drawing, a mask processing unit for fixing the sense voltage Vcs to a zero value for a predetermined mask period after the output switch 129 is turned on is provided at the front stage of the comparators 107 and 108. Good. With this configuration, the ringing noise of the sense voltage Vcs generated when the transistor N1 is turned on can be eliminated.

  Immediately after startup of isolated switching power supply 1 or in light load mode or no load mode (details will be described later) of power supply IC 100, starter 109 sets external terminal T8 high when power supply voltage Vcc falls below a predetermined threshold voltage. The power supply voltage Vcc is raised by charging or recharging the capacitor C2 externally attached to the external terminal T6 using the voltage VH.

  The controller 110 centrally controls the operation of each part of the power supply IC 100. For example, when focusing on the on-duty control of the transistor N1, the controller 110 controls the drive clock signal CLK (== on timing signal) input from the oscillator 116, the off timing signal S6 input from the comparator 106, and the maximum duty Based on the maximum duty setting signal Dmax input from the setting unit 117, pulse generation of the set signal S9 and the reset signal S10 is performed.

  Further, focusing on the abnormality protection function of the power supply IC 100, the controller 110 is reset to forcibly turn off the transistor N1 based on the overvoltage detection signal S1, the overload detection signal S7, and the overcurrent detection signal S8. The signal S10 is fixed at the off logic level.

  In addition, focusing on the operation mode switching function (details will be described later) of the power supply IC 100, the controller 110 generates a plurality of different power consumptions based on the light load detection signal S2, the no load detection signal S3, and the immediate recovery detection signal S4. Switch the operation mode (= normal mode and at least one power saving mode).

  Furthermore, the controller 110 also has a function of determining whether to perform burst control (= intermittent control) of the transistor N1 based on the burst detection signal S5. More specifically, the controller 110 basically keeps the transistor N1 off while the burst detection signal S5 is at high level.

  The RS flip flop 111 outputs PWM [pulse width modulation] output from the output terminal (Q) according to the set signal S9 input to the set terminal (S) and the reset signal S10 input to the reset terminal (R). ] To switch the logic level of the signal S11. Specifically, the RS flip flop 111 sets the PWM signal S11 to the high level when the set signal S9 rises to the high level, and the low level of the PWM signal S11 when the reset signal S10 rises to the high level. Reset to

  The driver 112 receives the input of the PWM signal S11, generates a gate signal G1, and outputs the gate signal G1 to the external terminal T5. More specifically, the driver 112 sets the gate signal G1 to high level when the PWM signal S11 is high level, and sets the gate signal G1 to low level when the PWM signal S11 is low level.

  The gain adjustment unit 113 generates a divided feedback voltage Vfb2 (= α × Vfb) by dividing the feedback voltage Vfb input from the external terminal T2 with a predetermined gain α (= voltage division ratio α). The gain adjustment unit 113 has a function of switching the gain α according to the operation mode of the power supply IC 100 (details will be described later).

  The slope compensation unit 114 generates a slope voltage Vslp having a triangular wave shape, a sawtooth wave shape, or an n-order slope wave shape (for example, n = 2) in synchronization with the drive clock signal CLK.

  The addition unit 115 adds the sense voltage Vcs (= voltage signal simulating the behavior of the primary current Ip) input from the external terminal T3 and the slope voltage Vslp input from the slope compensation unit 114 to generate the reference voltage Vref. Do. With this configuration, output feedback control of the current mode system is performed, so that stability of the output feedback loop can be enhanced, and transient response characteristics at the time of load fluctuation can be improved. However, it is also possible to omit the adding unit 115 when the voltage mode type output feedback control is sufficient.

  The oscillator 116 generates a driving clock signal CLK of the controller 110 and outputs the driving clock signal CLK to the controller 110. The oscillator 116 has a function of monitoring the divided feedback voltage Vfb2 and raising the oscillation frequency of the drive clock signal CLK for a certain period of time at peak load (= when the load becomes heavier than in steady state). It is good. If such a function is provided, price reduction of the transistor N1 and size reduction of the transformer TR can be realized.

  Maximum duty setting unit 117 generates maximum duty setting signal Dmax for limiting on duty Don of transistor N1 (= the ratio of on period Ton occupying switching cycle T) to a predetermined upper limit value or less, and outputs it to controller 110. Do.

  The resistor 118 (resistance value: R118) is connected between the application terminal of the constant voltage Vreg and the external terminal T2, and converts the feedback current Ifb flowing in the external terminal T2 into the feedback voltage Vfb (= Vreg−Ifb × R118). It is a current / voltage conversion element to be converted. Therefore, the feedback voltage Vfb decreases as the feedback current Ifb increases, and increases as the feedback current Ifb decreases.

  The source and back gate of the transistor 119 are connected to the application end of the constant voltage Vreg. The drain of the transistor 119 is connected to one end of the resistor 118. The gate of the transistor 119 is connected to the input end of the power save signal PS. The transistor 119 connected in this way turns on / off the current path through which the feedback current Ifb flows in response to the power save signal PS. More specifically, the transistor 119 is turned on when the power save signal PS is at low level, and is turned off when the power save signal PS is at high level.

  Although not shown in the figure, the power supply IC 100 includes, in addition to the above components, a constant voltage generation circuit, a charge pump circuit, a brownout circuit, a soft start circuit, an AC input compensation circuit, a frequency hopping circuit, and And various protection circuits (such as UVLO [under voltage lock out] circuits) may be integrated.

<On-duty control>
Next, on-duty control of the transistor N1 will be briefly described. As described above, when Vod> VoREF, as the difference value (= | Vod−VoREF |) between the two increases, the drive current ILED increases, so the feedback current Ifb also increases. When the feedback current Ifb increases, the feedback voltage Vfb decreases and the timing of intersection with the reference voltage Vref is advanced. Therefore, the rising timing of the off timing signal S6 is advanced, and the rising timing of the reset signal S10 is advanced. As a result, the falling timing of the PWM signal S11 (and thus the gate signal G1) is advanced, and the on-duty Don of the transistor N1 is reduced, so that the DC output voltage Vo is reduced.

  Conversely, when Vod <VoREF, the drive current ILED decreases as the difference value (= | Vod−VoREF |) between the two increases, so the feedback current Ifb also decreases. When the feedback current Ifb decreases, the feedback voltage Vfb rises and the timing of crossing with the reference voltage Vref is delayed. Therefore, the rising timing of the off timing signal S6 is delayed, and the rising timing of the reset signal S10 is delayed. As a result, the falling timing of the PWM signal S11 (and thus the gate signal G1) is delayed, and the on-duty Don of the transistor N1 is increased, so that the DC output voltage Vo is increased.

  By such on-duty control, the DC output voltage Vo can be maintained at its target value (= {(R7 + R8) / R8} × VoREF).

  Among the various components integrated in the power supply IC 100, the comparator 106, the controller 110, the RS flip flop 111, the driver 112, the gain adjustment unit 113, the slope compensation unit 114, and the resistor 118 Functions as an on-duty control unit that controls the on-duty Don of the transistor N1 based on the second output detection signal).

<Operation mode switching>
Next, switching of the operation mode of the power supply IC 100 will be described. As described above, the controller 110 has a function of switching between a plurality of operation modes with different power consumption based on the light load detection signal S2, the no load detection signal S3, and the immediate recovery detection signal S4. .

  The following description will be given taking as an example a case where a light load mode (MODE 2) and a no-load mode (MODE 3) are provided in addition to the normal mode (MODE 1) as the plurality of operation modes. The light load mode (MODE2) is the first power saving mode that consumes less power than the normal mode (MODE2), and the no load mode (MODE3) consumes more power than the light load mode (MODE2). This is a small second power saving mode (details of each will be described later).

  FIG. 3 is a diagram showing conditions of operation mode switching in the power supply IC 100. As shown in FIG. When the power supply IC 100 is in the normal mode (MODE 1), the monitor voltage Vm of the transistor N1 (more exactly, the monitor voltage Vm during the off period of the transistor N1) is lower than the threshold voltage Vth2, ie, light When the period in which the pulse edge of the load detection signal S2 is not detected continues for the determination time Tc1, the power supply IC 100 shifts from the normal mode (MODE1) to the light load mode (MODE2). Conversely, when the power supply IC 100 is in the light load mode (MODE 2), the monitor voltage Vm is higher than the threshold voltage Vth 2, that is, the pulse edge of the light load detection signal S 2 is periodically detected. When the period continues for the determination time Tc1, the power supply IC 100 returns from the light load mode (MODE 2) to the normal mode (MODE 1).

  Also, when the power supply IC 100 is in the light load mode (MODE 2), a state in which the monitor voltage Vm is lower than the threshold voltage Vth 3, that is, a period in which no pulse edge of the no load detection signal S 3 is detected continues over the determination time Tc 1. Then, the power supply IC 100 shifts from the light load mode (MODE 2) to the no load mode (MODE 3). Conversely, when the power supply IC 100 is in the no load mode (MODE 3), a state where the monitor voltage Vm is higher than the threshold voltage Vth 3, that is, a pulse edge of the no load detection signal S 3 is detected periodically. When the period continues for the determination time Tc1, the power supply IC 100 returns from the no load mode (MODE 3) to the light load mode (MODE 2).

  As described above, the controller 110 operates between the normal mode (MODE 1) and the light load mode (MODE 2) according to the monitoring result of the monitor voltage Vm (= light load detection signal S2 and no-load detection signal S3), or The operation mode switching of the power supply IC 100 is performed between the light load mode (MODE 2) and the no load mode (MODE 3).

  As described above, the monitor voltage Vm in the off period of the transistor N1 fluctuates depending on the DC output voltage Vo. Therefore, according to the above operation mode switching, for example, when the DC output voltage Vo is pulled down in the secondary circuit system 1s, this can be detected and the power consumption of the power supply IC 100 can also be pulled down. It is possible to realize a further reduction of standby power as a whole.

  In the power supply IC 100, since the monitor voltage Vm for detecting an overvoltage is also used for switching the operation mode, the number of external terminals does not have to be unnecessarily increased.

  In addition, regardless of whether the power supply IC 100 is in the light load mode (MODE 2) or the no-load mode (MODE 3), the feedback voltage Vfb is higher than the threshold voltage Vth4, that is, the immediate recovery detection signal S4 is high. When continuing for a predetermined determination time Tc2, the power supply IC 100 immediately returns to the normal mode (MODE 1).

  Note that “instant recovery” in this specification does not depend on the monitoring result of the monitor voltage Vm, and the normal mode (MODE 1) does not go through the light load mode (MODE 2) even in the no-load mode (MODE 3). In addition to the case where the immediate recovery detection signal S4 returns to the high level immediately returns to the normal mode (MODE 1), as described above, the normal mode passes through the predetermined determination time Tc2 as described above. The case of returning to (MODE 1) is also included.

  Thus, the controller 110 performs an immediate return to the normal mode (MODE 1) according to the monitoring result (= immediate return detection signal S4) of the feedback current Ifb (and thus the feedback voltage Vfb). Therefore, when the target value of the DC output voltage Vo is raised in the secondary circuit system 1s, the power supply IC 100 can be restored to the normal mode (MODE 1) without delay, and the power supplied to the load 2 can be increased. Even if 2 is heavy, the DC output voltage Vo can be raised without any problem.

  FIG. 4 is a timing chart showing an example of operation mode switching in the power supply IC 100. The gate signal G1, the switch voltage Vsw (= the drain voltage of the transistor N1), the monitor voltage Vm, and the mask signal MASK (= the controller 110) in order from the top. Internal signal), the light load detection signal S2, the no load detection signal S3, and the operation mode (MODE) of the power supply IC 100.

  The mask signal MASK is a binary signal for performing mask processing (= signal processing for extracting only the logic level in the off period of the transistor N1) on the light load detection signal S2 and the no load detection signal S3 respectively. After the gate signal G1 is lowered to the low level, it becomes the high level (= the logic level at the time of the mask release) for a predetermined monitoring period. Therefore, in this figure, not the output signals of the comparators 102 and 103 are depicted as they are but the signals subjected to the mask processing are depicted as the light load detection signal S2 and the no load detection signal S3.

  When the target value of the DC output voltage Vo is set to a normal value in the secondary circuit system 1s, Vm> Vth2 in the off period of the transistor N1 (= the low level period of the gate signal G1). At this time, periodic pulses appear in the light load detection signal S2 and the no-load detection signal S3, respectively. Controller 110 maintains power supply IC 100 in the normal mode (MODE 1) while these pulses are detected.

  On the other hand, when the target value of the DC output voltage Vo is reduced by one step in the secondary circuit system 1s, Vth3 <Vm <Vth2 is obtained in the off period of the transistor N1. At this time, as with the previous example, a periodic pulse appears in the no-load detection signal S3, but the light-load detection signal S2 is stuck to the low level. The controller 110 shifts the power supply IC 100 from the normal mode (MODE 1) to the light load mode (MODE 2) when this state continues for the predetermined determination time Tc1.

  Furthermore, when the target value of the DC output voltage Vo is reduced by one more step in the secondary circuit system 1s, Vm <Vth3 is obtained in the off period of the transistor N1. At this time, not only the light load detection signal S2 but also the no load detection signal S3 is stuck at the low level. When this state continues for a predetermined determination time Tc1, the controller 110 shifts the power supply IC 100 from the light load mode (MODE 2) to the no load mode (MODE 3).

<Controller (first configuration example)>
FIG. 5 is a diagram showing a first configuration example of the controller 110. As shown in FIG. The controller 110 of this configuration example includes an edge detection unit a, a first timer unit b, a second timer unit c, and an operation mode switching unit d as functional blocks related to operation mode switching of the power supply IC 100. .

  The edge detection unit a is a circuit block that detects pulse edges (for example, rising edges) of the light load detection signal S2 and the no-load detection signal S3, and includes an inverter a1 and D flip flops a2 to a5.

  The inverter a1 logically inverts the output state signal Nout to generate an inverted output state signal NoutB. Therefore, the inverted output state signal NoutB goes low when the output state signal Nout is high, and goes high when the output state signal Nout is low. The output state signal Nout is a signal indicating the on / off state of the transistor N1. For example, the output state signal Nout is high during the on period of the transistor N1, and is low during the off period of the transistor N1. The output state signal Nout may be generated, for example, by level shifting the gate signal G1.

  The D flip-flop a2 latches the high level signal input to the data input terminal (D) when the light load detection signal S2 input to the clock input terminal rises to high level, and the result is edged The detection signal Sa2 is output from the output terminal (Q).

  When the no-load detection signal S3 input to the clock input terminal rises to the high level, the D flip flop a3 latches the high level signal input to the data input terminal (D), and the result is edged The detection signal Sa3 is output from the output terminal (Q).

  The D flip flops a2 and a3 are reset by the inverted output state signal NoutB inputted to their respective reset input terminals. Specifically, the D flip flops a2 and a3 are reset (Sa2 = Sa3 = L) during the low level period (= the on period of the transistor N1) of the inverted output state signal NoutB and the high of the inverted output state signal NoutB In the level period (= the off period of the transistor N1), the reset release state is established.

  The D flip-flop a4 latches the edge detection signal Sa2 input to the data input terminal (D) when the output state signal Nout input to the clock input terminal rises to a high level, and the result is output as an edge The detection signal Sa4 is output from the output terminal (Q).

  The D flip-flop a5 latches the edge detection signal Sa3 input to the data input terminal (D) when the output state signal Nout input to the clock input terminal rises to a high level, and the result is edged The detection signal Sa5 is output from the output terminal (Q).

  Also, the D flip flops a4 and a5 are reset by the enable signal EN inputted to their respective reset input terminals. Specifically, the D flip flops a4 and a5 are reset (Sa4 = Sa5 = L) during the low level period of the enable signal EN (= the disable period of the power supply IC 100), and the high level period of the enable signal EN ( In the enable period of the power supply IC 100), the reset release state is established.

  The first timer unit b is a circuit block that counts a predetermined determination time Tc1, and includes timers b1 to b4, RS flip flops b5 and b6, and inverters b7 to b10.

  The timer b1 is for determining transition from the normal mode (MODE1) to the light load mode (MODE2), and counts the number of pulses of the clock pulse CK input to the clock input terminal, and the count value is a predetermined value (= When the determination time Tc1 is reached, the set signal Sb1 is raised to the high level. However, the timer b1 is reset by the inverted edge detection signal Sa4B input to the reset input terminal. More specifically, the timer b1 is reset during the low level period of the inverted edge detection signal Sa4B (= period in which the pulse edge of the light load detection signal S2 is periodically detected), and the inverted edge detection signal Sa4B is The reset release state is established in a high level period (= a period in which the pulse edge of the light load detection signal S2 is not detected). Therefore, the set signal Sb1 rises to the high level when the inverted edge detection signal Sa4B is maintained at the high level for the determination time Tc1.

  The timer b2 is used to determine the return from the light load mode (MODE2) to the normal mode (MODE1), and counts the number of pulses of the clock pulse CK input to the clock input terminal, and the count value is a predetermined value (= When the determination time Tc1 is reached, the reset signal Sb2 is raised to the high level. However, the timer b2 is reset by the edge detection signal Sa4 input to the reset input terminal. Specifically, the timer b2 is reset during the low level period of the edge detection signal Sa4 (= the period when the pulse edge of the light load detection signal S2 is not detected), and the high level period of the edge detection signal Sa4 (= light load During the period when the pulse edge of the detection signal S2 is periodically detected, the reset release state is established. Therefore, the reset signal Sb2 rises to the high level when the edge detection signal Sa4 is maintained at the high level for the determination time Tc1.

  The timer b3 is used to determine the transition from the light load mode (MODE2) to the no load mode (MODE3), and counts the number of pulses of the clock pulse CK input to the clock input terminal. = When the determination time Tc1 is reached, the set signal Sb3 is raised to the high level. However, the timer b3 is reset by the inverted edge detection signal Sa5B input to the reset input terminal. More specifically, the timer b3 is reset during the low level period of the inverted edge detection signal Sa5B (= period in which the pulse edge of the no-load detection signal S3 is periodically detected), and the inverted edge detection signal Sa5B The reset release state is entered in the high level period (= the period when the pulse edge of the no-load detection signal S3 is not detected). Accordingly, the set signal Sb3 rises to the high level when the inverted edge detection signal Sa5B is maintained at the high level for the determination time Tc1.

  The timer b4 is used to determine the return from the no-load mode (MODE3) to the light-load mode (MODE2), and counts the number of pulses of the clock pulse CK input to the clock input terminal. = When the judgment time Tc1 is reached, the reset signal Sb4 is raised to the high level. However, the timer b4 is reset by the edge detection signal Sa5 input to the reset input terminal. More specifically, the timer b4 is reset during the low level period of the edge detection signal Sa5 (= the period when the pulse edge of the no-load detection signal S3 is not detected), and the high level period of the edge detection signal Sa5 (= no During the period when the pulse edge of the load detection signal S3 is detected periodically, the reset release state is established. Therefore, the reset signal Sb4 rises to the high level when the edge detection signal Sa5 is maintained at the high level for the determination time Tc1.

  The RS flip flop b5 receives the transition return signal Sb5 output from the output end (Q) according to the set signal Sb1 input to the set end (S) and the reset signal Sb2 input to the reset end (R). Switch logic levels. Specifically, the RS flip flop b5 sets the transition return signal Sb5 to the high level when the set signal Sb1 rises to the high level, and the transition return signal Sb5 when the reset signal Sb2 rises to the high level. Reset to low level. That is, the transition return signal Sb5 rises to high level at the timing to shift from the normal mode (MODE1) to the light load mode (MODE2), and is low at the timing to shift from the light load mode (MODE2) to the normal mode (MODE1). Fall to the level.

  The RS flip flop b6 is a transition return signal Sb6 output from the output end (Q) according to the set signal Sb3 input to the set end (S) and the reset signal Sb4 input to the reset end (R). Switch logic levels. More specifically, the RS flip flop b6 sets the transition return signal Sb6 to the high level when the set signal Sb3 rises to the high level, and the transition return signal Sb6 when the reset signal Sb4 rises to the high level. Reset to low level. That is, the transition return signal Sb6 rises to the high level at the timing to shift from the light load mode (MODE2) to the no load mode (MODE3), and the timing to return from the no load mode (MODE3) to the light load mode (MODE2) Falls to low level.

  The inverter b7 logically inverts the edge detection signal Sa4 to generate an inverted edge detection signal Sa4B. Accordingly, the inverted edge detection signal Sa4B is low when the edge detection signal Sa4 is high, and is high when the edge detection signal Sa4 is low.

  The inverter b8 logically inverts the edge detection signal Sa5 to generate an inverted edge detection signal Sa5B. Therefore, the inverted edge detection signal Sa5B is low when the edge detection signal Sa5 is high, and is high when the edge detection signal Sa5 is low.

  The inverter b9 logically inverts the transition return signal Sb5 to generate an inversion transition return signal Sb5B. The inversion transition return signal Sb5B is at low level when the transition return signal Sb5 is at high level, and is at high level when the transition return signal Sb5 is at low level.

  The inverter b10 logically inverts the transition return signal Sb6 to generate an inversion transition return signal Sb6B. The inversion transition return signal Sb6B is low when the transition return signal Sb6 is high, and is high when the transition return signal Sb6 is low.

  The second timer unit c is a circuit block that counts a predetermined determination time Tc2, and includes a timer c1.

  The timer c1 is for determining an immediate return from the light load mode (MODE 2) and no load mode (MODE 3) to the normal mode (MODE 1), and counts the number of clock pulses CK input to the clock input terminal. When the count value reaches a predetermined value (= corresponding to the determination time Tc2), the immediate recovery signal Sc1 is raised to the high level. However, the timer c1 is reset by the immediate recovery detection signal S4 input to the reset input terminal. Specifically, the timer c1 is reset during the low level period of the immediate recovery detection signal S4 (= the period when the feedback voltage Vfb is lower than the threshold voltage Vth4), and the high level period of the immediate recovery detection signal S4 (= feedback) When the voltage Vfb is higher than the threshold voltage Vth4, the reset cancellation state is established. Therefore, the immediate return signal Sc1 rises to the high level when the immediate return detection signal S4 is maintained at the high level for the determination time Tc2.

  Note that, in the drawing, a configuration example using a pulse counter (= digital timer) as each of the timers b1 to b4 and the timer c1 has been described, but an analog timer may be used.

  The operation mode switching unit d is a circuit block that generates the mode signals M1 to M3 based on the inversion transition return signals Sb5B and Sb6B and the immediate return signal Sc1, and includes D flip flops d1 to d3 and an up / down counter d4.

  The D flip-flop d1 latches the inverted transition return signal Sb5B input to the data input terminal (D) when the drive clock signal CLK input to the clock input terminal rises to the high level, and the result is The up-down signal Sd1 is output from the output terminal (Q).

  The D flip-flop d2 latches the inverted transition return signal Sb6B input to the data input terminal (D) when the drive clock signal CLK input to the clock input terminal rises to the high level, and the result is The up-down signal Sd2 is output from the output terminal (Q).

  The D flip-flop d3 latches the immediate recovery signal Sc1 input to the data input terminal (D) when the drive clock signal CLK input to the clock input terminal rises to a high level, and resets the result. The signal Sd3 is output from the output end (Q).

  Also, the D flip flops d1 to d3 are reset by the enable signal EN inputted to their respective reset input terminals. More specifically, D flip flops d1 to d3 are reset (Sd1 = Sd2 = Sd3 = L) during the low level period of enable signal EN (= disable period of power supply IC 100), and enable signal EN is high. The reset release state is entered in the level period (= the enable period of the power supply IC 100).

  The up / down counter d4 switches the logic levels of the mode signals M1 to M3 when the rising and falling edges of the up / down signals Sd1 and Sd2 occur.

  As a premise of the following description, it is assumed that the mode signal M1 becomes high level when the power supply IC 100 is in the normal mode (MODE 1) and becomes low level in the other operation modes. On the other hand, the mode signal M2 is high when the power supply IC 100 is in the light load mode (MODE 2), and low in the other operation modes. The mode signal M3 is high when the power supply IC 100 is in the no-load mode (MODE 3), and low in the other operation modes.

  That is, if the mode signals M1 to M3 are understood as a 3-bit signal of "M1M2M3", the output value of the up / down counter d4 can take three values of "100b", "010b" and "001b", Each output value corresponds to the normal mode (MODE 1), the light load mode (MODE 2), and the no load mode (MODE 3).

  For example, when the output value of the up / down counter d4 is "100b", the pulse edge of the light load detection signal S2 is not detected over the determination time Tc1 and the up / down signal Sd1 falls to low level. The output value of the down counter d4 is counted down to "010b". By this countdown, the operation mode of the power supply IC 100 is shifted from the normal mode (MODE 1) to the light load mode (MODE 2).

  On the other hand, when the output value of the up / down counter d4 is "010b", the pulse edge of the light load detection signal S2 is periodically detected over the determination time Tc1, and the up / down signal Sd1 rises to the high level. The output value of the up / down counter d4 is counted up to "100b". By this count-up, the operation mode of the power supply IC 100 is returned from the light load mode (MODE 2) to the normal mode (MODE 1).

  Also, for example, when the output value of the up / down counter d4 is "010b", the pulse edge of the no-load detection signal S3 is not detected over the determination time Tc1, and the up / down signal Sd2 falls to the low level. The output value of the up / down counter d4 is counted down to "001b". By this countdown, the operation mode of the power supply IC 100 is shifted from the light load mode (MODE 2) to the no load mode (MODE 3).

  On the other hand, when the output value of the up / down counter d4 is "001b", if the pulse edge of the no-load detection signal S3 is periodically detected over the determination time Tc1, and the up / down signal Sd2 rises to the high level, The output value of the up / down counter d4 is counted up to "010b". By this count-up, the operation mode of the power supply IC 100 is returned from the no-load mode (MODE 3) to the light load mode (MODE 2).

  The up / down counter d4 is reset by the reset signal Sd3 input from the D flip flop d3. More specifically, when the output value of the up / down counter d4 is "010b" or "001b", the feedback voltage Vfb continuously exceeds the threshold voltage Vth4 over the determination time Tc2, and the reset signal Sd3 When rising to a high level, the output value of the up / down counter d4 is reset to "100b". By this reset, the operation mode of the power supply IC 100 is immediately restored from the light load mode (MODE 2) or no load mode (MODE 3) to the normal mode (MODE 1).

  The up / down counter d4 is also reset by the enable signal EN input to the reset input terminal. More specifically, the up / down counter d4 is reset during the low level period of the enable signal EN (= the disable period of the power supply IC 100), and during the high level period of the enable signal EN (= the enable period of the power supply IC 100). It becomes reset cancellation state.

<Light load mode>
FIG. 6 is a diagram showing an internal operation state of the power supply IC 100 in the light load mode (MODE 2). In the light load mode (MODE 2), as shown by the x marks in this figure, the comparators 101 and 107, and a part of the controller 110 (= a functional unit related to signal processing of the overvoltage detection signal S1 and the overload detection signal S7 Stops the operation, and the respective current consumption is reduced.

  FIG. 7 is a timing chart showing an example of peak current control in the light load mode (MODE 2). The feedback voltage Vfb is depicted on the upper stage, and the sense voltage Vcs is depicted on the lower stage.

  As shown in the figure, in the light load mode (MODE 2), for example, the peak current value (corresponding to the peak value Vcsp of the sense voltage Vcs) of the primary current Ip flowing through the transistor N1 is compared with that in the normal mode (MODE 1), for example It can be raised 1.5 times.

  According to such peak current control, more primary current Ip can be supplied by turning on the transistor N1 once. Therefore, for example, as shown in this figure, in the case where the feedback voltage Vfb falls below the threshold voltage Vth5 and the burst control of the transistor N1 is performed, the number of switchings at the time of burst release can be reduced, thereby reducing switching loss. It is possible to

  As described above, in the light load mode (MODE 2), the current consumption of the power supply IC 100 is reduced more than that in the normal mode (MODE 1), and the peak current value at the time of burst release is raised. Has been realized.

<No load mode>
FIG. 8 is a diagram showing an internal operation state of the power supply IC 100 in the no-load mode (MODE 3). In the no-load mode (MODE 3), as shown by the x marks in the figure, the same reduction of current consumption as the light-load mode (MODE 2) is performed, and the comparator 101 is further stopped during the burst stop period of the transistor N1. To 103, the comparators 106 to 108, the oscillator 116, the maximum duty setting unit 117, and almost all parts of the controller 110 (other than the functional units related to the signal processing of the immediate return detection signal S4 and the burst detection signal S5) operate. Stop and reduce the current consumption of each.

  In the no-load mode (MODE 3), the transistor 119 is turned off in the burst stop period of the transistor N1. Therefore, since the current path through which the feedback current Ifb flows is cut off, the current consumption of the power supply IC 100 is significantly reduced.

  FIG. 9 is a timing chart showing an example of peak current control in the no-load mode (MODE 3). As in FIG. 7 described above, the feedback voltage Vfb is depicted on the upper stage, and the sense voltage Vcs is depicted on the lower stage.

  As shown in the figure, in the no-load mode (MODE3), for example, the peak current value (corresponding to the peak value Vcsp of the sense voltage Vcs) of the primary current Ip flowing through the transistor N1 is compared with that in the normal mode (MODE1), for example Doubled. Therefore, since the number of switchings at the time of burst release can be further reduced compared to the light load mode (MODE 2), it is possible to further reduce the switching loss.

  Incidentally, even if the peak current value of the primary current Ip is doubled, the peak value (= 2 Vcsp) of the sense voltage Vcs is set to be sufficiently lower than the overcurrent detection value Vocp. Therefore, there is no unintended overcurrent protection in the no-load mode (MODE 3).

  Furthermore, in the no load mode (MODE 3), the burst stop time is controlled to be always equal to or more than a predetermined value (for example, 10 ms) (details will be described later).

  As described above, in the no-load mode (MODE 3), the burst stop time is controlled to be a predetermined value or more, and the current consumption at the burst stop is reduced as compared with the light load mode (MODE 2). By further raising the peak current value at the same time, a further reduction in standby power of the power supply IC 100 is realized.

<Controller (second configuration example)>
FIG. 10 is a diagram showing a second configuration example of the controller 110. As shown in FIG. The controller 110 of this configuration example includes a burst control unit e as a functional block related to burst control in no load mode (MODE 3).

  The burst control unit e is a circuit block that generates the burst stop signal STOP and the power save signal PS such that the burst stop time is always equal to or more than a predetermined value (for example, 10 ms) in the no-load mode (MODE3). It includes a pulse generation unit e1, timers e2 and e3, and an OR operator e4.

  The one-shot pulse generation unit e1 generates a one-shot pulse as the reset signal Se1 when the burst detection signal S5 rises to the high level.

  The timer e2 is for counting burst stop time Tc3 (for example, 10 ms), counts the number of pulses of the clock pulse CK input to the clock input terminal, and the count value corresponds to a predetermined value (= burst stop time Tc3). When it reaches, the timer signal Se2 falls from high level to low level. The timer e2 is reset by the one-shot pulse of the reset signal Se1 input to the reset input terminal. Therefore, the timer signal Se2 rises to the high level when the burst detection signal S5 rises to the high level, and falls to the low level when the burst stop time Tc3 elapses. The timer signal Se2 is output to the timer e3, and is also output to each part of the power supply IC 100 as the power save signal PS.

  The timer e3 is for generating the circuit recovery time Tc4 (for example, 150 μs). As the simplest circuit configuration, for example, a delay timer that delays the timer signal Se2 by the circuit recovery time Tc4 and generates the delay timer signal Se3 is used. be able to. The circuit recovery time Tc4 is a required standby time until the respective operations are stabilized after the current supply to the respective portions of the power supply IC 100 is restarted.

  The logical sum operator e4 generates a logical sum signal Se4 of the timer signal Se2 and the delay timer signal Se3. Therefore, the logical sum signal Se4 becomes high level when at least one of the timer signal Se2 and the delay timer signal Se3 is high level, and becomes low level when both the timer signal Se2 and the delay timer signal Se3 are low level. Become. The logical sum signal Se4 is used as the burst stop signal STOP.

<Burst control>
FIG. 11 is a timing chart showing an example of burst control in the no-load mode (MODE 3), and from top to bottom, feedback voltage Vfb, power save signal PS, burst stop signal STOP, gate signal G1, sense voltage Vcs, feedback current Ifb and power supply voltage Vcc are depicted.

  At time t1, when the feedback voltage Vfb falls below the threshold voltage Vth5, the power save signal PS and the burst stop signal STOP rise to the high level. As a result, the gate signal G1 is fixed at the low level, the switching of the transistor N1 is stopped, and the feedback current Ifb is cut off.

  When the burst stop time Tc3 has elapsed from time t1, the power save signal PS falls to low level at time t2. As a result, the feedback current Ifb starts to flow. In this figure, the feedback voltage Vfb exceeds the threshold voltage Vth5 before the burst stop time Tc3 elapses from the time t1. However, in the no-load mode (MODE 3), the power save signal PS is at that time. It can not be lowered to low level.

  When the circuit recovery time Tc4 elapses from time t2, the burst stop signal STOP falls to low level at time t3. As a result, the low level fixation of the gate signal G1 is released, and the switching of the transistor N1 is resumed.

  Thereafter, at time t4, when the feedback voltage Vfb falls below the threshold voltage Vth5 again, the same burst control as described above is repeated.

  As described above, in the burst control in the no-load mode (MODE 3), not only the switching of the transistor N1 is stopped but also the feedback current Ifb flowing in the phototransistor PT when the burst is stopped (see times t1 to t3). Therefore, the standby power of the power supply IC 100 (= power consumed by switching operation of the transistor N1 + power consumed by self operation of the power supply IC 100) can be significantly reduced.

  In particular, when the DC output voltage Vo is lowered in the secondary circuit system 1s, the power supply voltage Vcc generated from the induced voltage Vp of the auxiliary winding L3 is also lowered. Therefore, in the power supply IC 100, the capacitor C2 is recharged by the starter 109. However, in the case of the burst control in the no-load mode (MODE 3), the power consumption of the power supply IC 100 is significantly reduced to perform the above-mentioned recharge. The frequency of standby power can be kept to a minimum, so that the standby power does not deteriorate.

  Note that in this figure, while the feedback current Ifb is cut off (see time t1 to t2 etc.), it is understood that the fall of the power supply voltage Vcc is gradual and the frequency of recharging by the starter 109 is suppressed. .

<Gain Adjustment Unit (Peak Current Switching Unit)>
FIG. 12 is a diagram showing an exemplary configuration of the gain adjustment unit 113. As shown in FIG. The gain adjustment unit 113 of this configuration example is a circuit block that functions as a peak current switching unit that switches the peak current value of the primary current Ip flowing through the transistor N1 in each of a plurality of operation modes. It includes MOS field effect transistors N2 and N3, an NOR gate NOR, and an inverter INV.

  In the following description, the resistance of the resistor R9 is 3R, the resistance of the resistor R10 is R, the resistance of the resistor R11 is 0.5R, and the resistance of the resistor R12 is 1.5R.

  The first end of the resistor R9 is connected to the input end (= external terminal T2) of the feedback voltage Vfb. The second end of the resistor R9 and the first end of the resistor R10 are connected to the output end of the divided feedback voltage Vfb2. The second end of the resistor R10 and the first end of the resistor R11 are connected to the drain of the transistor N2. The first end of the resistor R11 and the second end of the resistor R12 are connected to the source and back gate of the transistor N2 and the drain of the transistor N3, respectively. The second end of the resistor R12 is connected to the source and back gate of the transistor N3 and the ground terminal GND1, respectively.

  The gate of the transistor N2 is connected to the output end of the NOR circuit NOR (= corresponding to the output end of the gate signal GN2). Therefore, the transistor N2 turns on when the gate signal GN2 is at high level, and turns off when the gate signal GN2 is at low level.

  The gate of the transistor N3 is connected to the output end of the inverter INV (= corresponding to the output end of the gate signal GN3). Therefore, the transistor N3 turns on when the gate signal GN3 is at high level, and turns off when the gate signal GN3 is at low level.

  The negative logical sum operator NOR generates a negative logical sum operation signal of the mode signals M2 and M3 and outputs it as a gate signal GN2. Therefore, the gate signal GN2 is at low level when at least one of the mode signals M2 and M3 is at high level, and is at high level when both of the mode signals M2 and M3 are at low level.

  The inverter INV generates a logic inversion signal of the mode signal M3 and outputs it as a gate signal GN3. Therefore, the gate signal GN3 becomes low level when the mode signal M3 is high level, and becomes high level when the mode signal M3 is low level.

  In the gain adjustment unit 113 configured as described above, when the power supply IC 100 is in the normal mode (MODE1), M2 = M3 = L and GN2 = GN3 = H, so N2 = N3 = ON. Accordingly, the gain α is “1/4 (= R / (3R + R))”.

  On the other hand, when the power supply IC 100 is in the light load mode (MODE 2), M2 = H and M3 = L, GN2 = L, and GN3 = H, so N2 = OFF and N3 = ON. Therefore, the gain α is “1/3 (= (R + 0.5R) / (3R + R + 0.5R))”.

  When the power supply IC 100 is in the no-load mode (MODE 3), M2 = L and M3 = H, and GN2 = GN3 = L, so N2 = N3 = OFF. Therefore, the gain α is “1/2 (= (R + 0.5R + 1.5R) / (3R + R + 0.5R + 1.5R))”.

  From the following equation (1), it is understood that the peak current value of the primary current Ip is also switched by switching the gain α.

  Ip = Vcs / Rs = α × Vfb / Rs (1)

  That is, in the light load mode (MODE 2), the peak current value of the primary current Ip is increased by 1.33 times as compared to the normal mode (MODE 1, α = 1/4) by switching to α = 1/3. It is possible to improve the efficiency at light load.

  Further, in the no-load mode (MODE 3), the peak current value of the primary current Ip can be doubled as compared with the normal mode (MODE 1, α = 1/4) by switching to α = 1/2. Therefore, it becomes possible to improve the efficiency at no load.

<Peak current switching>
In the above, the configuration has been described by way of example in which the peak current value of the primary current Ip is switched for each operation mode of the power supply IC 100. However, peak current switching (gain adjustment) needs to be implemented in combination with operation mode switching of the power Instead, by raising the peak current value of the primary current Ip at the time of light load detection, it is possible to realize high efficiency at light load (standby) time.

  Note that, as a method of light load detection, for example, when the feedback voltage Vfb falls below the threshold voltage Vth5 and the burst detection signal S5 rises to a high level and burst control of the transistor N1 by the controller 110 is started, light load The peak current value of the primary current Ip may be increased by detecting this.

  Also, for example, after the burst control of the transistor N1 by the controller 110 is started, when the burst stop period of the transistor N1 (= the period when the feedback voltage Vfb is lower than the threshold voltage Vth5) becomes longer than a predetermined value, The light load may be detected to raise the peak current value of the primary current Ip.

  Also, for example, it is possible to raise the peak current value of the primary current Ip by detecting that the peak voltage value of the sense voltage Vcs has decreased or that the on period Ton of the transistor N1 has become short.

  On the other hand, as described above, the peak current value of the primary current Ip may be increased by adjusting the gain α (= voltage division ratio) of the feedback voltage Vfb as a method of switching the peak current.

<Package layout>
FIG. 13 is a view (XZ plan view) showing an example of the package layout. In the power supply IC 100 of this figure, the first chip 100a and the second chip 100b are mounted on the island 100c.

  In the first chip 100a, circuit blocks (for example, a starter 109 that receives an input of the high voltage VH and the like) required to have a high breakdown voltage are integrated. The first chip 100a is connected to the external terminal T8 via the wires W1 and W2. The first chip 100a is connected to the second chip 100b through the wires W3 to W6.

  Circuit blocks (101 to 108 and 110 to 119) other than the above are integrated in the second chip 100b. The second chip 100b is connected to the external terminals T1 to T6 through the wires W7 to W12, respectively.

  In the package layout of this figure, the first chip 100a is arranged closer to the second side (side closer to the 5th pin to the 7th pin) on the island 100c, and the second chip 100b is closer to the first side It is arranged on the side close to 1 pin to 4 pins). Adopting such a package layout makes it possible to lay the wires W1 to W12 as short as possible.

  Next, the reason why the power supply IC 100 does not have a one-chip configuration but a two-chip configuration will be described. If a circuit block requiring high withstand voltage and a circuit block other than the above are formed on a single chip, it is necessary to provide a buffer region between the high withstand voltage process region and the low withstand voltage process region. Therefore, since the chip size becomes very large, a significant cost increase is caused.

  On the other hand, if the power supply IC 100 has a two-chip configuration, there is no need to provide a buffer region in any of the first chip 100a and the second chip 100b, and therefore the chip size can be reduced, resulting in cost reduction. It is possible to Further, since the first chip 100a and the second chip 100b are separated, it is very advantageous in terms of withstand voltage.

<Summary>
The following generally describes the various embodiments disclosed herein.

  The power supply control device disclosed in the present specification is a control main body of the isolated switching power supply, and comprises: a first output detection signal according to a DC output voltage to a load; A second output detection signal corresponding to the difference value from the target value is monitored, and the controller is configured to switch a plurality of operation modes having different power consumptions according to both monitoring results (first configuration).

  The power supply control device having the first configuration includes, as the plurality of operation modes, a normal mode and at least one power saving mode, and the controller is configured to execute the first output detection signal according to the monitoring result. Configuration switching between the normal mode and the power saving mode or between the plurality of power saving modes, and returning to the normal mode according to the monitoring result of the second output detection signal Configuration).

  Further, in the power supply control device having the second configuration, the controller determines whether or not to perform burst control of the output switch according to the monitoring result of the second output detection signal (third configuration) You should

  The power supply control device having the third configuration further includes a peak current switching unit that switches the peak current value of the primary current flowing through the output switch in each of the plurality of operation modes (fourth configuration). Good.

  Further, in the power supply control device having the fourth configuration, as the power saving mode, a light load mode in which current consumption is reduced more than the normal mode and the peak current value at the time of burst release is increased; And a no-load mode in which the time is controlled to be a predetermined value or more, and the current consumption at the burst stop is reduced more than the light load mode and the peak current value at the burst release is further increased. The configuration (fifth configuration) is preferable.

  Further, the isolated switching power supply disclosed in the present specification includes a power supply control device having any of the first to fifth configurations, and a switching output stage controlled by the power supply control device. (Sixth configuration).

  In the isolated switching power supply having the sixth configuration, the switching output stage is a DC input supplied to the primary circuit system while electrically insulating the primary circuit system and the secondary circuit system using a transformer. It is preferable that the DC output voltage is generated from a voltage and functions as a component of a DC / DC conversion unit to be supplied to the load of the secondary circuit system (a seventh configuration).

  Further, it is preferable that the isolated switching power supply having the seventh configuration has a configuration (eighth configuration) in which variable control of the DC output voltage is performed in the secondary circuit system.

  Moreover, it is preferable that the isolated switching power supply having the eighth configuration further has a configuration (ninth configuration) further including a rectifying unit that generates the DC input voltage from an AC input voltage.

  Further, an electronic device disclosed in the present specification includes: an isolated switching power supply having any one of the sixth to ninth configurations; and a load that operates by receiving power supply from the isolated switching power supply. It is set as the structure (10th structure) which it has.

  Further, the power supply control device disclosed in the present specification is a control main body of the isolated switching power supply, and is a peak current switching unit that raises the peak current value of the primary current flowing to the output switch when light load is detected. And an eleventh configuration.

  The on-duty control unit controls the on-duty of the output switch based on an output detection signal according to a difference value between a DC output voltage to a load and its target value. The peak current switching unit may be configured (12th configuration) to raise the peak current value by adjusting the gain of the output detection signal at the time of light load detection.

  Preferably, in the power supply control device having the twelfth configuration, the output detection signal is a voltage signal, and the gain is a voltage division ratio (a thirteenth configuration).

  The power supply control device having the twelfth or thirteenth configuration further includes a controller for determining whether or not to perform burst control of the output switch according to the monitoring result of the output detection signal (fourteenth configuration). Configuration).

  Further, in the power supply control device having the fourteenth configuration, the peak current switching unit may be configured to increase the peak current value when the controller performs burst control of the output switch (a fifteenth configuration). .

  Further, in the power supply control device having the fourteenth or fifteenth configuration, the peak current switching unit increases the peak current value when the burst stop period of the output switch becomes longer than a predetermined value. 16)).

  Further, the isolated switching power supply disclosed in the present specification includes a power supply control device having any of the above-described eleventh to sixteenth configurations, and a switching output stage controlled by the power supply control device. (The 17th configuration).

  In the insulated switching power supply having the seventeenth configuration, the switching output stage is a direct current supplied to the primary circuit system while electrically insulating the primary circuit system and the secondary circuit system using a transformer. The configuration may be such that the DC output voltage is generated from an input voltage and functions as a component of a DC / DC conversion unit to be supplied to the load of the secondary circuit system (18th configuration).

  The insulation type switching power supply having the eighteenth configuration preferably has a configuration (a nineteenth configuration) further including a rectifying unit that generates the DC input voltage from an AC input voltage.

  Further, an electronic device disclosed in the present specification includes: an isolated switching power supply having any of the seventeenth to nineteenth configurations; and a load that operates by receiving power supply from the isolated switching power supply. It is set as the structure (20th structure) which it has.

<Other Modifications>
In addition to the embodiments described above, various technical features disclosed in the present specification can be modified in various ways without departing from the scope of the technical creation. That is, the above embodiment should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is shown by the claims rather than the description of the above embodiment. It is to be understood that the present invention includes all modifications that fall within the meaning and scope equivalent to the claims.

  The invention disclosed in the present specification can be used for an insulated switching power supply used in all fields (home appliance field, automobile field, industrial machine field, etc.).

1 Isolated switching power supply 1p Primary circuit system (GND1 system)
1s Secondary circuit system (GND2 system)
DESCRIPTION OF SYMBOLS 2 load 10 rectification part 11 filter 12 diode bridge 13, 14 capacitor 20 DC / DC conversion part 100 power supply IC (power-supply control apparatus)
100a first chip 100b second chip 100c island 101 to 108 comparator 109 starter 110 controller 111 RS flip flop 112 driver 113 gain adjustment unit (peak current switching unit)
114 slope compensation unit 115 addition unit 116 oscillator 117 maximum duty setting unit 118 resistance 119 P channel type MOS field effect transistor a edge detection unit a1 inverter a2 to a5 D flip flop b first timer unit b1 to b4 timer b5, b6 RS flip flop B7 to b10 inverter c second timer unit c1 timer d operation mode switching unit d1 to d3 D flip flop d4 up / down counter e burst control unit e1 one shot pulse generation unit e2 and e3 timer e4 logical sum calculator PW commercial AC power supply X electronic equipment TR transformer L1 primary winding L2 secondary winding L3 auxiliary winding R1 to R12 resistance C1 to C4 capacitor D1 to D4 diode N1 to N3 N channel type MOS field effect transistor LED emission Diode PT phototransistor REG shunt regulator NOR NOR calculator INV Inverter T1~T8 external terminal W1~W12 wire

Claims (20)

A power supply control device serving as a control main body of an isolated switching power supply,
The first output detection signal according to the DC output voltage to the load and the second output detection signal according to the difference value between the DC output voltage and the target value thereof are monitored, and the power consumption is What is claimed is: 1. A power control apparatus comprising: a controller that switches between different operation modes. The plurality of operation modes include a normal mode and at least one power saving mode,
The controller performs operation mode switching between the normal mode and the power saving mode or between the plurality of power saving modes according to the monitoring result of the first output detection signal, and the second output detection signal The power supply control device according to claim 1, wherein return to the normal mode is performed according to a monitoring result.   The power supply control device according to claim 2, wherein the controller determines whether or not burst control of the output switch is to be performed according to a monitoring result of the second output detection signal.   The power supply control device according to claim 3, further comprising a peak current switching unit that switches a peak current value of the primary current flowing through the output switch for each of the plurality of operation modes. As the power saving mode,
A light load mode in which current consumption is reduced more than the normal mode and the peak current value at the time of burst release is increased;
No-load mode in which the burst stop time is controlled to be equal to or more than a predetermined value, and the current consumption at the burst stop is reduced more than the light load mode and the peak current value at the burst release is further increased;
The power supply control device according to claim 4, comprising: The power supply control device according to any one of claims 1 to 5.
A switching output stage controlled by the power supply control device;
An isolated switching power supply characterized by having:   The switching output stage electrically isolates the primary circuit system and the secondary circuit system using a transformer, and generates the DC output voltage from the DC input voltage supplied to the primary circuit system to generate the secondary circuit. 7. The isolated switching power supply according to claim 6, which functions as a component of a DC / DC conversion unit that supplies the load of the system.   The isolated switching power supply according to claim 7, wherein variable control of the DC output voltage is performed in the secondary circuit system.   The isolated switching power supply according to claim 8, further comprising a rectifying unit that generates the DC input voltage from an AC input voltage. The isolated switching power supply according to any one of claims 6 to 9.
A load operated by receiving power supply from the isolated switching power supply;
Electronic equipment characterized by having. A power supply control device serving as a control main body of an isolated switching power supply,
What is claimed is: 1. A power control apparatus comprising: a peak current switching unit for raising a peak current value of a primary current flowing through an output switch at the time of light load detection. The on-duty controller further controls an on-duty of the output switch based on an output detection signal corresponding to a difference between a DC output voltage to a load and a target value thereof.
The power supply control device according to claim 11, wherein the peak current switching unit raises the peak current value by adjusting a gain of the output detection signal at the time of light load detection.   The power supply control device according to claim 12, wherein the output detection signal is a voltage signal, and the gain is a voltage division ratio.   The power supply control device according to claim 12 or 13, further comprising a controller that determines whether or not to perform burst control of the output switch according to a monitoring result of the output detection signal.   The power supply control device according to claim 14, wherein the peak current switching unit raises the peak current value when the controller performs burst control of the output switch.   The power supply control device according to claim 14 or 15, wherein the peak current switching unit raises the peak current value when the burst stop period of the output switch becomes longer than a predetermined value. A power control device according to any one of claims 11 to 16;
A switching output stage controlled by the power supply control device;
An isolated switching power supply characterized by having:   The switching output stage electrically isolates the primary circuit system and the secondary circuit system using a transformer, and generates the DC output voltage from the DC input voltage supplied to the primary circuit system to generate the secondary circuit. The isolated switching power supply according to claim 17, which functions as a component of a DC / DC conversion unit that supplies the load of the system.   The isolated switching power supply according to claim 18, further comprising a rectifying unit that generates the DC input voltage from an AC input voltage. The isolated switching power supply according to any one of claims 17 to 19.
A load operated by receiving power supply from the isolated switching power supply;
Electronic equipment characterized by having.

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