JP2019121704A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform positioning with high accuracy when a semiconductor element is joined to a mounting substrate face-down. A semiconductor device disclosed in the present specification is a semiconductor device in which a SiC element is bonded to the surface of a mounting substrate. The mounting board includes a first electrode provided on the surface and a first alignment mark provided on the surface. The SiC element is provided on the lower surface, and the second electrode bonded to the first electrode, the third electrode provided on the upper surface, and the second electrode and the third electrode in the top view of the SiC element are provided. It includes a specific area that is not arranged and a second alignment mark that is arranged in the specific area. In the top view of the semiconductor device, the first alignment mark is located in a specific region. [Selection diagram] Fig. 1

Description

  The technology disclosed herein relates to a semiconductor device.

  Patent Document 1 discloses a power module in which vertical semiconductor elements having electrodes disposed on the upper and lower surfaces are mounted on a mounting substrate. In the power module, the lower surface electrode of the semiconductor element and the surface electrode of the mounting substrate are joined face-down.

JP, 2016-178334, A

  The positioning between the lower surface electrode of the semiconductor element and the surface electrode of the mounting substrate needs to be performed from the upper surface side of the semiconductor element, so positioning is difficult by visual observation. Therefore, for example, when the positioning is performed using the outer shape of the semiconductor element, the processing accuracy of the outer shape of the semiconductor element determines the positioning accuracy. The present specification provides a technique capable of performing positioning accurately when bonding a semiconductor element to a mounting substrate face down.

  The semiconductor device disclosed in this specification is a semiconductor device in which a silicon carbide (SiC) element is bonded to the surface of a mounting substrate. The mounting substrate includes a first electrode provided on the surface and a first alignment mark provided on the surface. The SiC element is provided on the lower surface, and the second electrode joined to the first electrode, the third electrode provided on the upper surface, and the second electrode and the third electrode in a top view of the SiC element It has a specific area which is not arranged and a second alignment mark which is arranged in the specific area. In the top view of the semiconductor device, the first alignment mark is located within the specific region.

  The SiC substrate is transparent. Further, the second electrode and the third electrode are not disposed in the specific region. Therefore, in the specific region, the first and second alignment marks can be visually observed from the upper surface side of the SiC element through the transparent SiC substrate. Positioning of the second electrode on the lower surface of the SiC element and the first electrode on the surface of the mounting substrate can be visually performed using the first and second alignment marks. Positioning accuracy can be enhanced as compared to the case where positioning is performed using the outer shape of the SiC element.

FIG. 1 is a view showing a semiconductor device according to a first embodiment. It is a top view of a mounting substrate. It is the figure which looked at the upper surface side of the undersurface side of a SiC element. It is the figure which looked at the upper surface side of the SiC element top view. FIG. 7 is a view showing a semiconductor device according to a second embodiment. It is the figure which looked at the upper surface side of the undersurface side of a SiC middle board. It is the figure which looked at the upper surface side of the SiC intermediate substrate top view. It is an enlarged view of the mark which appears in specific field R1a.

  One embodiment of the present technology is a semiconductor device in which a SiC intermediate substrate and a SiC element are stacked on the surface of a mounting substrate. The mounting substrate may include a first electrode provided on the surface and a first alignment mark provided on the surface. The SiC intermediate substrate is provided on the lower surface, and the lower surface electrode in contact with the first electrode, the upper surface electrode provided on the upper surface, and the upper surface electrode and the lower surface electrode in top view of the SiC intermediate substrate An intermediate substrate specific region that is not present and an intermediate alignment mark that is disposed in the intermediate substrate specific region may be provided. The SiC element is provided on the lower surface, and the second electrode in contact with the upper surface electrode, the third electrode provided on the upper surface, and the second electrode and the third electrode in top view of the SiC element It may have a SiC element specific area which is not formed and a second alignment mark arranged in the SiC element specific area. In a top view of the semiconductor device, the first alignment mark and the intermediate alignment mark may be located in the SiC element specific region. Thereby, in the SiC element specific region, the first, middle and second alignment marks can be visually observed from the upper surface side of the SiC element through the transparent SiC substrate. It is possible to visually position the SiC element, the SiC intermediate substrate, and the mounting substrate using the first, intermediate and second alignment marks. Positioning accuracy can be enhanced.

  In one embodiment of the present technology, the specific region may be disposed near the outer periphery of the SiC element. An active region is present at the center of the SiC device. Since the specific region is disposed in the vicinity of the outer periphery of the SiC element, these active regions are not affected.

  In one embodiment of the present technology, the SiC element may have a rectangular shape in top view. The specific region may be disposed in the vicinity of the facing corner of the SiC element. As a result, the specific region can be arranged on the diagonal of the rectangular shape, and the distance between the alignment marks can be maximized. It is possible to improve the alignment accuracy.

  FIG. 1 shows a semiconductor device 1 according to a first embodiment. FIG. 1A is a top view. FIG. 1 (B) is a cross-sectional view taken along the line B-B in FIG. 1 (A). The semiconductor device 1 has a structure in which the SiC element 20 is bonded to the surface of the mounting substrate 10. The SiC element 20 has a rectangular shape in top view. In the first embodiment, the case where the SiC element 20 is a vertical MOSFET will be described.

  FIG. 2 shows a top view of the mounting substrate 10 with the SiC element 20 removed. On the surface of the mounting substrate 10, signal electrodes 11a to 11e, power supply electrodes 12, and first alignment marks 13a and 13b are provided. The signal electrodes 11a to 11e are electrodes used for input / output of gate control signals and signals for various sensors. The area of each of the signal electrodes 11 a to 11 e is smaller than the area of the power supply electrode 12. The first alignment marks 13a and 13b, and the signal electrodes 11a to 11e and the power supply electrode 12 are made of the same material in the same process. Therefore, the relative positions of the first alignment marks 13a and 13b and the signal electrodes 11a to 11e are always constant. The first alignment marks and the signal electrodes 11a to 11e may be formed by a known printed wiring technology.

  FIG. 3 shows a top view of the lower surface side of the SiC element 20. The lower surface of the SiC element 20 is a surface to be bonded to the surface of the mounting substrate 10. On the surface of the lower surface of the SiC element 20, signal electrodes 21a to 21e, a source electrode 22, and second alignment marks 23a and 23b are provided. Each of the signal electrodes 21 a to 21 e of the SiC element 20 is bonded to each of the signal electrodes 11 a to 11 e of the mounting substrate 10. Further, the source electrode 22 of the SiC element 20 is joined to the power supply electrode 12 of the mounting substrate 10.

  The second alignment marks 23a and 23b, the signal electrodes 21a to 21e, and the source electrode 22 are made of the same material in the same process. Therefore, the relative positions of the second alignment marks 23a and 23b and the signal electrodes 21a to 21e are always constant. The second alignment marks and the signal electrodes 21a to 21e may be formed by a known lithography technique or etching technique.

  As described above, the first alignment marks 13a and 13b are marks indicating the positions of the signal electrodes 11a to 11e. The second alignment marks 23a and 23b are marks indicating the positions of the signal electrodes 21a to 21e. Therefore, by aligning the first alignment marks 13a and 13b with the second alignment marks 23a and 23b, it is possible to align the signal electrodes 11a to 11e with the signal electrodes 21a to 21e. .

  The figure which looked at the upper surface side of the SiC element 20 in the upper surface in FIG. 4 is shown. A drain electrode 23 is provided on the surface of the upper surface of the SiC element 20. As shown in FIG. 4, in the top view of the SiC element 20, specific regions R1a and R1b are provided. The specific regions R1a and R1b are regions in which none of the signal electrodes 21a to 21e, the source electrode 22, and the drain electrode 23 are disposed. The SiC element 20 is transparent. Therefore, the specific regions R1a and R1b are transparent regions. In addition, second alignment marks 23a and 23b are disposed in each of the specific regions R1a and R1b. Therefore, as shown in the top view of semiconductor device 1 of FIG. 1A, in a state where SiC element 20 is bonded to the surface of mounting substrate 10, second alignment mark 23a and first alignment mark 13a are provided in specific region R1a. Can be observed visually. Similarly, in the specific region R1b, the second alignment mark 23b and the first alignment mark 13b can be visually observed.

  The specific regions R1a and R1b are disposed near the outer periphery of the SiC element 20. Here, the area in the vicinity of the outer periphery is an area in which the distance to the contour of the SiC element 20 is closer than the distance to the center point of the SiC element 20. At the central portion of the SiC element 20, an active region that exhibits various functions such as a switching function is present. However, since the specific regions R1a and R1b are disposed in the vicinity of the outer periphery of the SiC element, they do not affect these active regions.

  Further, as the distance between alignment marks is larger, the alignment accuracy can be made higher. The specific regions R1a and R1b of the first embodiment are arranged in the vicinity of opposing corner portions of the rectangular SiC device 20. As a result, the specific regions R1a and R1b can be arranged diagonally, so the distance between the alignment marks 23a and 23b can be made the longest. It is possible to improve the alignment accuracy.

(effect)
As a comparative example, a bonding step of the mounting substrate and the SiC element in the case where the specific regions R1a and R1b of Example 1 are not provided will be described. The alignment between the lower surface electrode of the SiC element and the front surface electrode of the mounting substrate is difficult by visual observation, and thus positioning is performed using, for example, the outer shape of the SiC element. In this case, the processing accuracy of the outer shape of the SiC element determines the positioning accuracy. The processing of the outer shape of the SiC element is performed by mechanical processing such as dicing of a semiconductor chip, so a dimensional tolerance of, for example, about ± 0.1 mm exists, and the processing accuracy is low. Therefore, it has been necessary to increase the inter-electrode distances D1 to D4 of the signal electrodes 11a to 11e shown in FIG. 2 in consideration of the dimensional tolerance of the outer shape of the SiC element.

  On the other hand, in the semiconductor device 1 of the first embodiment, using the first and second alignment marks, positioning of the signal electrodes 21a to 21e on the lower surface of the SiC element 20 and the signal electrodes 11a to 11e on the surface of the mounting substrate 10 Can be performed visually. The first and second alignment marks can be formed by well-known printed wiring technology, lithography technology or etching technology as described above, and the dimensional tolerance of these technologies is machined to form the device outline. Less than dimensional tolerance. Therefore, compared with the case where the outline of a SiC element is used, the accuracy of alignment can be raised. Since the inter-electrode distances D1 to D4 of the signal electrodes 11a to 11e can be reduced, the size of the SiC element 20 can be reduced.

  FIG. 5 shows a semiconductor device 100 according to a second embodiment. FIG. 5A is a top view. FIG. 5 (B) is a cross-sectional view taken along the line B-B in FIG. 5 (A). In FIG. 5, the same structure as that of the semiconductor device 1 of the first embodiment is denoted by the same reference numeral, and the description is omitted. The semiconductor device 100 has a structure in which the SiC intermediate substrate 110 and the SiC element 20 are stacked on the surface of the mounting substrate 10. Further, FIG. 8 shows an enlarged view of the first alignment mark 13a, the intermediate alignment mark 123a and the second alignment mark 23a appearing in the specific region R1a of FIG. 5 (A).

  FIG. 6 shows a top view of the lower surface side of the SiC intermediate substrate 110. The lower surface of the SiC intermediate substrate 110 is a surface to be bonded to the surface of the mounting substrate 10. On the surface of the lower surface of the SiC intermediate substrate 110, a power supply electrode 112 and intermediate alignment marks 123a and 123b are provided. The power supply electrode 112 is joined to the power supply electrode 12 of the mounting substrate 10.

  FIG. 7 shows a top view of the upper surface side of the SiC intermediate substrate 110. A power supply electrode 111 is provided on the surface of the upper surface of the SiC intermediate substrate 110. As shown in FIG. 7, specific regions R2a and R2b are provided in the top view of the SiC intermediate substrate 110. The specific regions R2a and R2b are transparent regions in which neither the power supply electrode 111 nor the power supply electrode 112 is disposed. Therefore, as shown in FIG. 8, in the specific region R1a, the second alignment mark 23a, the intermediate alignment mark 123a and the first alignment mark 13a can be visually observed in the top view of the SiC intermediate substrate 110. Similarly, in the specific region R1b, the second alignment mark 23b, the intermediate alignment mark 123b, and the first alignment mark 13b can be visually observed.

  The function of the SiC intermediate substrate 110 will be described. The power supply electrode 111 and the power supply electrode 112 are electrically connected. Conduction of both electrodes may be performed by a wire (not shown) penetrating the SiC intermediate substrate 110, or may be performed by making the SiC intermediate substrate 110 a conductor by adding an impurity to the SiC intermediate substrate 110. Good. Further, as shown in the region R101 of FIG. 6 and the region R102 of FIG. 7, the SiC intermediate substrate 110 is not present in the region where the signal electrodes 11a to 11e are disposed in the top view of the semiconductor device 100. Therefore, by arranging the SiC intermediate substrate 110 between the mounting substrate 10 and the SiC element 20, the space S1 can be formed as shown in FIG. 5B. That is, the SiC intermediate substrate 110 functions as a spacer. Thus, it becomes possible to connect each of the signal electrodes 11 a to 11 e of the mounting substrate 10 with the signal electrodes 21 a to 21 e of the SiC element 20 by the wire bonding WB.

(effect)
In the case where the specific regions R1a, R1b, R2a, and R2b of Example 2 are not provided, the alignment between the mounting substrate 10 and the SiC intermediate substrate 110 and the alignment between the SiC intermediate substrate 110 and the SiC element 20 are visual It is difficult depending on Therefore, since positioning is performed using the outer shape of the SiC element 20 or the SiC intermediate substrate 110, the positioning accuracy is low. As a result, the fillet shape formed when electrodes are joined using solder or paste may not be uniform, and the reliability and life of the electrode joint may be reduced. On the other hand, in the semiconductor device 100 according to the second embodiment, the first, middle and second alignment marks can be used to visually position the SiC element 20, the SiC intermediate substrate 110, and the mounting substrate 10 between three parties visually. It becomes. Therefore, the alignment accuracy can be enhanced as compared with the alignment using the outer shapes of the mounting substrate 10 and the SiC intermediate substrate 110. The reliability and the life of the electrode junction can be enhanced.

  Although some specific examples have been described above in detail, these are merely examples and do not limit the scope of the claims. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations.

(Modification)
The first alignment marks 13a and 13b may be formed in a separate process from the signal electrodes 11a to 11e and the power supply electrode 12, or may be formed of a material different from these electrode materials. The first alignment marks 13a and 13b are not limited to the lower surface side of the SiC element 20, and may be formed on the upper surface side.

  The technology described in the present specification is applicable to semiconductors of any material as long as the semiconductor device is formed of a transparent semiconductor substrate. Therefore, the semiconductor material is not limited to SiC.

  In the second embodiment, an opaque conductive plate such as a copper plate may be used instead of the SiC intermediate substrate 110. In this case, the alignment may be performed by visually checking the positional relationship between the corner of the conductor plate and the first and second alignment marks. Since the conductor plate is easier to process than the SiC substrate, the processing accuracy can be enhanced compared to the SiC substrate. Therefore, even when using the outer shape of the conductive plate, it is possible to obtain high alignment accuracy.

  In the second embodiment, the SiC intermediate substrate 110 is not limited to one layer. Even when two or more intermediate substrates are inserted, the techniques described herein can be applied.

  The shapes and overlapping forms of the first, middle and second alignment marks in the present specification are an example. Free shapes such as line and space shapes and dot shapes can be used.

  The SiC element 20 is not particularly limited to a MOSFET element, and may be another power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) element.

  The signal electrodes 11a to 11e and the power supply electrode 12 are examples of a first electrode. The signal electrodes 21a to 21e and the source electrode 22 are an example of a second electrode. The drain electrode 23 is an example of a third electrode.

1, 100: semiconductor device 10: mounting substrates 11a to 11e, 21a to 21e: signal electrodes 12: power supply electrodes 13a, 13b: first alignment marks 20: SiC elements 22: source electrodes 23: drain electrodes 23a, 23b : Second alignment mark R1a, R1b: Specific area

Claims (1)

A semiconductor device in which a SiC element is bonded to the surface of a mounting substrate,
The mounting board is
A first electrode provided on the surface,
A first alignment mark provided on the surface,
Equipped with
The SiC device is
A second electrode provided on the lower surface and joined to the first electrode;
A third electrode provided on the upper surface,
A specific region in which the second electrode and the third electrode are not disposed in a top view of the SiC element;
A second alignment mark disposed in the specific area;
Equipped with
The semiconductor device according to claim 1, wherein the first alignment mark is located in the specific region in a top view of the semiconductor device.

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