JP2019121696A - Semiconductor device and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having improved reliability of a transistor. SOLUTION: In the method of manufacturing a semiconductor device, a first gate electrode is formed on a substrate, a gate insulating film is formed on the first gate electrode, and a region overlapping with the first gate electrode is formed on the gate insulating film. A first oxide semiconductor layer containing the oxide semiconductor layer is formed, a source electrode and a drain electrode are formed on the first oxide semiconductor layer, an oxide insulating layer is formed on the source electrode and the drain electrode, and the oxide insulating layer is formed on the oxide insulating layer. A second oxide semiconductor layer is formed by sputtering an oxide semiconductor target in an atmosphere containing oxygen, and oxygen is added to the oxide insulating layer and heat-treated to convert oxygen into the first oxide. This includes removing the second oxide semiconductor layer after diffusing it into the semiconductor layer and performing a heat treatment. [Selection diagram] FIG. 1B

Description

  One embodiment of the present invention relates to a semiconductor device containing an oxide semiconductor, and a method of manufacturing the same.

  Conventionally, in a display device such as a liquid crystal display device or an organic EL display device, a transistor using silicon as a semiconductor layer has been used. In recent years, in display devices, demands for large area, high resolution, high frame rate, and the like have been increasing, and efforts are being made actively to meet these demands.

  Thus, in recent years, development of a transistor using an oxide semiconductor in place of silicon has been promoted. A transistor including an oxide semiconductor is expected to be able to achieve high mobility. In particular, an oxide semiconductor layer of IGZO can be formed in a large area at a relatively low temperature. Therefore, oxide semiconductors are attracting attention as materials meeting the above requirements.

JP, 2016-146478, A Unexamined-Japanese-Patent No. 2016-225651

  However, in the case where the density of defect states in the insulating film in contact with the oxide semiconductor layer is high, deterioration of the characteristics of the transistor is likely to occur. In addition, there is a problem that in-plane variation of characteristics of a transistor using an oxide semiconductor layer is large.

  In view of the above problems, it is an object to provide a semiconductor device in which the reliability of a transistor is improved. Another object is to provide a semiconductor device in which the uniformity of transistor characteristics in a substrate surface is improved.

  In a method of manufacturing a semiconductor device according to an embodiment of the present invention, a first gate electrode is formed on a substrate, a gate insulating film is formed on the first gate electrode, and a first gate electrode is formed on the gate insulating film. The first oxide semiconductor layer including the overlapping region is formed, the source electrode and the drain electrode are formed over the first oxide semiconductor layer, the oxide insulating layer is formed over the source electrode and the drain electrode, and the oxide is formed. The oxide semiconductor target is sputtered in an atmosphere containing oxygen over the insulating layer to form a second oxide semiconductor layer, oxygen is added to the oxide insulating layer, and heat treatment is performed to form oxygen. After the first oxide semiconductor layer is diffused and subjected to heat treatment, the second oxide semiconductor layer is removed.

  A semiconductor device according to an embodiment of the present invention includes a first gate electrode on a substrate, a gate insulating film on the first gate electrode, and an oxide semiconductor layer overlapping the first gate electrode on the gate insulating film. And an oxide insulating layer over the oxide semiconductor layer, and indium is included in a first region whose thickness from the surface of the oxide insulating layer is 50 nm or less.

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view of the manufacturing method of the semiconductor device according to the one embodiment of the present invention. FIG. 7 is a cross-sectional view of the manufacturing method of the semiconductor device according to the one embodiment of the present invention. FIG. 7 is a cross-sectional view of the manufacturing method of the semiconductor device according to the one embodiment of the present invention. FIG. 7 is a cross-sectional view of the manufacturing method of the semiconductor device according to the one embodiment of the present invention. FIG. 7 is a cross-sectional view of the manufacturing method of the semiconductor device according to the one embodiment of the present invention. FIG. 7 is a cross-sectional view of the manufacturing method of the semiconductor device according to the embodiment of the present invention. FIG. 7 is a cross-sectional view of the manufacturing method of the semiconductor device according to the one embodiment of the present invention. FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. It is a top view of a display concerning one embodiment of the present invention. It is a sectional view of a pixel of a display concerning one embodiment of the present invention. It is a sectional view of a pixel of a display concerning one embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on a present Example. It is sectional drawing of the semiconductor device concerning a comparative example. A measurement point of the transistor 510 formed on the substrate 501 is shown. A measurement point of the transistor 610 formed on the substrate 601 is shown. It is a figure explaining the Id-Vg characteristic of the transistor concerning this example. It is a figure explaining the Id-Vg characteristic of the transistor concerning this example. It is a figure explaining the Id-Vg characteristic of the transistor concerning this example. It is a figure explaining the Id-Vg characteristic of the transistor concerning this example. It is a figure explaining the Id-Vg characteristic of the transistor concerning a comparative example. It is a figure explaining the Id-Vg characteristic of the transistor concerning a comparative example. It is a figure explaining the Id-Vg characteristic of the transistor concerning a comparative example. It is a figure explaining the Id-Vg characteristic of the transistor concerning a comparative example. It is a figure explaining the Id-Vg characteristic of the transistor concerning this example. It is a graph which shows the time dependency of the threshold voltage of the transistor which concerns on a present Example. It is a figure explaining the Id-Vg characteristic of the transistor concerning this example. It is a graph which shows the time dependency of the threshold voltage of the transistor which concerns on a present Example. It is a figure explaining the Id-Vg characteristic of the transistor concerning this example. It is a graph which shows the time dependency of the threshold voltage of the transistor which concerns on a present Example. It is a figure explaining the Id-Vg characteristic of the transistor concerning a comparative example. It is a graph which shows the time dependency of the threshold voltage of the transistor concerning a comparative example. It is a figure explaining the Id-Vg characteristic of the transistor concerning a comparative example. It is a graph which shows the time dependency of the threshold voltage of the transistor concerning a comparative example. It is a figure explaining the Id-Vg characteristic of the transistor concerning a comparative example. It is a graph which shows the time dependency of the threshold voltage of the transistor concerning a comparative example.

First Embodiment
In this embodiment, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1A to 2H. In the present embodiment, the structure of the bottom gate type transistor will be described.

<Structure of Semiconductor Device>
FIG. 1A is a plan view of the semiconductor device 100 according to the present embodiment, and FIG. 1B is a cross-sectional view taken along the line A1-A2 of FIG. 1A. The semiconductor device 100 includes a substrate 101, a gate electrode 111 over the substrate 101, a gate insulating film 112 over the gate electrode 111, an oxide semiconductor layer 113 overlapping with the gate electrode 111 over the gate insulating film 112, an oxide The source and drain electrodes 114 and 115 and the oxide insulating layer 116 over the source and drain electrodes 114 and 115 are provided over the semiconductor layer 113. Further, the gate electrode 111, the gate insulating film 112, the oxide semiconductor layer 113, and the source and drain electrodes 114 and 115 form a transistor 110.

  As the substrate 101, a glass substrate, a quartz substrate, a flexible substrate (polyimide, polyethylene terephthalate, polyethylene naphthalate, triacetyl cellulose, cyclic olefin copolymer, cycloolefin polymer, or other flexible resin substrate) can be used. . By using a flexible substrate, the semiconductor device 100 can be bent.

  As the gate electrode 111, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), zinc (Zn), molybdenum (Mo), copper (Cu), indium (In) , Tin (Sn), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), bismuth (Bi) and the like can be used. Also, alloys of these metals may be used. In addition, conductive oxides such as ITO (indium tin oxide), IGO (indium gallium oxide), IZO (indium zinc oxide), GZO (zinc oxide in which gallium is added as a dopant) may be used. . In addition, these films may be stacked.

When a flexible substrate is used as the substrate 101, an undercoat layer (not shown) is preferably provided on the substrate 101. This film has a function of preventing moisture and hydrogen contained in the substrate 101 from diffusing into the oxide semiconductor layer 113 and the like. The undercoat layer is made of silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon nitride oxide (SiN _x O _y ), aluminum nitride (AlN _x ), aluminum nitride oxide (AlN _x O _y ), aluminum oxide (AlO) _x), can be used such as aluminum oxynitride _{(AlO x N y) (x} , y are arbitrary integers).

As the gate insulating film 112, silicon nitride (SiN _x ), silicon nitride oxide (SiN _x O _y ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), aluminum nitride (AlN _x ), aluminum nitride oxide (AlN _x O _y ), aluminum oxide (AlO _x ), aluminum oxynitride (AlO _x N _y ), and the like can be used (x and y are arbitrary integers). The gate insulating film 112 can be provided with a single layer structure or a stacked structure using any of the above materials. Note that the insulating layer in contact with the oxide semiconductor layer 113 is preferably an insulating layer containing oxygen, such as a silicon oxide film.

  The oxide semiconductor layer 113 can contain a Group 13 element such as indium or gallium. It may contain a plurality of different Group 13 elements, or it may be a compound of indium and gallium (IGO). The oxide semiconductor layer 113 may further contain a Group 12 element, and examples thereof include a compound (IGZO) containing indium, gallium, and zinc. The oxide semiconductor layer 113 can contain other elements, and may contain tin which is a Group 14 element, titanium, zirconium which is a Group 4 element, or the like.

Specifically, as the oxide semiconductor layer 113, InO _x , ZnO _x , SnO _x , In-Ga-O, In-Zn-O, In-Al-O, In-Sn-O, In-Hf-O, In-Zr-O, In-W-O, In-Y-O, In-Ga-Zn-O, In-Al-Zn-O, In-Sn-Zn-O, In-Hf-Zn-O, In-Ga-Sn-O, In-Al-Sn-O, In-Hf-Sn-O, In-Ga-Al-Zn-O, In-Ga-Hf-Zn-O, In-Sn-Ga- Materials such as Zn-O can be used. The crystallinity of the oxide semiconductor layer 113 is also not limited, and may be single crystal, polycrystal, microcrystalline, or amorphous. The oxide semiconductor layer 113 preferably has few crystal defects such as oxygen vacancies. The oxide semiconductor layer 113 preferably has a low concentration of hydrogen.

For the oxide insulating layer 116, silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), aluminum oxide (AlO _x ), aluminum oxynitride (AlO _x N _y ), or the like can be used (x, y is any integer). The oxide insulating layer 116 is preferably a film which can release oxygen by heat treatment. The oxide insulating layer 116 preferably has a low density of defect states.

  In the semiconductor device 100 according to an embodiment of the present invention, the density of defect states in the oxide insulating layer 116 is reduced. In addition, oxygen vacancies in the oxide semiconductor layer 113 are reduced. Therefore, variation in characteristics of the transistor 110 can be reduced. Thus, the reliability of the semiconductor device including the transistor 110 can be improved.

<Method of Manufacturing Semiconductor Device>
Next, a method of manufacturing the semiconductor device 100 according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2H.

  FIG. 2A is a view for explaining a process of forming the gate electrode 111 and the gate insulating film 112 on the substrate 101.

  The gate electrode 111 is formed by processing a conductive film to a desired shape by patterning after a conductive film is formed over the substrate 101. The conductive film can be formed to have a single-layer structure or a stacked-layer structure by a sputtering method using the above-described material. The thickness of the gate electrode 111 is preferably 100 nm to 500 nm.

  Next, the gate insulating film 112 is formed over the gate electrode 111. The gate insulating film 112 can be formed to have a single-layer structure or a stacked-layer structure by a sputtering method or a plasma CVD method using the above-described material. The thickness of the gate insulating film 112 is preferably 100 nm to 500 nm. Further, as the gate insulating film 112, a material which can release oxygen by heat treatment is preferably used. For example, a silicon oxide film is preferably used as the gate insulating film 112. After the oxide semiconductor layer 113 is provided in contact with the gate insulating film 112, heat treatment is performed, whereby oxygen is released from the gate insulating film 112.

  FIG. 2B is a diagram illustrating a process of forming the oxide semiconductor layer 113. The oxide semiconductor layer 113 is formed by processing an oxide semiconductor film over the gate insulating film 112 and patterning the oxide semiconductor film into a desired shape. The oxide semiconductor film is preferably formed to a thickness of 30 nm to 100 nm by, for example, a sputtering method.

The power source applied to the oxide semiconductor target may be a direct current (DC) or an alternating current power source (AC), and can be determined by the shape, composition, or the like of the oxide semiconductor target. As an oxide semiconductor target, for example, in the case of InGaZnO, In: Ga: Zn: O = 1: 1: 1: 4 (In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2) etc. It can be used. In addition, the composition ratio can be determined in accordance with the purpose such as the characteristics of the transistor.

  As a sputtering gas for forming the oxide semiconductor film, oxygen gas, a mixed gas of oxygen and a rare gas, or a rare gas can be used. The sputtering gas for forming the oxide semiconductor film is preferably a mixed gas atmosphere of oxygen and a rare gas, and more preferably, the oxygen gas flow ratio to the rare gas is 5% or more. When the oxygen gas flow rate ratio is 5% or more, oxygen is easily added to the oxide insulating layer 216, which is preferable.

  Further, heat treatment may be performed on the oxide semiconductor layer 113. The heat treatment may be performed before or after patterning of the oxide semiconductor film. It is preferable to perform the heat treatment before the patterning because the oxide semiconductor layer 113 may have a small volume (shrink) due to the heat treatment. Further, by performing heat treatment on the oxide semiconductor layer 113, the film quality can be improved, such as reduction of the hydrogen concentration of the oxide semiconductor layer 113 and improvement in density.

The heat treatment performed on the oxide semiconductor layer 113 can be performed at atmospheric pressure or low pressure (vacuum) in the presence of nitrogen, dry air, or the air. The heating temperature is 250 ° C. to 500 ° C., preferably 350 ° C. to 450 ° C. The heating time is, for example, 15 minutes or more and 1 hour or less. By heat treatment, oxygen is introduced into oxygen vacancies in the oxide semiconductor layer 113 or oxygen is rearranged, so that the oxide semiconductor layer 113 with few crystal defects and high crystallinity can be obtained. Further, the heat treatment can reduce the concentration of hydrogen in the oxide semiconductor layer 113.

  FIG. 2C is a diagram illustrating a process of forming the source and drain electrodes 114 and 115 over the oxide semiconductor layer 113. The source and drain electrodes 114 and 115 are formed by processing a conductive film to a desired shape by patterning after a conductive film is formed over the oxide semiconductor layer 113. The conductive film can be formed to have a single-layer structure or a stacked-layer structure by a sputtering method using the above-described material. The film thickness of the source and drain electrodes 114 and 115 is preferably 100 nm to 800 nm.

  When the conductive film over the oxide semiconductor layer 113 is processed into a desired shape, a surface of the oxide semiconductor layer 113 may be damaged. The damaged region 121 contains a large amount of oxygen deficiency. The region 121 is a region corresponding to the back channel of the transistor. Further, as shown in FIG. 1A, the oxide semiconductor layer 113 is a region exposed from the source and drain electrodes 114 and 115. When the region 121 contains many oxygen vacancies, the characteristics of the transistor may be degraded.

  Thus, oxygen vacancies are preferably compensated for by supplying oxygen to the region 121 in which the oxide semiconductor layer 113 is damaged. Accordingly, oxygen vacancies contained in the oxide semiconductor layer 113 can be reduced.

  In this embodiment, the oxide insulating layer 116 is formed over the oxide semiconductor layer 113. FIG. 2D is a diagram illustrating a process of forming the oxide insulating layer 116 over the oxide semiconductor layer 113. The oxide insulating layer 116 can be formed to have a single-layer structure or a stacked-layer structure by a plasma CVD method using any of the above-described materials. The thickness of the gate insulating film 112 is preferably 100 nm to 500 nm. Further, as the oxide insulating layer 116, a material capable of releasing oxygen by heat treatment is preferably used. As the oxide insulating layer 116, for example, a silicon oxide film is preferably used. After the oxide insulating layer 116 is provided in contact with the oxide semiconductor layer 113, heat treatment is performed, whereby oxygen is released from the oxide insulating layer 116. The released oxygen can compensate oxygen in the region 121 in which the oxide semiconductor layer 113 is damaged. Accordingly, oxygen vacancies contained in the oxide semiconductor layer 113 can be reduced.

  However, some oxide insulating layers which release oxygen by heat treatment have a high density of defect states. In addition, when oxygen is released to the outside of the oxide insulating layer by heat treatment, the density of defect states in the oxide insulating layer may be further increased. When the density of defect states in the oxide insulating layer is high, the transistor operates, and when voltage stress is applied to the gate insulating film and the oxide insulating layer, electrons are trapped in the defect states. As a result, the trapped electrons may change the threshold voltage of the transistor.

  Therefore, it is necessary to reduce not only the oxygen vacancies included in the oxide semiconductor layer 113 but also the density of defect states in the oxide insulating layer. Therefore, oxygen is added to the oxide insulating layer 116, and a barrier film which prevents oxygen from being released to the outside of the oxide insulating layer 116 by heat treatment is provided over the oxide insulating layer 116. In this embodiment, the oxide semiconductor layer 117 is provided over the oxide insulating layer 116 as a barrier film which prevents oxygen from being released to the outside of the oxide insulating layer 116.

  FIG. 2E is a diagram illustrating a process of forming the oxide semiconductor layer 117 over the oxide insulating layer 116. The oxide semiconductor layer 117 can be formed under the same conditions as the oxide semiconductor layer 113 described in FIG. 2B. The oxide semiconductor layer 117 is preferably formed to have a thickness of 5 nm to 60 nm by AC sputtering or DC sputtering, for example.

  As a sputtering gas for forming the oxide semiconductor layer 117, oxygen gas, a mixed gas of oxygen and a rare gas, or a rare gas can be used. The sputtering gas for forming the oxide semiconductor layer 117 is preferably a mixed gas atmosphere of oxygen and a rare gas, and more preferably, the oxygen gas flow ratio is 5% or more.

  The oxide semiconductor layer 117 is formed by a sputtering method, and oxygen is added to the oxide insulating layer 116. Thus, oxygen contained in the oxide insulating layer 116 can be increased. Further, the density of defect states included in the oxide insulating layer 116 can be reduced.

As the oxide semiconductor layer 117, specifically, InO _x , ZnO _x , SnO _x , In-Ga-O, In-Zn-O, In-Al-O, In-Sn-O, In-Hf-O , In-Zr-O, In-W-O, In-Y-O, In-Ga-Zn-O, In-Al-Zn-O, In-Sn-Zn-O, In-Hf-Zn-O , In-Ga-Sn-O, In-Al-Sn-O, In-Hf-Sn-O, In-Ga-Al-Zn-O, In-Ga-Hf-Zn-O, In-Sn-Ga Materials such as -Zn-O can be used.

The power source applied to the target may be a direct current (DC) or an AC power source (AC), and can be determined by the shape, composition, etc. of the target. As a target, for example, in the case of InGaZnO, use In: Ga: Zn: O = 1: 1: 1: 4 (In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2), etc. Can.

  The material of the oxide semiconductor layer 117 is preferably the same as the material of the oxide semiconductor layer 113 because a manufacturing process can be simplified. For example, in the case where In-Ga-Zn-O is used as the oxide semiconductor layer 113, In-Ga-Zn-O is preferably used as the oxide semiconductor layer 117. As described above, when the material of the oxide semiconductor layer 117 is the same as the material of the oxide semiconductor layer 113, film formation conditions and the like can be made the same without changing the target. Productivity is improved. Note that in one embodiment of the present invention, the material of the oxide semiconductor layer 117 and the material of the oxide semiconductor layer 113 may be different. In one embodiment of the present invention, for example, when In—Ga—Zn—O is used as the oxide semiconductor layer 113, In—Ga—Zn—O is preferably used as the oxide semiconductor layer 117.

The oxide semiconductor layer 117 preferably has a low hydrogen concentration. When hydrogen is mixed in the oxide semiconductor layer 117, carriers are generated, which results in shift of the threshold voltage and deterioration of characteristics of the transistor, which causes reduction in reliability of a semiconductor device using the transistor. Therefore, it is effective to use a film with low hydrogen concentration as the insulating layer in contact with the oxide semiconductor layer 113. In this embodiment, the hydrogen concentration in the oxide semiconductor layer ^{117, 1 × 10 19 atom / cm} 3 or less, preferably 1 × ^{10 18} and the atom / cm ^3.

  In addition, the oxide semiconductor layer 117 preferably contains much oxygen. In other words, the coefficient of the element of the composition formula of the oxide semiconductor layer 117 is preferably a non-stoichiometric coefficient which does not have a simple integer ratio. When the oxide semiconductor layer 117 contains a large amount of oxygen, the barrier function against oxygen of the oxide semiconductor layer 117 is improved.

The carrier concentration of the oxide semiconductor layer 117 is 1 × 10 ¹³ or more and 1 × 10 ²⁰ cm ⁻³ or less, preferably 1 × 10 ¹⁴ or more and 1 × 10 ¹⁶ cm ⁻³ or less.

  The thickness of the oxide semiconductor layer 117 is preferably smaller than the thickness of the oxide semiconductor layer 113. The thickness of the oxide semiconductor layer 117 is preferably larger than that of the region 121 with many oxygen vacancies formed in the oxide semiconductor layer 113. For example, when the thickness of the oxide semiconductor layer 113 is 50 nm, the thickness of the oxide semiconductor layer 117 is preferably 20 nm. Specifically, the thickness of the oxide semiconductor layer 117 is preferably 5 nm or more and 50 nm or less. If the thickness is less than 5 nm, the thickness may be smaller than the thickness of the region 121 where there are many oxygen vacancies, so it is difficult to compensate for the oxygen vacancies sufficiently. Moreover, if it is 50 nm, it is possible to fully compensate the oxygen deficiency of the region 121.

  By thus forming the oxide semiconductor layer 117 over the oxide insulating layer 116, oxygen can be added to the oxide insulating layer 116 at the time of forming the oxide semiconductor layer 117. In addition, after the oxide semiconductor layer 117 is formed, release of oxygen to the outside can be suppressed.

  FIG. 2F illustrates a step of performing heat treatment on the oxide insulating layer 116 and the oxide semiconductor layer 117. The heat treatment can be carried out at atmospheric pressure or low pressure (vacuum) in the presence of nitrogen, dry air or the atmosphere. The temperature of the heat treatment is 300.degree. C. to 400.degree. The heating time is, for example, 15 minutes or more and 1 hour or less.

  By heat treatment, oxygen is released from the oxide insulating layer 116. With the oxide semiconductor layer 117 provided over the oxide insulating layer 116, release of oxygen in the oxide insulating layer 116 can be suppressed. Thus, oxygen is efficiently supplied to the region 121 in which the oxide semiconductor layer 113 is damaged. In addition, oxygen is compensated for in the oxygen deficiency included in the region 121, so that the oxygen deficiency can be reduced.

  Finally, the oxide semiconductor layer 117 is removed, whereby the semiconductor device 100 illustrated in FIG. 1B can be manufactured.

  In forming the oxide semiconductor layer 117 over the oxide insulating layer 116, oxygen can be added to the oxide insulating layer 116. By oxygen added in forming the oxide semiconductor layer 117, the density of defect states included in the oxide insulating layer 116 can be reduced.

  The oxide semiconductor layer 117 can prevent oxygen from being released from the oxide insulating layer 116 to the outside by heat treatment. Accordingly, oxygen can be compensated for in the oxygen vacancies formed in the region 121 of the oxide semiconductor layer 113 when the source or drain electrodes 114 and 115 are formed. Accordingly, oxygen vacancies in the oxide semiconductor layer 113 can be reduced. Thus, variations in the characteristics of the transistor can be suppressed, whereby the reliability of the transistor can be improved.

In the case where the oxide semiconductor layer 117 contains indium, indium contained in the oxide semiconductor layer 117 may be diffused to the oxide insulating layer 116 by heat treatment. In addition, when the oxide semiconductor layer 117 is formed, mixing may occur with the oxide insulating layer 116. Thus, indium is contained in a region where the thickness from the surface of the oxide insulating layer 116 is 50 nm or less. The concentration of indium contained in the region can be measured by secondary ion mass spectrometry (SIMS). The indium contained in the region of the oxide insulating layer 116 is, for example, 1 × 10 ¹⁷ atoms / cm ³ or more and 1 × 10 ¹⁸ atoms / cm ³ . Even if indium is diffused in the oxide insulating layer 116, the amount of indium is small and distant from the channel as described above; therefore, the characteristics of the transistor are not affected. In addition, since indium diffuses uniformly in the oxide insulating layer 116, it functions as a conductive shield. As a result, the influence of the charge-up of the planarizing film and the like becomes less likely.

  Note that also by forming an insulating film such as an aluminum oxide film over the oxide insulating layer 116, release of oxygen from the oxide insulating layer 116 to the outside due to heat treatment can be suppressed. However, the aluminum oxide film is formed by reactive sputtering using an aluminum target and using oxygen as a sputtering gas. Electrons are likely to be charged on the surface of the target by oxidizing the surface of the aluminum target by oxygen of the sputtering gas. As a result, abnormal discharge occurs on the surface of the target to generate many particles. In addition, since the oxygen injected when forming the aluminum oxide film depends only on the sputtering gas, the amount of oxygen implanted in the vicinity of the gas injection port in the sputtering apparatus may be different from the amount of the oxygen implanted, The in-plane uniformity of the amount of oxygen added to the insulating layer 116 is low. Thus, the amount of oxygen supplied to the oxide semiconductor layer 113 also differs in the substrate surface. Therefore, the variation in the characteristics of the transistor becomes large in the substrate surface. Moreover, the control of the etching rate is difficult for the aluminum oxide film.

  An oxide semiconductor target can be used for the oxide semiconductor layer 117 described in this embodiment. As the oxide semiconductor target, an oxide semiconductor target similar to the oxide semiconductor target used when forming the oxide semiconductor layer 113 can be used. Thus, even if oxygen is used as the sputtering gas, the surface state of the oxide semiconductor target is unlikely to change. In addition, since the oxide semiconductor target has conductivity, charging of electrons on the surface of the oxide semiconductor target can be suppressed. Thus, abnormal discharge on the surface of the oxide semiconductor target can be suppressed, and generation of particles can be suppressed. Further, in IGZO, since the conductivity of the target can be controlled, AC sputtering or DC sputtering can be used even in the oxide state, and such a problem does not occur even with a large-area substrate. When the oxide semiconductor layer 117 is formed, the in-plane uniformity of oxygen added to the oxide insulating layer 116 is high. Therefore, the amount of oxygen supplied to the oxide semiconductor layer 113 also has high uniformity in the substrate surface. Therefore, variations in transistor characteristics can be reduced in the surface of the substrate 101. Further, in this embodiment, since the oxide semiconductor layer 117 is removed, it is not necessary to consider control of the etching rate in the subsequent steps.

Second Embodiment
In the present embodiment, a semiconductor device 100A according to an embodiment of the present invention will be described with reference to FIGS. 3A and 3B. In this embodiment, the structure of the dual gate transistor is described. The description of the same structures and processes as those of the semiconductor device according to the first embodiment will be omitted.

<Structure of Semiconductor Device>
FIG. 3A is a plan view of the semiconductor device 100 according to the present embodiment, and FIG. 3B is a cross-sectional view taken along line B1-B2 of FIG. 3A. The semiconductor device 100A includes a substrate 101A, a gate electrode 111A over the substrate 101A, a gate insulating film 112A over the gate electrode 111A, an oxide semiconductor layer 113A overlapping with the gate electrode 111 over the gate insulating film 112A, and an oxide The semiconductor device includes the source and drain electrodes 114A and 115A over the semiconductor layer 113A, and the oxide insulating layer 116A over the source and drain electrodes 114A and 115A. Further, the gate electrode 111A, the gate insulating film 112A, the oxide semiconductor layer 113A, and the source and drain electrodes 114A and 115A form a transistor 110A.

  The semiconductor device 100A illustrated in FIG. 3B is different from the semiconductor device 100 illustrated in FIG. 1 in that a gate electrode 118A overlapping with the oxide semiconductor layer 113A is provided over the oxide insulating layer 116A. The gate electrode 118A functions as a back gate electrode for controlling the threshold voltage of the transistor 110A. By controlling the potential applied to the gate electrode 118A, the threshold voltage of the transistor 110A can be controlled.

<Method of Manufacturing Semiconductor Device>
Next, a method of manufacturing the semiconductor device 100A according to the present embodiment will be described. The semiconductor device 100A performs heat treatment on the oxide insulating layer 116A and the oxide semiconductor layer 117A in accordance with the steps of FIGS. 2A to 2F described in the first embodiment. After that, the oxide semiconductor layer 117A is removed, and a gate electrode 118A overlapping with the oxide semiconductor layer 113A is formed over the oxide insulating layer 116A. The gate electrode 118A is formed by processing a conductive film to a desired shape by patterning after a conductive film is formed over the oxide insulating layer 116A. The conductive film can be formed by a sputtering method using the material described for the gate electrode 111 shown in FIG.

  In order to supply oxygen to the damaged region of the oxide semiconductor layer 113A, the thickness of the oxide insulating layer 116A is preferably large. However, as described in the steps of FIGS. 2A to 2F, oxygen is released from the oxide insulating layer 116 to the outside by forming the oxide semiconductor layer 117 over the oxide insulating layer 116 and performing heat treatment. Can be suppressed. Accordingly, oxygen can be efficiently supplied to the oxide semiconductor layer 113A. Thus, the thickness of the oxide insulating layer 116A can be smaller than in the case where heat treatment is performed without capping with the oxide semiconductor layer 117. Accordingly, the gate electrode 118A is provided over the oxide insulating layer 116A, which facilitates voltage control. In the case where the oxide semiconductor layer 117 is not removed, the amount of oxygen supplied to the oxide semiconductor layer 113A may decrease due to reaction with the gate electrode 118A. These problems can be prevented by heat treatment and removal of the oxide semiconductor layer 117 in advance.

Third Embodiment
In the present embodiment, a semiconductor device 100A according to an embodiment of the present invention will be described with reference to FIGS. 4A to 5B. In the present embodiment, the structure of a channel protective transistor will be described. The description of the same structures and processes as those of the semiconductor device according to the first embodiment will be omitted.

<Structure of Semiconductor Device>
FIG. 4A is a plan view of the semiconductor device 100 according to this embodiment, and FIG. 4B is a cross-sectional view taken along line C1-C2 of FIG. 4A. The semiconductor device 100B includes a substrate 101B, a gate electrode 111B over the substrate 101B, a gate insulating film 112B over the gate electrode 111B, an oxide semiconductor layer 113B overlapping with the gate electrode 111B over the gate insulating film 112B, and an oxide The oxide insulating layer 116B over the semiconductor layer 113B and source and drain electrodes 114B and 115B which are provided over the oxide insulating layer 116B and connected to the oxide semiconductor layer 113B through an opening are provided. In addition, the gate electrode 111B, the gate insulating film 112B, the oxide semiconductor layer 113B, and the source and drain electrodes 114B and 115B form a transistor 110B.

  In the semiconductor device 100B illustrated in FIG. 4B, the oxide insulating layer 116B is provided over the oxide semiconductor layer 113B, the source is provided over the oxide insulating layer 116B, and is connected to the oxide semiconductor layer 113B through an opening. The semiconductor device 100 is different from the semiconductor device 100 shown in FIG.

<Method of Manufacturing Semiconductor Device>
Next, a method of manufacturing the semiconductor device 100B according to the present embodiment will be described with reference to FIGS. 5A and 5B. The semiconductor device 100A forms the oxide semiconductor layer 113B on the gate insulating film 112B in accordance with the steps of FIGS. 2A and 2B described in the first embodiment. FIG. 5A is a diagram illustrating a state after the oxide semiconductor layer 113B is formed over the gate insulating film 112B.

  Next, as illustrated in FIG. 5B, the oxide insulating layer 116B is formed over the oxide semiconductor layer 113B. The formation method of the oxide insulating layer 116B is similar to that of the oxide insulating layer 116 described in FIG. 2D. Next, the oxide semiconductor layer 117B is formed over the oxide insulating layer 116B. The method for forming the oxide semiconductor layer 117B is the same as the method for forming the oxide semiconductor layer 117B described with reference to FIG. 2E. Next, heat treatment is performed on the oxide insulating layer 116B and the oxide semiconductor layer 117B. The conditions of the heat treatment are the same as the conditions of the heat treatment described in FIG. 2F. Next, the oxide semiconductor layer 117B is removed.

  Next, an opening is formed in the oxide insulating layer 116B. Next, source and drain electrodes 114B and 115B which are provided over the oxide insulating layer 116B and connected to the oxide semiconductor layer 113B through the openings are formed. The source and drain electrodes 114B and 115B are formed by forming a conductive film over the oxide insulating layer 116B and patterning it to a desired shape. The conductive film can be formed by a sputtering method using the materials described for the source and drain electrodes 114 and 115 illustrated in FIG.

  As compared with a bottom gate transistor, oxygen vacancies can be reduced because damage to the back channel in the manufacturing process is small. Further, oxygen can be supplied to the oxide semiconductor layer 113B by providing the oxide insulating layer 116B in contact with the oxide semiconductor layer 113B. Thus, variation in the characteristics of the transistor 110B can be suppressed, whereby the reliability of the semiconductor device 100B can be improved.

Fourth Embodiment
In the present embodiment, a display device 200 according to an embodiment of the present invention will be described with reference to FIGS. 6 and 7. The display device 200 is an example of a display device using the semiconductor device 100 according to the first embodiment. However, the semiconductor device 100A and the semiconductor device 100B of the second embodiment and the third embodiment may be used as a transistor used for the display device 200.

<Overview of Display Device 200>
FIG. 6 is a plan view showing an outline of a display device 200 according to an embodiment of the present invention. FIG. 6 shows a simplified circuit diagram of a transistor array substrate in which transistors and wirings are arranged. The transistor array substrate has a plurality of pixels 208 arranged in a matrix of M rows and N columns (M and N are natural numbers). Each pixel 208 is connected to the common wiring 214. Further, a region in which the plurality of pixels 208 are provided is referred to as a display region 202.

  The gate driver circuit 203 is a driver circuit that selects a row to which a data signal corresponding to the gray level of each pixel 208 is supplied. A gate line 211 extending in the first direction D1 is connected to the gate driver circuit 203. The gate line 211 is a driver circuit that supplies a data signal to each pixel 208. A data line 212 extending in the second direction D2 is connected to the data driver circuit 204. The data line 212 is provided corresponding to each pixel 208. The common wiring 214 is a wiring to which a voltage common to the pixels 208 is supplied. The common wiring 214 is commonly connected to each pixel 208 via a common line 213 extending in the first direction D1. The data driver circuit 204 sequentially supplies data signals to the pixels in the row selected by the gate driver circuit 203.

  The gate driver circuit 203 and the data driver circuit 204 are each connected to the driver IC 205 through a wire. The data driver circuit 204 may be provided inside the driver IC 205. The common wiring 214 is also connected to the driver IC 205. The driver IC 205 is connected to the FPC 206 through a terminal. The FPC 206 is provided with an external terminal 207 for connecting to an external device.

<Configuration 1 of Pixel 208>
In the present embodiment, a case where the display device is a top emission type organic EL display device will be described. FIG. 7 is a cross-sectional view of the pixel 208. The pixel 208 at least includes the transistor 110 according to the first embodiment and the light emitting element 330 on the substrate 301.

  In FIG. 7, the undercoat layer 102 is provided between the substrate 101 and the gate electrode 111. With the undercoat layer 102, diffusion of moisture or hydrogen from the substrate 101 into the oxide semiconductor layer 113 or the like can be suppressed.

  An oxide insulating layer 116 is provided over the transistor 110. In addition, a planarization film 318 is provided over the oxide insulating layer 118. As the planarization film 318, polyimide, polyamide, acrylic, epoxy or the like can be used. These materials are characterized in that they can form a film by a solution coating method and have a high planarization effect. In addition, an opening is provided in the oxide insulating layer 116 and the planarization film 318.

  Transparent conductive layers 319 and 321 are provided on the planarization film 318. The transparent conductive layer 319 is connected to the source or drain electrode 115 through the opening. As the transparent conductive layers 319 and 321, for example, an indium oxide based transparent conductive film (for example, ITO) or a zinc oxide based transparent conductive film (for example, IZO, ZnO) can be used. An insulating layer 322 is provided on the transparent conductive layers 319 and 321. As the insulating layer 322, a silicon oxide film or a silicon nitride film can be used.

  The pixel electrode 323 is provided on the insulating layer 322. In the present embodiment, the pixel electrode 323 functions as an anode. For example, in the case of the top emission type, a metal film with high reflectance can be used as the pixel electrode 323. Alternatively, a stacked structure of a metal film and a transparent conductive layer having a high work function, such as an indium oxide based transparent conductive layer (for example, ITO) or a zinc oxide based transparent conductive layer (for example, IZO or ZnO), may be used as the pixel electrode 323. it can. In the case of the bottom emission type, the above-described transparent conductive layer can be used as the pixel electrode 323.

  An insulating layer 324 is provided over the pixel electrode 323. As the insulating layer 324, an organic resin such as polyimide, polyamide, acrylic, epoxy, or siloxane can be used. The insulating layer 324 has an opening in part on the pixel electrode 323. The insulating layer 324 is provided so as to cover an end portion of the pixel electrode 323, and functions as a member for separating the adjacent pixel electrode 323. For this reason, the insulating layer 324 is also generally referred to as "partition wall" or "bank". A part of the pixel electrode 323 exposed from the insulating layer 324 serves as a light emitting region of the light emitting element 330. The opening of the insulating layer 324 is preferably formed so that the inner wall has a tapered shape. Thereby, coverage defects can be reduced at the time of formation of the organic layer to be formed later. The insulating layer 234 may not only cover the end portion of the pixel electrode 323, but also may function as a filling material which fills a concave portion due to the opening of the planarization film 318 and the insulating layer 322.

  An organic layer 325 is provided on the pixel electrode 323. The organic layer 325 includes at least a light emitting layer formed of an organic material and functions as a light emitting portion of the light emitting element 330. The organic layer 325 includes various charge transport layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, in addition to the light emitting layer. The organic layer 325 is provided to cover the light emitting region, that is, to cover the opening of the insulating layer 324 in the light emitting region.

  In the present embodiment, the organic layer 325 includes a light emitting layer that emits light of a desired color. In addition, an organic layer 325 having different light emitting layers is provided on each pixel electrode. Thereby, the display device can display each color of RGB. That is, in the present embodiment, the light emitting layer of the organic layer 325 is discontinuous between the adjacent pixel electrodes 323. In addition, various charge transport layers are continuous between the adjacent pixel electrodes 323. For the organic layer 325, a known structure or a known material can be used, and is not particularly limited. In addition, the organic layer 325 may have a light emitting layer that emits white light, and the display device may display each color of RGB through a color filter. In this case, the organic layer 325 may also be provided on the insulating layer 324.

  A counter electrode 326 is provided over the insulating layer 324 and the organic layer 325. In the present embodiment, the counter electrode 326 functions as a cathode. The display device 200 of this embodiment is a top emission type, and thus a transparent electrode is used as the counter electrode 326. As a thin film which comprises a transparent electrode, a MgAg thin film or a transparent conductive layer (ITO or IZO) is used. The counter electrode 326 is also provided on the insulating layer 324, between the pixels. The counter electrode 326 is electrically connected to the external terminal through the lower conductive layer in the peripheral area near the end of the display area.

  In the present embodiment, the light emitting element 330 is configured by the pixel electrode 323 (anode), the organic layer 325, and the counter electrode 326 (cathode).

  An inorganic insulating layer 331, an organic insulating layer 332, and an inorganic insulating layer 333 are provided over the counter electrode 326. The inorganic insulating layer 331, the organic insulating layer 332, and the inorganic insulating layer 333 function as sealing films for preventing moisture and oxygen from entering the light emitting element 330. By providing the sealing film over the light emitting element 339, entry of moisture or oxygen into the light emitting element 330 can be prevented. Thereby, the reliability of the display device can be improved.

As the inorganic insulating layer 331 and the inorganic insulating layer 333, for example, silicon nitride _{(Si x N} y), silicon oxynitride _{(SiO x N} y), silicon nitride oxide _{(SiN x O} y), aluminum oxide _{(Al x O} y) , Films such as aluminum nitride (Al _x N _y ), aluminum oxynitride (Al _x O _y N _z ), aluminum nitride oxide (Al _x N _y O _z ), etc. can be used (where x, y and z are arbitrary) Integer). As the organic insulating layer 332, an organic resin such as polyimide, acrylic, epoxy, silicone, fluorine, or siloxane can be used.

  A substrate 335 is provided over the inorganic insulating layer 333 with an adhesive 334 interposed therebetween. As the adhesive material 334, for example, an acrylic, rubber, silicone, urethane or other adhesive can be used. The adhesive 334 may contain a hygroscopic substance such as calcium or zeolite. By containing the moisture absorbing substance in the adhesive material 334, even when moisture intrudes into the display device 200, the moisture can be delayed from reaching the light emitting element 330.

  As the substrate 335, a glass substrate, a quartz substrate, a flexible substrate (polyimide, polyethylene terephthalate, polyethylene naphthalate, triacetyl cellulose, cyclic olefin copolymer, cycloolefin polymer, or other flexible resin substrate) can be used. .

  Further, the adhesive 334 may be provided with a spacer in order to secure a gap between the substrate 101 and the substrate 335. Such a spacer may be mixed with the adhesive 334 or may be formed on the substrate 101 by a resin or the like.

  The transistor 110 according to an embodiment of the present invention is used for the pixel 208 of the display device 200. The transistor 110 has suppressed variation in characteristics. Therefore, the reliability of the display device 200 can be improved. In addition, variation in the characteristics of the transistor 110 in the substrate surface is suppressed. This facilitates gradation control of the light emitting element.

Fifth Embodiment
In the present embodiment, a display device according to an embodiment of the present invention will be described with reference to FIGS. 6 and 8. In this embodiment, a case where a liquid crystal element is used as the pixel 208 illustrated in FIG. 6 will be described. In addition, in the pixel 208, an example using the semiconductor device 100 according to the first embodiment will be described, but the semiconductor device 100A and the semiconductor device 100B according to the second embodiment and the third embodiment may be used.

<Configuration 2 of Pixel 208>
In the present embodiment, the case where the display device is a liquid crystal display device will be described. FIG. 8 is a cross-sectional view of the pixel 208. The pixel 208 at least includes the transistor 110 according to the first embodiment and the liquid crystal element 430 on the substrate 301.

  An oxide insulating layer 116 is provided over the transistor 110. In addition, a planarization film 418 is provided over the oxide insulating layer 118. As the planarization film 418, polyimide, polyamide, acrylic, epoxy, or the like can be used. These materials are characterized in that they can form a film by a solution coating method and have a high planarization effect. In addition, an opening is provided in the oxide insulating layer 116 and the planarization film 418.

  A pixel electrode 421 is provided on the planarization film 418. As the pixel electrode 421, for example, an indium oxide based transparent conductive film (for example, ITO) or a zinc oxide based transparent conductive film (for example, IZO, ZnO) can be used. The pixel electrode 421 is connected to the source or drain electrode 115 through the opening. Note that the pixel electrode 421 is separated for each pixel in a plan view, and is provided in a comb shape.

  An insulating layer 422 is provided over the pixel electrode 421. As the insulating layer 422, a silicon oxide film or a silicon nitride film can be used. A common electrode 423 is provided on the insulating layer 422. For the common electrode 423, a material similar to that of the pixel electrode 421 can be used. Further, the common electrode 423 is provided straddling each pixel in a plan view, and an opening is provided in a region overlapping with the transistor 110.

  The substrate 427 is provided with a color filter 426 and a planarization film 425. In addition, a liquid crystal layer 424 is provided between the planarization film 425 and the common electrode 423.

  The transistor 110 according to an embodiment of the present invention is used for the pixel 208 of the display device 200. The transistor 110 has suppressed variation in characteristics. Therefore, the reliability of the display device 200 can be improved. In addition, variation in the characteristics of the transistor 110 in the substrate surface is suppressed.

  In the present embodiment, the semiconductor device according to the present invention is manufactured, and the results of investigation of variations in Id-Vg characteristics of the transistor in the substrate surface will be described.

  First, the semiconductor device 500 manufactured in this embodiment will be described with reference to FIG. 9A.

  As illustrated in FIG. 9A, the semiconductor device 500 includes an oxide semiconductor layer which overlaps with the gate electrode 511, the gate insulating film 512 over the gate electrode 511, and the gate electrode 511 over the substrate 501. 513, the source electrode 514 and the drain electrode 515 over the oxide semiconductor layer 513, and the oxide insulating layer 516 over the source electrode 514 and the drain electrode 515. Further, the gate electrode 511, the gate insulating film 512, the oxide semiconductor layer 513, the source electrode 514, and the drain electrode 515 form a transistor 510.

  A method for manufacturing the semiconductor device 500 shown in FIG. 9A will be described. First, the gate electrode 511 was formed over the substrate 501. As the gate electrode 511, MoW of 200 nm was formed by DC sputtering to perform patterning. Next, the gate insulating film 512 was formed over the gate electrode 511. As the gate insulating film 512, a 150 nm silicon nitride film and a 100 nm silicon oxide film were formed by plasma CVD. Next, the oxide semiconductor layer 513 which overlaps with the gate electrode 511 was formed over the gate insulating film 512. As the oxide semiconductor layer 513, a 75 nm IGZO film was formed over the gate insulating film 512 by an AC sputtering method, and patterning was performed. Next, the source electrode 514 and the drain electrode 515 were formed over the oxide semiconductor layer 513. As the source electrode 514 and the drain electrode 515, 50 nm Ti, 200 nm Al, and 50 nm Ti were deposited by sputtering over the oxide semiconductor layer 513 and patterned. Next, the oxide insulating layer 516 was formed over the source electrode 514 and the drain electrode 515. As the oxide insulating layer 516, a 300-nm-thick silicon oxide film was formed by a plasma CVD method.

  Next, an oxide semiconductor layer was formed over the oxide insulating layer 516. For the oxide semiconductor layer, a 30 nm IGZO film was formed by AC sputtering. Next, heat treatment was performed on the oxide insulating layer 516 and the oxide semiconductor layer. The heat treatment conditions were a dry air atmosphere at 350 ° C. for 30 minutes. Finally, the oxide semiconductor layer was removed. Through the above steps, the semiconductor device 500 including the transistor 510 is formed. A plurality of transistors 510 is formed on the substrate 501.

  Next, a semiconductor device 600 manufactured as a comparative example will be described with reference to FIG. 9B.

  As illustrated in FIG. 9B, in the semiconductor device 600, the gate electrode 611, the gate insulating film 612 over the gate electrode 611, and the oxide semiconductor layer overlapping with the gate electrode 611 over the substrate 601 are provided. 613, a source electrode 614 and a drain electrode 615 over the oxide semiconductor layer 613, and an oxide insulating layer 616 over the source electrode 614 and the drain electrode 615. Further, the gate electrode 611, the gate insulating film 612, the oxide semiconductor layer 613, the source electrode 614, and the drain electrode 615 form a transistor 610.

  A method for manufacturing the semiconductor device 600 shown in FIG. 9B will be described. The semiconductor device 600 includes the substrate of the semiconductor device 500 up to the step of forming the gate electrode 611, the gate insulating film 612, the oxide semiconductor layer 613, the source electrode 614, the drain electrode 615, and the oxide insulating layer 616 over the substrate 601. The gate electrode 511, the gate insulating film 512, the oxide semiconductor layer 513, the source electrode 514, the drain electrode 515, and the oxide insulating layer 516 are formed over the 501 under the same conditions. After that, heat treatment was performed without forming an oxide semiconductor layer. The heat treatment conditions were a dry air atmosphere at 350 ° C. for 30 minutes. Through the above steps, the semiconductor device 600 including the transistor 610 is formed. On the substrate 601, a plurality of transistors 510 are formed.

  Variations in the Id-Vg characteristics of the transistor 510 in the plane of the substrate 501 were investigated. The Id-Vg characteristics were measured for 200 transistors 510 among the plurality of transistors 510 formed over the substrate 501. FIG. 10A shows a portion of the substrate 501 where the Id-Vg characteristics of the transistor 510 were measured. The part shown by x shown in FIG. 10A is the part where the Id-Vg characteristic of the transistor 510 was measured.

  The measurement of the Id-Vg characteristics of the transistor 510 was performed in steps of 0.1 V from -15 V to +15 V as a voltage (Vg) applied to the gate electrode 511 of the transistor 510. The voltage (Vs) applied to the source electrode 514 was 0 V, and the voltages (Vd) applied to the drain electrode 515 were 0.1 V and 10 V. The measurement of Id-Vg characteristics was performed at room temperature.

  Variations in the Id-Vg characteristics of the transistor 610 in the plane of the substrate 601 were examined. The Id-Vg characteristics were measured for 200 transistors 610 among the plurality of transistors 610 formed on the substrate 601. FIG. 10B shows a portion of the substrate 601 where the Id-Vg characteristics of the transistor 610 were measured. The part shown by x shown in FIG. 10B is the part where the Id-Vg characteristic of the transistor 610 was measured.

  The measurement of the Id-Vg characteristics of the transistor 610 was performed under the same conditions as the measurement of the characteristics of the Id-Vg of the transistor 510.

  11A to 11D show the results of the Id-Vg characteristics of the transistor 510 according to this example. FIG. 11A shows the result of the Id-Vg characteristic of the transistor 510 in the region 501a. FIG. 11B shows the result of the Id-Vg characteristic of the transistor 510 in the region 501b. FIG. 11C shows the result of the Id-Vg characteristic of the transistor 510 in the region 501c. FIG. 11D shows the result of the Id-Vg characteristic of the transistor 510 in the region 501d. The average value and standard deviation (3σ) of the threshold voltage distributions of the 200 transistors 510 were Vth = 0.42V ± 0.48V (3σ).

  12A to 12D show the results of the Id-Vg characteristics of the transistor 610 according to the comparative example. FIG. 12A shows the result of the Id-Vg characteristic of the transistor 610 in the region 601a. FIG. 12B shows the result of the Id-Vg characteristic of the transistor 610 in the region 601b. FIG. 12C shows the result of Id-Vg characteristics of the transistor 610 in the region 601c. FIG. 12D shows the result of the Id-Vg characteristic of the transistor 610 in the region 601d. The average value and standard deviation (3σ) of the threshold voltage distributions of the 200 transistors 610 were Vth = 0.35V ± 1.01V (3σ).

Table 1 shows the results of investigation of the average value and the standard deviation (σ) for the threshold voltage Vth of the 200 transistors 510 and 610, the field effect mobility μ _FE , and the subthreshold value S value.

  As shown in FIGS. 12A to 12D, in the transistor 610 according to the comparative example, it is confirmed that the variation in the characteristics of the transistor 610 is large in any of the regions 601a to 601b of the substrate 601. On the other hand, as shown in FIGS. 11A to 11D, in the transistor 510 according to this example, it was confirmed that the variation in the characteristics of the transistor 510 is small in any of the regions 501a to 501b of the substrate 501.

  From the above results, it was shown that in the semiconductor device according to the present invention, the variation in the characteristics of the transistor in the substrate surface is reduced.

  In this example, the semiconductor device according to the present invention is manufactured, and the result of evaluating the reliability of the transistor will be described.

  The semiconductor device 500 according to the present example was manufactured under the same configuration and conditions as the semiconductor device 500 described in the first example. Further, a semiconductor device 600 according to the comparative example was manufactured under the same configuration and conditions as the semiconductor device 600 shown in the first embodiment.

  Next, a bias-heat stress test (hereinafter, referred to as a GBT test) was performed on the manufactured semiconductor device 500 and the semiconductor device 600. In the GBT test in this example, the gate voltage (Vg) was +30 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V, the stress temperature was 60 ° C., and the measurement environment was dark. In addition, Id-Vg characteristics of the transistors 510 and 610 were measured at stress times of 0 sec, 100 sec, 500 sec, 1000 sec, 1500 sec, 2000 sec, and 3600 sec, respectively.

  FIG. 13A shows the result of the Id-Vg characteristic of the transistor 510 at the measurement point 502 a in the center of the substrate 501. FIG. 13B is a graph showing the time dependency of the threshold voltage Vth of the transistor 510 at the measurement point 502 a in the center of the substrate 501. FIG. 14A shows the result of the Id-Vg characteristic of the transistor 510 at the measurement point 502 b in the center of the region 501 a of the substrate 501. FIG. 14B is a graph showing the time dependency of the threshold voltage Vth of the transistor 510 at the measurement point 502 b in the center of the region 501 a of the substrate 501. FIG. 15A shows the result of the Id-Vg characteristics of the transistor 510 at the measurement point 502c at the edge of the region 501a of the substrate 501. FIG. 15B is a graph showing time dependency of the threshold voltage Vth of the transistor 510 at the measurement point 502c at the edge of the region 501a of the substrate 501. 13A, FIG. 14A, and FIG. 15A, the Id-Vg characteristics of the transistor 510 at 0 sec, 1500 sec, and 3600 sec are shown, respectively.

  FIG. 16A shows the result of the Id-Vg characteristics of the transistor 610 at the center measurement point 602 a of the substrate 601. FIG. 16B is a graph showing time dependency of the threshold voltage Vth of the transistor 610 at the measurement point 602 a in the center of the substrate 601. FIG. 17A shows the result of the Id-Vg characteristic of the transistor 610 at the measurement point 602 b in the center of the region 601 a of the substrate 601. FIG. 17B is a graph showing the time dependency of the threshold voltage Vth of the transistor 610 at the measurement point 602 b in the center of the region 601 a of the substrate 601. FIG. 18A shows the result of the Id-Vg characteristic of the transistor 610 at the measurement point 602c at the edge of the region 601a of the substrate 601. FIG. FIG. 18B is a graph showing the time dependency of the threshold voltage Vth of the transistor 610 at the measurement point 602 c at the edge of the region 601 a of the substrate 601. 16A, FIG. 17A, and FIG. 18A, the Id-Vg characteristics of the transistor 610 at 0 sec, 1500 sec, and 3600 sec are shown, respectively.

  Table 1 shows the variation value ΔVth of the threshold voltage at each of the measurement points 502 a to 502 c and 602 a to 602 c.

  For the transistor 610 according to Comparative Example 1, it was shown that the threshold voltage ΔVth after 3600 sec fluctuates by 2 V to 7 V at the measurement points 602 a to 602 c. On the other hand, in the transistor 510 according to the example, it was shown that the threshold voltage ΔVth after 3600 sec fluctuates only at about 1 V at the measurement points 502 a to 502 c. As a result, it was confirmed that in the transistor according to this example, the fluctuation of the threshold voltage of the transistor is smaller than that of the transistor according to the comparative example.

  The above results show that the semiconductor device according to the present invention can improve the reliability of the transistor.

Claims (13)

Forming a first gate electrode on the substrate;
Forming a gate insulating film on the first gate electrode;
A first oxide semiconductor layer including a region overlapping with the first gate electrode is formed on the gate insulating film,
A source electrode and a drain electrode are formed on the first oxide semiconductor layer,
Forming an oxide insulating layer on the source and drain electrodes;
An oxide semiconductor target is sputtered on the oxide insulating layer in an atmosphere containing oxygen to form a second oxide semiconductor layer, and oxygen is added to the oxide insulating layer.
The heat treatment is performed to diffuse the oxygen into the first oxide semiconductor layer,
A method for manufacturing a semiconductor device, wherein the second oxide semiconductor layer is removed after the heat treatment.   The method for manufacturing a semiconductor device according to claim 1, wherein a film thickness of the second oxide semiconductor layer is smaller than a film thickness of the first oxide semiconductor layer. The method for manufacturing a semiconductor device according to claim 1, wherein a carrier concentration of the second oxide semiconductor layer is 1 × 10 ¹³ or more and 1 × 10 ²⁰ cm ⁻³ or less.   The method for manufacturing a semiconductor device according to claim 1, wherein a temperature of the heat treatment is 300 ° C. or more and 400 ° C. or less.   The method of manufacturing a semiconductor device according to claim 1, wherein in the sputtering, an oxygen gas flow ratio to a rare gas is 30% or more.   The method of manufacturing a semiconductor device according to claim 1, wherein a material of the second oxide semiconductor layer is the same as a material of the first oxide semiconductor layer.   The method of manufacturing a semiconductor device according to claim 6, wherein the first oxide semiconductor layer and the second oxide semiconductor layer contain at least indium, gallium, and zinc.   The method of manufacturing a semiconductor device according to claim 1, wherein a material of the second oxide semiconductor layer is different from a material of the first oxide semiconductor layer.   The method of manufacturing a semiconductor device according to claim 8, wherein the first oxide semiconductor layer and the second oxide semiconductor layer contain at least indium.   The method for manufacturing the semiconductor device according to claim 1, wherein a second gate electrode overlapping with the first oxide semiconductor layer is formed on the oxide insulating layer after removing the second oxide semiconductor layer. A first gate electrode on the substrate,
A gate insulating film on the first gate electrode;
An oxide semiconductor layer overlapping the first gate electrode on the gate insulating film;
An oxide insulating layer on the oxide semiconductor layer;
A semiconductor device comprising indium in a first region whose thickness from the surface of the oxide insulating layer is 50 nm or less. The semiconductor device according to claim 11, wherein a concentration of the indium contained in the first region is 1 × 10 ¹⁷ atoms / cm ³ or more and 1 × 10 ¹⁸ atoms / cm ³ or less.   The semiconductor device according to claim 12, further comprising a second gate electrode overlapping the oxide semiconductor layer, on the oxide insulating layer.