JP2019115033A - Power amplifier circuit - Google Patents

Abstract

To provide a power amplifier circuit capable of improving linearity of gain with accuracy.SOLUTION: A power amplifier circuit 100A comprises: a first transistor Q1 that amplifies a first signal; a second transistor Q2 that amplifies a second signal depending on an output signal of the first transistor; a bias circuit 121A that supplies a bias current or voltage to a base or a gate of the second transistor; and an attenuator 140A that attenuates the first or second signal depending on a control voltage supplied from the bias circuit. The attenuator includes: a first diode Q7; a third transistor Q6 to whose base the control voltage is supplied from a cathode of the first diode; and a capacitor C4 connected in parallel with the first diode. The control voltage is a voltage that is lower as a power level of the second signal is larger. The third transistor applies a part of the first or second signal from a collector of the third transistor to an emitter depending on the control voltage supplied to its base.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a power amplification circuit.

  In a power amplification circuit that amplifies a radio frequency (RF: Radio Frequency) signal, an attenuator may be provided to reduce the gain of the power amplification circuit in the low power mode. For example, Patent Document 1 discloses an attenuator shunt-connected to an input path of an RF signal to an amplification transistor. The attenuator includes a transistor, the voltage applied to the base of the transistor is controlled, and the amount of attenuation is controlled by switching the transistor on and off.

U.S. Patent No. 6842072

  In the attenuator disclosed in Patent Document 1, the transistor included in the attenuator is controlled according to the operation mode such that it is on in the low power mode and off in the high power mode. However, the gain of the power amplification circuit generally decreases continuously as the output power increases. Therefore, as described above, depending on the configuration in which the attenuator is switched according to the operation mode, it is difficult to accurately improve the linearity of the gain.

  The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a power amplification circuit that accurately improves the linearity of gain.

  In order to achieve such an object, a power amplification circuit according to an aspect of the present invention includes a first transistor that amplifies a first signal, and a second transistor that amplifies a second signal according to an output signal of the first transistor. Attenuator comprising: a bias circuit for supplying a bias current or a bias voltage to the base or gate of the second transistor; and an attenuator for attenuating the first signal or the second signal in accordance with a control voltage supplied from the bias circuit. Is connected to the first diode of which the control voltage is supplied to the anode, and the collector is connected to the supply path of the first signal to the first transistor or the supply path of the second signal to the second transistor, and the emitter is connected to the ground side A third transistor to which a control voltage is supplied from the cathode of the first diode to the base, and a capacitor connected in parallel to the first diode. The control voltage is lower as the power level of the second signal is higher, and the third transistor receives a portion of the first signal or the second signal according to the control voltage supplied to the base of the third transistor. It flows from the collector to the emitter of the third transistor.

  According to the present invention, it is possible to provide a power amplification circuit that improves the linearity of the gain with high accuracy.

It is a figure showing an outline of composition of a power amplification circuit concerning a 1st embodiment of the present invention. It is a figure showing an example of composition of a power amplification circuit concerning a 1st embodiment of the present invention. It is a figure which shows the relationship between the output power of a power amplification circuit, and the control voltage Vctrl. It is a figure which shows the relationship between the output electric power of a power amplification circuit, and the collector-emitter resistance of transistor Q6. It is a figure which shows the relationship between the collector-emitter resistance of transistor Q6, and the attenuation amount of RF signal. It is a figure which shows the relationship between the output power of a power amplification circuit, and the attenuation amount of RF signal. It is a figure which shows the relationship between the output power of a power amplification circuit, and gain. It is a figure which shows the structural example of the power amplification circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows the other structural example of the power amplification circuit which concerns on 2nd Embodiment of this invention. It is a figure showing an outline of composition of a power amplification circuit concerning a 3rd embodiment of the present invention. It is a figure showing the example of composition of the power amplification circuit concerning a 3rd embodiment of the present invention. It is a figure which shows the relationship between the output power of a power amplification circuit, and the control voltage Vctrl. It is a figure which shows the relationship between the output electric power of a power amplification circuit, and the collector-emitter resistance of transistor Q12. It is a figure which shows the relationship between the output power of a power amplification circuit, and the attenuation amount of RF signal. It is a figure showing the example of composition of the power amplification circuit concerning a 4th embodiment of the present invention. It is a figure which shows the relationship between the output electric power at the time of raising the gain of a power amplification circuit as a whole, and gain. It is a figure which shows the outline | summary of a structure of the power amplification circuit which concerns on 5th Embodiment of this invention. It is a figure which shows the outline | summary of a structure of the power amplification circuit which concerns on 6th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  FIG. 1 is a diagram showing an outline of a configuration of a power amplification circuit according to a first embodiment of the present invention. The power amplification circuit 100 shown in FIG. 1 is mounted on, for example, a mobile communication device such as a cellular phone and amplifies the power of a radio frequency (RF: Radio Frequency) signal to a level necessary to transmit it to a base station. It is a circuit. The power amplification circuit 100 may be, for example, 2G (second generation mobile communication system), 3G (third generation mobile communication system), 4G (fourth generation mobile communication system), 5G (fifth generation mobile communication system), LTE ( Long Term Evolution)-A transmission signal of a communication standard such as Frequency Division Duplex (FDD), Time Division Duplex (LTE- TDD), LTE-Advanced, or LTE-Advanced Pro is amplified. The frequency of the RF signal is, for example, about several hundred MHz to several tens of GHz. The communication standard and the frequency of the signal amplified by the power amplification circuit 100 are not limited to these.

  Specifically, the power amplification circuit 100 includes, for example, amplifiers 110 and 111, bias circuits 120 and 121, matching circuits 130 and 131, an attenuator 140, and capacitors C1 and C2.

  The amplifiers 110 and 111 respectively amplify and output the input RF signal. That is, the power amplification circuit 100 amplifies power in two stages. Specifically, the amplifier 110 of the first stage (driver stage) amplifies the RF signal RF1 (first signal) input from the input terminal via the matching circuit 130, and outputs an RF signal RF2. The amplifier 111 in the subsequent stage (power stage) amplifies the RF signal RF2 (second signal) supplied from the amplifier 110 and outputs an RF signal RF3. The amplifiers 110 and 111 are each formed of, for example, a bipolar transistor such as a heterojunction bipolar transistor (HBT) of a compound semiconductor made of GaAs or the like. The amplifiers 110 and 111 may be configured by field effect transistors (MOSFETs: Metal-oxide-semiconductor Field-Effect Transistors) instead of the HBTs. In this case, the collector, the base, and the emitter may be replaced with the drain, the gate, and the source, respectively. In the following, unless otherwise specified, the case where the transistor is formed of HBT will be described as an example.

  The bias circuits 120 and 121 supply a bias current or a bias voltage to the amplifiers 110 and 111, respectively. The bias circuits 120 and 121 control the gains of the amplifiers 110 and 111 by adjusting the bias current or the bias voltage.

  The matching circuit (MN: Matching Network) 130 matches the impedance of the circuit (not shown) provided in the previous stage and the amplifier 110. The matching circuit 131 matches the impedance of the amplifier 111 with a circuit (not shown) provided in the subsequent stage. Although not shown in FIG. 1, the power amplification circuit 100 may be provided with an inter-stage matching circuit between the amplifier 110 and the amplifier 111.

  The attenuator 140 is for reducing the gain of the power amplification circuit 100 when the output power of the power amplification circuit 100 is relatively small. That is, in general, the power amplification circuit may start to reduce its gain when the output power exceeds a certain level, and the linearity may deteriorate due to the performance of the transistor. In order to cope with this problem, in the power amplification circuit 100, the gain is adjusted by the attenuator 140 attenuating the RF signal RF1 supplied to the amplifier 110 based on the control voltage Vctrl output from the bias circuit 121. . Details of the attenuation by the attenuator 140 will be described later.

  The capacitors C1 and C2 are provided at the inputs of the amplifiers 110 and 111, respectively. The capacitors C1 and C2 are coupling capacitors that block a direct current component included in the RF signal and allow an alternating current component to pass through.

  The details of the attenuation of the RF signal by the attenuator 140 will now be described with reference to FIG.

  FIG. 2 is a view showing a configuration example of the power amplification circuit according to the first embodiment of the present invention. The power amplification circuit 100A shown in FIG. 2 particularly shows a specific configuration of the bias circuit 121 and the attenuator 140 among the power amplification circuit 100 shown in FIG.

  Amplifiers 110 and 111 include transistors Q1 and Q2, respectively. The transistor Q1 (first transistor) has a collector supplied with the power supply voltage Vcc via the inductor L1, a base supplied with the RF signal RF1 and a bias current or bias voltage, and an emitter connected to ground. Thereby, the transistor Q1 outputs the RF signal RF2 obtained by amplifying the RF signal RF1 from the collector. The transistor Q2 (second transistor) has a collector supplied with the power supply voltage Vcc via the inductor L2, a base supplied with the RF signal RF2 and a bias current or bias voltage, and an emitter connected to ground. Thereby, the transistor Q2 outputs an RF signal RF3 obtained by amplifying the RF signal RF2 from the collector.

  One end of each of the inductors L1 and L2 is supplied with the power supply voltage Vcc, and the other end is connected to the collectors of the transistors Q1 and Q2. The inductors L1 and L2 are choke inductors for suppressing leakage of the AC component to the power supply voltage Vcc side.

  The bias circuit 121A includes, for example, transistors Q3 to Q5 and resistance elements R1 to R3. The configuration of the bias circuit 120 at the first stage can be the same as the configuration of the bias circuit 121A at the subsequent stage, and thus detailed description will be omitted.

  The transistor Q3 (fourth transistor) has a collector supplied with the battery voltage Vbatt, a base connected to the base of the transistor Q4, and an emitter connected to the base of the transistor Q2 via the resistor element R1.

  The transistor Q4 has a collector and a base connected (hereinafter also referred to as "diode connection"), a bias control voltage VB is supplied to the collector via the resistance element R2, and an emitter is connected to the collector of the transistor Q5. The transistor Q5 is diode-connected, the collector is connected to the emitter of the transistor Q4, and the emitter is connected to the ground via the resistor element R3. A diode-connected bipolar transistor behaves as a diode equivalent diode. Of the two terminals of the diode-connected bipolar transistor, the higher one in the forward bias corresponds to the anode, and the lower one corresponds to the cathode. That is, the transistor Q4 and the transistor Q5 constitute a second diode and a third diode, respectively. Thereby, a voltage (for example, about 2.6 V) of a predetermined level is generated at the collector of the transistor Q4. The second and third diodes may be replaced by diodes instead of the transistors Q4 and Q5. In this case, the collector (or base) and the emitter may be replaced with an anode and a cathode, respectively. The same applies to a diode-connected transistor described below.

  One end of the resistive element R1 is connected to the emitter of the transistor Q3, and the other end is connected to the base of the transistor Q2. The resistance element R1 suppresses an increase in bias current accompanying a temperature rise of the transistor. One end of the resistance element R2 is supplied with the bias control voltage VB, and the other end is connected to the collector of the transistor Q4. One end of the resistive element R3 is connected to the emitter of the transistor Q5, and the other end is connected to the ground.

  With the above configuration, transistor Q3 supplies a bias current from the emitter to the base of transistor Q2. The amount of current of the bias current is controlled by the bias control voltage VB or the bias control current supplied to the collector of the transistor Q4. In addition, the bias circuit 121A may not include the resistance elements R1 to R3.

  Attenuator 140A includes transistors Q6 and Q7, resistance element R4 and capacitors C3 and C4.

  The transistor Q6 (third transistor) has a collector connected to the supply path of the RF signal RF1 to the transistor Q1 via the capacitor C3, a base connected to the emitter of the transistor Q7 via the resistor element R4, and an emitter Connected to the ground side. In the present specification, “connected to the supply path” is not limited to the aspect directly connected to the supply path, but includes the aspect connected via components such as other elements. . The operating state of the transistor Q6 is controlled in accordance with the control voltage Vctrl supplied from the bias circuit 121A to the base of the transistor Q6. Specifically, the transistor Q6 is turned on when the control voltage Vctrl is high, and turned off when the voltage is low. Then, the transistor Q6 attenuates the RF signal RF1 passing through the supply path to the transistor Q1 by flowing part of the RF signal RF1 from the collector to the emitter when it is on.

  The capacitor C3 is connected between the supply path of the RF signal RF1 and the collector of the transistor Q6. The capacitor C3 prevents the DC component of the collector of the transistor Q6 from being supplied to the supply path of the RF signal RF1.

  Attenuator 140A may be provided with a resistive element instead of capacitor C3, or may be provided with a resistive element connected in series with capacitor C3. When the attenuator includes the resistance element, the RF signal RF1 is attenuated by the combination of the resistance value between the collector and the emitter of the transistor Q6 and the resistance value of the resistance element. That is, by adjusting the resistance value of the resistive element, the relationship between the control voltage Vctrl and the attenuation amount of the RF signal can be adjusted, and thereby the attenuation amount of the RF signal can be controlled.

  The transistor Q7 is diode-connected, the collector thereof is supplied with the control voltage Vctrl, and the emitter is connected to the base of the transistor Q6 via the resistance element R4. The transistor Q7 constitutes a first diode. One end of the resistive element R4 is connected to the emitter of the transistor Q7, and the other end is connected to the base of the transistor Q6. The transistor Q7 is provided to match the voltage value supplied to the base of the transistor Q6 to the drive level by stepping down the control voltage Vctrl by the base-emitter voltage of the transistor Q7. The voltage supplied to the base of the transistor Q6 can also be adjusted by adjusting the resistance value of the resistance element R4.

  Capacitor C4 is connected in parallel with transistor Q7 and resistor element R4. Specifically, one end of the capacitor C4 is connected to the collector of the transistor Q7, and the other end is connected to the base of the transistor Q6. The capacitor C4 has, for example, a capacitance value larger than the capacitance value between the collector and the emitter of the transistor Q7, and has the following function. That is, since the amplitude of the RF signal RF2 supplied to the transistor Q2 fluctuates at the envelope frequency (several MHz to several tens of MHz), the control voltage Vctrl also fluctuates accordingly. Therefore, in order to improve the linearity of the gain, it is necessary to change the attenuation of the RF signal according to the change of the control voltage Vctrl. However, when the current drive capability of the transistor Q7 is low, the transistor Q7 alone may not be able to follow the voltage change at the envelope frequency. In this respect, in the attenuator 140A, the variation of the control voltage Vctrl is transmitted to the base of the transistor Q6 via the capacitor C4 by including the capacitor C4. Thereby, in the attenuator 140A, the tracking performance of the attenuation amount to the control voltage Vctrl is further enhanced.

  Next, the operation principle and effect of the power amplification circuit 100A will be described with reference to FIGS. 3A to 3E. Here, FIG. 3A is a diagram showing the relationship between the output power of the power amplification circuit and the control voltage Vctrl, and FIG. 3B is a diagram showing the relationship between the output power of the power amplification circuit and the collector-emitter resistance of the transistor Q6. FIG. 3C is a diagram showing the relationship between the collector-emitter resistance of the transistor Q6 and the amount of attenuation of the RF signal, and FIG. 3D is a diagram showing the relationship between the output power of the power amplifier circuit and the amount of attenuation of the RF signal. FIG. 3E is a diagram showing the relationship between the output power of the power amplification circuit and the gain.

  In FIG. 3A, the horizontal axis indicates the output power (dBm) of the power amplification circuit, and the vertical axis indicates the control voltage Vctrl (V). The control voltage Vctrl (ie, the base voltage of the transistor Q3) fluctuates according to the power level of the RF signal RF2 supplied to the transistor Q2. Specifically, as the power level of the RF signal RF2 increases (ie, the output power level increases), the current amplitude at the collector of the transistor Q2 increases. Here, the collector current does not flow in the negative direction. Therefore, the current amplitude at the collector of the transistor Q2 is cut at a portion below the idle current value in the negative direction of the amplitude when the amplitude becomes large. At this time, since the positive increase of the amplitude is not limited, as a result, the average direct current of the collector and the base of the transistor Q2 increases. The emitter voltage of the transistor Q3 fluctuates to compensate for the increase in the average DC current, and the DC current at the collector and the base of the transistor Q3 increases (self-bias effect). On the other hand, the base current of the transistor Q3 is supplied from the power supply of the bias control voltage VB via the resistance element R2. When the base current of the transistor Q3 increases, assuming that the control voltage Vctrl rises, the current flowing to the collectors of the transistors Q4 and Q5 also increases, and the voltage drop in the resistance element R2 should increase, thereby causing a contradiction. . That is, when the base current of the transistor Q3 increases, the control voltage Vctrl decreases. Thus, the control voltage Vctrl is a lower voltage as the power level of the RF signal RF2 is higher (see FIG. 3A). Here, in a region where the output power is relatively low (hereinafter also referred to as “low power region”), control voltage Vctrl maintains a level at which transistor Q6 is turned on. On the other hand, in a region where the output power exceeds a certain level (hereinafter also referred to as "high power region"), control voltage Vctrl gradually decreases, so that the current flowing between the collector and the emitter of transistor Q6 also decreases. When the control voltage Vctrl further decreases, the transistor Q6 is turned off.

  In FIG. 3B, the horizontal axis represents the output power (dBm) of the power amplification circuit, and the vertical axis represents the collector-emitter resistance (Ω) of the transistor Q6. As described above, since the transistor Q6 is on in the low power region, the collector-emitter resistance of the transistor Q6 maintains the value of the on resistance. On the other hand, in the high power region, the resistance between the collector and the emitter of the transistor Q6 gradually rises as the control voltage Vctrl decreases. That is, as shown in FIG. 3B, the collector-emitter resistance of the transistor Q6 rises as the output power increases.

  In FIG. 3C, the abscissa represents the collector-emitter resistance (Ω) of the transistor Q6, and the ordinate represents the attenuation (dB) of the RF signal. As shown in FIG. 3C, when the resistance between the collector and the emitter of the transistor Q6 is low, the amount of attenuation of the RF signal RF1 is large because many RF signals flow from the supply path of the RF signal RF1 to the transistor Q6 via the capacitor C3. Is large. On the other hand, as the collector-emitter resistance of the transistor Q6 rises, the RF signal flowing to the transistor Q6 decreases, so the attenuation of the RF signal RF1 decreases.

  In FIG. 3D, the horizontal axis represents output power (dBm) of the power amplification circuit, and the vertical axis represents attenuation (dB) of the RF signal. As described above, in the power amplification circuit 100A, the transistor Q6 is turned on in the low power region, and the attenuation amount of the RF signal is large. On the other hand, since the resistance value of the transistor Q6 becomes higher as the output power increases, the RF signal flowing to the transistor Q6 decreases, and the attenuation of the RF signal becomes smaller continuously. For example, as shown in FIG. 3D, assuming that the attenuation at the output power P1 is ΔGain1, and the attenuation at the output power P2 (> P1) is ΔGain2, then ΔGain1> ΔGain2.

  In FIG. 3E, the horizontal axis indicates the output power (dBm) of the power amplification circuit, and the vertical axis indicates the gain (dB) of the power amplification circuit. The solid line shows the gain when the attenuator 140A is not provided, the broken line shows the gain when the attenuator 140A is provided, and the alternate long and short dash line shows the gain of the configuration (comparative example) including the attenuator whose attenuation is fixed. It shows. As shown in FIG. 3E, without the attenuator 140A, the gain starts to decrease when the output power exceeds a certain level, and the linearity is degraded (see a solid line). On the other hand, in the power amplification circuit 100A, the gain is reduced by ΔGain1 by the attenuator 140A in the low power region. Then, as the output power level increases, the amount of attenuation decreases, and at the output power P2, the reduction of the gain is suppressed to ΔGain2 minutes. That is, in the power amplification circuit 100A, the amount of attenuation is large in the low power region and controlled to be small in the high power region, so the linearity of gain including the low power region and the high power region is improved. (See dashed line). In the comparative example in which the amount of attenuation is fixed regardless of the output power, the gain is reduced even in the high power region (see the dashed-dotted line). In the power amplification circuit 100A, the linearity can be further improved as compared with such a comparative example.

  As described above, in the power amplification circuit 100A, by using the base voltage of the transistor Q3 in the bias circuit 121A as a supply source of the control voltage Vctrl, the attenuation amount of the RF signal can be continuously changed according to the output power. Therefore, as compared with the configuration disclosed in Patent Document 1, the linearity of the gain of the power amplification circuit 100A can be accurately improved.

  Further, in the power amplification circuit 100A, as in the configuration disclosed in Patent Document 1, there is no need to generate a control signal supplied to the base of the transistor Q3, so the circuit configuration can be simplified.

  Furthermore, by providing the capacitor C4, the attenuator 140A can improve the ability to follow the amount of attenuation of the control voltage Vctrl even if the envelope frequency of the RF signal is high. Therefore, this also improves the linearity of the gain of the power amplification circuit 100A.

  FIG. 4 is a view showing a configuration example of a power amplification circuit according to a second embodiment of the present invention, and FIG. 5 is a view showing another configuration example of the power amplification circuit according to the second embodiment of the present invention is there. In the second and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only different points will be described. In particular, the same operation and effect by the same configuration will not be sequentially referred to in each embodiment. Further, in FIG. 4 and FIG. 5, among the elements included in the power amplification circuits 100B and 100C, only the elements related to the first stage are illustrated, and the elements related to the latter stage are not illustrated.

  The power amplification circuit 100B shown in FIG. 4 shows a specific configuration of the bias circuit 120 and the attenuator 140 in the power amplification circuit 100 shown in FIG.

  Attenuator 140B further includes transistors Q8 and Q9, resistance elements R5 and R6, and inductor L3 as compared to attenuator 140A shown in FIG. 2, and includes capacitor C5 instead of capacitor C3.

  The transistor Q8 is diode-connected and connected in series to the supply path of the RF signal RF1 to the transistor Q1 to form a fourth diode. Specifically, in the transistor Q8, the base is supplied with the RF signal RF1 via the matching circuit 130, and the emitter is connected to the base of the transistor Q1 via the capacitor C1. The base of the transistor Q8 is connected to the collector of the transistor Q6 via the resistor element R5, and the emitter is connected to ground via the inductor L3.

  The transistor Q9 is diode-connected, the collector is connected to the base of the transistor Q10, and the emitter is connected to the collector of the transistor Q6 via the resistance elements R6 and R5.

  One end of the resistive element R5 is connected to the base of the transistor Q8, and the other end is connected to the collector of the transistor Q6. One end of the resistive element R6 is connected to the emitter of the transistor Q9, and the other end is connected to one end of the resistive element R5. The resistance elements R5 and R6 are provided to adjust the voltage level so that the transistors Q6, Q9 and Q10 operate properly.

  One end of the inductor L3 is connected to the emitter of the transistor Q8, and the other end is connected to the ground. The inductor L3 has a function of flowing the DC component of the emitter of the transistor Q8 to the ground.

  Capacitor C5 is a decoupling capacitor for releasing the high frequency component included in control voltage Vctrl supplied to the base of transistor Q6 to the ground.

  The bias circuit 120A includes a transistor Q10 and a resistive element R7. The transistor Q10 has its base supplied with the collector voltage of the transistor Q9, and has the same function as the transistor Q3 shown in FIG. Resistive element R7 has the same function as resistive element R1 shown in FIG.

  In the power amplification circuit 100B, the resistance between the collector and the emitter of the transistor Q6 is high in the high power region, as in the above-described power amplification circuit 100A. As a result, the base voltage of the transistor Q8 increases, and the collector-emitter resistance of the transistor Q8 decreases. Therefore, the attenuation of the RF signal in the supply path of the RF signal RF1 is reduced. As described above, in the power amplification circuit 100B, the amount of change in attenuation of the RF signal relative to the amount of increase in output power is larger than that in the power amplification circuit 100A. Therefore, for example, when the degree of decrease in gain accompanying increase in output power is steeper, the accuracy of gain linearity is further improved by applying the power amplification circuit 100B as compared to the power amplification circuit 100A. Can.

  The power amplification circuit 100C shown in FIG. 5 includes an attenuator 140C instead of the attenuator 140B as compared to the power amplification circuit 100B shown in FIG.

  The attenuator 140C includes a transistor Q11 in place of the transistor Q8 and an inductor L4 in place of the inductor L3 as compared to the attenuator 140B.

  The transistor Q11 is diode-connected (fourth diode), and is connected in series to the supply path of the RF signal RF1 in the reverse direction to the transistor Q8 to form a fourth diode. Specifically, in the transistor Q11, the RF signal RF1 is supplied to the emitter via the matching circuit 130, and the base is connected to the base of the transistor Q1 via the capacitor C1. In the transistor Q11, as in the transistor Q8, the collector-emitter resistance decreases as the output power increases. As a result, as the output power increases, the amount of attenuation of the RF signal decreases. Therefore, even with such a configuration, it is possible to further improve the linearity of the gain as in the power amplification circuit 100B.

  In the attenuators 140B and 140C, as in the case of the attenuator 140A, the capacitor C4 connected in parallel to the transistor Q7 may be provided. In addition, the attenuators 140B and 140C may not include the capacitor C5.

  FIG. 6 is a diagram showing an outline of a configuration of a power amplification circuit according to a third embodiment of the present invention, and FIG. 7 is a view showing a configuration example of a power amplification circuit according to the third embodiment of the present invention. . The power amplification circuit 100D shown in FIGS. 6 and 7 includes an attenuator 140D instead of the attenuator 140 as compared to the power amplification circuit 100 shown in FIG. The attenuator 140D is provided at the input of the subsequent stage amplifier 111, and attenuates the RF signal RF2 supplied to the subsequent stage amplifier 111.

  The attenuator 140D includes a transistor Q12 instead of the transistor Q6, and further includes a capacitor C5, as compared to the attenuator 140A.

  The transistor Q12 (third transistor) has the same connection as the transistor Q6 except that it is diode-connected.

  In the attenuator 140D, when the RF signal RF2 is supplied to the collector of the transistor Q12 via the capacitor C3, the collector voltage of the transistor Q12 oscillates, and the base voltage connected to the collector also oscillates. When the power level of the RF signal RF2 increases, a state in which the transistor Q12 is turned off occurs, which causes a change in the collector-emitter resistance of the transistor Q12. Also, the transistor Q7 repeats on and off alternately with the switching on and off of the transistor Q12. As a result, compared to the configuration in which the transistor Q12 is not diode-connected, the charge of the base of the transistor Q3 is extracted, and the control voltage Vctrl is further lowered as the output power is increased.

  FIG. 8A is a diagram showing the relationship between the output power of the power amplification circuit and the control voltage Vctrl, and FIG. 8B is a diagram showing the relationship between the output power of the power amplification circuit and the collector-emitter resistance of the transistor Q12. 8C is a diagram showing the relationship between the output power of the power amplification circuit and the attenuation of the RF signal. Further, in FIGS. 8A to 8C, a solid line indicates the attenuator 140D and a broken line indicates the attenuator 140A.

  As shown in FIG. 8A, according to the attenuator 140D, the degree of decrease of the control voltage Vctrl with the increase of the output power is larger than that of the attenuator 140A. Further, as described above, the base voltage of the transistor Q12 vibrates, which causes a change in the collector-emitter resistance of the transistor Q12. Due to these effects, as shown in FIG. 8B, in the attenuator 140D, the curve of the increase in the collector-emitter resistance of the transistor Q12 with the increase of the output power becomes gentler as compared with the attenuator 140A. As a result, as shown in FIG. 8C, in the attenuator 140D, the amount of change in attenuation of the attenuator 140D due to the increase in the output power becomes gentler than that of the attenuator 140A. Therefore, for example, when the reduction level of the gain accompanying the increase of the output power is moderate, the linearity of the gain can be improved by applying the configuration of the attenuator 140D. As such, various configurations can be applied as attenuator 140, depending on the level of gain reduction.

  Also in the attenuator 140D, a capacitor C4 may be provided as in the case of the attenuator 140A.

  6 and 7 show an example in which the attenuator 140D is provided at the input of the subsequent stage amplifier, it is not intended to exclude the configuration in which the attenuator 140D is provided at the input of the first stage amplifier. When the attenuator 140D is provided at the input of the subsequent stage amplifier, the voltage amplitude at the collector of the transistor Q12 is larger than that provided in the previous stage amplifier, so the effect of making the transistor Q12 diode-connected is more remarkable Become.

  FIG. 9 is a view showing a configuration example of a power amplification circuit according to a fourth embodiment of the present invention. The power amplification circuit 100E shown in FIG. 9 includes a bias circuit 121B instead of the bias circuit 121A as compared to the power amplification circuit 100A, and includes an attenuator 140E instead of the attenuator 140A.

  Bias circuit 121B is similar to bias circuit 121A in configuration but differs in that the collector voltage of transistor Q5 (ie, the anode voltage of transistor Q5) is output as control voltage Vctrl instead of the base voltage of transistor Q3. Do. The collector voltage of the transistor Q5 is a value obtained by subtracting the base-emitter voltage of the transistor Q4 from the base voltage of the transistor Q3.

  Attenuator 140E is configured without including transistor Q7 and capacitor C4 as compared to attenuator 140A. That is, in the power amplification circuit 100E, the control voltage Vctrl is lower than the power amplification circuit 100A by the voltage between the collector and the emitter of the transistor Q4, so the transistor Q7 may not be provided. Further, in the power amplification circuit 100E, the control voltage Vctrl is supplied to the base of the transistor Q6 without passing through the transistor Q7. Therefore, the capacitor C4 may not be provided.

  The control voltage Vctrl in the present embodiment changes similarly to the base voltage of the transistor Q3 shown in FIG. 3A as the output power increases. Therefore, even with such a configuration, the power amplification circuit 100E can obtain the same effect as that of the power amplification circuit 100A.

  In the power amplification circuit 100E, when the current drive capability of the transistor Q5 is higher than the current drive capability of the transistor Q7, the operating speed of the attenuator 140E is faster than that of the power amplification circuit 100A. Therefore, it is possible to enhance the ability to follow the fluctuation of the amplitude of the RF signal RF1 without using the capacitor C4.

  The source of the control voltage Vctrl is not limited to the base of the transistor Q3 or the collector of the transistor Q5 as described above. For example, the source of the control voltage Vctrl may be the emitter voltage of the transistor Q3.

  In the above, the example which adjusts attenuation amount of RF signal by attenuator 140A-140E was demonstrated. On the other hand, in the power amplification circuit 100, further improvement in linearity can be expected by applying the attenuators 140A to 140E after raising the gain throughout the low power region and the high power region. This will be described with reference to FIG.

  FIG. 10 is a diagram showing the relationship between the output power and the gain when the gain of the power amplification circuit is generally increased. In FIG. 10, the horizontal axis represents output power (dBm), and the vertical axis represents gain (dB). Also, the solid line indicates the case where the gain is not generally increased and the attenuator is not provided, the dashed dotted line indicates the case where the gain is generally increased and the attenuator is not provided, and the broken line indicates the entire gain. , And the attenuator attenuates the RF signal.

  First, as shown in FIG. 10, it is assumed that the gain of the power amplification circuit 100 can be entirely increased (see the dashed line in FIG. 10). Further, the attenuator 140 has, for example, an attenuation of ΔGain3 (> ΔGain1) at the output power P1 and an attenuation of the output power P2 at ΔGain4 (<ΔGain2) as compared with the attenuation shown in FIG. 3E. Be configured to be The amount of change in attenuation (.DELTA.Gain3-.DELTA.Gain4) at this time is larger than the amount of change in attenuation (.DELTA.Gain1-.DELTA.Gain2) shown in FIG. 3E. As described above, the linearity of the gain can be further accurately improved by increasing the gain as a whole and further attenuating the RF signal using an attenuator with a larger amount of change in attenuation (FIG. 10). See dashed line).

  Although the method of raising the gain of the power amplification circuit 100 as a whole is not particularly limited, the following three methods are shown as an example. The first method is to change the semiconductor chip in which the power amplification circuit 100 is formed to a wire bonding structure to a flip chip structure. Thus, in the connection between the emitters of the transistors Q1 and Q2 and the ground, the parasitic inductance generated between the emitter and the ground can be suppressed to about half through the bumps instead of via vias. Therefore, by applying the flip chip structure to the semiconductor chip, the gain of the power amplification circuit 100 can be increased by about 2 dB.

  The second method is to increase the number of stages of amplifiers provided in the power amplification circuit 100. For example, in the configuration including three stages of amplifiers, the gain of the power amplification circuit 100 can be increased by about 3 dB or more as compared to the configuration including two stages of amplifiers.

  In addition, if, for example, the power amplification circuit 100 includes a three-stage amplifier, an attenuator may be provided at the input of the first and second-stage amplifiers. Thereby, compared with the structure provided with one attenuator, the variation | change_quantity of attenuation amount accompanying increase in output power can be enlarged. Therefore, as shown in FIG. 10, the linearity can be further accurately improved. Note that attenuators may be provided at the inputs of the amplifiers of all stages. Also, the specific configuration of the attenuator may be any of the attenuators 140A to 140E described above, and these may be combined and applied.

  The third is a method in which at least one of the transistors Q1 and Q2 included in the power amplification circuit 100 is configured by an FET instead of the HBT. Thereby, the gain of the power amplification circuit 100 can be increased by about 2 dB as compared to the HBT. The transistor replaced with the FET may be only the first stage, only the second stage, or any transistor of the first stage and the second stage.

  FIG. 11 is a diagram showing an outline of a configuration of a power amplification circuit according to a fifth embodiment of the present invention. As shown in FIG. 11, the power amplification circuit 100F further includes an attenuator 141 as compared to the power amplification circuit 100 shown in FIG. The attenuator 141 is provided at the input of the amplifier 111 in the subsequent stage. Thus, attenuators may be respectively provided at the inputs of both the front and rear amplifiers. In addition, as a specific configuration of the attenuator 141, for example, the configuration of any of the above-described attenuators 140A to 140E can be applied, and thus the detailed description will be omitted.

  FIG. 12 is a diagram showing an outline of a configuration of a power amplification circuit according to a sixth embodiment of the present invention. As shown in FIG. 12, the power amplification circuit 100G includes three stages of amplifiers and amplifies power over three stages. Specifically, the power amplifier 100G further includes an attenuator 112 at a third stage, a bias circuit 122, and a capacitor C6, as compared to the power amplifier circuit 100F.

  The third stage amplifier 112 amplifies the RF signal RF3 supplied from the second stage amplifier 111 and outputs an RF signal RF4. In the present embodiment, attenuators 140 and 141 are provided at the inputs of the first stage amplifier 110 and the second stage amplifier 111, respectively. In addition, since the bias circuit 122 and the capacitor C6 correspond to the bias circuit 121 and the capacitor C2, respectively, the detailed description will be omitted.

  As described above, even in the case where the power amplification circuit 100G includes three stages of amplifiers, the same effects as those of the above-described embodiments can be obtained. The attenuator may be provided only in the first stage amplifier, or may be provided at the input of all the first to third stage amplifiers. Even in these cases, it is preferable that the control voltage Vctrl be supplied from the bias circuit connected to the final stage amplifier.

  The exemplary embodiments of the present invention have been described above. The power amplification circuit 100A includes a transistor Q1 that amplifies the RF signal RF1, a transistor Q2 that amplifies the RF signal RF2 according to the output signal of the transistor Q1, and a bias that supplies a bias current or bias voltage to the base or gate of the transistor Q2. A circuit 121A, and an attenuator 140A for attenuating the RF signal RF1 according to the control voltage Vctrl supplied from the bias circuit 121A, wherein the attenuator 140A has a first diode to which the control voltage Vctrl is supplied to the anode. The collector is connected to the supply path of the RF signal RF1 to the transistor Q1, the emitter is connected to the ground, and the base is connected in parallel to the transistor Q6 to which the control voltage Vctrl is supplied from the cathode of the first diode Capacitors, including The voltage Vctrl is lower as the power level of the RF signal RF2 is higher, and the transistor Q6 emits a part of the RF signal RF1 from the collector of the transistor Q6 in accordance with the control voltage Vctrl supplied to the base of the transistor Q6. Let flow. As a result, the amount of attenuation of the RF signal can be continuously changed according to the output power, so that the linearity of the gain of the power amplification circuit 100A can be accurately improved as compared with the configuration disclosed in Patent Document 1. Can. Further, by including the capacitor C4, the power amplification circuit 100A can improve the tracking performance of the attenuation amount to the fluctuation of the control voltage Vctrl even when the envelope frequency of the RF signal is high.

  The power amplification circuit 100D supplies a bias current or a bias voltage to the transistor Q1 amplifying the RF signal RF1, the transistor Q2 amplifying the RF signal RF2 according to the output signal of the transistor Q1, and the base or gate of the transistor Q2. And an attenuator 140D for attenuating the RF signal RF2 in accordance with the control voltage Vctrl supplied from the bias circuit 121A. The attenuator 140D is a first diode in which the control voltage Vctrl is supplied to the anode. And a transistor Q12 having a collector connected to the base and a supply path of the RF signal RF2 to the transistor Q2, an emitter connected to the ground, and a control voltage Vctrl supplied from the cathode of the first diode to the base , And the control voltage Vc rl is a lower voltage as the power level of the RF signal RF2 is higher, and the transistor Q12 transmits a part of the RF signal RF2 from the collector to the emitter of the transistor Q12 according to the control voltage Vctrl supplied to the base of the transistor Q12. Flow. Thus, power amplification circuit 100D has a greater degree of decrease in control voltage Vctrl as output power increases, as compared to power amplification circuit 100A, so the amount of change in attenuation of attenuator 140D as output power increases. Becomes loose. Therefore, for example, when the reduction level of the gain accompanying the increase of the output power is moderate, it is possible to improve the linearity of the gain.

  In power amplification circuits 100A to 100D, bias circuit 121A includes transistor Q3 supplied with a voltage of a predetermined level to the base and outputting a bias current or a bias voltage from the emitter, and uses the base voltage of transistor Q3 as control voltage Vctrl. Output. Thus, the control voltage Vctrl becomes lower as the power level of the RF signal RF2 increases.

  The power amplification circuit 100E supplies a bias current or a bias voltage to the transistor Q1 amplifying the RF signal RF1, the transistor Q3 amplifying the RF signal RF2 according to the output signal of the transistor Q1, and the base or gate of the transistor Q2. And an attenuator 140E for attenuating the RF signal RF1 in accordance with the control voltage Vctrl supplied from the bias circuit 121B. The attenuator 140E has a collector that supplies the RF signal RF1 to the transistor Q1. And the bias circuit 121B is a second and a third diode connected in series, the bias control voltage VB being supplied to the anode of the second diode, and the transistor Q6 having the emitter connected to the ground side. The cathode of the third diode is connected to the ground side And a transistor Q3 whose base is connected to the anode of the second diode and which outputs a bias current or a bias voltage from the emitter, and the transistor Q6 is connected to the anode of the third diode from the anode of the third diode. Depending on the control voltage Vctrl supplied to the base, a part of the RF signal RF1 flows from the collector to the emitter of the transistor Q6. As a result, the operating speed of the attenuator 140E is faster than that of the power amplification circuit 100A, so that the performance following the fluctuation of the amplitude of the RF signal RF1 can be enhanced without using the capacitor C4.

  In power amplification circuits 100B and 100C, attenuators 140B and 140C are connected between the fourth diode connected in series in the supply path on the side where transistor Q6 is provided, the cathode of the fourth diode, and the ground. And included inductors L3 and L4. As a result, in the power amplification circuits 100B and 100C, the amount of change in attenuation of the RF signal with respect to the amount of increase in output power is larger than in the power amplification circuit 100A. Therefore, the accuracy of the linearity of the gain can be improved, for example, when the degree of reduction of the gain accompanying the increase of the output power is steeper.

  Further, in the power amplification circuits 100A to 100E, the emitter or source of the transistor Q1 and the emitter or source of the transistor Q2 may be connected to the ground via a bump. Thereby, parasitic inductance generated between the emitter and the ground can be suppressed. Therefore, since the gain of the power amplification circuit is entirely increased, the linearity of the gain can be further accurately improved by using an attenuator with a larger amount of change in attenuation.

  Further, in the power amplification circuits 100A to 100E, at least one of the transistors Q1 and Q2 may be configured by an FET. Also in this case, the gain of the power amplification circuit is increased, and therefore, the linearity of the gain can be further accurately improved by using the attenuator having a larger amount of change in attenuation.

  Each embodiment described above is for facilitating the understanding of the present invention, and is not for limiting and interpreting the present invention. The present invention can be changed or improved without departing from the gist thereof, and the present invention also includes the equivalents thereof. That is, those in which persons skilled in the art appropriately modify the design of each embodiment are also included in the scope of the present invention as long as they have the features of the present invention. For example, each element included in each embodiment and its arrangement, material, conditions, shape, size, and the like are not limited to those illustrated, and may be changed as appropriate. Further, the elements included in each embodiment can be combined as much as technically possible, and combinations of these are included in the scope of the present invention as long as they include the features of the present invention.

100 (100A to 100G) ... power amplification circuit, 110, 111, 112 ... amplifier, 120 (120A), 121 (121A, 121B), 122 ... bias circuit, 130, 131 ... matching circuit, 140 (140A to 140E), 141: Attenuator, C1 to C6: Capacitor, Q1 to Q12: Transistor, R1 to R7: Resistive element, L1 to L4: Inductor

Claims (7)

A first transistor for amplifying a first signal;
A second transistor that amplifies a second signal according to the output signal of the first transistor;
A bias circuit for supplying a bias current or a bias voltage to the base or gate of the second transistor;
An attenuator for attenuating the first signal or the second signal according to a control voltage supplied from the bias circuit;
Equipped with
The attenuator is
A first diode whose anode is supplied with the control voltage;
A collector is connected to a supply path of the first signal to the first transistor or a supply path of the second signal to the second transistor, an emitter is connected to the ground side, and a base of the first diode is connected to the base. A third transistor to which the control voltage is supplied;
A capacitor connected in parallel with the first diode;
Including
The control voltage is a lower voltage as the power level of the second signal is higher,
The power amplifier circuit, wherein the third transistor causes part of the first signal or the second signal to flow from the collector to the emitter of the third transistor in accordance with the control voltage supplied to the base of the third transistor. . A first transistor for amplifying a first signal;
A second transistor that amplifies a second signal according to the output signal of the first transistor;
A bias circuit for supplying a bias current or a bias voltage to the base or gate of the second transistor;
An attenuator for attenuating the first signal or the second signal according to a control voltage supplied from the bias circuit;
Equipped with
The attenuator is
A first diode whose anode is supplied with the control voltage;
A collector is connected to the base and to a supply path of the first signal to the first transistor or to a supply path of the second signal to the second transistor, an emitter is connected to the ground side, and the base is connected to the base A third transistor to which the control voltage is supplied from the cathode of the first diode;
Including
The control voltage is a lower voltage as the power level of the second signal is higher,
The power amplifier circuit, wherein the third transistor causes part of the first signal or the second signal to flow from the collector to the emitter of the third transistor in accordance with the control voltage supplied to the base of the third transistor. . The bias circuit
A fourth transistor supplied with a voltage of a predetermined level to a base and outputting the bias current or bias voltage from an emitter;
Outputting a base voltage of the fourth transistor as the control voltage;
The power amplification circuit according to claim 1. A first transistor for amplifying a first signal;
A second transistor that amplifies a second signal according to the output signal of the first transistor;
A bias circuit for supplying a bias current or a bias voltage to the base or gate of the second transistor;
An attenuator for attenuating the first signal or the second signal according to a control voltage supplied from the bias circuit;
Equipped with
The attenuator is
And a third transistor including a collector connected to a supply path of the first signal to the first transistor or a supply path of the second signal to the second transistor, and an emitter connected to the ground side.
The bias circuit
Second and third diodes connected in series, wherein a bias control voltage is supplied to the anode of the second diode, and a cathode of the third diode is connected to the ground side;
A fourth transistor having a base connected to an anode of the second diode and outputting the bias current or bias voltage from an emitter;
Including
The third transistor transmits a part of the first signal or the second signal from the collector of the third transistor in accordance with the control voltage supplied from the anode of the third diode to the base of the third transistor. Power amplifier circuit that flows to the emitter. The attenuator is
A fourth diode connected in series in the supply path on the side where the third transistor is provided;
An inductor connected between the cathode of the fourth diode and the ground;
Further include,
The power amplification circuit according to any one of claims 1 to 4. The emitter or source of the first transistor and the emitter or source of the second transistor are connected to ground via bumps.
The power amplification circuit according to any one of claims 1 to 5. At least one of the first transistor and the second transistor is configured by an FET.
The power amplification circuit according to any one of claims 1 to 6.

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